* Re: [PATCH v2 4/5] arm64: dts: add support for A4 based Amlogic BA400
From: Xianwei Zhao @ 2024-03-20 10:06 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Martin Blumenstingl, Jerome Brunet,
Kevin Hilman, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial
In-Reply-To: <f0050b33-c4fb-4263-aee6-4542e2be39e8@linaro.org>
Hi Krzysztof,
Thanks for your reply.
On 2024/3/20 17:48, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 20/03/2024 10:44, Xianwei Zhao via B4 Relay wrote:
>> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>
>> Amlogic A4 is an application processor designed for smart audio
>> and IoT applications.
>>
>> Add basic support for the A4 based Amlogic BA400 board, which describes
>> the following components: CPU, GIC, IRQ, Timer and UART.
>> These are capable of booting up into the serial console.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>> .../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
>> arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
>> 4 files changed, 149 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
>> index 1ab160bf928a..9a50ec11bb8d 100644
>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>> @@ -1,4 +1,5 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
>> dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
>> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
>> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
>> new file mode 100644
>> index 000000000000..43a9c666e1de
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
>> @@ -0,0 +1,42 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "amlogic-a4.dtsi"
>> +
>> +/ {
>> + model = "Amlogic A113L2 ba400 Development Board";
>> + compatible = "amlogic,ba400","amlogic,a4";
>
> Still missing space.
>
> You received comment about this. Fix entire file, not just one occurrence.
>
Will fix. I got it.
>
> Best regards,
> Krzysztof
>
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^ permalink raw reply
* [PATCH 1/2] iio: adc: imx93: Make calibration properties configurable
From: Andrej Picej @ 2024-03-20 10:04 UTC (permalink / raw)
To: haibo.chen, linux-iio, devicetree
Cc: jic23, lars, shawnguo, s.hauer, kernel, festevam, imx,
linux-arm-kernel, linux-kernel, robh, krzysztof.kozlowski+dt,
conor+dt, upstream
In-Reply-To: <20240320100407.1639082-1-andrej.picej@norik.com>
Make calibration properties:
- AVGEN: allow averaging of calibration time,
- NRSMPL: select the number of averaging samples during calibration and
- TSAMP: specifies the sample time of calibration conversions
configurable with device tree properties:
- nxp,calib-avg-en,
- nxp,calib-nr-samples and
- nxp,calib-t-samples.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
---
drivers/iio/adc/imx93_adc.c | 66 ++++++++++++++++++++++++++++++++++---
1 file changed, 61 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/imx93_adc.c b/drivers/iio/adc/imx93_adc.c
index 4ccf4819f1f1..ad24105761ab 100644
--- a/drivers/iio/adc/imx93_adc.c
+++ b/drivers/iio/adc/imx93_adc.c
@@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
+#include <linux/property.h>
#define IMX93_ADC_DRIVER_NAME "imx93-adc"
@@ -43,6 +44,9 @@
#define IMX93_ADC_MCR_MODE_MASK BIT(29)
#define IMX93_ADC_MCR_NSTART_MASK BIT(24)
#define IMX93_ADC_MCR_CALSTART_MASK BIT(14)
+#define IMX93_ADC_MCR_AVGEN_MASK BIT(13)
+#define IMX93_ADC_MCR_NRSMPL_MASK GENMASK(12, 11)
+#define IMX93_ADC_MCR_TSAMP_MASK GENMASK(10, 9)
#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8)
#define IMX93_ADC_MCR_PWDN_MASK BIT(0)
#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30)
@@ -145,7 +149,7 @@ static void imx93_adc_config_ad_clk(struct imx93_adc *adc)
static int imx93_adc_calibration(struct imx93_adc *adc)
{
- u32 mcr, msr;
+ u32 mcr, msr, value;
int ret;
/* make sure ADC in power down mode */
@@ -156,12 +160,64 @@ static int imx93_adc_calibration(struct imx93_adc *adc)
mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1);
writel(mcr, adc->regs + IMX93_ADC_MCR);
- imx93_adc_power_up(adc);
-
/*
- * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR,
- * can add the setting of these bit if need in future.
+ * Set calibration settings:
+ * - AVGEN: allow averaging of calibration time,
+ * - NRSMPL: select the number of averaging samples during calibration,
+ * - TSAMP: specifies the sample time of calibration conversions.
*/
+ if (!device_property_read_u32(adc->dev, "nxp,calib-avg-en", &value)) {
+ mcr &= ~IMX93_ADC_MCR_AVGEN_MASK;
+ mcr |= FIELD_PREP(IMX93_ADC_MCR_AVGEN_MASK, value);
+ }
+
+ if (!device_property_read_u32(adc->dev, "nxp,calib-nr-samples", &value)) {
+ switch (value) {
+ case 16:
+ value = 0x0;
+ break;
+ case 32:
+ value = 0x1;
+ break;
+ case 128:
+ value = 0x2;
+ break;
+ case 512:
+ value = 0x3;
+ break;
+ default:
+ dev_warn(adc->dev, "NRSMPL: wrong value, using default: 512\n");
+ value = 0x3;
+ }
+ mcr &= ~IMX93_ADC_MCR_NRSMPL_MASK;
+ mcr |= FIELD_PREP(IMX93_ADC_MCR_NRSMPL_MASK, value);
+ }
+
+ if (!device_property_read_u32(adc->dev, "nxp,calib-t-samples", &value)) {
+ switch (value) {
+ case 8:
+ value = 0x1;
+ break;
+ case 16:
+ value = 0x2;
+ break;
+ case 22:
+ value = 0x0;
+ break;
+ case 32:
+ value = 0x3;
+ break;
+ default:
+ dev_warn(adc->dev, "TSAMP: wrong value, using default: 22\n");
+ value = 0x0;
+ }
+ mcr &= ~IMX93_ADC_MCR_TSAMP_MASK;
+ mcr |= FIELD_PREP(IMX93_ADC_MCR_TSAMP_MASK, value);
+ }
+
+ writel(mcr, adc->regs + IMX93_ADC_MCR);
+
+ imx93_adc_power_up(adc);
/* run calibration */
mcr = readl(adc->regs + IMX93_ADC_MCR);
--
2.25.1
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^ permalink raw reply related
* [PATCH 0/2] i.MX93 ADC calibration settings
From: Andrej Picej @ 2024-03-20 10:04 UTC (permalink / raw)
To: haibo.chen, linux-iio, devicetree
Cc: jic23, lars, shawnguo, s.hauer, kernel, festevam, imx,
linux-arm-kernel, linux-kernel, robh, krzysztof.kozlowski+dt,
conor+dt, upstream
Hi all,
we had some problems with failing ADC calibration on the i.MX93 boards.
Changing default calibration settings fixed this. The board where this
patches are useful is not yet upstream but will be soon (hopefully).
Since we had these patches laying around we thought they might also be
useful for someone else.
Best regards,
Andrej
Andrej Picej (2):
iio: adc: imx93: Make calibration properties configurable
dt-bindings: iio: adc: nxp,imx93-adc.yaml: Add calibration properties
.../bindings/iio/adc/nxp,imx93-adc.yaml | 15 +++++
drivers/iio/adc/imx93_adc.c | 66 +++++++++++++++++--
2 files changed, 76 insertions(+), 5 deletions(-)
--
2.25.1
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^ permalink raw reply
* [PATCH 2/2] dt-bindings: iio: adc: nxp,imx93-adc.yaml: Add calibration properties
From: Andrej Picej @ 2024-03-20 10:04 UTC (permalink / raw)
To: haibo.chen, linux-iio, devicetree
Cc: jic23, lars, shawnguo, s.hauer, kernel, festevam, imx,
linux-arm-kernel, linux-kernel, robh, krzysztof.kozlowski+dt,
conor+dt, upstream
In-Reply-To: <20240320100407.1639082-1-andrej.picej@norik.com>
Document calibration properties and how to set them.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
---
.../bindings/iio/adc/nxp,imx93-adc.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
index dacc526dc695..64958be62a6a 100644
--- a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
@@ -46,6 +46,21 @@ properties:
"#io-channel-cells":
const: 1
+ nxp,calib-avg-en:
+ description:
+ Enable or disable averaging of calibration time.
+ enum: [ 0, 1 ]
+
+ nxp,calib-nr-samples:
+ description:
+ Selects the number of averaging samples to be used during calibration.
+ enum: [ 16, 32, 128, 512 ]
+
+ nxp,calib-t-samples:
+ description:
+ Specifies the sample time of calibration conversions.
+ enum: [ 8, 16, 22, 32 ]
+
required:
- compatible
- reg
--
2.25.1
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^ permalink raw reply related
* Re: [PATCH v8] dt-bindings: ata: imx-pata: Convert to dtschema
From: Animesh Agarwal @ 2024-03-20 9:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Damien Le Moal, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-ide, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <5056862e-a815-43ce-bb82-4cde39fffb2c@linaro.org>
On Wed, Mar 20, 2024 at 3:20 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Hi Krzysztof,
Thanks for the review.
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^ permalink raw reply
* Re: [PATCH v2 3/5] dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
From: Xianwei Zhao @ 2024-03-20 9:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neil Armstrong, Martin Blumenstingl, Jerome Brunet,
Kevin Hilman, Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial
In-Reply-To: <402e56ec-7fee-40a9-995b-b737d4a53d60@linaro.org>
Hi Krzysztof,
Thanks for reply.
On 2024/3/20 17:47, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 20/03/2024 10:44, Xianwei Zhao via B4 Relay wrote:
>> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>
>> Amlogic A4 SoCs uses the same UART controller as S4 SoCs and G12A.
>> There is no need for an extra compatible line in the driver, but
>> add A4 compatible line for documentation.
>>
>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>> ---
>> Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
>> index 2e189e548327..d05c45815dc2 100644
>> --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
>> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
>> @@ -54,7 +54,9 @@ properties:
>> - const: amlogic,meson-gx-uart
>> - description: UART controller on S4 compatible SoCs
>> items:
>> - - const: amlogic,t7-uart
>> + - enum:
>> + - amlogic,t7-uart
>> + - amlogic,a4-uart
>
> Keep alphabetical order. Don't add stuff to the end of lists. This
> comment applies in general, for almost all your patches, so also future
> submissions.
>
Will do. Thanks, I remembered.
> Best regards,
> Krzysztof
>
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^ permalink raw reply
* Re: [PATCH v5 4/4] pinctrl: Implementation of the generic scmi-pinctrl driver
From: Dan Carpenter @ 2024-03-20 9:53 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Oleksii Moisieiev, Linus Walleij, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-arm-kernel, linux-kernel, devicetree,
linux-gpio, AKASHI Takahiro, Peng Fan
In-Reply-To: <20240314-pinctrl-scmi-v5-4-b19576e557f2@nxp.com>
On Thu, Mar 14, 2024 at 09:35:21PM +0800, Peng Fan (OSS) wrote:
> +/* Define num configs, if not large than 4 use stack, else use kcalloc */
> +#define SCMI_NUM_CONFIGS 4
> +
> +static const struct scmi_pinctrl_proto_ops *pinctrl_ops;
> +
> +struct scmi_pinctrl_funcs {
> + unsigned int num_groups;
> + const char **groups;
> +};
> +
> +struct scmi_pinctrl {
> + struct device *dev;
> + struct scmi_protocol_handle *ph;
> + struct pinctrl_dev *pctldev;
> + struct pinctrl_desc pctl_desc;
> + struct scmi_pinctrl_funcs *functions;
> + unsigned int nr_functions;
> + char **groups;
> + unsigned int nr_groups;
groups and nr_groups are set/allocated but not used anywhere. Delete
them.
> + struct pinctrl_pin_desc *pins;
> + unsigned int nr_pins;
These last two struct members duplicate the information in
pmx->pctl_desc.pins and pmx->pctl_desc.npins. They're not used outside
of the pinctrl_scmi_get_pins() function. Delete them.
> +};
> +
> +static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE);
> +}
> +
> +static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + int ret;
> + const char *name;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE, &name);
> + if (ret) {
> + dev_err(pmx->dev, "get name failed with err %d", ret);
> + return NULL;
> + }
> +
> + return name;
> +}
> +
> +static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const unsigned int **pins,
> + unsigned int *num_pins)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->group_pins_get(pmx->ph, selector, pins, num_pins);
> +}
> +
> +static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = {
> + .get_groups_count = pinctrl_scmi_get_groups_count,
> + .get_group_name = pinctrl_scmi_get_group_name,
> + .get_group_pins = pinctrl_scmi_get_group_pins,
> +#ifdef CONFIG_OF
> + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
> + .dt_free_map = pinconf_generic_dt_free_map,
> +#endif
> +};
> +
> +static int pinctrl_scmi_get_functions_count(struct pinctrl_dev *pctldev)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE);
> +}
> +
> +static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev,
> + unsigned int selector)
> +{
> + int ret;
> + const char *name;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name);
> + if (ret) {
> + dev_err(pmx->dev, "get name failed with err %d", ret);
> + return NULL;
> + }
> +
> + return name;
> +}
> +
> +static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev,
> + unsigned int selector,
> + const char * const **groups,
> + unsigned int * const num_groups)
> +{
> + const unsigned int *group_ids;
> + int ret, i;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + if (!groups || !num_groups)
> + return -EINVAL;
> +
> + if (selector < pmx->nr_functions &&
> + pmx->functions[selector].num_groups) {
> + *groups = (const char * const *)pmx->functions[selector].groups;
> + *num_groups = pmx->functions[selector].num_groups;
> + return 0;
> + }
> +
> + ret = pinctrl_ops->function_groups_get(pmx->ph, selector,
> + &pmx->functions[selector].num_groups,
> + &group_ids);
> + if (ret) {
> + dev_err(pmx->dev, "Unable to get function groups, err %d", ret);
> + return ret;
> + }
> +
> + *num_groups = pmx->functions[selector].num_groups;
> + if (!*num_groups)
> + return -EINVAL;
> +
> + pmx->functions[selector].groups =
> + devm_kcalloc(pmx->dev, *num_groups,
> + sizeof(*pmx->functions[selector].groups),
> + GFP_KERNEL);
> + if (!pmx->functions[selector].groups)
> + return -ENOMEM;
> +
> + for (i = 0; i < *num_groups; i++) {
> + pmx->functions[selector].groups[i] =
> + pinctrl_scmi_get_group_name(pmx->pctldev,
> + group_ids[i]);
> + if (!pmx->functions[selector].groups[i]) {
> + ret = -ENOMEM;
-EINVAL would be a more appropriate error code than -ENOMEM. Nothing
is allocated here.
> + goto err_free;
> + }
> + }
> +
> + *groups = (const char * const *)pmx->functions[selector].groups;
> +
> + return 0;
> +
> +err_free:
> + devm_kfree(pmx->dev, pmx->functions[selector].groups);
> +
> + return ret;
> +}
I re-wrote this function. I'm not totally sure it's better...
static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **p_groups,
unsigned int * const p_num_groups)
{
struct scmi_pinctrl_funcs *func;
const unsigned int *group_ids;
unsigned int num_groups;
const char **groups;
int ret, i;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
if (!p_groups || !p_num_groups)
return -EINVAL;
if (selector >= pmx->nr_functions)
return -EINVAL;
func = &pmx->functions[selector];
if (func->num_groups)
goto done;
ret = pinctrl_ops->function_groups_get(pmx->ph, selector, &num_groups,
&group_ids);
if (ret) {
dev_err(pmx->dev, "Unable to get function groups, err %d", ret);
return ret;
}
if (!num_groups)
return -EINVAL;
groups = devm_kcalloc(pmx->dev, num_groups, sizeof(*groups), GFP_KERNEL);
if (!groups)
return -ENOMEM;
for (i = 0; i < num_groups; i++) {
groups[i] = pinctrl_scmi_get_group_name(pctldev, group_ids[i]);
if (!groups[i]) {
ret = -EINVAL;
goto err_free;
}
}
func->num_groups = num_groups;
func->groups = groups;
done:
*p_groups = (const char * const *)func->groups;
*p_num_groups = func->num_groups;
return 0;
err_free:
devm_kfree(pmx->dev, groups);
return ret;
}
> +
> +static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev,
> + unsigned int selector, unsigned int group)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->mux_set(pmx->ph, selector, group);
> +}
> +
> +static int pinctrl_scmi_request(struct pinctrl_dev *pctldev,
> + unsigned int offset)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->pin_request(pmx->ph, offset);
> +}
> +
> +static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned int offset)
> +{
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> +
> + return pinctrl_ops->pin_free(pmx->ph, offset);
> +}
> +
> +static const struct pinmux_ops pinctrl_scmi_pinmux_ops = {
> + .request = pinctrl_scmi_request,
> + .free = pinctrl_scmi_free,
> + .get_functions_count = pinctrl_scmi_get_functions_count,
> + .get_function_name = pinctrl_scmi_get_function_name,
> + .get_function_groups = pinctrl_scmi_get_function_groups,
> + .set_mux = pinctrl_scmi_func_set_mux,
> +};
> +
> +static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param,
> + enum scmi_pinctrl_conf_type *type)
> +{
> + u32 arg = param;
> +
> + switch (arg) {
> + case PIN_CONFIG_BIAS_BUS_HOLD:
> + *type = SCMI_PIN_BIAS_BUS_HOLD;
> + break;
> + case PIN_CONFIG_BIAS_DISABLE:
> + *type = SCMI_PIN_BIAS_DISABLE;
> + break;
> + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
> + *type = SCMI_PIN_BIAS_HIGH_IMPEDANCE;
> + break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + *type = SCMI_PIN_BIAS_PULL_DOWN;
> + break;
> + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
> + *type = SCMI_PIN_BIAS_PULL_DEFAULT;
> + break;
> + case PIN_CONFIG_BIAS_PULL_UP:
> + *type = SCMI_PIN_BIAS_PULL_UP;
> + break;
> + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> + *type = SCMI_PIN_DRIVE_OPEN_DRAIN;
> + break;
> + case PIN_CONFIG_DRIVE_OPEN_SOURCE:
> + *type = SCMI_PIN_DRIVE_OPEN_SOURCE;
> + break;
> + case PIN_CONFIG_DRIVE_PUSH_PULL:
> + *type = SCMI_PIN_DRIVE_PUSH_PULL;
> + break;
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + *type = SCMI_PIN_DRIVE_STRENGTH;
> + break;
> + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> + *type = SCMI_PIN_DRIVE_STRENGTH;
> + break;
> + case PIN_CONFIG_INPUT_DEBOUNCE:
> + *type = SCMI_PIN_INPUT_DEBOUNCE;
> + break;
> + case PIN_CONFIG_INPUT_ENABLE:
> + *type = SCMI_PIN_INPUT_MODE;
> + break;
> + case PIN_CONFIG_INPUT_SCHMITT:
> + *type = SCMI_PIN_INPUT_SCHMITT;
> + break;
> + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> + *type = SCMI_PIN_INPUT_MODE;
> + break;
> + case PIN_CONFIG_MODE_LOW_POWER:
> + *type = SCMI_PIN_LOW_POWER_MODE;
> + break;
> + case PIN_CONFIG_OUTPUT:
> + *type = SCMI_PIN_OUTPUT_VALUE;
> + break;
> + case PIN_CONFIG_OUTPUT_ENABLE:
> + *type = SCMI_PIN_OUTPUT_MODE;
> + break;
> + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
> + *type = SCMI_PIN_OUTPUT_VALUE;
> + break;
> + case PIN_CONFIG_POWER_SOURCE:
> + *type = SCMI_PIN_POWER_SOURCE;
> + break;
> + case PIN_CONFIG_SLEW_RATE:
> + *type = SCMI_PIN_SLEW_RATE;
> + break;
> + case SCMI_PIN_OEM_START ... SCMI_PIN_OEM_END:
> + *type = arg;
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev,
> + unsigned int _pin, unsigned long *config)
> +{
> + int ret;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param config_type;
> + enum scmi_pinctrl_conf_type type;
> + u32 config_value;
> +
> + if (!config)
> + return -EINVAL;
> +
> + config_type = pinconf_to_config_param(*config);
> +
> + ret = pinctrl_scmi_map_pinconf_type(config_type, &type);
> + if (ret) {
> + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
> + return ret;
> + }
> +
> + ret = pinctrl_ops->config_get(pmx->ph, _pin, PIN_TYPE, type,
> + &config_value);
> + if (ret)
> + return ret;
> +
> + *config = pinconf_to_config_packed(config_type, config_value);
> +
> + return 0;
> +}
> +
> +static int
> +pinctrl_scmi_alloc_configs(struct pinctrl_dev *pctldev, u32 num_configs,
> + u32 **p_config_value,
> + enum scmi_pinctrl_conf_type **p_config_type)
> +{
> + if (num_configs <= SCMI_NUM_CONFIGS)
> + return 0;
> +
> + *p_config_value = kcalloc(num_configs, sizeof(u32), GFP_KERNEL);
> + *p_config_type = kcalloc(num_configs,
> + sizeof(enum scmi_pinctrl_conf_type),
> + GFP_KERNEL);
> +
> + if (!*p_config_value || !*p_config_type) {
> + kfree(*p_config_value);
> + kfree(*p_config_type);
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static void
> +pinctrl_scmi_free_configs(struct pinctrl_dev *pctldev, u32 num_configs,
> + u32 **p_config_value,
> + enum scmi_pinctrl_conf_type **p_config_type)
> +{
> + if (num_configs <= SCMI_NUM_CONFIGS)
> + return;
> +
> + kfree(*p_config_value);
> + kfree(*p_config_type);
> +}
> +
> +static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev,
> + unsigned int _pin,
> + unsigned long *configs,
> + unsigned int num_configs)
> +{
> + int i, ret;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
> + u32 config_value[SCMI_NUM_CONFIGS];
> + enum scmi_pinctrl_conf_type *p_config_type = config_type;
> + u32 *p_config_value = config_value;
> + enum pin_config_param param;
> +
> + if (!configs || !num_configs)
> + return -EINVAL;
> +
> + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs, &p_config_type,
> + &p_config_value);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < num_configs; i++) {
> + param = pinconf_to_config_param(configs[i]);
> + ret = pinctrl_scmi_map_pinconf_type(param, &p_config_type[i]);
> + if (ret) {
> + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
> + goto free_config;
> + }
> + p_config_value[i] = pinconf_to_config_argument(configs[i]);
> + }
> +
> + ret = pinctrl_ops->config_set(pmx->ph, _pin, PIN_TYPE, num_configs,
> + p_config_type, p_config_value);
> + if (ret)
> + dev_err(pmx->dev, "Error parsing config %d\n", ret);
> +
> +free_config:
> + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type,
> + &p_config_value);
> + return ret;
> +}
> +
> +static int pinctrl_scmi_pinconf_group_set(struct pinctrl_dev *pctldev,
> + unsigned int group,
> + unsigned long *configs,
> + unsigned int num_configs)
> +{
> + int i, ret;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
> + u32 config_value[SCMI_NUM_CONFIGS];
> + enum scmi_pinctrl_conf_type *p_config_type = config_type;
> + u32 *p_config_value = config_value;
> + enum pin_config_param param;
> +
> + if (!configs || !num_configs)
> + return -EINVAL;
> +
> + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs, &p_config_type,
> + &p_config_value);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < num_configs; i++) {
> + param = pinconf_to_config_param(configs[i]);
> + ret = pinctrl_scmi_map_pinconf_type(param,
> + &p_config_type[i]);
> + if (ret) {
> + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
> + goto free_config;
> + }
> +
> + p_config_value[i] = pinconf_to_config_argument(configs[i]);
> + }
> +
> + ret = pinctrl_ops->config_set(pmx->ph, group, GROUP_TYPE, num_configs,
> + p_config_type, p_config_value);
> + if (ret)
> + dev_err(pmx->dev, "Error parsing config %d", ret);
> +
> +free_config:
> + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type,
> + &p_config_value);
> + return ret;
> +};
> +
> +static int pinctrl_scmi_pinconf_group_get(struct pinctrl_dev *pctldev,
> + unsigned int group,
> + unsigned long *config)
> +{
> + int ret;
> + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> + enum pin_config_param config_type;
> + enum scmi_pinctrl_conf_type type;
> + u32 config_value;
> +
> + if (!config)
> + return -EINVAL;
> +
> + config_type = pinconf_to_config_param(*config);
> + ret = pinctrl_scmi_map_pinconf_type(config_type, &type);
> + if (ret) {
> + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
> + return ret;
> + }
> +
> + ret = pinctrl_ops->config_get(pmx->ph, group, GROUP_TYPE, type,
> + &config_value);
> + if (ret)
> + return ret;
> +
> + *config = pinconf_to_config_packed(config_type, config_value);
> +
> + return 0;
> +}
> +
> +static const struct pinconf_ops pinctrl_scmi_pinconf_ops = {
> + .is_generic = true,
> + .pin_config_get = pinctrl_scmi_pinconf_get,
> + .pin_config_set = pinctrl_scmi_pinconf_set,
> + .pin_config_group_set = pinctrl_scmi_pinconf_group_set,
> + .pin_config_group_get = pinctrl_scmi_pinconf_group_get,
> + .pin_config_config_dbg_show = pinconf_generic_dump_config,
> +};
> +
> +static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
> + unsigned int *nr_pins,
> + const struct pinctrl_pin_desc **pins)
> +{
> + int ret, i;
> +
> + if (!pins || !nr_pins)
> + return -EINVAL;
> +
> + if (pmx->nr_pins) {
This condition is testing whether we can re-use the information from the
previous call. However, the function is only called once (from probe)
so there is no previous call and this condition can be removed.
> + *pins = pmx->pins;
> + *nr_pins = pmx->nr_pins;
> + return 0;
> + }
> +
> + *nr_pins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
> +
> + pmx->nr_pins = *nr_pins;
> + pmx->pins = devm_kmalloc_array(pmx->dev, *nr_pins, sizeof(*pmx->pins),
> + GFP_KERNEL);
> + if (!pmx->pins)
> + return -ENOMEM;
If we were going to re-use the information then we'd need to set
pmx->nr_pins = 0; on this path. But we're not, so that's fine.
> +
> + for (i = 0; i < *nr_pins; i++) {
> + pmx->pins[i].number = i;
> + ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE,
> + &pmx->pins[i].name);
> + if (ret) {
> + dev_err(pmx->dev, "Can't get name for pin %d: rc %d", i, ret);
> + pmx->nr_pins = 0;
No need to set ->nr_pins = 0;
> + return ret;
> + }
> + }
> +
> + *pins = pmx->pins;
> + dev_dbg(pmx->dev, "got pins %d", *nr_pins);
> +
> + return 0;
> +}
Ok, I put way too much thought into reviewing this function and I ended
up re-writing it slightly:
static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
struct pinctrl_desc *desc)
{
struct pinctrl_pin_desc *pins;
unsigned int npins;
int ret, i;
npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < npins; i++) {
pins[i].number = i;
ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
if (ret)
return dev_err_probe(pmx->dev, ret,
"Can't get name for pin %d", i);
}
desc->npins = npins;
desc->pins = pins;
dev_dbg(pmx->dev, "got pins %d", npins);
return 0;
}
> +
> +static const struct scmi_device_id scmi_id_table[] = {
> + { SCMI_PROTOCOL_PINCTRL, "pinctrl" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(scmi, scmi_id_table);
> +
> +static int scmi_pinctrl_probe(struct scmi_device *sdev)
> +{
> + int ret;
> + struct device *dev = &sdev->dev;
> + struct scmi_pinctrl *pmx;
> + const struct scmi_handle *handle;
> + struct scmi_protocol_handle *ph;
> +
> + if (!sdev || !sdev->handle)
> + return -EINVAL;
> +
> + handle = sdev->handle;
> +
> + pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL,
> + &ph);
> + if (IS_ERR(pinctrl_ops))
> + return PTR_ERR(pinctrl_ops);
> +
> + pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
> + if (!pmx)
> + return -ENOMEM;
> +
> + pmx->ph = ph;
> +
> + pmx->dev = dev;
> + pmx->pctl_desc.name = DRV_NAME;
> + pmx->pctl_desc.owner = THIS_MODULE;
> + pmx->pctl_desc.pctlops = &pinctrl_scmi_pinctrl_ops;
> + pmx->pctl_desc.pmxops = &pinctrl_scmi_pinmux_ops;
> + pmx->pctl_desc.confops = &pinctrl_scmi_pinconf_ops;
> +
> + ret = pinctrl_scmi_get_pins(pmx, &pmx->pctl_desc.npins,
> + &pmx->pctl_desc.pins);
> + if (ret)
> + return ret;
> +
> + ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
> + &pmx->pctldev);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
> +
> + pmx->nr_functions = pinctrl_scmi_get_functions_count(pmx->pctldev);
> + pmx->nr_groups = pinctrl_scmi_get_groups_count(pmx->pctldev);
> +
> + if (pmx->nr_functions) {
You don't need to have this condition. kcalloc() can allocate zero
element arrays.
> + pmx->functions = devm_kcalloc(dev, pmx->nr_functions,
> + sizeof(*pmx->functions),
> + GFP_KERNEL);
> + if (!pmx->functions)
> + return -ENOMEM;
> + }
> +
> + if (pmx->nr_groups) {
Same.
> + pmx->groups = devm_kcalloc(dev, pmx->nr_groups,
> + sizeof(*pmx->groups), GFP_KERNEL);
> + if (!pmx->groups)
> + return -ENOMEM;
> + }
> +
> + return pinctrl_enable(pmx->pctldev);
There is a double free bug in pinctrl_enable() but it's not related to
your patch. I'll send a fix for that.
> +}
regards,
dan carpenter
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v8] dt-bindings: ata: imx-pata: Convert to dtschema
From: Krzysztof Kozlowski @ 2024-03-20 9:50 UTC (permalink / raw)
To: Animesh Agarwal
Cc: Damien Le Moal, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-ide, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240320090733.96828-1-animeshagarwal28@gmail.com>
On 20/03/2024 10:07, Animesh Agarwal wrote:
> Convert the imx-pata bindings to DT schema.
> Add missing fsl,imx31-pata and fsl,imx51-pata compatibles during
> conversion, because they are already being used in existing DTS.
>
> Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2] clk: imx: imx8mp: Add pm_runtime support for power saving
From: Marc Kleine-Budde @ 2024-03-20 9:50 UTC (permalink / raw)
To: Shengjiu Wang
Cc: abelvesa, peng.fan, mturquette, sboyd, shawnguo, s.hauer, kernel,
festevam, linux-imx, shengjiu.wang, linux-clk, linux-arm-kernel,
linux-kernel
In-Reply-To: <1710925851-5643-1-git-send-email-shengjiu.wang@nxp.com>
[-- Attachment #1.1: Type: text/plain, Size: 8359 bytes --]
On 20.03.2024 17:10:51, Shengjiu Wang wrote:
> Add pm_runtime support for power saving. In pm runtime suspend
> state the registers will be reseted, so add registers save
> in pm runtime suspend and restore them in pm runtime resume.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
> changes in v2:
> - move pm_runtime_enable before the clk register
>
> drivers/clk/imx/clk-imx8mp-audiomix.c | 150 +++++++++++++++++++++++---
> 1 file changed, 137 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
> index 55ed211a5e0b..6042280d6404 100644
> --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> @@ -7,10 +7,12 @@
>
> #include <linux/clk-provider.h>
> #include <linux/device.h>
> +#include <linux/io.h>
> #include <linux/mod_devicetable.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>
> #include <dt-bindings/clock/imx8mp-clock.h>
>
> @@ -18,6 +20,7 @@
>
> #define CLKEN0 0x000
> #define CLKEN1 0x004
> +#define EARC 0x200
> #define SAI1_MCLK_SEL 0x300
> #define SAI2_MCLK_SEL 0x304
> #define SAI3_MCLK_SEL 0x308
> @@ -26,6 +29,12 @@
> #define SAI7_MCLK_SEL 0x314
> #define PDM_SEL 0x318
> #define SAI_PLL_GNRL_CTL 0x400
> +#define SAI_PLL_FDIVL_CTL0 0x404
> +#define SAI_PLL_FDIVL_CTL1 0x408
> +#define SAI_PLL_SSCG_CTL 0x40C
> +#define SAI_PLL_MNIT_CTL 0x410
> +#define IPG_LP_CTRL 0x504
> +#define REGS_NUM 16
not needed
>
> #define SAIn_MCLK1_PARENT(n) \
> static const struct clk_parent_data \
> @@ -182,13 +191,65 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
> CLK_SAIn(7)
> };
>
> +struct clk_imx8mp_audiomix_regs {
> + u32 regs_num;
> + u32 regs_off[];
nitpick: if the offsets fit into an u16 you can save some space.
> +};
> +
> +static const struct clk_imx8mp_audiomix_regs audiomix_regs = {
> + .regs_num = REGS_NUM,
> + .regs_off = {
> + CLKEN0,
> + CLKEN1,
> + EARC,
> + SAI1_MCLK_SEL,
> + SAI2_MCLK_SEL,
> + SAI3_MCLK_SEL,
> + SAI5_MCLK_SEL,
> + SAI6_MCLK_SEL,
> + SAI7_MCLK_SEL,
> + PDM_SEL,
> + SAI_PLL_GNRL_CTL,
> + SAI_PLL_FDIVL_CTL0,
> + SAI_PLL_FDIVL_CTL1,
> + SAI_PLL_SSCG_CTL,
> + SAI_PLL_MNIT_CTL,
> + IPG_LP_CTRL
> + },
> +};
You only need an array with the offsets, use ARRAY_SIZE() to get the
number of entries in the array.
> +
> +struct clk_imx8mp_audiomix_drvdata {
> + void __iomem *base;
> + u32 regs_save[REGS_NUM];
make use of ARRAY_SIZE() here
> +};
> +
> +static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
> +{
> + struct clk_imx8mp_audiomix_drvdata *drvdata = dev_get_drvdata(dev);
> + void __iomem *base = drvdata->base;
> + int i;
> +
> + if (save) {
> + for (i = 0; i < audiomix_regs.regs_num; i++)
> + drvdata->regs_save[i] = readl(base + audiomix_regs.regs_off[i]);
> + } else {
> + for (i = 0; i < audiomix_regs.regs_num; i++)
> + writel(drvdata->regs_save[i], base + audiomix_regs.regs_off[i]);
> + }
> +}
> +
> static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> {
> + struct clk_imx8mp_audiomix_drvdata *drvdata;
> struct clk_hw_onecell_data *priv;
> struct device *dev = &pdev->dev;
> void __iomem *base;
> struct clk_hw *hw;
> - int i;
> + int i, ret;
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
You already allocate memory with devm_kzalloc() below. Why not increase
the size?
Rename clk_imx8mp_audiomix_drvdata to clk_imx8mp_audiomix_priv
and add struct clk_hw_onecell_data to it.
> + if (!drvdata)
> + return -ENOMEM;
>
> priv = devm_kzalloc(dev,
> struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
> @@ -202,6 +263,18 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> + drvdata->base = base;
> + dev_set_drvdata(dev, drvdata);
> +
> + /*
> + * pm_runtime_enable needs to be called before clk register.
> + * That is to make core->rpm_enabled to be true for clock
> + * usage.
> + */
> + pm_runtime_get_noresume(dev);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
> for (i = 0; i < ARRAY_SIZE(sels); i++) {
> if (sels[i].num_parents == 1) {
> hw = devm_clk_hw_register_gate_parent_data(dev,
> @@ -216,8 +289,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> 0, NULL, NULL);
> }
>
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(hw)) {
> + ret = PTR_ERR(hw);
> + goto err_clk_register;
> + }
>
> priv->hws[sels[i].clkid] = hw;
> }
> @@ -232,8 +307,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
>
> hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
> base + 0x400, &imx_1443x_pll);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(hw)) {
> + ret = PTR_ERR(hw);
> + goto err_clk_register;
> + }
> priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
>
> hw = devm_clk_hw_register_mux_parent_data_table(dev,
> @@ -241,26 +318,71 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
> CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(hw)) {
> + ret = PTR_ERR(hw);
> + goto err_clk_register;
> + }
> +
> priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
>
> hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
> 0, base + SAI_PLL_GNRL_CTL, 13,
> 0, NULL);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(hw)) {
> + ret = PTR_ERR(hw);
> + goto err_clk_register;
> + }
> priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
>
> hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
> "sai_pll_out", 0, 1, 2);
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(hw)) {
> + ret = PTR_ERR(hw);
> + goto err_clk_register;
> + }
> +
> + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> + priv);
> + if (ret)
> + goto err_clk_register;
> +
> + pm_runtime_put_sync(dev);
> + return 0;
> +
> +err_clk_register:
> + pm_runtime_put_sync(dev);
> + pm_runtime_disable(dev);
> + return ret;
> +}
> +
> +static int clk_imx8mp_audiomix_remove(struct platform_device *pdev)
> +{
> + pm_runtime_disable(&pdev->dev);
>
> - return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> - priv);
> + return 0;
> }
>
> +static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
> +{
> + clk_imx8mp_audiomix_save_restore(dev, true);
> +
> + return 0;
> +}
> +
> +static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
> +{
> + clk_imx8mp_audiomix_save_restore(dev, false);
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
> + SET_RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
> + clk_imx8mp_audiomix_runtime_resume, NULL)
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> + pm_runtime_force_resume)
> +};
> +
> static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
> { .compatible = "fsl,imx8mp-audio-blk-ctrl" },
> { /* sentinel */ }
> @@ -269,9 +391,11 @@ MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
>
> static struct platform_driver clk_imx8mp_audiomix_driver = {
> .probe = clk_imx8mp_audiomix_probe,
> + .remove = clk_imx8mp_audiomix_remove,
> .driver = {
> .name = "imx8mp-audio-blk-ctrl",
> .of_match_table = clk_imx8mp_audiomix_of_match,
> + .pm = &clk_imx8mp_audiomix_pm_ops,
> },
> };
>
> --
> 2.34.1
>
>
>
regards,
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
[-- Attachment #1.2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: add support for A5 based Amlogic AV400
From: Krzysztof Kozlowski @ 2024-03-20 9:48 UTC (permalink / raw)
To: xianwei.zhao, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial
In-Reply-To: <20240320-basic_dt-v2-5-681ecfb23baf@amlogic.com>
On 20/03/2024 10:44, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> Amlogic A5 is an application processor designed for smart audio
> and IoT applications.
>
> Add basic support for the A5 based Amlogic AV400 board, which describes
> the following components: CPU, GIC, IRQ, Timer and UART.
> These are capable of booting up into the serial console.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
> index 9a50ec11bb8d..154c9efb26e4 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
> +dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
> new file mode 100644
> index 000000000000..2f5f5ea74bc9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "amlogic-a5.dtsi"
> +
> +/ {
> + model = "Amlogic A113X2 av400 Development Board";
> + compatible = "amlogic,av400","amlogic,a5";
Please fix missing space in all your patches.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 4/5] arm64: dts: add support for A4 based Amlogic BA400
From: Krzysztof Kozlowski @ 2024-03-20 9:48 UTC (permalink / raw)
To: xianwei.zhao, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial
In-Reply-To: <20240320-basic_dt-v2-4-681ecfb23baf@amlogic.com>
On 20/03/2024 10:44, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> Amlogic A4 is an application processor designed for smart audio
> and IoT applications.
>
> Add basic support for the A4 based Amlogic BA400 board, which describes
> the following components: CPU, GIC, IRQ, Timer and UART.
> These are capable of booting up into the serial console.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
> arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
> 4 files changed, 149 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
> index 1ab160bf928a..9a50ec11bb8d 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
> new file mode 100644
> index 000000000000..43a9c666e1de
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "amlogic-a4.dtsi"
> +
> +/ {
> + model = "Amlogic A113L2 ba400 Development Board";
> + compatible = "amlogic,ba400","amlogic,a4";
Still missing space.
You received comment about this. Fix entire file, not just one occurrence.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 3/5] dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
From: Krzysztof Kozlowski @ 2024-03-20 9:47 UTC (permalink / raw)
To: xianwei.zhao, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial
In-Reply-To: <20240320-basic_dt-v2-3-681ecfb23baf@amlogic.com>
On 20/03/2024 10:44, Xianwei Zhao via B4 Relay wrote:
> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>
> Amlogic A4 SoCs uses the same UART controller as S4 SoCs and G12A.
> There is no need for an extra compatible line in the driver, but
> add A4 compatible line for documentation.
>
> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
> ---
> Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
> index 2e189e548327..d05c45815dc2 100644
> --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
> @@ -54,7 +54,9 @@ properties:
> - const: amlogic,meson-gx-uart
> - description: UART controller on S4 compatible SoCs
> items:
> - - const: amlogic,t7-uart
> + - enum:
> + - amlogic,t7-uart
> + - amlogic,a4-uart
Keep alphabetical order. Don't add stuff to the end of lists. This
comment applies in general, for almost all your patches, so also future
submissions.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2 1/5] dt-bindings: arm: amlogic: add A4 support
From: Xianwei Zhao via B4 Relay @ 2024-03-20 9:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao, Krzysztof Kozlowski
In-Reply-To: <20240320-basic_dt-v2-0-681ecfb23baf@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Document the new A4 SoC/board device tree bindings.
Amlogic A4 is an application processor designed for smart audio
and IoT applications.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 949537cea6be..520975e7cac0 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -201,6 +201,12 @@ properties:
- amlogic,ad402
- const: amlogic,a1
+ - description: Boards with the Amlogic A4 A113L2 SoC
+ items:
+ - enum:
+ - amlogic,ba400
+ - const: amlogic,a4
+
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
--
2.37.1
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^ permalink raw reply related
* [PATCH v2 4/5] arm64: dts: add support for A4 based Amlogic BA400
From: Xianwei Zhao via B4 Relay @ 2024-03-20 9:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240320-basic_dt-v2-0-681ecfb23baf@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A4 is an application processor designed for smart audio
and IoT applications.
Add basic support for the A4 based Amlogic BA400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART.
These are capable of booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
4 files changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 1ab160bf928a..9a50ec11bb8d 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
new file mode 100644
index 000000000000..43a9c666e1de
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "amlogic-a4.dtsi"
+
+/ {
+ model = "Amlogic A113L2 ba400 Development Board";
+ compatible = "amlogic,ba400","amlogic,a4";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_b;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 10 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x05000000 0x0 0xa00000>;
+ no-map;
+ };
+ };
+};
+
+&uart_b {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
new file mode 100644
index 000000000000..b6106ad4a072
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@fff01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfff01000 0 0x1000>,
+ <0x0 0xfff02000 0 0x2000>,
+ <0x0 0xfff04000 0 0x2000>,
+ <0x0 0xfff06000 0 0x2000>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ apb: bus@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x480000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+
+ uart_b: serial@7a000 {
+ compatible = "amlogic,a4-uart",
+ "amlogic,meson-s4-uart";
+ reg = <0x0 0x7a000 0x0 0x18>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&xtal>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
new file mode 100644
index 000000000000..73ca1d7eed81
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include "amlogic-a4-common.dtsi"
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+};
--
2.37.1
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* [PATCH v2 5/5] arm64: dts: add support for A5 based Amlogic AV400
From: Xianwei Zhao via B4 Relay @ 2024-03-20 9:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240320-basic_dt-v2-0-681ecfb23baf@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A5 is an application processor designed for smart audio
and IoT applications.
Add basic support for the A5 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART.
These are capable of booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++++++++++
3 files changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 9a50ec11bb8d..154c9efb26e4 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
+dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
new file mode 100644
index 000000000000..2f5f5ea74bc9
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5-a113x2-av400.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "amlogic-a5.dtsi"
+
+/ {
+ model = "Amlogic A113X2 av400 Development Board";
+ compatible = "amlogic,av400","amlogic,a5";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_b;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 10 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x05000000 0x0 0xa00000>;
+ no-map;
+ };
+ };
+};
+
+&uart_b {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
new file mode 100644
index 000000000000..43f68a7da2f7
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ */
+
+#include "amlogic-a4-common.dtsi"
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+ };
+};
--
2.37.1
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* [PATCH v2 0/5] Baisc devicetree support for Amlogic A4 and A5
From: Xianwei Zhao via B4 Relay @ 2024-03-20 9:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao, Krzysztof Kozlowski
Amlogic A4 and A5 are application processors designed for smart audio
and IoT applications.
Add the new A4 SoC/board device tree bindings.
Add the new A5 SoC/board device tree bindings.
Add A4 UART compatible line for documentation.
Add basic support for the A4 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Add basic support for the A5 based Amlogic AV400 board, which describes
the following components: CPU, GIC, IRQ, Timer and UART. These are capable of
booting up into the serial console.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Changes in v2:
- Delete bindings for uncommitted boards.
- Add A4 UART compatible line for documentation.
- Use common dtsi for a4 and a5.
- Fix psci version 1.0, and fix some formats.
- Modify secmon reserved memory size 10M(actual using).
- Link to v1: https://lore.kernel.org/r/20240312-basic_dt-v1-0-7f11df3a0896@amlogic.com
---
Xianwei Zhao (5):
dt-bindings: arm: amlogic: add A4 support
dt-bindings: arm: amlogic: add A5 support
dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
arm64: dts: add support for A4 based Amlogic BA400
arm64: dts: add support for A5 based Amlogic AV400
Documentation/devicetree/bindings/arm/amlogic.yaml | 12 ++++
.../bindings/serial/amlogic,meson-uart.yaml | 4 +-
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4-common.dtsi | 66 ++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 40 +++++++++++++
.../boot/dts/amlogic/amlogic-a5-a113x2-av400.dts | 42 ++++++++++++++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 40 +++++++++++++
8 files changed, 247 insertions(+), 1 deletion(-)
---
base-commit: 7092cfae086f0bc235baca413d0bd904f182670c
change-id: 20240312-basic_dt-15e47525a413
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
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^ permalink raw reply
* [PATCH v2 3/5] dt-bindings: serial: amlogic,meson-uart: Add compatible string for A4
From: Xianwei Zhao via B4 Relay @ 2024-03-20 9:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Martin Blumenstingl, Jerome Brunet, Kevin Hilman,
Greg Kroah-Hartman, Jiri Slaby
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-serial, Xianwei Zhao
In-Reply-To: <20240320-basic_dt-v2-0-681ecfb23baf@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Amlogic A4 SoCs uses the same UART controller as S4 SoCs and G12A.
There is no need for an extra compatible line in the driver, but
add A4 compatible line for documentation.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
index 2e189e548327..d05c45815dc2 100644
--- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
@@ -54,7 +54,9 @@ properties:
- const: amlogic,meson-gx-uart
- description: UART controller on S4 compatible SoCs
items:
- - const: amlogic,t7-uart
+ - enum:
+ - amlogic,t7-uart
+ - amlogic,a4-uart
- const: amlogic,meson-s4-uart
reg:
--
2.37.1
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^ permalink raw reply related
* Re: [PATCH v4 4/5] media: platform: mediatek: isp_30: add mediatek ISP3.0 camsv
From: CK Hu (胡俊光) @ 2024-03-20 9:36 UTC (permalink / raw)
To: jstephan@baylibre.com
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
robh+dt@kernel.org, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, paul.elder@ideasonboard.com,
mchehab@kernel.org, conor+dt@kernel.org,
Andy Hsieh (謝智皓),
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org,
Louis Kuo (郭德寧),
laurent.pinchart@ideasonboard.com, fsylvestre@baylibre.com,
matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com,
pnguyen@baylibre.com
In-Reply-To: <20240110141443.364655-5-jstephan@baylibre.com>
Hi, Julien:
On Wed, 2024-01-10 at 15:14 +0100, Julien Stephan wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> From: Phi-bang Nguyen <pnguyen@baylibre.com>
>
> This driver provides a path to bypass the SoC ISP so that image data
> coming from the SENINF can go directly into memory without any image
> processing. This allows the use of an external ISP.
>
> Signed-off-by: Phi-bang Nguyen <pnguyen@baylibre.com>
> Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com>
> [Paul Elder fix irq locking]
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Co-developed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Co-developed-by: Julien Stephan <jstephan@baylibre.com>
> Signed-off-by: Julien Stephan <jstephan@baylibre.com>
> ---
[snip]
> +
> +static int mtk_cam_vb2_queue_setup(struct vb2_queue *vq,
> + unsigned int *num_buffers,
> + unsigned int *num_planes,
> + unsigned int sizes[],
> + struct device *alloc_devs[])
> +{
> + struct mtk_cam_video_device *vdev =
> + vb2_queue_to_mtk_cam_video_device(vq);
> + unsigned int max_buffer_count = vdev->desc->max_buf_count;
> + const struct v4l2_pix_format_mplane *fmt = &vdev->format;
> + unsigned int size;
> + unsigned int np_conf;
> + unsigned int i;
> +
> + /* Check the limitation of buffer size */
> + if (max_buffer_count)
max_buffer_count is always zero, so this checking is redundant.
Regards,
CK
> + *num_buffers = clamp_val(*num_buffers, 1,
> max_buffer_count);
> +
> + size = fmt->plane_fmt[0].sizeimage;
> + /* Add for q.create_bufs with fmt.g_sizeimage(p) / 2 test */
> +
> + np_conf = 1;
> +
> + if (*num_planes == 0) {
> + *num_planes = np_conf;
> + for (i = 0; i < *num_planes; ++i)
> + sizes[i] = size;
> + } else if (*num_planes != np_conf || sizes[0] < size) {
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
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* Re: [PATCH 1/3] ARM: dts: renesas: r8a73a4: Add TMU nodes
From: Krzysztof Kozlowski @ 2024-03-20 9:33 UTC (permalink / raw)
To: Niklas Söderlund, Geert Uytterhoeven
Cc: Magnus Damm, linux-renesas-soc, linux-arm-kernel
In-Reply-To: <20240319224223.GC3438308@ragnatech.se>
On 19/03/2024 23:42, Niklas Söderlund wrote:
> Hi Geert,
>
> Thanks for your patch.
>
> On 2024-03-19 17:29:05 +0100, Geert Uytterhoeven wrote:
>> Add device nodes for the Timer Units (TMU) on the R-Mobile APE6 SoC,
>> and the clocks serving them.
>>
>> Note that TMU channels 1 and 2 are not added, as their interrupts are
>> not wired to the interrupt controller for the AP-System Core (INTC-SYS),
>> only to the interrupt controller for the AP-Realtime Core (INTC-RT).
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Please run scripts/checkpatch.pl and fix reported warnings. Some
warnings can be ignored, but the code here looks like it needs a fix.
Feel free to get in touch if the warning is not clear.
DT bindings are separate patches.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2] clk: imx: imx8mp: Add pm_runtime support for power saving
From: Shengjiu Wang @ 2024-03-20 9:10 UTC (permalink / raw)
To: abelvesa, peng.fan, mturquette, sboyd, shawnguo, s.hauer, kernel,
festevam, linux-imx, shengjiu.wang
Cc: linux-clk, linux-arm-kernel, linux-kernel
Add pm_runtime support for power saving. In pm runtime suspend
state the registers will be reseted, so add registers save
in pm runtime suspend and restore them in pm runtime resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
changes in v2:
- move pm_runtime_enable before the clk register
drivers/clk/imx/clk-imx8mp-audiomix.c | 150 +++++++++++++++++++++++---
1 file changed, 137 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
index 55ed211a5e0b..6042280d6404 100644
--- a/drivers/clk/imx/clk-imx8mp-audiomix.c
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -7,10 +7,12 @@
#include <linux/clk-provider.h>
#include <linux/device.h>
+#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <dt-bindings/clock/imx8mp-clock.h>
@@ -18,6 +20,7 @@
#define CLKEN0 0x000
#define CLKEN1 0x004
+#define EARC 0x200
#define SAI1_MCLK_SEL 0x300
#define SAI2_MCLK_SEL 0x304
#define SAI3_MCLK_SEL 0x308
@@ -26,6 +29,12 @@
#define SAI7_MCLK_SEL 0x314
#define PDM_SEL 0x318
#define SAI_PLL_GNRL_CTL 0x400
+#define SAI_PLL_FDIVL_CTL0 0x404
+#define SAI_PLL_FDIVL_CTL1 0x408
+#define SAI_PLL_SSCG_CTL 0x40C
+#define SAI_PLL_MNIT_CTL 0x410
+#define IPG_LP_CTRL 0x504
+#define REGS_NUM 16
#define SAIn_MCLK1_PARENT(n) \
static const struct clk_parent_data \
@@ -182,13 +191,65 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
CLK_SAIn(7)
};
+struct clk_imx8mp_audiomix_regs {
+ u32 regs_num;
+ u32 regs_off[];
+};
+
+static const struct clk_imx8mp_audiomix_regs audiomix_regs = {
+ .regs_num = REGS_NUM,
+ .regs_off = {
+ CLKEN0,
+ CLKEN1,
+ EARC,
+ SAI1_MCLK_SEL,
+ SAI2_MCLK_SEL,
+ SAI3_MCLK_SEL,
+ SAI5_MCLK_SEL,
+ SAI6_MCLK_SEL,
+ SAI7_MCLK_SEL,
+ PDM_SEL,
+ SAI_PLL_GNRL_CTL,
+ SAI_PLL_FDIVL_CTL0,
+ SAI_PLL_FDIVL_CTL1,
+ SAI_PLL_SSCG_CTL,
+ SAI_PLL_MNIT_CTL,
+ IPG_LP_CTRL
+ },
+};
+
+struct clk_imx8mp_audiomix_drvdata {
+ void __iomem *base;
+ u32 regs_save[REGS_NUM];
+};
+
+static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
+{
+ struct clk_imx8mp_audiomix_drvdata *drvdata = dev_get_drvdata(dev);
+ void __iomem *base = drvdata->base;
+ int i;
+
+ if (save) {
+ for (i = 0; i < audiomix_regs.regs_num; i++)
+ drvdata->regs_save[i] = readl(base + audiomix_regs.regs_off[i]);
+ } else {
+ for (i = 0; i < audiomix_regs.regs_num; i++)
+ writel(drvdata->regs_save[i], base + audiomix_regs.regs_off[i]);
+ }
+}
+
static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
{
+ struct clk_imx8mp_audiomix_drvdata *drvdata;
struct clk_hw_onecell_data *priv;
struct device *dev = &pdev->dev;
void __iomem *base;
struct clk_hw *hw;
- int i;
+ int i, ret;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
priv = devm_kzalloc(dev,
struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
@@ -202,6 +263,18 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ drvdata->base = base;
+ dev_set_drvdata(dev, drvdata);
+
+ /*
+ * pm_runtime_enable needs to be called before clk register.
+ * That is to make core->rpm_enabled to be true for clock
+ * usage.
+ */
+ pm_runtime_get_noresume(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
for (i = 0; i < ARRAY_SIZE(sels); i++) {
if (sels[i].num_parents == 1) {
hw = devm_clk_hw_register_gate_parent_data(dev,
@@ -216,8 +289,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
0, NULL, NULL);
}
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_clk_register;
+ }
priv->hws[sels[i].clkid] = hw;
}
@@ -232,8 +307,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
base + 0x400, &imx_1443x_pll);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_clk_register;
+ }
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
hw = devm_clk_hw_register_mux_parent_data_table(dev,
@@ -241,26 +318,71 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_clk_register;
+ }
+
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
0, base + SAI_PLL_GNRL_CTL, 13,
0, NULL);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_clk_register;
+ }
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
"sai_pll_out", 0, 1, 2);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_clk_register;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+ priv);
+ if (ret)
+ goto err_clk_register;
+
+ pm_runtime_put_sync(dev);
+ return 0;
+
+err_clk_register:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+ return ret;
+}
+
+static int clk_imx8mp_audiomix_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
- return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
- priv);
+ return 0;
}
+static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
+{
+ clk_imx8mp_audiomix_save_restore(dev, true);
+
+ return 0;
+}
+
+static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
+{
+ clk_imx8mp_audiomix_save_restore(dev, false);
+
+ return 0;
+}
+
+static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
+ SET_RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
+ clk_imx8mp_audiomix_runtime_resume, NULL)
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
{ /* sentinel */ }
@@ -269,9 +391,11 @@ MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
static struct platform_driver clk_imx8mp_audiomix_driver = {
.probe = clk_imx8mp_audiomix_probe,
+ .remove = clk_imx8mp_audiomix_remove,
.driver = {
.name = "imx8mp-audio-blk-ctrl",
.of_match_table = clk_imx8mp_audiomix_of_match,
+ .pm = &clk_imx8mp_audiomix_pm_ops,
},
};
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH v2 1/2] arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3
From: Krzysztof Kozlowski @ 2024-03-20 9:24 UTC (permalink / raw)
To: Ghennadi Procopciuc, Wadim Mueller
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Jiri Slaby, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Chester Lin, Andreas Färber, Matthias Brugger,
NXP S32 Linux Team, Tim Harvey, Alexander Stein, Marek Vasut,
Gregor Herburger, Marco Felsch, Joao Paulo Goncalves,
Markus Niebel, Matthias Schiffer, Stefan Wahren, Bjorn Helgaas,
Josua Mayer, Yannic Moog, Li Yang, devicetree, linux-kernel,
linux-serial, linux-arm-kernel
In-Reply-To: <6830dee9-2378-4742-8ec4-aada9b5aba17@oss.nxp.com>
On 20/03/2024 09:24, Ghennadi Procopciuc wrote:
> On 3/20/24 09:49, Krzysztof Kozlowski wrote:
>> On 20/03/2024 08:00, Ghennadi Procopciuc wrote:
>>> On 3/20/24 00:16, Wadim Mueller wrote:
>>> [...]
>>>> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
>>>> @@ -0,0 +1,236 @@
>>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>>> +/*
>>>> + * Copyright 2021-2023 NXP
>>>> + *
>>>> + * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
>>>> + * Ciprian Costea <ciprianmarian.costea@nxp.com>
>>>> + * Andra-Teodora Ilie <andra.ilie@nxp.com>
>>>
>>> This pollutes the content of the file. Please make them part of the
>>> commit description using 'Signed-off-by' tags.
>>>
>>
>> No, that's not how process works. SoB are part of DCO and Ghennadi is
>> allowed to skip them. Just read the DCO. Don't add fake SoB tags just
>> because someone wants...
>>
>> Nothing is polluted in the file. That's what this section you have (if
>> someone wants).
>>
>
> I apologize for not getting it right earlier. After reviewing the
> information available at [0], I noticed that it suggests using
> Co-developed-by and Signed-off-by when a patch has multiple
> contributors. However, I could not find any mention of the 'Authors'
> section in the file although it seems to be a common practice.
submitting-patches describes the process, thus also patches, but not the
Linux code. Whatever is in the C/H/DTS/SH/COCCI code, is independent.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH] media: mediatek: vcodec: Handle invalid decoder vsi
From: AngeloGioacchino Del Regno @ 2024-03-20 9:13 UTC (permalink / raw)
To: Irui Wang, Hans Verkuil, Mauro Carvalho Chehab, Matthias Brugger,
Yunfei Dong, nicolas.dufresne, sebastian.fricke
Cc: Longfei Wang, Maoguang Meng, Project_Global_Chrome_Upstream_Group,
linux-media, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240320061336.2615-1-irui.wang@mediatek.com>
Il 20/03/24 07:13, Irui Wang ha scritto:
> Handle invalid decoder vsi in vpu_dec_init to ensure the decoder vsi is
> valid for future use.
>
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
This commit needs a Fixes tag, can you please add the relevant one and resend?
Thanks,
Angelo
> ---
> .../media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
> index 82e57ae983d5..17770993fe5a 100644
> --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
> +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec_vpu_if.c
> @@ -231,6 +231,12 @@ int vpu_dec_init(struct vdec_vpu_inst *vpu)
> mtk_vdec_debug(vpu->ctx, "vdec_inst=%p", vpu);
>
> err = vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg));
> +
> + if (IS_ERR_OR_NULL(vpu->vsi)) {
> + mtk_vdec_err(vpu->ctx, "invalid vdec vsi, status=%d", err);
> + return -EINVAL;
> + }
> +
> mtk_vdec_debug(vpu->ctx, "- ret=%d", err);
> return err;
> }
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* Re: [PATCH 2/4] dt-bindings: media: Add bindings for raspberrypi,rp1-cfe
From: Krzysztof Kozlowski @ 2024-03-20 9:12 UTC (permalink / raw)
To: Naushir Patuck, Tomi Valkeinen
Cc: linux-media, linux-kernel, devicetree, linux-rpi-kernel,
linux-arm-kernel, Laurent Pinchart, Sakari Ailus, Jacopo Mondi,
Kieran Bingham, Mauro Carvalho Chehab,
Raspberry Pi Kernel Maintenance, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Florian Fainelli,
Broadcom internal kernel review list
In-Reply-To: <CAEmqJPoBA4PrbvoGHtiah1B=C7WO+MODUUY0qr0ZdF2eWEB3TA@mail.gmail.com>
On 20/03/2024 09:50, Naushir Patuck wrote:
>>>>
>>>> Also, I'm still wondering about the RP1 part there in the compatible
>>>> string. Is it necessary? The CFE is located in the RP1 co-processor, but
>>>> is that relevant?
>>>>
>>>> Is there a versioning for the whole RP1 chip? Maybe it's going to the
>>>> wrong direction if we use the board/SoC for this compatible name, as
>>>> it's actually the RP1 where the CFE is located in, not the SoC.
>>>>
>>>
>>> I don't really know the conversion required to answer this one.
>>> Logically CFE is on RP1, so it makes sense to me to have "rp1" in the
>>> string, but I will follow the judgment of the maintainers.
>>
>> Well, my thinking here was that if we have a register from which to read
>> the version, and Raspberry Pi would create a new co-processor, RP2, with
>> the same CFE. Would we then have "raspberrypi,rp1-cfe" and
>> "raspberrypi,rp2-cfe", even if there are no changes?
That would follow guidelines as expressed in writing bindings.
>>Or would a plain
>> "raspberrypi,cfe" do for both?
>>
>> In other words, if we don't need the "rp1" for versioning purposes,
>> should it then be dropped?
>
> I agree with the above, you've convinced me that "raspberrypi,cfe"
> might be the more appropriate string, or a convincing argument for
> that to be a fallback string.
Just follow the guidelines. If you come up with generic compatible
alone, you could run to the same problems everyone is running.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v3 09/14] drm/mediatek: Rename files "mtk_drm_ddp_comp.c" to "mtk_ddp_comp.c"
From: AngeloGioacchino Del Regno @ 2024-03-20 9:09 UTC (permalink / raw)
To: Shawn Sung, Chun-Kuang Hu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Matthias Brugger,
Sumit Semwal, Christian König, dri-devel, linux-mediatek,
linux-kernel, linux-arm-kernel, linux-media, linaro-mm-sig,
Hsiao Chien Sung
In-Reply-To: <20240320024222.14234-10-shawn.sung@mediatek.com>
Il 20/03/24 03:42, Shawn Sung ha scritto:
> From: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
>
> Rename files mtk_drm_ddp_comp.c to mtk_ddp_comp.c and
> modify the Makefile accordingly.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply
* Re: [PATCH v3 07/14] drm/mediatek: Rename files "mtk_drm_crtc.c" to "mtk_crtc.c"
From: AngeloGioacchino Del Regno @ 2024-03-20 9:08 UTC (permalink / raw)
To: Shawn Sung, Chun-Kuang Hu
Cc: Philipp Zabel, David Airlie, Daniel Vetter, Matthias Brugger,
Sumit Semwal, Christian König, dri-devel, linux-mediatek,
linux-kernel, linux-arm-kernel, linux-media, linaro-mm-sig,
Hsiao Chien Sung
In-Reply-To: <20240320024222.14234-8-shawn.sung@mediatek.com>
Il 20/03/24 03:42, Shawn Sung ha scritto:
> From: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
>
> Rename files mtk_drm_crtc.c to mtk_crtc.c and
> modify the Makefile accordingly.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.corp-partner.google.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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