* RE: [PATCH] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
From: Hongxing Zhu @ 2024-03-22 8:01 UTC (permalink / raw)
To: Frank Li
Cc: l.stach@pengutronix.de, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, marex@denx.de,
manivannan.sadhasivam@linaro.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de, dl-linux-imx
In-Reply-To: <ZfyBDBGizGwiQvgs@lizhi-Precision-Tower-5810>
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2024年3月22日 2:49
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: l.stach@pengutronix.de; bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> marex@denx.de; manivannan.sadhasivam@linaro.org; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH] PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
>
> On Wed, Mar 20, 2024 at 11:45:38AM +0800, Richard Zhu wrote:
> > Fix i.MX8MP PCIe EP can't trigger MSI issue.
> > There is one 64Kbytes minimal requirement on i.MX8M PCIe outbound
> > region configuration.
> >
> > EP uses Bar0 to set the outboud region to configure the MSI setting.
> > Set the page_size to "epc_features->align" to meet the requirement,
> > let the MSI can be triggered successfully.
> >
> > Fixes: 1bd0d43dcf3b ("PCI: imx6: Clean up addr_space retrieval code")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <frank.li@nxp.com>
> > Acked-by: Jason Liu <jason.hui.liu@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 99a60270b26c..3238b63721bc 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1013,9 +1013,14 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep
> > *ep) {
> > enum pci_barno bar;
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + const struct pci_epc_features *epc_features;
> >
> > for (bar = BAR_0; bar <= BAR_5; bar++)
> > dw_pcie_ep_reset_bar(pci, bar);
> > + if (ep->ops->get_features) {
> > + epc_features = ep->ops->get_features(ep);
> > + ep->page_size = epc_features->align;
> > + }
>
> I suggest in imx6_add_pcie_ep()
>
> ep->page_size = imx_pcie->drvdata->epc_features->aglgin;
>
> it should be set before call dw_pcie_ep_init().
>
> If you like, I can add this fixed to my patch serial to avoid conflict
> https://lore.kernel.org/linux-pci/Zfm720fz9NE0fD%2FP@lizhi-Precision-Tower-5
> 810/T/#t
>
Thanks, I'm fine and glad about that.
Best Regards
Richard Zhu
> Frank
>
> > }
> >
> > static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > --
> > 2.37.1
> >
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^ permalink raw reply
* [PATCH V2] firmware: arm_scmi: perf: print domain name in error path
From: Peng Fan (OSS) @ 2024-03-22 8:05 UTC (permalink / raw)
To: sudeep.holla, cristian.marussi; +Cc: linux-arm-kernel, linux-kernel, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
It would be easier to locate the problem if domain name is printed out.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V2:
Update extra two places
drivers/firmware/arm_scmi/perf.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c
index 345fff167b52..c36a390bba60 100644
--- a/drivers/firmware/arm_scmi/perf.c
+++ b/drivers/firmware/arm_scmi/perf.c
@@ -387,8 +387,8 @@ process_response_opp(struct device *dev, struct perf_dom_info *dom,
ret = xa_insert(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL);
if (ret)
- dev_warn(dev, "Failed to add opps_by_lvl at %d - ret:%d\n",
- opp->perf, ret);
+ dev_warn(dev, "Failed to add opps_by_lvl at %d for %s- ret:%d\n",
+ opp->perf, dom->info.name, ret);
}
static inline void
@@ -405,8 +405,8 @@ process_response_opp_v4(struct device *dev, struct perf_dom_info *dom,
ret = xa_insert(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL);
if (ret)
- dev_warn(dev, "Failed to add opps_by_lvl at %d - ret:%d\n",
- opp->perf, ret);
+ dev_warn(dev, "Failed to add opps_by_lvl at %d for %s - ret:%d\n",
+ opp->perf, dom->info.name, ret);
/* Note that PERF v4 reports always five 32-bit words */
opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq);
@@ -417,8 +417,8 @@ process_response_opp_v4(struct device *dev, struct perf_dom_info *dom,
GFP_KERNEL);
if (ret)
dev_warn(dev,
- "Failed to add opps_by_idx at %d - ret:%d\n",
- opp->level_index, ret);
+ "Failed to add opps_by_idx at %d for %s - ret:%d\n",
+ opp->level_index, dom->info.name, ret);
hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq);
}
@@ -879,7 +879,8 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph,
ret = dev_pm_opp_add_dynamic(dev, &data);
if (ret) {
- dev_warn(dev, "failed to add opp %luHz\n", freq);
+ dev_warn(dev, "[%d][%s]: Failed to add OPP[%d] %lu\n",
+ domain, dom->info.name, idx, freq);
dev_pm_opp_remove_all_dynamic(dev);
return ret;
}
--
2.37.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v8 7/8] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
Add JSON metrics for i.MX95 DDR Performance Monitor.
Reviewed-by: John Garry <john.g.garry@oracle.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- fix wrong AXI_MASK setting
- remove unnecessary metrics
- add bandwidth_usage, camera_all, disp_all metrics
Changes in v3:
- no changes
Changes in v4:
- add Reviewed-by tag
Changes in v5:
- fix typo
Changes in v6:
- remove "counter=X" from each metric
Changes in v7:
- add RB tag
Changes in v8:
- no changes
---
.../arch/arm64/freescale/imx95/sys/ddrc.json | 9 +
.../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++
tools/perf/pmu-events/jevents.py | 1 +
3 files changed, 788 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
new file mode 100644
index 000000000000..4dc9d2968bdc
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json
@@ -0,0 +1,9 @@
+[
+ {
+ "BriefDescription": "ddr cycles event",
+ "EventCode": "0x00",
+ "EventName": "imx95_ddr.cycles",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
new file mode 100644
index 000000000000..a3ae787d448c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json
@@ -0,0 +1,778 @@
+[
+ {
+ "BriefDescription": "bandwidth usage for lpddr5 evk board",
+ "MetricName": "imx95_bandwidth_usage.lpddr5",
+ "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)",
+ "ScaleUnit": "1e2%",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all masters read from ddr",
+ "MetricName": "imx95_ddr_read.all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all masters write to ddr",
+ "MetricName": "imx95_ddr_write.all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.a55_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all a55 write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.a55_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 0 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 0 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 1 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 1 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 2 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 2 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 3 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 3 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 4 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 4 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 5 read from ddr",
+ "MetricName": "imx95_ddr_read.a55_5",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of a55 core 5 write to ddr",
+ "MetricName": "imx95_ddr_write.a55_5",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr",
+ "MetricName": "imx95_ddr_read.cortexa_dsu_l3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr",
+ "MetricName": "imx95_ddr_write.cortexa_dsu_l3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m33 read from ddr",
+ "MetricName": "imx95_ddr_read.m33",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m33 write to ddr",
+ "MetricName": "imx95_ddr_write.m33",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m7 read from ddr",
+ "MetricName": "imx95_ddr_read.m7",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of m7 write to ddr",
+ "MetricName": "imx95_ddr_write.m7",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of sentinel read from ddr",
+ "MetricName": "imx95_ddr_read.sentinel",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of sentinel write to ddr",
+ "MetricName": "imx95_ddr_write.sentinel",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma1 read from ddr",
+ "MetricName": "imx95_ddr_read.edma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma1 write to ddr",
+ "MetricName": "imx95_ddr_write.edma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma2 read from ddr",
+ "MetricName": "imx95_ddr_read.edma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of edma2 write to ddr",
+ "MetricName": "imx95_ddr_write.edma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of netc read from ddr",
+ "MetricName": "imx95_ddr_read.netc",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of netc write to ddr",
+ "MetricName": "imx95_ddr_write.netc",
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+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of npu read from ddr",
+ "MetricName": "imx95_ddr_read.npu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of npu write to ddr",
+ "MetricName": "imx95_ddr_write.npu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of gpu read from ddr",
+ "MetricName": "imx95_ddr_read.gpu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of gpu write to ddr",
+ "MetricName": "imx95_ddr_write.gpu",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc1 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of usdhc1 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc1",
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+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc2 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of usdhc2 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usdhc3 read from ddr",
+ "MetricName": "imx95_ddr_read.usdhc3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of usdhc3 write to ddr",
+ "MetricName": "imx95_ddr_write.usdhc3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of xspi read from ddr",
+ "MetricName": "imx95_ddr_read.xspi",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of xspi write to ddr",
+ "MetricName": "imx95_ddr_write.xspi",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie1 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie1 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie2 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie2 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
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+ "MetricName": "imx95_ddr_read.pcie3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie3 write to ddr",
+ "MetricName": "imx95_ddr_write.pcie3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of pcie4 read from ddr",
+ "MetricName": "imx95_ddr_read.pcie4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
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+ "Compat": "imx95"
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+ {
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+ "MetricName": "imx95_ddr_write.pcie4",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb1 read from ddr",
+ "MetricName": "imx95_ddr_read.usb1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb1 write to ddr",
+ "MetricName": "imx95_ddr_write.usb1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb2 read from ddr",
+ "MetricName": "imx95_ddr_read.usb2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of usb2 write to ddr",
+ "MetricName": "imx95_ddr_write.usb2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec primary bus read from ddr",
+ "MetricName": "imx95_ddr_read.vpu_primy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
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+ "Compat": "imx95"
+ },
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+ "MetricName": "imx95_ddr_write.vpu_primy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec secondary bus read from ddr",
+ "MetricName": "imx95_ddr_read.vpu_secndy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
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+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of vpu codec secondary bus write to ddr",
+ "MetricName": "imx95_ddr_write.vpu_secndy",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of jpeg decoder read from ddr",
+ "MetricName": "imx95_ddr_read.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
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+ {
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+ "MetricName": "imx95_ddr_write.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32",
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+ "Compat": "imx95"
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+ {
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+ "MetricName": "imx95_ddr_read.jpeg_dec",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
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+ "MetricName": "imx95_ddr_write.jpeg_enc",
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+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
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+ "MetricName": "imx95_ddr_read.vpu_all",
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+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of all vpu submodules write to ddr",
+ "MetricName": "imx95_ddr_write.vpu_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of cortex m0+ read from ddr",
+ "MetricName": "imx95_ddr_read.m0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of cortex m0+ write to ddr",
+ "MetricName": "imx95_ddr_write.m0",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of camera edma read from ddr",
+ "MetricName": "imx95_ddr_read.camera_edma",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of camera edma write to ddr",
+ "MetricName": "imx95_ddr_write.camera_edma",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi rd read from ddr",
+ "MetricName": "imx95_ddr_read.isi_rd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi rd write to ddr",
+ "MetricName": "imx95_ddr_write.isi_rd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr y read from ddr",
+ "MetricName": "imx95_ddr_read.isi_wr_y",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
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+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr y write to ddr",
+ "MetricName": "imx95_ddr_write.isi_wr_y",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isi wr u read from ddr",
+ "MetricName": "imx95_ddr_read.isi_wr_u",
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+ "Compat": "imx95"
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+ "Compat": "imx95"
+ },
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+ "Compat": "imx95"
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+ {
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+ "MetricName": "imx95_ddr_write.isi_wr_v",
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+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp input dma1 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_in_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp input dma1 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_in_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp input dma2 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_in_dma2",
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+ "ScaleUnit": "9.765625e-4KB",
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+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp input dma2 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_in_dma2",
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+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp output dma1 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_out_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp output dma1 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_out_dma1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of isp output dma2 read from ddr",
+ "MetricName": "imx95_ddr_read.isp_out_dma2",
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+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
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+ {
+ "BriefDescription": "bytes of isp output dma2 write to ddr",
+ "MetricName": "imx95_ddr_write.isp_out_dma2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules read from ddr",
+ "MetricName": "imx95_ddr_read.camera_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.camera_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.camera_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all camera submodules write to ddr (part3)",
+ "MetricName": "imx95_ddr_write.camera_all_3",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display blitter store read from ddr",
+ "MetricName": "imx95_ddr_read.disp_blit",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display blitter write to ddr",
+ "MetricName": "imx95_ddr_write.disp_blit",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display command sequencer read from ddr",
+ "MetricName": "imx95_ddr_read.disp_cmd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of display command sequencer write to ddr",
+ "MetricName": "imx95_ddr_write.disp_cmd",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules read from ddr",
+ "MetricName": "imx95_ddr_read.disp_all",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules write to ddr (part1)",
+ "MetricName": "imx95_ddr_write.disp_all_1",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ },
+ {
+ "BriefDescription": "bytes of all display submodules write to ddr (part2)",
+ "MetricName": "imx95_ddr_write.disp_all_2",
+ "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx95"
+ }
+]
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index e42efc16723e..ac9b7ca41856 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -284,6 +284,7 @@ class JsonEvent:
'hisi_sccl,hha': 'hisi_sccl,hha',
'hisi_sccl,l3c': 'hisi_sccl,l3c',
'imx8_ddr': 'imx8_ddr',
+ 'imx9_ddr': 'imx9_ddr',
'L3PMC': 'amd_l3',
'DFPMC': 'amd_df',
'UMCPMC': 'amd_umc',
--
2.34.1
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* [PATCH v8 6/8] perf: imx_perf: add support for i.MX95 platform
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
read beat and write beat filter capabilities. This will add support for
i.MX95 and enhance the driver to support specific filter handling for it.
Usage:
For read beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,axi_mask=ID_MASK,axi_id=ID/
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,axi_mask=0x00f,axi_id=0x00c/
For write beat:
~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=ID_MASK,axi_id=ID/
eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,axi_mask=0x00f,axi_id=0x00c/
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- put soc spefific axi filter events to drvdata according
to franks suggestions.
- adjust pmcfg axi_id and axi_mask config
Changes in v3:
- no changes
Changes in v4:
- only contain imx95 parts
Changes in v5:
- improve imx95_ddr_perf_monitor_config()
- use write_relaxed to pair read_relaxed
Changes in v6:
- no changes
Changes in v7:
- no changes
Changes in v8:
- add definition IMX95_DDR_PMU_EVENT_ATTR
---
drivers/perf/fsl_imx9_ddr_perf.c | 89 ++++++++++++++++++++++++++++++--
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index fab6596d3e28..9dcab4192d6e 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -17,9 +17,19 @@
#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
+#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31)
+#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30)
+
#define PMCFG2 0x04
#define MX93_PMCFG2_ID GENMASK(17, 0)
+#define PMCFG3 0x08
+#define PMCFG4 0x0C
+#define PMCFG5 0x10
+#define PMCFG6 0x14
+#define MX95_PMCFG_ID_MASK GENMASK(9, 0)
+#define MX95_PMCFG_ID GENMASK(25, 16)
+
/* Global control register affects all counters and takes priority over local control registers */
#define PMGC0 0x40
/* Global control register bits */
@@ -76,13 +86,23 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = {
.identifier = "imx93",
};
+static const struct imx_ddr_devtype_data imx95_devtype_data = {
+ .identifier = "imx95",
+};
+
static inline bool is_imx93(struct ddr_pmu *pmu)
{
return pmu->devtype_data == &imx93_devtype_data;
}
+static inline bool is_imx95(struct ddr_pmu *pmu)
+{
+ return pmu->devtype_data == &imx95_devtype_data;
+}
+
static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
- {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
+ { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
+ { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
@@ -158,6 +178,9 @@ static ssize_t ddr_pmu_event_show(struct device *dev,
#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
+#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \
+ DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data)
+
static struct attribute *ddr_perf_events_attrs[] = {
/* counter0 cycles event */
IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
@@ -204,6 +227,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
+ IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/
/* counter3 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
@@ -216,6 +240,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
+ IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/
/* counter4 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
@@ -228,6 +253,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
+ IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/
/* counter5 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
@@ -239,6 +265,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)),
+ IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/
/* counter6 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)),
@@ -430,6 +457,57 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
writel_relaxed(pmcfg2, pmu->base + PMCFG2);
}
+static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
+ int counter, int axi_id, int axi_mask)
+{
+ u32 pmcfg1, pmcfg, offset = 0;
+
+ pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
+
+ if (event == 73) {
+ switch (counter) {
+ case 2:
+ pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN;
+ offset = PMCFG3;
+ break;
+ case 3:
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG4;
+ break;
+ case 4:
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG5;
+ break;
+ case 5:
+ pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN;
+ offset = PMCFG6;
+ break;
+ }
+ } else {
+ switch (counter) {
+ case 2:
+ pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN;
+ break;
+ case 3:
+ case 4:
+ case 5:
+ pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN;
+ break;
+ }
+ }
+
+ writel_relaxed(pmcfg1, pmu->base + PMCFG1);
+
+ if (offset) {
+ pmcfg = readl_relaxed(pmu->base + offset);
+ pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
+ FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
+ pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) |
+ FIELD_PREP(MX95_PMCFG_ID, axi_id));
+ writel_relaxed(pmcfg, pmu->base + offset);
+ }
+}
+
static void ddr_perf_event_update(struct perf_event *event)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -539,8 +617,13 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
- /* read trans, write trans, read beat */
- imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
+ if (is_imx93(pmu))
+ /* read trans, write trans, read beat */
+ imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
+
+ if (is_imx95(pmu))
+ /* write beat, read beat2, read beat1, read beat */
+ imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
if (flags & PERF_EF_START)
ddr_perf_event_start(event, flags);
--
2.34.1
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^ permalink raw reply related
* [PATCH v8 5/8] perf: imx_perf: fix counter start and config sequence
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.
Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: <stable@vger.kernel.org>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v5:
- new patch
Changes in v6:
- no changes
Changes in v7:
- no changes
Changes in v8:
- add fix tag
---
drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 011377c01dea..fab6596d3e28 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -539,12 +539,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- ddr_perf_event_start(event, flags);
-
/* read trans, write trans, read beat */
imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
+ if (flags & PERF_EF_START)
+ ddr_perf_event_start(event, flags);
+
return 0;
}
--
2.34.1
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^ permalink raw reply related
* Re: [RFC PATCH v3 1/5] arm64: mm: swap: support THP_SWAP on hardware with MTE
From: Barry Song @ 2024-03-22 7:41 UTC (permalink / raw)
To: Ryan Roberts
Cc: akpm, linux-mm, chengming.zhou, chrisl, david, hannes, kasong,
linux-arm-kernel, linux-kernel, mhocko, nphamcs, shy828301,
steven.price, surenb, wangkefeng.wang, willy, xiang, ying.huang,
yosryahmed, yuzhao, Barry Song, Catalin Marinas, Will Deacon,
Mark Rutland, Kemeng Shi, Anshuman Khandual, Peter Collingbourne,
Peter Xu, Lorenzo Stoakes, Mike Rapoport (IBM), Hugh Dickins,
Aneesh Kumar K.V, Rick Edgecombe
In-Reply-To: <CAGsJ_4zT5YCkSLthCGDe5t3B4dR2syJa_MA3ytZ3YmSCERn_TQ@mail.gmail.com>
On Fri, Mar 22, 2024 at 3:51 PM Barry Song <21cnbao@gmail.com> wrote:
>
> On Thu, Mar 21, 2024 at 11:31 PM Ryan Roberts <ryan.roberts@arm.com> wrote:
> >
> > On 21/03/2024 08:42, Barry Song wrote:
> > > Hi Ryan,
> > > Sorry for the late reply.
> >
> > No problem!
> >
> > >
> > > On Tue, Mar 12, 2024 at 5:56 AM Ryan Roberts <ryan.roberts@arm.com> wrote:
> > >>
> > >> On 04/03/2024 08:13, Barry Song wrote:
> > >>> From: Barry Song <v-songbaohua@oppo.com>
> > >>>
> > >>> Commit d0637c505f8a1 ("arm64: enable THP_SWAP for arm64") brings up
> > >>> THP_SWAP on ARM64, but it doesn't enable THP_SWP on hardware with
> > >>> MTE as the MTE code works with the assumption tags save/restore is
> > >>> always handling a folio with only one page.
> > >>>
> > >>> The limitation should be removed as more and more ARM64 SoCs have
> > >>> this feature. Co-existence of MTE and THP_SWAP becomes more and
> > >>> more important.
> > >>>
> > >>> This patch makes MTE tags saving support large folios, then we don't
> > >>> need to split large folios into base pages for swapping out on ARM64
> > >>> SoCs with MTE any more.
> > >>>
> > >>> arch_prepare_to_swap() should take folio rather than page as parameter
> > >>> because we support THP swap-out as a whole. It saves tags for all
> > >>> pages in a large folio.
> > >>>
> > >>> As now we are restoring tags based-on folio, in arch_swap_restore(),
> > >>> we may increase some extra loops and early-exitings while refaulting
> > >>> a large folio which is still in swapcache in do_swap_page(). In case
> > >>> a large folio has nr pages, do_swap_page() will only set the PTE of
> > >>> the particular page which is causing the page fault.
> > >>> Thus do_swap_page() runs nr times, and each time, arch_swap_restore()
> > >>> will loop nr times for those subpages in the folio. So right now the
> > >>> algorithmic complexity becomes O(nr^2).
> > >>>
> > >>> Once we support mapping large folios in do_swap_page(), extra loops
> > >>> and early-exitings will decrease while not being completely removed
> > >>> as a large folio might get partially tagged in corner cases such as,
> > >>> 1. a large folio in swapcache can be partially unmapped, thus, MTE
> > >>> tags for the unmapped pages will be invalidated;
> > >>> 2. users might use mprotect() to set MTEs on a part of a large folio.
> > >>>
> > >>> arch_thp_swp_supported() is dropped since ARM64 MTE was the only one
> > >>> who needed it.
> >
> > I think we should decouple this patch from your swap-in series. I suspect this
> > one could be ready and go in sooner than the swap-in series based on the current
> > discussions :)
> >
> > >>>
> > >>> Cc: Catalin Marinas <catalin.marinas@arm.com>
> > >>> Cc: Will Deacon <will@kernel.org>
> > >>> Cc: Ryan Roberts <ryan.roberts@arm.com>
> > >>> Cc: Mark Rutland <mark.rutland@arm.com>
> > >>> Cc: David Hildenbrand <david@redhat.com>
> > >>> Cc: Kemeng Shi <shikemeng@huaweicloud.com>
> > >>> Cc: "Matthew Wilcox (Oracle)" <willy@infradead.org>
> > >>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> > >>> Cc: Peter Collingbourne <pcc@google.com>
> > >>> Cc: Steven Price <steven.price@arm.com>
> > >>> Cc: Yosry Ahmed <yosryahmed@google.com>
> > >>> Cc: Peter Xu <peterx@redhat.com>
> > >>> Cc: Lorenzo Stoakes <lstoakes@gmail.com>
> > >>> Cc: "Mike Rapoport (IBM)" <rppt@kernel.org>
> > >>> Cc: Hugh Dickins <hughd@google.com>
> > >>> CC: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
> > >>> Cc: Rick Edgecombe <rick.p.edgecombe@intel.com>
> > >>> Signed-off-by: Barry Song <v-songbaohua@oppo.com>
> > >>> Reviewed-by: Steven Price <steven.price@arm.com>
> > >>> Acked-by: Chris Li <chrisl@kernel.org>
> > >>> ---
> > >>> arch/arm64/include/asm/pgtable.h | 19 ++------------
> > >>> arch/arm64/mm/mteswap.c | 43 ++++++++++++++++++++++++++++++++
> > >>> include/linux/huge_mm.h | 12 ---------
> > >>> include/linux/pgtable.h | 2 +-
> > >>> mm/page_io.c | 2 +-
> > >>> mm/swap_slots.c | 2 +-
> > >>> 6 files changed, 48 insertions(+), 32 deletions(-)
> > >>>
> > >>> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> > >>> index 401087e8a43d..7a54750770b8 100644
> > >>> --- a/arch/arm64/include/asm/pgtable.h
> > >>> +++ b/arch/arm64/include/asm/pgtable.h
> > >>> @@ -45,12 +45,6 @@
> > >>> __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
> > >>> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
> > >>>
> > >>> -static inline bool arch_thp_swp_supported(void)
> > >>> -{
> > >>> - return !system_supports_mte();
> > >>> -}
> > >>> -#define arch_thp_swp_supported arch_thp_swp_supported
> > >>> -
> > >>> /*
> > >>> * Outside of a few very special situations (e.g. hibernation), we always
> > >>> * use broadcast TLB invalidation instructions, therefore a spurious page
> > >>> @@ -1095,12 +1089,7 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
> > >>> #ifdef CONFIG_ARM64_MTE
> > >>>
> > >>> #define __HAVE_ARCH_PREPARE_TO_SWAP
> > >>> -static inline int arch_prepare_to_swap(struct page *page)
> > >>> -{
> > >>> - if (system_supports_mte())
> > >>> - return mte_save_tags(page);
> > >>> - return 0;
> > >>> -}
> > >>> +extern int arch_prepare_to_swap(struct folio *folio);
> > >>>
> > >>> #define __HAVE_ARCH_SWAP_INVALIDATE
> > >>> static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
> > >>> @@ -1116,11 +1105,7 @@ static inline void arch_swap_invalidate_area(int type)
> > >>> }
> > >>>
> > >>> #define __HAVE_ARCH_SWAP_RESTORE
> > >>> -static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
> > >>> -{
> > >>> - if (system_supports_mte())
> > >>> - mte_restore_tags(entry, &folio->page);
> > >>> -}
> > >>> +extern void arch_swap_restore(swp_entry_t entry, struct folio *folio);
> > >>>
> > >>> #endif /* CONFIG_ARM64_MTE */
> > >>>
> > >>> diff --git a/arch/arm64/mm/mteswap.c b/arch/arm64/mm/mteswap.c
> > >>> index a31833e3ddc5..295836fef620 100644
> > >>> --- a/arch/arm64/mm/mteswap.c
> > >>> +++ b/arch/arm64/mm/mteswap.c
> > >>> @@ -68,6 +68,13 @@ void mte_invalidate_tags(int type, pgoff_t offset)
> > >>> mte_free_tag_storage(tags);
> > >>> }
> > >>>
> > >>> +static inline void __mte_invalidate_tags(struct page *page)
> > >>> +{
> > >>> + swp_entry_t entry = page_swap_entry(page);
> > >>> +
> > >>> + mte_invalidate_tags(swp_type(entry), swp_offset(entry));
> > >>> +}
> > >>> +
> > >>> void mte_invalidate_tags_area(int type)
> > >>> {
> > >>> swp_entry_t entry = swp_entry(type, 0);
> > >>> @@ -83,3 +90,39 @@ void mte_invalidate_tags_area(int type)
> > >>> }
> > >>> xa_unlock(&mte_pages);
> > >>> }
> > >>> +
> > >>> +int arch_prepare_to_swap(struct folio *folio)
> > >>> +{
> > >>> + long i, nr;
> > >>> + int err;
> > >>> +
> > >>> + if (!system_supports_mte())
> > >>> + return 0;
> > >>> +
> > >>> + nr = folio_nr_pages(folio);
> > >>> +
> > >>> + for (i = 0; i < nr; i++) {
> > >>> + err = mte_save_tags(folio_page(folio, i));
> > >>> + if (err)
> > >>> + goto out;
> > >>> + }
> > >>> + return 0;
> > >>> +
> > >>> +out:
> > >>> + while (i--)
> > >>> + __mte_invalidate_tags(folio_page(folio, i));
> > >>> + return err;
> > >>> +}
> > >>> +
> > >>> +void arch_swap_restore(swp_entry_t entry, struct folio *folio)
> > >>
> > >> I'm still not a fan of the fact that entry could be anywhere within folio.
> > >>
> > >>> +{
> > >>> + if (system_supports_mte()) {
> > >>
> > >> nit: if you do:
> > >>
> > >> if (!system_supports_mte())
> > >> return;
> > >
> > > Acked
> > >
> > >>
> > >> It will be consistent with arch_prepare_to_swap() and reduce the indentation of
> > >> the main body.
> > >>
> > >>> + long i, nr = folio_nr_pages(folio);
> > >>> +
> > >>> + entry.val -= swp_offset(entry) & (nr - 1);
> > >>
> > >> This assumes that folios are always stored in swap with natural alignment. Is
> > >> that definitely a safe assumption? My swap-out series is currently ensuring that
> > >> folios are swapped-out naturally aligned, but that is an implementation detail.
> > >>
> > >
> > > I concur that this is an implementation detail. However, we should be
> > > bold enough
> > > to state that swap slots will be contiguous, considering we are
> > > currently utilizing
> > > folio->swap instead of subpage->swap ?
> >
> > Yes, I agree about contiguity. My objection is about assuming natural alignment
> > though. It can still be contiguous while not naturally aligned in swap.
>
> Hi Ryan,
>
> While working on the new version of this patch, I've come to recognize
> that, for the time being, it's
> imperative to maintain a natural alignment. The following code
> operates on the basis of this
> assumption.
>
> /**
> * folio_file_page - The page for a particular index.
> * @folio: The folio which contains this index.
> * @index: The index we want to look up.
> *
> * Sometimes after looking up a folio in the page cache, we need to
> * obtain the specific page for an index (eg a page fault).
> *
> * Return: The page containing the file data for this index.
> */
> static inline struct page *folio_file_page(struct folio *folio, pgoff_t index)
> {
> return folio_page(folio, index & (folio_nr_pages(folio) - 1));
> }
>
>
> It's invoked everywhere, particularly within do_swap_page(). Nonetheless,
> I remain confident that I can consistently pass the first entry to
> arch_swap_restore().
After grappling for a couple of hours, I've realized that the only
viable approach
is as follows: shifting the task of obtaining the first entry from the
callee to the
callers( looks silly). This is necessary due to various scenarios like
swap cache,
non-swap cache, and KSM, each presenting different cases. Since there's no
assurance of folio->swap being present, forcibly setting folio->swap could pose
risks (There might not even be any risk involved, but the associated
task getting
the first entry still cannot be overlooked by callers).
diff --git a/mm/internal.h b/mm/internal.h
index 7e486f2c502c..94d5b4b5a5da 100644
--- a/mm/internal.h
+++ b/mm/internal.h
@@ -76,6 +76,20 @@ static inline int folio_nr_pages_mapped(struct folio *folio)
return atomic_read(&folio->_nr_pages_mapped) & FOLIO_PAGES_MAPPED;
}
+/*
+ * Retrieve the first entry of a folio based on a provided entry within the
+ * folio. We cannot rely on folio->swap as there is no guarantee that it has
+ * been initialized. Used by arch_swap_restore()
+ */
+static inline swp_entry_t folio_swap(swp_entry_t entry, struct folio *folio)
+{
+ swp_entry_t swap = {
+ .val = entry.val & (folio_nr_pages(folio) - 1),
+ };
+
+ return swap;
+}
+
static inline void *folio_raw_mapping(struct folio *folio)
{
unsigned long mapping = (unsigned long)folio->mapping;
diff --git a/mm/memory.c b/mm/memory.c
index f2bc6dd15eb8..b7cab8be8632 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -4188,7 +4188,7 @@ vm_fault_t do_swap_page(struct vm_fault *vmf)
* when reading from swap. This metadata may be indexed by swap entry
* so this must be called before swap_free().
*/
- arch_swap_restore(entry, folio);
+ arch_swap_restore(folio_swap(entry, folio), folio);
/*
* Remove the swap entry and conditionally try to free up the swapcache.
diff --git a/mm/shmem.c b/mm/shmem.c
index 0aad0d9a621b..82c9df4628f2 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -1913,7 +1913,7 @@ static int shmem_swapin_folio(struct inode
*inode, pgoff_t index,
* Some architectures may have to restore extra metadata to the
* folio after reading from swap.
*/
- arch_swap_restore(swap, folio);
+ arch_swap_restore(folio_swap(entry, folio), folio);
if (shmem_should_replace_folio(folio, gfp)) {
error = shmem_replace_folio(&folio, gfp, info, index);
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 4919423cce76..5e6d2304a2a4 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -1806,7 +1806,7 @@ static int unuse_pte(struct vm_area_struct *vma,
pmd_t *pmd,
* when reading from swap. This metadata may be indexed by swap entry
* so this must be called before swap_free().
*/
- arch_swap_restore(entry, folio);
+ arch_swap_restore(folio_swap(entry, folio), folio);
dec_mm_counter(vma->vm_mm, MM_SWAPENTS);
inc_mm_counter(vma->vm_mm, MM_ANONPAGES);
Meanwhile, natural alignment is essential even during the execution of
add_to_swap(), as failure to
do so will trigger the VM_BUG_ON condition below.
int add_to_swap_cache(struct folio *folio, swp_entry_t entry,
gfp_t gfp, void **shadowp)
{
struct address_space *address_space = swap_address_space(entry);
pgoff_t idx = swp_offset(entry);
XA_STATE_ORDER(xas, &address_space->i_pages, idx, folio_order(folio));
unsigned long i, nr = folio_nr_pages(folio);
...
folio_set_swapcache(folio);
folio->swap = entry;
do {
xas_lock_irq(&xas);
xas_create_range(&xas);
if (xas_error(&xas))
goto unlock;
for (i = 0; i < nr; i++) {
VM_BUG_ON_FOLIO(xas.xa_index != idx + i, folio);
if (shadowp) {
old = xas_load(&xas);
if (xa_is_value(old))
*shadowp = old;
}
xas_store(&xas, folio);
xas_next(&xas);
}
}
Based on the information provided, Ryan, would it be feasible to retain the task
of obtaining the first entry within the callee? Or, are you in favor
of utilizing the
new folio_swap() helper?
>
> >
> > >
> > >> Your cover note for swap-in says that you could technically swap in a large
> > >> folio without it having been swapped-out large. If you chose to do that in
> > >> future, this would break, right? I don't think it's good to couple the swap
> > >
> > > Right. technically I agree. Given that we still have many tasks involving even
> > > swapping in contiguous swap slots, it's unlikely that swapping in large folios
> > > for non-contiguous entries will occur in the foreseeable future :-)
> > >
> > >> storage layout to the folio order that you want to swap into. Perhaps that's an
> > >> argument for passing each *page* to this function with its exact, corresponding
> > >> swap entry?
> > >
> > > I recall Matthew Wilcox strongly objected to using "page" as the
> > > parameter, so I've
> > > discarded that approach. Alternatively, it appears I can consistently pass
> > > folio->swap to this function and ensure the function always retrieves
> > > the first entry?
> >
> > Yes, if we must pass a folio here, I'd prefer that entry always corresponds to
> > the first entry for the folio. That will remove the need for this function to do
> > the alignment above too. So win-win.
> >
> > >
> > >>
> > >>> + for (i = 0; i < nr; i++) {
> > >>> + mte_restore_tags(entry, folio_page(folio, i));
> > >>> + entry.val++;
> > >>> + }
> > >>> + }
> > >>> +}
> > >>> diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
> > >>> index de0c89105076..e04b93c43965 100644
> > >>> --- a/include/linux/huge_mm.h
> > >>> +++ b/include/linux/huge_mm.h
> > >>> @@ -535,16 +535,4 @@ static inline int split_folio_to_order(struct folio *folio, int new_order)
> > >>> #define split_folio_to_list(f, l) split_folio_to_list_to_order(f, l, 0)
> > >>> #define split_folio(f) split_folio_to_order(f, 0)
> > >>>
> > >>> -/*
> > >>> - * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to
> > >>> - * limitations in the implementation like arm64 MTE can override this to
> > >>> - * false
> > >>> - */
> > >>> -#ifndef arch_thp_swp_supported
> > >>> -static inline bool arch_thp_swp_supported(void)
> > >>> -{
> > >>> - return true;
> > >>> -}
> > >>> -#endif
> > >>> -
> > >>> #endif /* _LINUX_HUGE_MM_H */
> > >>> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
> > >>> index e1b22903f709..bfcfe3386934 100644
> > >>> --- a/include/linux/pgtable.h
> > >>> +++ b/include/linux/pgtable.h
> > >>> @@ -1106,7 +1106,7 @@ static inline int arch_unmap_one(struct mm_struct *mm,
> > >>> * prototypes must be defined in the arch-specific asm/pgtable.h file.
> > >>> */
> > >>> #ifndef __HAVE_ARCH_PREPARE_TO_SWAP
> > >>> -static inline int arch_prepare_to_swap(struct page *page)
> > >>> +static inline int arch_prepare_to_swap(struct folio *folio)
> > >>> {
> > >>> return 0;
> > >>> }
> > >>> diff --git a/mm/page_io.c b/mm/page_io.c
> > >>> index ae2b49055e43..a9a7c236aecc 100644
> > >>> --- a/mm/page_io.c
> > >>> +++ b/mm/page_io.c
> > >>> @@ -189,7 +189,7 @@ int swap_writepage(struct page *page, struct writeback_control *wbc)
> > >>> * Arch code may have to preserve more data than just the page
> > >>> * contents, e.g. memory tags.
> > >>> */
> > >>> - ret = arch_prepare_to_swap(&folio->page);
> > >>> + ret = arch_prepare_to_swap(folio);
> > >>> if (ret) {
> > >>> folio_mark_dirty(folio);
> > >>> folio_unlock(folio);
> > >>> diff --git a/mm/swap_slots.c b/mm/swap_slots.c
> > >>> index 90973ce7881d..53abeaf1371d 100644
> > >>> --- a/mm/swap_slots.c
> > >>> +++ b/mm/swap_slots.c
> > >>> @@ -310,7 +310,7 @@ swp_entry_t folio_alloc_swap(struct folio *folio)
> > >>> entry.val = 0;
> > >>>
> > >>> if (folio_test_large(folio)) {
> > >>> - if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported())
> > >>> + if (IS_ENABLED(CONFIG_THP_SWAP))
> > >>> get_swap_pages(1, &entry, folio_nr_pages(folio));
> > >>> goto out;
> > >>> }
> > >>
> > >
> > > Thanks
> > > Barry
> >
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^ permalink raw reply related
* Re: [PATCH 2/2] dt-bindings: iio: adc: nxp,imx93-adc.yaml: Add calibration properties
From: Andrej Picej @ 2024-03-22 7:39 UTC (permalink / raw)
To: Krzysztof Kozlowski, haibo.chen, linux-iio, devicetree
Cc: jic23, lars, shawnguo, s.hauer, kernel, festevam, imx,
linux-arm-kernel, linux-kernel, robh, krzysztof.kozlowski+dt,
conor+dt, upstream
In-Reply-To: <7e58bf96-3c38-467f-86b6-06ff5feedb31@linaro.org>
On 20. 03. 24 13:15, Krzysztof Kozlowski wrote:
> On 20/03/2024 13:05, Andrej Picej wrote:
>> Hi Krzysztof,
>>
>> On 20. 03. 24 11:26, Krzysztof Kozlowski wrote:
>>> On 20/03/2024 11:04, Andrej Picej wrote:
>>>> Document calibration properties and how to set them.
>>>
>>> Bindings are before users.
>>
>> will change patch order when I send a v2.
>>
>>>
>>> Please use subject prefixes matching the subsystem. You can get them for
>>> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
>>> your patch is touching.
>>> There is no file extension in prefixes.
>>
>> So: dt-bindings: iio/adc: nxp,imx93-adc: Add calibration properties?
>
> Did you run the command I proposed? I don't see much of "/", but except
> that looks good.
Ok noted.
>
>>
>>>
>>>>
>>>> Signed-off-by: Andrej Picej <andrej.picej@norik.com>
>>>> ---
>>>> .../bindings/iio/adc/nxp,imx93-adc.yaml | 15 +++++++++++++++
>>>> 1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
>>>> index dacc526dc695..64958be62a6a 100644
>>>> --- a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
>>>> +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml
>>>> @@ -46,6 +46,21 @@ properties:
>>>> "#io-channel-cells":
>>>> const: 1
>>>>
>>>> + nxp,calib-avg-en:
>>>> + description:
>>>> + Enable or disable averaging of calibration time.
>>>> + enum: [ 0, 1 ]
>>>> +
>>>> + nxp,calib-nr-samples:
>>>> + description:
>>>> + Selects the number of averaging samples to be used during calibration.
>>>> + enum: [ 16, 32, 128, 512 ]
>>>> +
>>>> + nxp,calib-t-samples:
>>>> + description:
>>>> + Specifies the sample time of calibration conversions.
>>>> + enum: [ 8, 16, 22, 32 ]
>>>
>>> No, use existing, generic properties. Open other bindings for this.
>>
>> You mean I should use generic properties for the ADC calibration
>> settings? Is there already something in place? Because as I understand
>> it, these calib-* values only effect the calibration process of the ADC.
>
> Please take a look at other devices and dtschema. We already have some
> properties for this... but maybe they cannot be used?
>
I did look into other ADC devices, grep across iio/adc, adc bindings
folders and couldn't find anything closely related to what we are
looking for. Could you please point me to the properties that you think
should be used for this?
Thank you.
Andrej
>
> Best regards,
> Krzysztof
>
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: mtd: atmel-nand: convert txt to yaml
From: Conor Dooley @ 2024-03-22 7:30 UTC (permalink / raw)
To: Balamanikandan.Gunasundar
Cc: robh, conor+dt, linux-kernel, vigneshr, alexandre.belloni,
devicetree, richard, conor, claudiu.beznea, linux-mtd,
krzysztof.kozlowski+dt, miquel.raynal, linux-arm-kernel
In-Reply-To: <3c199359-f0d8-4ec0-bf86-930b2ecfb876@microchip.com>
[-- Attachment #1.1: Type: text/plain, Size: 2313 bytes --]
On Fri, Mar 22, 2024 at 04:27:29AM +0000, Balamanikandan.Gunasundar@microchip.com wrote:
> On 20/03/24 10:05 pm, Conor Dooley wrote:
> > On Wed, Mar 20, 2024 at 11:22:07AM +0530, Balamanikandan Gunasundar wrote:
> >> +allOf:
> >> + - if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + enum:
> >> + - atmel,at91rm9200-nand-controller
> >> + - atmel,at91sam9260-nand-controller
> >> + - atmel,at91sam9261-nand-controller
> >> + - atmel,at91sam9g45-nand-controller
> >> + - atmel,sama5d3-nand-controller
> >> + - microchip,sam9x60-nand-controller
> >> + then:
> >> + properties:
> >> + "#address-cells":
> >> + const: 2
> >> +
> >> + "#size-cells":
> >> + const: 1
> > Why is this in an if? Isn't this all of the devices in the binding?
> >
>
> The default nand-controller.yaml defines this as const values.
> (#address-cell : 1 and #size-cells : 1). I am trying to override this
> const value.
You're not overriding anything as you don't have a ref to
nand-controller.yaml in this file, AFAICT. Why don't you?
> May be I should think about better approach ?
You should be able to apply this unconditionally for this file. I don't
see why the if would be needed?
> >> +patternProperties:
> >> + "^nand@[a-f0-9]$":
> >> + type: object
> >> + $ref: nand-chip.yaml#
> >> + description:
> >> + NAND chip bindings. All generic properties described in
> >> + Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to
> >> + the NAND device node, and NAND partitions should be defined under the
> >> + NAND node as described in
> >> + Documentation/devicetree/bindings/mtd/partition.txt.
> > These files do not exist.
> >
>
> Apologies for copying the content from the text file. I will correct this.
You don't need these comments at all I think. You have the ref to
nand-chip.yaml, so at least the first text file reference can be
removed.
> Yes. I should fix the alignment. I will send a v2 shortly
I did make other comments, so I assume you agree with everything else I
mentioned and will implement them in v2.
Thanks,
Conor.
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^ permalink raw reply
* Re: [PATCH 1/3] drm/mediatek: drm_ddp_comp: Fix and cleanup DDP component CRTC search
From: CK Hu (胡俊光) @ 2024-03-22 7:30 UTC (permalink / raw)
To: angelogioacchino.delregno@collabora.com, chunkuang.hu@kernel.org
Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
wenst@chromium.org, kernel@collabora.com,
Nancy Lin (林欣螢), daniel@ffwll.ch,
p.zabel@pengutronix.de, dri-devel@lists.freedesktop.org,
Nathan Lu (呂東霖), airlied@gmail.com,
linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com
In-Reply-To: <20240201125304.218467-2-angelogioacchino.delregno@collabora.com>
Hi, Angelo:
On Thu, 2024-02-01 at 13:53 +0100, AngeloGioacchino Del Regno wrote:
> Finding a possible CRTC by DDP component is done by first checking
> static routes in three paths (main, external, third/extra path) and
> then, if not found, we check for dynamic connection on a per-route
> basis because, for example, on some SoCs the main route may output
> to either a DSI display or DisplayPort and this is finally done by
> assigning a CRTC mask to `possible_crtcs`, found with function
> mtk_drm_find_comp_in_ddp_conn_path(): being that a mask the possible
> values are BIT(x) and, if no CRTC is possible, zero.
>
> Problem is, both mtk_drm_find_possible_crtc_by_comp() and the
> aforementioned function are trying to return a negative error value
> (but it's unsigned int!) if no CRTC was found, which is wrong for
> multiple obvious reasons.
I does not find anywhere to return negative value. So this patch just
like a refine patch not bug fix.
Regards,
CK
>
> Cleanup both functions, so that:
> - mtk_drm_find_comp_in_ddp_conn_path() returns a signed integer
> with a negative number for error, or a bit/bitmask of the found
> possible CRTC; and
> - mtk_drm_find_possible_crtc_by_comp() always returns either a
> bitmask of the possible CRTC, or zero if none available.
>
> Fixes: 01389b324c97 ("drm/mediatek: Add connector dynamic selection
> capability")
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 ++++++++++---------
> --
> 1 file changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index a9b5a21cde2d..c13359eeb3cd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -513,29 +513,25 @@ static bool mtk_drm_find_comp_in_ddp(struct
> device *dev,
> return false;
> }
>
> -static unsigned int mtk_drm_find_comp_in_ddp_conn_path(struct device
> *dev,
> - const struct
> mtk_drm_route *routes,
> - unsigned int
> num_routes,
> - struct
> mtk_ddp_comp *ddp_comp)
> +static int mtk_drm_find_comp_in_ddp_conn_path(struct device *dev,
> + const struct
> mtk_drm_route *routes,
> + unsigned int num_routes,
> + struct mtk_ddp_comp
> *ddp_comp)
> {
> - int ret;
> - unsigned int i;
> + int i;
>
> - if (!routes) {
> - ret = -EINVAL;
> - goto err;
> + if (!routes || !num_routes) {
> + DRM_ERROR("No connection routes specified!\n");
> + return -EINVAL;
> }
>
> for (i = 0; i < num_routes; i++)
> if (dev == ddp_comp[routes[i].route_ddp].dev)
> return BIT(routes[i].crtc_id);
>
> - ret = -ENODEV;
> -err:
> -
> - DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
> + DRM_ERROR("Failed to find component in ddp table\n");
>
> - return 0;
> + return -ENODEV;
> }
>
> int mtk_ddp_comp_get_id(struct device_node *node,
> @@ -557,22 +553,24 @@ unsigned int
> mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
> struct device *dev)
> {
> struct mtk_drm_private *private = drm->dev_private;
> - unsigned int ret = 0;
> + int ret;
>
> if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path,
> private->data->main_len,
> private->ddp_comp))
> - ret = BIT(0);
> + return BIT(0);
> else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
> private->data->ext_len,
> private->ddp_comp))
> - ret = BIT(1);
> + return BIT(1);
> else if (mtk_drm_find_comp_in_ddp(dev, private->data-
> >third_path,
> private->data->third_len,
> private->ddp_comp))
> - ret = BIT(2);
> - else
> - ret = mtk_drm_find_comp_in_ddp_conn_path(dev,
> - private->data-
> >conn_routes,
> - private->data-
> >num_conn_routes,
> - private-
> >ddp_comp);
> + return BIT(2);
> +
> + ret = mtk_drm_find_comp_in_ddp_conn_path(dev, private->data-
> >conn_routes,
> + private->data-
> >num_conn_routes,
> + private->ddp_comp);
> + /* No CRTC is available: return a zero mask */
> + if (ret < 0)
> + return 0;
>
> return ret;
> }
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^ permalink raw reply
* Re: [PATCH 1/5] dt-bindings: mfd: Add rk816 binding
From: Krzysztof Kozlowski @ 2024-03-22 7:07 UTC (permalink / raw)
To: Alex Bee, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Linus Walleij, Liam Girdwood,
Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio
In-Reply-To: <20240321143911.90210-4-knaerzche@gmail.com>
On 21/03/2024 15:39, Alex Bee wrote:
> Add DT binding document for Rockchip's RK816 PMIC
>
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
> new file mode 100644
> index 000000000000..b46de99f60ff
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
> @@ -0,0 +1,259 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/rockchip,rk816.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RK816 Power Management Integrated Circuit
> +
> +maintainers:
> + - Chris Zhong <zyw@rock-chips.com>
> + - Zhang Qing <zhangqing@rock-chips.com>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + Rockchip RK816 series PMIC. This device consists of an i2c controlled MFD
> + that includes regulators, a RTC, a gpio controller, and a power button.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk816
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + '#clock-cells':
> + description: |
Do not need '|' unless you need to preserve formatting.
> + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
> + const: 1
> +
> + clock-output-names:
> + description:
> + From common clock binding to override the default output clock name.
Drop description, it's obvious.
> + maxItems: 2
> +
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> + system-power-controller:
> + type: boolean
> + description:
> + Telling whether or not this PMIC is controlling the system power.
> +
> + wakeup-source:
> + type: boolean
> + description:
> + Device can be used as a wakeup source.
Drop description, it's obvious. It's considered generic property, even
if we did not document it in dtschema yet.
> +
> + vcc1-supply:
> + description:
> + The input supply for DCDC_REG1.
> +
> + vcc2-supply:
> + description:
> + The input supply for DCDC_REG2.
> +
> + vcc3-supply:
> + description:
> + The input supply for DCDC_REG3.
> +
> + vcc4-supply:
> + description:
> + The input supply for DCDC_REG4.
> +
> + vcc5-supply:
> + description:
> + The input supply for LDO_REG1, LDO_REG2, and LDO_REG3.
> +
> + vcc6-supply:
> + description:
> + The input supply for LDO_REG4, LDO_REG5, and LDO_REG6.
> +
> + vcc7-supply:
> + description:
> + The input supply for BOOST.
> +
> + vcc8-supply:
> + description:
> + The input supply for OTG_SWITCH.
> +
> + regulators:
> + type: object
> + patternProperties:
> + "^(DCDC_REG[1-4]|LDO_REG[1-6]|BOOST|OTG_SWITCH)$":
Lowercase. No underscores allowed, use hyphens.
> + type: object
> + $ref: ../regulator/regulator.yaml#
Full path, so /schemas/regulator/
> + unevaluatedProperties: false
> + unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: arm: qcom,coresight-funnel: Add label for multi-ouput
From: Tingwei Zhang @ 2024-03-22 7:02 UTC (permalink / raw)
To: Rob Herring, Tao Zhang
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin,
Konrad Dybcio, Mike Leach, Krzysztof Kozlowski, Jinlong Mao,
Leo Yan, Greg Kroah-Hartman, coresight, linux-arm-kernel,
linux-kernel, devicetree, Yuanfang Zhang, Trilok Soni, Song Chai,
linux-arm-msm, andersson
In-Reply-To: <20240321144226.GA1689544-robh@kernel.org>
On 3/21/2024 10:42 PM, Rob Herring wrote:
> On Thu, Mar 21, 2024 at 04:32:04PM +0800, Tao Zhang wrote:
>> Add new property "label" to label the source corresponding to the
>> output connection. When the funnel supports multi-output, this
>> property needs to be introduced to mark which source component a
>> certain output connection corresponds to.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> ---
>> .../arm/arm,coresight-dynamic-funnel.yaml | 34 ++++++++++++++++---
>> 1 file changed, 30 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
>> index 44a1041cb0fc..cde62c286d29 100644
>> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
>> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
>> @@ -66,13 +66,39 @@ properties:
>> $ref: /schemas/graph.yaml#/properties/port
>>
>> out-ports:
>> - $ref: /schemas/graph.yaml#/properties/ports
>> - additionalProperties: false
>> -
>> + type: object
>> properties:
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 0
>> +
>> port:
>> + type: object
>> +
>> + patternProperties:
>> + '^port(@[0-7])?$':
>> + type: object
>> description: Output connection to CoreSight Trace bus
>> - $ref: /schemas/graph.yaml#/properties/port
>
> Nope, now you have no constraints on port node properties. Please look
> at how other bindings are done to add properties on endpoint node.
>
Thanks for pointing this out, Rob. Shall we ref port-base and
endpoint-base then add new properties on endpoint? In this way, the
redundant code from port schema is not required.
>> +
>> + patternProperties:
>> + "^endpoint(@[0-9a-f]+)?$":
>> + type: object
>> + properties:
>> + remote-endpoint:
>> + description: |
>> + phandle to an 'endpoint' subnode of a remote device node.
>> + $ref: /schemas/types.yaml#/definitions/phandle
>
> Don't need this.
>
>> + label:
>> + description: Label the source corresponding to the output connection
>> + $ref: /schemas/types.yaml#/definitions/string
>
> label already has a type.
>
> As this node is an output, aren't you labeling what the destination is,
> not the "source"?
>
> Why can't you look at the remote connection to identify what it is?
>
This funnel can route data stream from different trace source to
different output ports. This lable property is added to describe which
source is routed to this output port.
For example, the graph is as below. Funnel3 routes trace data from TPDM0
to output[0] and output[0] of funnel3 is connected to input[0] of TPDA0.
While Funnels routes trace data from TPDM1 to output[1] which connects
to input[1] of TPDA0. Hope that clarifies this a little bit.
|---------| |---------| |---------| |---------| |---------|
| TPDM0 | | TPDM1 | | TPDM2 | | TPDM3 | | TPDM4 |
|---------| |---------| |---------| |---------| |---------|
| | | | |
| | | | |
| | | | |
|-----| |-----| |-----| |-----| |
| | | | |
| | | | |
[0]| |[1] [0]| |[1] |
\-------------/ \-------------/ \------------/
\ FUNNEL0 / \ FUNNEL1 / \ FUNNEL2 /
----------- ----------- -----------
| | |
\-------------/ \-------------/ |
\ FUNNEL3 / \ FUNNEL4 / |
----------- ----------- |
| | | |
[0]| |[1] [0]| |[1] |
| |---------- | | |
| | | | |
|-------| | |------- | | |--------- |
| | | | |
| | | | |
[0]| |[1] |[2] |[3] |[4]
\ ---------------------------------------------------/
\ TPDA0 /
\ /
------------------------------------------------
>
>> + oneOf:
>> + - required:
>> + - port
>> + - required:
>> + - "#address-cells"
>> + - "#size-cells"
>
> The common schema that you removed handles this.
>
> Rob
--
Thanks,
Tingwei
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^ permalink raw reply
* Re: [PATCH v6 08/14] drm/mediatek: Support "Pre-multiplied" alpha blending in OVL
From: CK Hu (胡俊光) @ 2024-03-22 6:43 UTC (permalink / raw)
To: Shawn Sung (宋孝謙), chunkuang.hu@kernel.org,
angelogioacchino.delregno@collabora.com
Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
Bibby Hsieh (謝濟遠),
jason-ch.chen@mediatek.corp-partner.google.com,
Nancy Lin (林欣螢), daniel@ffwll.ch,
p.zabel@pengutronix.de, dri-devel@lists.freedesktop.org,
airlied@gmail.com, sean@poorly.run, matthias.bgg@gmail.com,
fshao@chromium.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20240322052829.9893-9-shawn.sung@mediatek.com>
Hi, Shawn:
On Fri, 2024-03-22 at 13:28 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
>
> Support "Pre-multiplied" blend mode on MediaTek's chips.
> Before this patch, only the "coverage" mode is supported.
>
> Please refer to the description of the commit
> "drm/mediatek: Support alpha blending in display driver"
> for more information.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 84 +++++++++++++++++++++
> ----
> 1 file changed, 73 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 2a767a823c83a..b1e5d453316cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -38,6 +38,7 @@
> #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
> #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
> #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20
> * (n))
> +#define OVL_CONST_BLEND BIT(28)
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> #define DISP_REG_OVL_ADDR_MT2701 0x0040
> @@ -51,13 +52,16 @@
> #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
> #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
>
> +#define OVL_CON_CLRFMT_MAN BIT(23)
> #define OVL_CON_BYTE_SWAP BIT(24)
> -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
> +#define OVL_CON_RGB_SWAP BIT(25)
> #define OVL_CON_CLRFMT_RGB (1 << 12)
> #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
> #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
> #define OVL_CON_CLRFMT_UYVY (4 << 12)
> #define OVL_CON_CLRFMT_YUYV (5 << 12)
> +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
> +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 |
> OVL_CON_CLRFMT_MAN)
> #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ?
> \
> 0 : OVL_CON_CLRFMT_RGB)
> #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ?
> \
> @@ -71,6 +75,24 @@
> #define OVL_CON_VIRT_FLIP BIT(9)
> #define OVL_CON_HORZ_FLIP BIT(10)
>
> +#define OVL_COLOR_ALPHA GENMASK(31, 24)
> +
> +static inline bool is_10bit_rgb(u32 fmt)
> +{
> + switch (fmt) {
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_RGBX1010102:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_BGRX1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return true;
> + }
> + return false;
> +}
> +
> static const u32 mt8173_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_ARGB8888,
> @@ -88,12 +110,20 @@ static const u32 mt8173_formats[] = {
> static const u32 mt8195_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XRGB2101010,
As I know, the 'X' in XRGB means garbage data. It's not alpha. And pre-
multiplied alpha formula is:
result = source RGB + (destination RGB * (1 - source alpha))
So pre-multiplied alpha need source alpha. I think XRGB is not related
to pre-multiplied alpha. So separate X-related format to another patch.
> DRM_FORMAT_ARGB2101010,
> DRM_FORMAT_BGRX8888,
> DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_BGRX1010102,
> DRM_FORMAT_BGRA1010102,
> DRM_FORMAT_ABGR8888,
> DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_ABGR2101010,
It seems 10 bits format has no pre-multiplied alpha function. So
separate 10 bits format modification to another patch.
> + DRM_FORMAT_RGBX8888,
> + DRM_FORMAT_RGBA8888,
For RGBA8888, it both has coverage mode and pre-multiplied mode, so
it's not strongly related to pre-multiplied alpha. Separate this to
another patch which add support this new format.
> + DRM_FORMAT_RGBX1010102,
> + DRM_FORMAT_RGBA1010102,
> DRM_FORMAT_RGB888,
> DRM_FORMAT_BGR888,
> DRM_FORMAT_RGB565,
> @@ -253,9 +283,7 @@ static void mtk_ovl_set_bit_depth(struct device
> *dev, int idx, u32 format,
> reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
> reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
>
> - if (format == DRM_FORMAT_RGBA1010102 ||
> - format == DRM_FORMAT_BGRA1010102 ||
> - format == DRM_FORMAT_ARGB2101010)
> + if (is_10bit_rgb(format))
> bit_depth = OVL_CON_CLRFMT_10_BIT;
>
> reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
> @@ -273,7 +301,13 @@ void mtk_ovl_config(struct device *dev, unsigned
> int w,
> if (w != 0 && h != 0)
> mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl-
> >cmdq_reg, ovl->regs,
> DISP_REG_OVL_ROI_SIZE);
> - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_ROI_BGCLR);
> +
> + /*
> + * The background color should be opaque black (ARGB),
> + * otherwise there will be no effect with alpha blend
> + */
> + mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl-
> >cmdq_reg,
> + ovl->regs, DISP_REG_OVL_ROI_BGCLR);
The pre-multiplied alpha formula is:
result = source RGB + (destination RGB * (1 - source alpha))
It does not care destination alpha. Background color is the
destination, so describe more detail why need this modification. For
example, how does hardware calculate with back ground color?
>
> mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
> mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
> @@ -353,7 +387,8 @@ void mtk_ovl_layer_off(struct device *dev,
> unsigned int idx,
> DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt)
> +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt,
> + unsigned int blend_mode)
> {
> /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
> * is defined in mediatek HW data sheet.
> @@ -372,17 +407,37 @@ static unsigned int ovl_fmt_convert(struct
> mtk_disp_ovl *ovl, unsigned int fmt)
> return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGBX8888:
> case DRM_FORMAT_RGBA8888:
> + return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_ARGB8888 :
> + OVL_CON_CLRFMT_PARGB8888;
> + case DRM_FORMAT_RGBX1010102:
> + case DRM_FORMAT_RGBA1010102:
> return OVL_CON_CLRFMT_ARGB8888;
> case DRM_FORMAT_BGRX8888:
> case DRM_FORMAT_BGRA8888:
> + return OVL_CON_BYTE_SWAP |
> + (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_ARGB8888 :
> + OVL_CON_CLRFMT_PARGB8888);
> + case DRM_FORMAT_BGRX1010102:
> case DRM_FORMAT_BGRA1010102:
> return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_ARGB8888:
> + return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_RGBA8888 :
> + OVL_CON_CLRFMT_PARGB8888;
> + case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_ARGB2101010:
> return OVL_CON_CLRFMT_RGBA8888;
> case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_ABGR8888:
> + return OVL_CON_RGB_SWAP |
> + (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_RGBA8888 :
> + OVL_CON_CLRFMT_PARGB8888);
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ABGR2101010:
> return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_UYVY:
> return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
> @@ -404,6 +459,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
> unsigned int fmt = pending->format;
> unsigned int offset = (pending->y << 16) | pending->x;
> unsigned int src_size = (pending->height << 16) | pending-
> >width;
> + unsigned int blend_mode = state->base.pixel_blend_mode;
> + unsigned int ignore_pixel_alpha = 0;
> unsigned int con;
> bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
> union overlay_pitch {
> @@ -421,9 +478,14 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
> return;
> }
>
> - con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb && state->base.fb->format->has_alpha)
> - con |= OVL_CON_AEN | OVL_CON_ALPHA;
> + con = ovl_fmt_convert(ovl, fmt, blend_mode);
> + if (state->base.fb) {
> + con |= OVL_CON_AEN;
> + con |= state->base.alpha & OVL_CON_ALPHA;
Now support pixel alpha, and this seems to support plane alpha. So
separate this to another patch. If possible, describe how plane alpha
calculate with pixel alpha.
> + }
> +
> + if (state->base.fb && !state->base.fb->format->has_alpha)
> + ignore_pixel_alpha = OVL_CONST_BLEND;
Ditto.
Regards,
CK
>
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> con |= OVL_CON_VIRT_FLIP;
> @@ -440,8 +502,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>
> mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_CON(idx));
> - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb,
> &ovl->cmdq_reg, ovl->regs,
> - DISP_REG_OVL_PITCH(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb |
> ignore_pixel_alpha,
> + &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_PITCH(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl-
> >regs,
> DISP_REG_OVL_SRC_SIZE(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl-
> >regs,
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* Re: [PATCH 2/2] dt-bindings: iio: adc: nxp,imx93-adc.yaml: Add calibration properties
From: kernel test robot @ 2024-03-22 6:47 UTC (permalink / raw)
To: Andrej Picej, haibo.chen, linux-iio, devicetree
Cc: oe-kbuild-all, jic23, lars, shawnguo, s.hauer, kernel, festevam,
imx, linux-arm-kernel, linux-kernel, robh, krzysztof.kozlowski+dt,
conor+dt, upstream
In-Reply-To: <20240320100407.1639082-3-andrej.picej@norik.com>
Hi Andrej,
kernel test robot noticed the following build warnings:
[auto build test WARNING on jic23-iio/togreg]
[also build test WARNING on linus/master v6.8 next-20240322]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Andrej-Picej/iio-adc-imx93-Make-calibration-properties-configurable/20240320-184314
base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
patch link: https://lore.kernel.org/r/20240320100407.1639082-3-andrej.picej%40norik.com
patch subject: [PATCH 2/2] dt-bindings: iio: adc: nxp,imx93-adc.yaml: Add calibration properties
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240322/202403221438.trdG8I0x-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403221438.trdG8I0x-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition
>> Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml: nxp,calib-avg-en: missing type definition
>> Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml: nxp,calib-nr-samples: missing type definition
>> Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml: nxp,calib-t-samples: missing type definition
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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^ permalink raw reply
* Re: [PATCH v1 2/2] arm64: dts: rockchip: Add RGA2 support to rk3588
From: Jianfeng Liu @ 2024-03-22 6:47 UTC (permalink / raw)
To: liujianfeng1994
Cc: conor+dt, devicetree, ezequiel, heiko, jacob-chen,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-kernel,
linux-media, linux-rockchip, mchehab, robh, sfr
In-Reply-To: <20240322052915.3507937-3-liujianfeng1994@gmail.com>
This node is not sorted by bus-address, and anthoer patch adding hantro g1
with addreess fdb50000 is not merged. I will send v2 after that patch is
merged.
Jianfeng
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^ permalink raw reply
* [PATCH v8 8/8] perf vendor events arm64:: Add i.MX93 DDR Performance Monitor metrics
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
Add JSON metrics for i.MX93 DDR Performance Monitor.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v7:
- new patch
Changes in v8:
- no changes
---
.../arch/arm64/freescale/imx93/sys/ddrc.json | 9 +++++++
.../arm64/freescale/imx93/sys/metrics.json | 26 +++++++++++++++++++
2 files changed, 35 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json
create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json
new file mode 100644
index 000000000000..eeeae4d49fce
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/ddrc.json
@@ -0,0 +1,9 @@
+[
+ {
+ "BriefDescription": "ddr cycles event",
+ "EventCode": "0x00",
+ "EventName": "imx93_ddr.cycles",
+ "Unit": "imx9_ddr",
+ "Compat": "imx93"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json
new file mode 100644
index 000000000000..4d2454ca1259
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/freescale/imx93/sys/metrics.json
@@ -0,0 +1,26 @@
+[
+ {
+ "BriefDescription": "bandwidth usage for lpddr4x evk board",
+ "MetricName": "imx93_bandwidth_usage.lpddr4x",
+ "MetricExpr": "(((( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8 ) + (( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32 )) / duration_time) / (3733 * 1000000 * 2)",
+ "ScaleUnit": "1e2%",
+ "Unit": "imx9_ddr",
+ "Compat": "imx93"
+ },
+ {
+ "BriefDescription": "bytes all masters read from ddr",
+ "MetricName": "imx93_ddr_read.all",
+ "MetricExpr": "( imx9_ddr0@ddrc_pm_0@ ) * 2 * 8",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx93"
+ },
+ {
+ "BriefDescription": "bytes all masters write to ddr",
+ "MetricName": "imx93_ddr_write.all",
+ "MetricExpr": "( imx9_ddr0@ddrc_pm_3@ + imx9_ddr0@ddrc_pm_5@ + imx9_ddr0@ddrc_pm_7@ + imx9_ddr0@ddrc_pm_9@ - imx9_ddr0@ddrc_pm_2@ - imx9_ddr0@ddrc_pm_4@ - imx9_ddr0@ddrc_pm_6@ - imx9_ddr0@ddrc_pm_8@ ) * 32",
+ "ScaleUnit": "9.765625e-4KB",
+ "Unit": "imx9_ddr",
+ "Compat": "imx93"
+ }
+]
--
2.34.1
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^ permalink raw reply related
* [PATCH v8 3/8] perf: imx_perf: let the driver manage the counter usage rather the user
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
In current design, the user of perf app needs to input counter ID to count
events. However, this is not user-friendly since the user needs to lookup
the map table to find the counter. Instead of letting the user to input
the counter, let this driver to manage the counters in this patch.
This will be implemented by:
1. allocate counter 0 for cycle event.
2. find unused counter from 1-10 for reference events.
3. allocate specific counter for counter-specific events.
In this patch, counter attribute is removed too. To mark counter-specific
events, counter ID will be encoded into perf_pmu_events_attr.id.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v6:
- new patch
Changes in v7:
- no changes
Changes in v8:
- add Rb tag
---
drivers/perf/fsl_imx9_ddr_perf.c | 168 ++++++++++++++++++-------------
1 file changed, 99 insertions(+), 69 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 0017f2c9ef91..b728719b494c 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -41,9 +41,11 @@
#define NUM_COUNTERS 11
#define CYCLES_COUNTER 0
+#define CYCLES_EVENT_ID 0
#define CONFIG_EVENT GENMASK(7, 0)
#define CONFIG_COUNTER GENMASK(15, 8)
+#define CONFIG_COUNTER_OFFSET 8
#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
@@ -130,6 +132,8 @@ static ssize_t ddr_pmu_event_show(struct device *dev,
return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
}
+#define ID(counter, id) ((counter << CONFIG_COUNTER_OFFSET) | id)
+
#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
(&((struct perf_pmu_events_attr[]) { \
{ .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
@@ -162,81 +166,81 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63),
/* counter1 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, 66),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, 67),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, 68),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, 69),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, 70),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, 71),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)),
/* counter2 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, 66),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, 67),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, 68),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, 69),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),
/* counter3 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, 66),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, 67),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, 68),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, 69),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),
/* counter4 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, 66),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, 67),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, 68),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, 69),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),
/* counter5 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, 66),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, 67),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, 68),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, 69),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70),
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)),
/* counter6 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, 72),
+ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)),
/* counter7 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, 64),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, 65),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)),
/* counter8 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, 64),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, 65),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)),
/* counter9 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, 65),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, 66),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)),
/* counter10 specific events */
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, 65),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, 66),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)),
+ IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)),
NULL,
};
@@ -245,14 +249,12 @@ static const struct attribute_group ddr_perf_events_attr_group = {
.attrs = ddr_perf_events_attrs,
};
-PMU_FORMAT_ATTR(event, "config:0-7");
-PMU_FORMAT_ATTR(counter, "config:8-15");
+PMU_FORMAT_ATTR(event, "config:0-15");
PMU_FORMAT_ATTR(axi_id, "config1:0-17");
PMU_FORMAT_ATTR(axi_mask, "config2:0-17");
static struct attribute *ddr_perf_format_attrs[] = {
&format_attr_event.attr,
- &format_attr_counter.attr,
&format_attr_axi_id.attr,
&format_attr_axi_mask.attr,
NULL,
@@ -366,13 +368,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
}
}
-static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2)
+static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
+ int counter, int axi_id, int axi_mask)
{
u32 pmcfg1, pmcfg2;
- int event, counter;
-
- event = FIELD_GET(CONFIG_EVENT, cfg);
- counter = FIELD_GET(CONFIG_COUNTER, cfg);
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
@@ -392,12 +391,12 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int
pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
- pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2);
+ pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask);
writel(pmcfg1, pmu->base + PMCFG1);
pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
- pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1);
+ pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id);
writel(pmcfg2, pmu->base + PMCFG2);
}
@@ -465,6 +464,28 @@ static void ddr_perf_event_start(struct perf_event *event, int flags)
hwc->state = 0;
}
+static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter)
+{
+ int i;
+
+ if (event == CYCLES_EVENT_ID) {
+ // Cycles counter is dedicated for cycle event.
+ if (pmu->events[CYCLES_COUNTER] == NULL)
+ return CYCLES_COUNTER;
+ } else if (counter != 0) {
+ // Counter specific event use specific counter.
+ if (pmu->events[counter] == NULL)
+ return counter;
+ } else {
+ // Auto allocate counter for referene event.
+ for (i = 1; i < NUM_COUNTERS; i++)
+ if (pmu->events[i] == NULL)
+ return i;
+ }
+
+ return -ENOENT;
+}
+
static int ddr_perf_event_add(struct perf_event *event, int flags)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -472,10 +493,17 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
int cfg = event->attr.config;
int cfg1 = event->attr.config1;
int cfg2 = event->attr.config2;
- int counter;
+ int event_id, counter;
+ event_id = FIELD_GET(CONFIG_EVENT, cfg);
counter = FIELD_GET(CONFIG_COUNTER, cfg);
+ counter = ddr_perf_alloc_counter(pmu, event_id, counter);
+ if (counter < 0) {
+ dev_dbg(pmu->dev, "There are not enough counters\n");
+ return -EOPNOTSUPP;
+ }
+
pmu->events[counter] = event;
pmu->active_events++;
hwc->idx = counter;
@@ -485,7 +513,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
ddr_perf_event_start(event, flags);
/* read trans, write trans, read beat */
- ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
+ ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
return 0;
}
@@ -506,9 +534,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
+ int counter = hwc->idx;
ddr_perf_event_stop(event, PERF_EF_UPDATE);
+ pmu->events[counter] = NULL;
pmu->active_events--;
hwc->idx = -1;
}
--
2.34.1
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^ permalink raw reply related
* [PATCH v8 4/8] perf: imx_perf: refactor driver for imx93
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
This driver is initinally used to support imx93 Soc and now it's time to
add support for imx95 Soc. However, some macro definitions and events are
different on these two Socs. For preparing imx95 supports, this will
refactor driver for imx93.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- new patch
Changes in v5:
- use is_visible to hide unwanted attributes as suggested by Will
Changes in v6:
- improve imx93_ddr_perf_monitor_config()
Changes in v7:
- improve imx93_ddr_perf_monitor_config() as suggested by Frank
Changes in v8:
- adjust is_visable() as suggested by Frank
---
drivers/perf/fsl_imx9_ddr_perf.c | 106 ++++++++++++++++++++-----------
1 file changed, 68 insertions(+), 38 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index b728719b494c..011377c01dea 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -11,14 +11,14 @@
#include <linux/perf_event.h>
/* Performance monitor configuration */
-#define PMCFG1 0x00
-#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
-#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
-#define PMCFG1_RD_BT_FILT_EN BIT(29)
-#define PMCFG1_ID_MASK GENMASK(17, 0)
+#define PMCFG1 0x00
+#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
+#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
+#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
+#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
-#define PMCFG2 0x04
-#define PMCFG2_ID GENMASK(17, 0)
+#define PMCFG2 0x04
+#define MX93_PMCFG2_ID GENMASK(17, 0)
/* Global control register affects all counters and takes priority over local control registers */
#define PMGC0 0x40
@@ -76,6 +76,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = {
.identifier = "imx93",
};
+static inline bool is_imx93(struct ddr_pmu *pmu)
+{
+ return pmu->devtype_data == &imx93_devtype_data;
+}
+
static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
{.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
{ /* sentinel */ }
@@ -123,23 +128,36 @@ static const struct attribute_group ddr_perf_cpumask_attr_group = {
.attrs = ddr_perf_cpumask_attrs,
};
+struct imx9_pmu_events_attr {
+ struct device_attribute attr;
+ u64 id;
+ const void *devtype_data;
+};
+
static ssize_t ddr_pmu_event_show(struct device *dev,
struct device_attribute *attr, char *page)
{
- struct perf_pmu_events_attr *pmu_attr;
+ struct imx9_pmu_events_attr *pmu_attr;
- pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
+ pmu_attr = container_of(attr, struct imx9_pmu_events_attr, attr);
return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
}
#define ID(counter, id) ((counter << CONFIG_COUNTER_OFFSET) | id)
-#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
- (&((struct perf_pmu_events_attr[]) { \
+#define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \
+ (&((struct imx9_pmu_events_attr[]) { \
{ .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
- .id = _id, } \
+ .id = _id, \
+ .devtype_data = _data, } \
})[0].attr.attr)
+#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
+ DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL)
+
+#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \
+ DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data)
+
static struct attribute *ddr_perf_events_attrs[] = {
/* counter0 cycles event */
IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
@@ -185,7 +203,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),
+ IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
/* counter3 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
@@ -197,7 +215,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),
+ IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
/* counter4 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
@@ -209,7 +227,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
- IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),
+ IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
/* counter5 specific events */
IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
@@ -244,9 +262,29 @@ static struct attribute *ddr_perf_events_attrs[] = {
NULL,
};
+static umode_t
+ddr_perf_events_attrs_is_visible(struct kobject *kobj,
+ struct attribute *attr, int unused)
+{
+ struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
+ struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
+ struct imx9_pmu_events_attr *eattr;
+
+ eattr = container_of(attr, typeof(*eattr), attr.attr);
+
+ if (!eattr->devtype_data)
+ return attr->mode;
+
+ if (eattr->devtype_data != ddr_pmu->devtype_data)
+ return 0;
+
+ return attr->mode;
+}
+
static const struct attribute_group ddr_perf_events_attr_group = {
.name = "events",
.attrs = ddr_perf_events_attrs,
+ .is_visible = ddr_perf_events_attrs_is_visible,
};
PMU_FORMAT_ATTR(event, "config:0-15");
@@ -368,36 +406,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
}
}
-static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
- int counter, int axi_id, int axi_mask)
+static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
+ int counter, int axi_id, int axi_mask)
{
u32 pmcfg1, pmcfg2;
+ u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN,
+ MX93_PMCFG1_WR_TRANS_FILT_EN,
+ MX93_PMCFG1_RD_BT_FILT_EN };
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
- if (counter == 2 && event == 73)
- pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
- else if (counter == 2 && event != 73)
- pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
-
- if (counter == 3 && event == 73)
- pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
- else if (counter == 3 && event != 73)
- pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
-
- if (counter == 4 && event == 73)
- pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
- else if (counter == 4 && event != 73)
- pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
+ if (counter >= 2 && counter <= 4)
+ pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] :
+ pmcfg1 & ~mask[counter - 2];
- pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
- pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask);
- writel(pmcfg1, pmu->base + PMCFG1);
+ pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
+ pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
+ writel_relaxed(pmcfg1, pmu->base + PMCFG1);
pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
- pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
- pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id);
- writel(pmcfg2, pmu->base + PMCFG2);
+ pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
+ pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id);
+ writel_relaxed(pmcfg2, pmu->base + PMCFG2);
}
static void ddr_perf_event_update(struct perf_event *event)
@@ -513,7 +543,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
ddr_perf_event_start(event, flags);
/* read trans, write trans, read beat */
- ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
+ imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
return 0;
}
--
2.34.1
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^ permalink raw reply related
* [PATCH v8 2/8] perf: imx_perf: add macro definitions for parsing config attr
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
In-Reply-To: <20240322063930.749126-1-xu.yang_2@nxp.com>
The user can set event and counter in cmdline and the driver need to parse
it using 'config' attr value. This will add macro definitions to avoid
hard-code in driver.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- new patch
Changes in v5:
- move this patch earlier
Changes in v6:
- no changes
Changes in v7:
- use FIELD_*
Changes in v8:
- add Rb tag
---
drivers/perf/fsl_imx9_ddr_perf.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 72c2d3074cde..0017f2c9ef91 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -42,6 +42,9 @@
#define NUM_COUNTERS 11
#define CYCLES_COUNTER 0
+#define CONFIG_EVENT GENMASK(7, 0)
+#define CONFIG_COUNTER GENMASK(15, 8)
+
#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
#define DDR_PERF_DEV_NAME "imx9_ddr"
@@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
int counter, bool enable)
{
u32 ctrl_a;
+ int event;
ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
+ event = FIELD_GET(CONFIG_EVENT, config);
if (enable) {
ctrl_a |= PMLCA_FC;
@@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
ctrl_a &= ~PMLCA_FC;
ctrl_a |= PMLCA_CE;
ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
- ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF));
+ ctrl_a |= FIELD_PREP(PMLCA_EVENT, event);
writel(ctrl_a, pmu->base + PMLCA(counter));
} else {
/* Freeze counter. */
@@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int
u32 pmcfg1, pmcfg2;
int event, counter;
- event = cfg & 0x000000FF;
- counter = (cfg & 0x0000FF00) >> 8;
+ event = FIELD_GET(CONFIG_EVENT, cfg);
+ counter = FIELD_GET(CONFIG_COUNTER, cfg);
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
@@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
int cfg2 = event->attr.config2;
int counter;
- counter = (cfg & 0x0000FF00) >> 8;
+ counter = FIELD_GET(CONFIG_COUNTER, cfg);
pmu->events[counter] = event;
pmu->active_events++;
--
2.34.1
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^ permalink raw reply related
* [PATCH v8 1/8] dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible
From: Xu Yang @ 2024-03-22 6:39 UTC (permalink / raw)
To: frank.li, will, mark.rutland, robh+dt, krzysztof.kozlowski+dt,
conor+dt, shawnguo, s.hauer, kernel, festevam, john.g.garry,
jolsa, namhyung, irogers
Cc: mike.leach, peterz, mingo, acme, alexander.shishkin,
adrian.hunter, linux-arm-kernel, devicetree, linux-kernel,
linux-perf-users, imx
i.MX95 has a DDR pmu. This will add a compatible for it.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- no changes
Changes in v3:
- let imx95 compatilbe with imx93
Changes in v4:
- add Acked-by tag
Changes in v5:
- no changes
Changes in v6:
- no changes
Changes in v7:
- no changes
Changes in v8:
- no changes
---
Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
index 6c96a4204e5d..37e8b98f2cdc 100644
--- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
@@ -30,6 +30,9 @@ properties:
- items:
- const: fsl,imx8dxl-ddr-pmu
- const: fsl,imx8-ddr-pmu
+ - items:
+ - const: fsl,imx95-ddr-pmu
+ - const: fsl,imx93-ddr-pmu
reg:
maxItems: 1
--
2.34.1
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^ permalink raw reply related
* RE: [PATCH v7 5/8] perf: imx_perf: fix counter start and config sequence
From: Xu Yang @ 2024-03-22 6:31 UTC (permalink / raw)
To: Frank Li
Cc: will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org,
irogers@google.com, mike.leach@linaro.org, peterz@infradead.org,
mingo@redhat.com, acme@kernel.org,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <ZfiJFj1IO67FR/z4@lizhi-Precision-Tower-5810>
>
> On Fri, Mar 15, 2024 at 05:55:52PM +0800, Xu Yang wrote:
> > In current driver, the counter will start firstly and then be configured.
> > This sequence is not correct for AXI filter events since the correct
> > AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
>
> This one should be bug fix. Can you add fixes tag?
Sure.
Thanks,
Xu Yang
>
> >
> > ---
> > Changes in v5:
> > - new patch
> > Changes in v6:
> > - no changes
> > Changes in v7:
> > - no changes
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> > index 5537f4e07852..c99c43b214cb 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -523,12 +523,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
> > hwc->idx = counter;
> > hwc->state |= PERF_HES_STOPPED;
> >
> > - if (flags & PERF_EF_START)
> > - ddr_perf_event_start(event, flags);
> > -
> > /* read trans, write trans, read beat */
> > imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> >
> > + if (flags & PERF_EF_START)
> > + ddr_perf_event_start(event, flags);
> > +
> > return 0;
> > }
> >
> > --
> > 2.34.1
> >
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^ permalink raw reply
* RE: [PATCH v7 4/8] perf: imx_perf: refactor driver for imx93
From: Xu Yang @ 2024-03-22 6:31 UTC (permalink / raw)
To: Frank Li
Cc: will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org,
irogers@google.com, mike.leach@linaro.org, peterz@infradead.org,
mingo@redhat.com, acme@kernel.org,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <ZfiIU6EyI9J4ynTk@lizhi-Precision-Tower-5810>
>
> On Fri, Mar 15, 2024 at 05:55:51PM +0800, Xu Yang wrote:
> > This driver is initinally used to support imx93 Soc and now it's time to
> > add support for imx95 Soc. However, some macro definitions and events are
> > different on these two Socs. For preparing imx95 supports, this will
> > refactor driver for imx93.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v4:
> > - new patch
> > Changes in v5:
> > - use is_visible to hide unwanted attributes as suggested by Will
> > Changes in v6:
> > - improve imx93_ddr_perf_monitor_config()
> > Changes in v7:
> > - improve imx93_ddr_perf_monitor_config() as suggested by Frank
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 80 +++++++++++++++++++-------------
> > 1 file changed, 47 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> > index 4fdf8bcf6646..5537f4e07852 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -11,14 +11,14 @@
> > #include <linux/perf_event.h>
> >
> > /* Performance monitor configuration */
> > -#define PMCFG1 0x00
> > -#define PMCFG1_RD_TRANS_FILT_EN BIT(31)
> > -#define PMCFG1_WR_TRANS_FILT_EN BIT(30)
> > -#define PMCFG1_RD_BT_FILT_EN BIT(29)
> > -#define PMCFG1_ID_MASK GENMASK(17, 0)
> > +#define PMCFG1 0x00
> > +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31)
> > +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30)
> > +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29)
> > +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0)
> >
> > -#define PMCFG2 0x04
> > -#define PMCFG2_ID GENMASK(17, 0)
> > +#define PMCFG2 0x04
> > +#define MX93_PMCFG2_ID GENMASK(17, 0)
> >
> > /* Global control register affects all counters and takes priority over local control registers */
> > #define PMGC0 0x40
> > @@ -76,6 +76,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = {
> > .identifier = "imx93",
> > };
> >
> > +static inline bool is_imx93(struct ddr_pmu *pmu)
> > +{
> > + return pmu->devtype_data == &imx93_devtype_data;
> > +}
> > +
> > static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> > {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
> > { /* sentinel */ }
> > @@ -185,7 +190,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/
> >
> > /* counter3 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
> > @@ -197,7 +202,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/
> >
> > /* counter4 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
> > @@ -209,7 +214,7 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
> > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
> > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),
> > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/
> >
> > /* counter5 specific events */
> > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
> > @@ -244,9 +249,26 @@ static struct attribute *ddr_perf_events_attrs[] = {
> > NULL,
> > };
> >
> > +static umode_t
> > +ddr_perf_events_attrs_is_visible(struct kobject *kobj,
> > + struct attribute *attr, int unused)
> > +{
> > + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
> > + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
> > +
> > + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") ||
> > + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") ||
> > + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) &&
> > + !is_imx93(ddr_pmu))
> > + return 0;
>
> I think use name to check visible is not good enough.
Yeah, I failed to find out a better way to deal with it.
>
> struct imx9_pmu_events_attr
> {
> struct perf_pmu_events_attr perf_attr;
> void * drv_data;
> };
>
> #define IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, drv_data) \
> (&((struct imx9_pmu_events_attr[]) { \
> { .perf_attr.attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
> .perf_attr.id = _id,
> .drv_data = drv_data,
> } \
> })[0].perf_attr.attr.attr)
>
> #define IMX9_DDR_PMU_EVENT_ATTR(_namee, _id,)
> IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, NULL)
>
> #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id)
> IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, &imx93_devtype_data)
>
> So
>
> ddr_perf_events_attrs_is_visible()
> {
> struct imx9_pmu_events_attr *imx9_attr = container_of(attr, imx9_pmu_events_attr, perf_attr)
>
> if (!imx9_attr->drv_data)
> return attr->mode;
>
> if (imx9_attr->drv_data ! = ddr_pmu->drv_data)
> return 0;
>
> return attr->mode;
> }
I've tried your suggestion, it works and make sense for me.
I'll integrate this in next version.
Thanks,
Xu Yang
>
> Frank
>
> > +
> > + return attr->mode;
> > +}
> > +
> > static const struct attribute_group ddr_perf_events_attr_group = {
> > .name = "events",
> > .attrs = ddr_perf_events_attrs,
> > + .is_visible = ddr_perf_events_attrs_is_visible,
> > };
> >
> > PMU_FORMAT_ATTR(event, "config:0-15");
> > @@ -368,36 +390,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
> > }
> > }
> >
> > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
> > - int counter, int axi_id, int axi_mask)
> > +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
> > + int counter, int axi_id, int axi_mask)
> > {
> > u32 pmcfg1, pmcfg2;
> > + u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN,
> > + MX93_PMCFG1_WR_TRANS_FILT_EN,
> > + MX93_PMCFG1_RD_BT_FILT_EN };
> >
> > pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
> >
> > - if (counter == 2 && event == 73)
> > - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN;
> > - else if (counter == 2 && event != 73)
> > - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN;
> > -
> > - if (counter == 3 && event == 73)
> > - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN;
> > - else if (counter == 3 && event != 73)
> > - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN;
> > -
> > - if (counter == 4 && event == 73)
> > - pmcfg1 |= PMCFG1_RD_BT_FILT_EN;
> > - else if (counter == 4 && event != 73)
> > - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN;
> > + if (counter >= 2 && counter <= 4)
> > + pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] :
> > + pmcfg1 & ~mask[counter - 2];
> >
> > - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> > - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask);
> > - writel(pmcfg1, pmu->base + PMCFG1);
> > + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
> > + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
> > + writel_relaxed(pmcfg1, pmu->base + PMCFG1);
> >
> > pmcfg2 = readl_relaxed(pmu->base + PMCFG2);
> > - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> > - pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id);
> > - writel(pmcfg2, pmu->base + PMCFG2);
> > + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
> > + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id);
> > + writel_relaxed(pmcfg2, pmu->base + PMCFG2);
> > }
> >
> > static void ddr_perf_event_update(struct perf_event *event)
> > @@ -513,7 +527,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
> > ddr_perf_event_start(event, flags);
> >
> > /* read trans, write trans, read beat */
> > - ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> > + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> >
> > return 0;
> > }
> > --
> > 2.34.1
> >
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^ permalink raw reply
* Re: [PATCH 1/2] remoteproc: mediatek: Make sure IPI buffer fits in L2TCM
From: Tzung-Bi Shih @ 2024-03-22 6:16 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: mathieu.poirier, andersson, matthias.bgg, tinghan.shen,
linux-remoteproc, linux-kernel, linux-arm-kernel, linux-mediatek,
wenst, kernel
In-Reply-To: <20240321084614.45253-2-angelogioacchino.delregno@collabora.com>
On Thu, Mar 21, 2024 at 09:46:13AM +0100, AngeloGioacchino Del Regno wrote:
> The IPI buffer location is read from the firmware that we load to the
> System Companion Processor, and it's not granted that both the SRAM
> (L2TCM) size that is defined in the devicetree node is large enough
> for that, and while this is especially true for multi-core SCP, it's
> still useful to check on single-core variants as well.
>
> Failing to perform this check may make this driver perform R/W
> oeprations out of the L2TCM boundary, resulting (at best) in a
> kernel panic.
>
> To fix that, check that the IPI buffer fits, otherwise return a
> failure and refuse to boot the relevant SCP core (or the SCP at
> all, if this is single core).
>
> Fixes: 3efa0ea743b7 ("remoteproc/mediatek: read IPI buffer offset from FW")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
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^ permalink raw reply
* Re: [PATCH] drm: zynqmp_dpsub: Always register bridge
From: Tomi Valkeinen @ 2024-03-22 6:01 UTC (permalink / raw)
To: Sean Anderson
Cc: linux-arm-kernel, Michal Simek, linux-kernel, Daniel Vetter,
David Airlie, Laurent Pinchart, dri-devel, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann
In-Reply-To: <20240308204741.3631919-1-sean.anderson@linux.dev>
Hi,
On 08/03/2024 22:47, Sean Anderson wrote:
> We must always register the DRM bridge, since zynqmp_dp_hpd_work_func
> calls drm_bridge_hpd_notify, which in turn expects hpd_mutex to be
> initialized. We do this before zynqmp_dpsub_drm_init since that calls
> drm_bridge_attach. This fixes the following lockdep warning:
>
> [ 19.217084] ------------[ cut here ]------------
> [ 19.227530] DEBUG_LOCKS_WARN_ON(lock->magic != lock)
> [ 19.227768] WARNING: CPU: 0 PID: 140 at kernel/locking/mutex.c:582 __mutex_lock+0x4bc/0x550
> [ 19.241696] Modules linked in:
> [ 19.244937] CPU: 0 PID: 140 Comm: kworker/0:4 Not tainted 6.6.20+ #96
> [ 19.252046] Hardware name: xlnx,zynqmp (DT)
> [ 19.256421] Workqueue: events zynqmp_dp_hpd_work_func
> [ 19.261795] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 19.269104] pc : __mutex_lock+0x4bc/0x550
> [ 19.273364] lr : __mutex_lock+0x4bc/0x550
> [ 19.277592] sp : ffffffc085c5bbe0
> [ 19.281066] x29: ffffffc085c5bbe0 x28: 0000000000000000 x27: ffffff88009417f8
> [ 19.288624] x26: ffffff8800941788 x25: ffffff8800020008 x24: ffffffc082aa3000
> [ 19.296227] x23: ffffffc080d90e3c x22: 0000000000000002 x21: 0000000000000000
> [ 19.303744] x20: 0000000000000000 x19: ffffff88002f5210 x18: 0000000000000000
> [ 19.311295] x17: 6c707369642e3030 x16: 3030613464662072 x15: 0720072007200720
> [ 19.318922] x14: 0000000000000000 x13: 284e4f5f4e524157 x12: 0000000000000001
> [ 19.326442] x11: 0001ffc085c5b940 x10: 0001ff88003f388b x9 : 0001ff88003f3888
> [ 19.334003] x8 : 0001ff88003f3888 x7 : 0000000000000000 x6 : 0000000000000000
> [ 19.341537] x5 : 0000000000000000 x4 : 0000000000001668 x3 : 0000000000000000
> [ 19.349054] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff88003f3880
> [ 19.356581] Call trace:
> [ 19.359160] __mutex_lock+0x4bc/0x550
> [ 19.363032] mutex_lock_nested+0x24/0x30
> [ 19.367187] drm_bridge_hpd_notify+0x2c/0x6c
> [ 19.371698] zynqmp_dp_hpd_work_func+0x44/0x54
> [ 19.376364] process_one_work+0x3ac/0x988
> [ 19.380660] worker_thread+0x398/0x694
> [ 19.384736] kthread+0x1bc/0x1c0
> [ 19.388241] ret_from_fork+0x10/0x20
> [ 19.392031] irq event stamp: 183
> [ 19.395450] hardirqs last enabled at (183): [<ffffffc0800b9278>] finish_task_switch.isra.0+0xa8/0x2d4
> [ 19.405140] hardirqs last disabled at (182): [<ffffffc081ad3754>] __schedule+0x714/0xd04
> [ 19.413612] softirqs last enabled at (114): [<ffffffc080133de8>] srcu_invoke_callbacks+0x158/0x23c
> [ 19.423128] softirqs last disabled at (110): [<ffffffc080133de8>] srcu_invoke_callbacks+0x158/0x23c
> [ 19.432614] ---[ end trace 0000000000000000 ]---
>
> Fixes: eb2d64bfcc17 ("drm: xlnx: zynqmp_dpsub: Report HPD through the bridge")
> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> ---
>
> drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> index 88eb33acd5f0..639fff2c693f 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> @@ -256,12 +256,11 @@ static int zynqmp_dpsub_probe(struct platform_device *pdev)
> if (ret)
> goto err_dp;
>
> + drm_bridge_add(dpsub->bridge);
> if (dpsub->dma_enabled) {
> ret = zynqmp_dpsub_drm_init(dpsub);
> if (ret)
> goto err_disp;
> - } else {
> - drm_bridge_add(dpsub->bridge);
> }
>
> dev_info(&pdev->dev, "ZynqMP DisplayPort Subsystem driver probed");
> @@ -288,9 +287,8 @@ static void zynqmp_dpsub_remove(struct platform_device *pdev)
>
> if (dpsub->drm)
> zynqmp_dpsub_drm_cleanup(dpsub);
> - else
> - drm_bridge_remove(dpsub->bridge);
>
> + drm_bridge_remove(dpsub->bridge);
> zynqmp_disp_remove(dpsub);
> zynqmp_dp_remove(dpsub);
>
I sent a similar patch:
https://lore.kernel.org/all/20240312-xilinx-dp-lock-fix-v1-1-1698f9f03bac@ideasonboard.com/
I have the drm_bridge_add() call in zynqmp_dp_probe(), as that's where
the bridge is set up, so it felt like a logical place. You add it later,
just before the bridge is used the first time.
I like mine a bit more as it has all the bridge code in the same place,
but I also wonder if there might be some risks in adding the bridge
early (before zynqmp_disp_probe()), although I can't see any issue right
away...
In any case, as this works for me too:
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Tomi
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^ permalink raw reply
* Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
From: Krzysztof Kozlowski @ 2024-03-22 5:59 UTC (permalink / raw)
To: Anatoliy Klymenko, Laurent Pinchart, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Michal Simek, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mauro Carvalho Chehab
Cc: Tomi Valkeinen, dri-devel, linux-arm-kernel, linux-kernel,
devicetree, linux-media
In-Reply-To: <20240321-dp-live-fmt-v3-8-d5090d796b7e@amd.com>
On 21/03/2024 21:43, Anatoliy Klymenko wrote:
> diff --git a/include/dt-bindings/media/media-bus-format.h b/include/dt-bindings/media/media-bus-format.h
> new file mode 100644
> index 000000000000..60fc6e11dabc
> --- /dev/null
> +++ b/include/dt-bindings/media/media-bus-format.h
> @@ -0,0 +1,177 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Media Bus API header
> + *
> + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
That's not true. Your SPDX tells something entirely different.
Anyway, you did not explain why you need to copy anything anywhere.
Specifically, random hex values *are not bindings*.
Best regards,
Krzysztof
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* Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
From: Krzysztof Kozlowski @ 2024-03-22 5:57 UTC (permalink / raw)
To: Anatoliy Klymenko, Laurent Pinchart, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Michal Simek, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mauro Carvalho Chehab
Cc: Tomi Valkeinen, dri-devel, linux-arm-kernel, linux-kernel,
devicetree, linux-media
In-Reply-To: <20240321-dp-live-fmt-v3-8-d5090d796b7e@amd.com>
On 21/03/2024 21:43, Anatoliy Klymenko wrote:
> DO NOT MERGE. REFERENCE ONLY.
Why? What are you doing here and why nothing about this is explained?
>
> Add binding for AMD/Xilinx Video Timing Controller and Test Pattern
> Generator.
>
> Copy media-bus-formats.h into dt-bindings/media to suplement TPG DT node.
Still not tested. Do not send untested code to the lists.
NAK
Best regards,
Krzysztof
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