* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Kent Overstreet @ 2024-03-25 23:02 UTC (permalink / raw)
To: Boqun Feng
Cc: Linus Torvalds, Philipp Stanner, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <ZgH86EUON30lUk6m@boqun-archlinux>
On Mon, Mar 25, 2024 at 03:38:32PM -0700, Boqun Feng wrote:
> On Mon, Mar 25, 2024 at 06:09:19PM -0400, Kent Overstreet wrote:
> > On Mon, Mar 25, 2024 at 02:37:14PM -0700, Boqun Feng wrote:
> > > On Mon, Mar 25, 2024 at 05:14:41PM -0400, Kent Overstreet wrote:
> > > > On Mon, Mar 25, 2024 at 12:44:34PM -0700, Linus Torvalds wrote:
> > > > > On Mon, 25 Mar 2024 at 11:59, Kent Overstreet <kent.overstreet@linux.dev> wrote:
> > > > > >
> > > > > > To be fair, "volatile" dates from an era when we didn't have the haziest
> > > > > > understanding of what a working memory model for C would look like or
> > > > > > why we'd even want one.
> > > > >
> > > > > I don't disagree, but I find it very depressing that now that we *do*
> > > > > know about memory models etc, the C++ memory model basically doubled
> > > > > down on the same "object" model.
> > > > >
> > > > > > The way the kernel uses volatile in e.g. READ_ONCE() is fully in line
> > > > > > with modern thinking, just done with the tools available at the time. A
> > > > > > more modern version would be just
> > > > > >
> > > > > > __atomic_load_n(ptr, __ATOMIC_RELAXED)
> > >
> > > Note that Rust does have something similiar:
> > >
> > > https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
> > >
> > > pub unsafe fn read_volatile<T>(src: *const T) -> T
> > >
> > > (and also write_volatile()). So they made a good design putting the
> > > volatile on the accesses rather than the type. However, per the current
> > > Rust memory model these two primitives will be UB when data races happen
> > > :-(
> > >
> > > I mean, sure, if I use read_volatile() on an enum (whose valid values
> > > are only 0, 1, 2), and I get a value 3, and the compiler says "you have
> > > a logic bug and I refuse to compile the program correctly", I'm OK. But
> > > if I use read_volatile() to read something like a u32, and I know it's
> > > racy so my program actually handle that, I don't know any sane compiler
> > > would miss-compile, so I don't know why that has to be a UB.
> >
> > Well, if T is too big to read/write atomically then you'll get torn
> > reads, including potentially a bit representation that is not a valid T.
> >
> > Which is why the normal read_volatile<> or Volatile<> should disallow
> > that.
> >
>
> Well, why a racy read_volatile<> is UB on a T who is valid for all bit
> representations is what I was complaining about ;-)
yeah, that should not be considered UB; that should be an easy fix. Are
you talking to Rust compiler people about this stuff? I've been meaning
to make my own contacts there, but - sadly, busy as hell.
> > > > where T is any type that fits in a machine word, and the only operations
> > > > it supports are get(), set(), xchg() and cmpxchG().
> > > >
> > > > You DO NOT want it to be possible to transparantly use Volatile<T> in
> > > > place of a regular T - in exactly the same way as an atomic_t can't be
> > > > used in place of a regular integer.
> > >
> > > Yes, this is useful. But no it's not that useful, how could you use that
> > > to read another CPU's stack during some debug functions in a way you
> > > know it's racy?
> >
> > That's a pretty difficult thing to do, because you don't know the
> > _layout_ of the other CPU's stack, and even if you do it's going to be
> > changing underneath you without locking.
> >
>
> It's a debug function, I don't care whether the data is accurate, I just
> want to get much information as possible.
yeah, if you just want the typical backtrace functionality where you're
just looking for instruction pointers - that's perfectly
straightforward.
> This kinda of usage, along
> with cases where the alorigthms are racy themselves are the primary
> reasons of volatile _accesses_ instead of volatile _types_. For example,
> you want to read ahead of a counter protected by a lock:
>
> if (unlikely(READ_ONCE(cnt))) {
> spin_lock(lock);
> int c = cnt; // update of the cnt is protected by a lock.
> ...
> }
>
> because you want to skip the case where cnt == 0 in a hotpath, and you
> know someone is going to check this again in some slowpath, so
> inaccurate data doesn't matter.
That's an interesting one because in Rust cnt is "inside" the lock, you
can't access it at all without taking the lock - and usually that's
exactly right.
So to allow this we'd annotate in the type definition (with an
attribute) which fields we allow read access to without the lock, then
with some proc macro wizardry we'd get accessors that we can call without
the lock held.
So that probably wouldn't be a Volatile<T> thing, that'd be coupled with
the lock implementation because that's where the accessors would hang
off of and they'd internally probably just use mem::volatile_read().
> > So the races thare are equivalent to a bad mem::transmute(), and that is
> > very much UB.
> >
> > For a more typical usage of volatile, consider a ringbuffer with one
> > thread producing and another thread consuming. Then you've got head and
> > tail pointers, each written by one thread and read by another.
> >
> > You don't need any locking, just memory barriers and
> > READ_ONCE()/WRITE_ONCE() to update the head and tail pointers. If you
> > were writing this in Rust today the easy way would be an atomic integer,
> > but that's not really correct - you're not doing atomic operations
> > (locked arithmetic), just volatile reads and writes.
> >
>
> Confused, I don't see how Volatile<T> is better than just atomic in this
> case, since atomc_load() and atomic_store() are also not locked in any
> memory model if lockless implementation is available.
It certainly compiles to the same code, yeah. But Volatile<T> really is
the more primitive/generic concept, Atomic<T> is a specialization.
> > Volatile<T> would be Send and Sync, just like atomic integers. You don't
> > need locking if you're just working with single values that are small
> > enough for the machine to read/write atomically.
>
> So to me Volatile<T> can help in the cases where we know some memory is
> "external", for example a MMIO address, or ringbuffer between guests and
> hypervisor. But it doesn't really fix the missing functionality here:
> allow generating a plain "mov" instruction on x86 for example on _any
> valid memory_, and programmers can take care of the result.
You're talking about going completely outside the type system, though.
There is a need for that, but it's very rare and something we really
want to discourage. Usually, even with volatile access, you do know the
type - and even if you don't, you have to treat it as _something_ so
Volatile<ulong> is probably as good as anything.
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^ permalink raw reply
* Re: [PATCH v5 00/27] Update SMMUv3 to the modern iommu API (part 2/3)
From: Jason Gunthorpe @ 2024-03-25 22:44 UTC (permalink / raw)
To: Mostafa Saleh
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <ZgHnT8ZoOtzUwYwb@google.com>
On Mon, Mar 25, 2024 at 09:06:23PM +0000, Mostafa Saleh wrote:
> On Mon, Mar 25, 2024 at 11:35:03AM -0300, Jason Gunthorpe wrote:
> > On Sat, Mar 23, 2024 at 01:38:04PM +0000, Mostafa Saleh wrote:
> > > Hi Jason,
> > >
> > > On Mon, Mar 04, 2024 at 07:43:48PM -0400, Jason Gunthorpe wrote:
> > > > Continuing the work of part 1 this focuses on the CD, PASID and SVA
> > > > components:
> > > >
> > > > - attach_dev failure does not change the HW configuration.
> > > >
> > > > - Full PASID API support including:
> > > > - S1/SVA domains attached to PASIDs
> > >
> > > I am still going through the series, but I see at the end the main SMMUv3
> > > driver has set_dev_pasid operation, are there any in-tree drivers that
> > > use that? (and how can I test it).
> >
> > Not yet, but some will be coming. Currently only Intel driver supports
> > it, but Intel HW has other problems making it unusable..
> >
> > A big part of the effort here is to enable the platform ecosystem so
> > devices and drivers can use it. Moritz has access to a device that
> > can exercise this, though we are still working on it.
>
> Just out of curiosity, are there plans to upstream that driver?
I expect so, but until it passes out of the evaluation stage and into
a production stage it isn't something guaranteed. The team working on
it needs a HW/SW ecosystem to test the device on which is only now
just barely starting to exist.
> I see, thanks for confirming, I am still going through the series, but
> I now wonder if this case is worth the extra complexity, unlike the STE
> where the hitless transition was usefull in many cases.
Well, it is worth it to convert everything into 'make' functions for
sure.
At that point it is just re-using the complexity that already
exists. Implementing a special programming logic just for CD that did
the V/0=1 and EPD0 special case as open coded would be more code than
adding ops.
Jason
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* [PATCH] arm64: dts: debix-a: Remove i2c2 from base .dts
From: Laurent Pinchart @ 2024-03-25 22:50 UTC (permalink / raw)
To: devicetree, imx, linux-arm-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Jacopo Mondi, Jacopo Mondi
From: Jacopo Mondi <jacopo@jmondi.org>
The I2C2 bus is used for the CSI and DSI connectors only, no devices are
connected to it on neither the Debix Model A nor its IO board. Remove
the bus from the board's .dts and rely on display panel or camera sensor
overlsy to enable it when necessary.
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
.../boot/dts/freescale/imx8mp-debix-model-a.dts | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
index 5ac77eaf23d5..26c303b7c7fa 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
@@ -210,13 +210,6 @@ ldo5: LDO5 {
};
};
-&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-};
-
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -392,13 +385,6 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
--
Regards,
Laurent Pinchart
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* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Boqun Feng @ 2024-03-25 22:38 UTC (permalink / raw)
To: Kent Overstreet
Cc: Linus Torvalds, Philipp Stanner, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <jyijwrrzzhlsrffj37xj4sskipxqbxfewydnb3yzgybjobj6tg@cbv5y7znhm3n>
On Mon, Mar 25, 2024 at 06:09:19PM -0400, Kent Overstreet wrote:
> On Mon, Mar 25, 2024 at 02:37:14PM -0700, Boqun Feng wrote:
> > On Mon, Mar 25, 2024 at 05:14:41PM -0400, Kent Overstreet wrote:
> > > On Mon, Mar 25, 2024 at 12:44:34PM -0700, Linus Torvalds wrote:
> > > > On Mon, 25 Mar 2024 at 11:59, Kent Overstreet <kent.overstreet@linux.dev> wrote:
> > > > >
> > > > > To be fair, "volatile" dates from an era when we didn't have the haziest
> > > > > understanding of what a working memory model for C would look like or
> > > > > why we'd even want one.
> > > >
> > > > I don't disagree, but I find it very depressing that now that we *do*
> > > > know about memory models etc, the C++ memory model basically doubled
> > > > down on the same "object" model.
> > > >
> > > > > The way the kernel uses volatile in e.g. READ_ONCE() is fully in line
> > > > > with modern thinking, just done with the tools available at the time. A
> > > > > more modern version would be just
> > > > >
> > > > > __atomic_load_n(ptr, __ATOMIC_RELAXED)
> >
> > Note that Rust does have something similiar:
> >
> > https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
> >
> > pub unsafe fn read_volatile<T>(src: *const T) -> T
> >
> > (and also write_volatile()). So they made a good design putting the
> > volatile on the accesses rather than the type. However, per the current
> > Rust memory model these two primitives will be UB when data races happen
> > :-(
> >
> > I mean, sure, if I use read_volatile() on an enum (whose valid values
> > are only 0, 1, 2), and I get a value 3, and the compiler says "you have
> > a logic bug and I refuse to compile the program correctly", I'm OK. But
> > if I use read_volatile() to read something like a u32, and I know it's
> > racy so my program actually handle that, I don't know any sane compiler
> > would miss-compile, so I don't know why that has to be a UB.
>
> Well, if T is too big to read/write atomically then you'll get torn
> reads, including potentially a bit representation that is not a valid T.
>
> Which is why the normal read_volatile<> or Volatile<> should disallow
> that.
>
Well, why a racy read_volatile<> is UB on a T who is valid for all bit
representations is what I was complaining about ;-)
> > > where T is any type that fits in a machine word, and the only operations
> > > it supports are get(), set(), xchg() and cmpxchG().
> > >
> > > You DO NOT want it to be possible to transparantly use Volatile<T> in
> > > place of a regular T - in exactly the same way as an atomic_t can't be
> > > used in place of a regular integer.
> >
> > Yes, this is useful. But no it's not that useful, how could you use that
> > to read another CPU's stack during some debug functions in a way you
> > know it's racy?
>
> That's a pretty difficult thing to do, because you don't know the
> _layout_ of the other CPU's stack, and even if you do it's going to be
> changing underneath you without locking.
>
It's a debug function, I don't care whether the data is accurate, I just
want to get much information as possible. This kinda of usage, along
with cases where the alorigthms are racy themselves are the primary
reasons of volatile _accesses_ instead of volatile _types_. For example,
you want to read ahead of a counter protected by a lock:
if (unlikely(READ_ONCE(cnt))) {
spin_lock(lock);
int c = cnt; // update of the cnt is protected by a lock.
...
}
because you want to skip the case where cnt == 0 in a hotpath, and you
know someone is going to check this again in some slowpath, so
inaccurate data doesn't matter.
> So the races thare are equivalent to a bad mem::transmute(), and that is
> very much UB.
>
> For a more typical usage of volatile, consider a ringbuffer with one
> thread producing and another thread consuming. Then you've got head and
> tail pointers, each written by one thread and read by another.
>
> You don't need any locking, just memory barriers and
> READ_ONCE()/WRITE_ONCE() to update the head and tail pointers. If you
> were writing this in Rust today the easy way would be an atomic integer,
> but that's not really correct - you're not doing atomic operations
> (locked arithmetic), just volatile reads and writes.
>
Confused, I don't see how Volatile<T> is better than just atomic in this
case, since atomc_load() and atomic_store() are also not locked in any
memory model if lockless implementation is available.
> Volatile<T> would be Send and Sync, just like atomic integers. You don't
> need locking if you're just working with single values that are small
> enough for the machine to read/write atomically.
So to me Volatile<T> can help in the cases where we know some memory is
"external", for example a MMIO address, or ringbuffer between guests and
hypervisor. But it doesn't really fix the missing functionality here:
allow generating a plain "mov" instruction on x86 for example on _any
valid memory_, and programmers can take care of the result.
Regards,
Boqun
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* [PATCH] wifi: mt76: mt7603: add debugfs attr for disabling frames buffering
From: Rafał Miłecki @ 2024-03-25 22:33 UTC (permalink / raw)
To: Felix Fietkau, Lorenzo Bianconi, Ryder Lee, Shayne Chen,
Sean Wang
Cc: Kalle Valo, Matthias Brugger, AngeloGioacchino Del Regno,
linux-wireless, linux-kernel, linux-arm-kernel, linux-mediatek,
openwrt-devel, Rafał Miłecki
From: Rafał Miłecki <rafal@milecki.pl>
MT7603EN and MT7628AN were reported by multiple users to be unstable
under high traffic. Transmission of packets could stop for seconds often
leading to disconnections.
Long research & debugging revelaed a close relation between MCU
interrupts of type PKT_TYPE_TXS and slowdowns / stalls. That led to
questioning frames buffering feature.
It turns out that disabling SKBs loopback code makes mt7603 devices much
more stable under load. There are still some traffic hiccups but those
happen like once every an hour and end up in recovery in most cases.
Add a debugfs option for disabling frames buffering so users can give it
a try. If this solution yields a success we can make this feature
disabled by default.
This change was successfully tested using 2 GHz AP interface on:
1. Netgear R6220 - MT7621ST (SoC) + MT7603EN (WiFi) + MT7612EN (WiFi)
2. Xiaomi Mi Router 4C - MT7628AN (Wi-Fi SoC)
Link: https://lore.kernel.org/linux-wireless/7c96d5ee-86c1-8068-1b58-40db6087a24f@gmail.com/
Closes: https://github.com/openwrt/mt76/issues/865
Fixes: c8846e101502 ("mt76: add driver for MT7603E and MT7628/7688")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c | 2 ++
drivers/net/wireless/mediatek/mt76/mt7603/dma.c | 3 +++
drivers/net/wireless/mediatek/mt76/mt7603/init.c | 1 +
drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h | 2 ++
4 files changed, 8 insertions(+)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c
index 3967f2f05774..c80baba7a402 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7603/debugfs.c
@@ -115,4 +115,6 @@ void mt7603_init_debugfs(struct mt7603_dev *dev)
&dev->sensitivity_limit);
debugfs_create_bool("dynamic_sensitivity", 0600, dir,
&dev->dynamic_sensitivity);
+ debugfs_create_bool("frames_buffering", 0600, dir,
+ &dev->frames_buffering);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/dma.c b/drivers/net/wireless/mediatek/mt76/mt7603/dma.c
index 7a2f5d38562b..f5ab729dec31 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7603/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7603/dma.c
@@ -27,6 +27,9 @@ mt7603_rx_loopback_skb(struct mt7603_dev *dev, struct sk_buff *skb)
u32 val;
u8 tid = 0;
+ if (!dev->frames_buffering)
+ goto free;
+
if (skb->len < MT_TXD_SIZE + sizeof(struct ieee80211_hdr))
goto free;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/init.c b/drivers/net/wireless/mediatek/mt76/mt7603/init.c
index 6c55c72f28a2..5abc2618ec8b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7603/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7603/init.c
@@ -515,6 +515,7 @@ int mt7603_register_device(struct mt7603_dev *dev)
dev->slottime = 9;
dev->sensitivity_limit = 28;
dev->dynamic_sensitivity = true;
+ dev->frames_buffering = true;
ret = mt7603_init_hardware(dev);
if (ret)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h b/drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h
index 9e58df7042ad..02c88334cdc0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h
@@ -155,6 +155,8 @@ struct mt7603_dev {
u32 reset_test;
unsigned int reset_cause[__RESET_CAUSE_MAX];
+
+ bool frames_buffering;
};
extern const struct mt76_driver_ops mt7603_drv_ops;
--
2.35.3
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* Re: [PATCH 1/5] dt-bindings: iio: dac: ti,dac5571: Add DAC081C081 support
From: Laurent Pinchart @ 2024-03-25 22:23 UTC (permalink / raw)
To: Jonathan Cameron
Cc: devicetree, imx, linux-arm-kernel, Trevor Zaharichuk, Greg Lytle,
Lars-Peter Clausen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sean Nyekjaer, linux-iio
In-Reply-To: <20240325205641.GD23988@pendragon.ideasonboard.com>
On Mon, Mar 25, 2024 at 10:56:44PM +0200, Laurent Pinchart wrote:
> On Mon, Mar 25, 2024 at 08:48:57PM +0000, Jonathan Cameron wrote:
> > On Mon, 25 Mar 2024 22:32:41 +0200 Laurent Pinchart wrote:
> >
> > > The DAC081C081 is a TI DAC whose software interface is compatible with
> > > the DAC5571. It is the 8-bit version of the DAC121C081, already
> > > supported by the DAC5571 bindings. Extends the bindings to support this
> > > chip.
> > >
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> >
> > Hi Laurent,
> >
> > Given it's a part number where no one is going to guess it is compatible
> > with the DAC5571 and that we don't have a history of fallback compatibles
> > I'm fine with this change, but just wanted to ask is a fallback compatible
> > useful to you to run with older kernels?
> >
> > I should have noticed when Peter added the dac121c081. If we add a fallback
> > should do that one as well.
>
> I've indeed noticed that there should have been a fallback for
> dac121c081, but didn't stop to ponder why that wasn't the case, and just
> went along with the flow :-) I agree a fallback could be useful, which
> would then allow dropping patch 2/5 from this series (*). I can do so if
> you prefer.
And in that case, should I first introduce support in the bindings for
"ti,dac121c081", "ti,dac7571" and deprecate usage of "ti,dac121c081"
alone ?
> * This is not entirely true. While the DAC1081C081 is largely compatible
> with the DAC5573, they have different values for one of the power-down
> resistors (2.5kΩ instead of 1kΩ if I recall correctly). To be completely
> accurate, the driver should report that. We could still use the fallback
> compatible, reporting the wrong power-down resistor value.
>
> > > ---
> > > Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
> > > index 79da0323c327..e59db861e2eb 100644
> > > --- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
> > > +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml
> > > @@ -21,6 +21,7 @@ properties:
> > > - ti,dac5573
> > > - ti,dac6573
> > > - ti,dac7573
> > > + - ti,dac081c081
> > > - ti,dac121c081
> > >
> > > reg:
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Kent Overstreet @ 2024-03-25 22:09 UTC (permalink / raw)
To: Boqun Feng
Cc: Linus Torvalds, Philipp Stanner, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <ZgHuioMM1cAWNDiX@boqun-archlinux>
On Mon, Mar 25, 2024 at 02:37:14PM -0700, Boqun Feng wrote:
> On Mon, Mar 25, 2024 at 05:14:41PM -0400, Kent Overstreet wrote:
> > On Mon, Mar 25, 2024 at 12:44:34PM -0700, Linus Torvalds wrote:
> > > On Mon, 25 Mar 2024 at 11:59, Kent Overstreet <kent.overstreet@linux.dev> wrote:
> > > >
> > > > To be fair, "volatile" dates from an era when we didn't have the haziest
> > > > understanding of what a working memory model for C would look like or
> > > > why we'd even want one.
> > >
> > > I don't disagree, but I find it very depressing that now that we *do*
> > > know about memory models etc, the C++ memory model basically doubled
> > > down on the same "object" model.
> > >
> > > > The way the kernel uses volatile in e.g. READ_ONCE() is fully in line
> > > > with modern thinking, just done with the tools available at the time. A
> > > > more modern version would be just
> > > >
> > > > __atomic_load_n(ptr, __ATOMIC_RELAXED)
>
> Note that Rust does have something similiar:
>
> https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
>
> pub unsafe fn read_volatile<T>(src: *const T) -> T
>
> (and also write_volatile()). So they made a good design putting the
> volatile on the accesses rather than the type. However, per the current
> Rust memory model these two primitives will be UB when data races happen
> :-(
>
> I mean, sure, if I use read_volatile() on an enum (whose valid values
> are only 0, 1, 2), and I get a value 3, and the compiler says "you have
> a logic bug and I refuse to compile the program correctly", I'm OK. But
> if I use read_volatile() to read something like a u32, and I know it's
> racy so my program actually handle that, I don't know any sane compiler
> would miss-compile, so I don't know why that has to be a UB.
Well, if T is too big to read/write atomically then you'll get torn
reads, including potentially a bit representation that is not a valid T.
Which is why the normal read_volatile<> or Volatile<> should disallow
that.
> > where T is any type that fits in a machine word, and the only operations
> > it supports are get(), set(), xchg() and cmpxchG().
> >
> > You DO NOT want it to be possible to transparantly use Volatile<T> in
> > place of a regular T - in exactly the same way as an atomic_t can't be
> > used in place of a regular integer.
>
> Yes, this is useful. But no it's not that useful, how could you use that
> to read another CPU's stack during some debug functions in a way you
> know it's racy?
That's a pretty difficult thing to do, because you don't know the
_layout_ of the other CPU's stack, and even if you do it's going to be
changing underneath you without locking.
So the races thare are equivalent to a bad mem::transmute(), and that is
very much UB.
For a more typical usage of volatile, consider a ringbuffer with one
thread producing and another thread consuming. Then you've got head and
tail pointers, each written by one thread and read by another.
You don't need any locking, just memory barriers and
READ_ONCE()/WRITE_ONCE() to update the head and tail pointers. If you
were writing this in Rust today the easy way would be an atomic integer,
but that's not really correct - you're not doing atomic operations
(locked arithmetic), just volatile reads and writes.
Volatile<T> would be Send and Sync, just like atomic integers. You don't
need locking if you're just working with single values that are small
enough for the machine to read/write atomically.
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^ permalink raw reply
* Re: [PATCH v2 1/2] perf/arm-cmn: Decouple wp_config registers from filter group number
From: Ilkka Koskinen @ 2024-03-25 22:03 UTC (permalink / raw)
To: Robin Murphy
Cc: Ilkka Koskinen, Will Deacon, Mark Rutland, Jing Zhang,
linux-arm-kernel, linux-kernel
In-Reply-To: <69a17eff-5338-44a5-a53e-4b8142c21bf1@arm.com>
Hi Robin,
On Fri, 8 Mar 2024, Robin Murphy wrote:
> On 2024-03-07 11:09 pm, Ilkka Koskinen wrote:
>> Previously, wp_config0/2 registers were used for primary match group and
>> wp_config1/3 registers for secondary match group. In order to support
>> tertiary match group, this patch decouples the registers and the groups.
>>
>> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
>> ---
>> drivers/perf/arm-cmn.c | 125 ++++++++++++++++++++++++++++++++++-------
>> 1 file changed, 105 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c
>> index 7e3aa7e2345f..29d46e0cf1cd 100644
>> --- a/drivers/perf/arm-cmn.c
>> +++ b/drivers/perf/arm-cmn.c
>> @@ -589,6 +589,13 @@ struct arm_cmn_hw_event {
>> s8 dtc_idx[CMN_MAX_DTCS];
>> u8 num_dns;
>> u8 dtm_offset;
>> +
>> + /*
>> + * WP config registers are divided to UP and DOWN events. We need to
>> + * keep to track only one of them.
>> + */
>> + DECLARE_BITMAP(wp_cfg, 2 * CMN_MAX_XPS);
>
> What I had in mind was a wp_idx field which works the same way as dtm_idx,
> i.e. we just store the allocated index per relevant DN, since a single event
> can never use *both* watchpoints on a single XP. Each index then need only be
> 0 or 1 since they're already scoped by the watchpoint direction of the base
> event, thus we should only need one bit per XP.
Ah, I got it now.
>
>> +
>> bool wide_sel;
>> enum cmn_filter_select filter_sel;
>> };
>> @@ -1335,9 +1342,51 @@ static const struct attribute_group
>> *arm_cmn_attr_groups[] = {
>> NULL
>> };
>> -static int arm_cmn_wp_idx(struct perf_event *event)
>> +static inline unsigned int arm_cmn_get_xp_idx(struct arm_cmn *cmn,
>> + struct arm_cmn_node *xp)
>> {
>> - return CMN_EVENT_EVENTID(event) + CMN_EVENT_WP_GRP(event);
>> + return ((unsigned long) xp - (unsigned long) cmn->xps) /
>> sizeof(struct arm_cmn_node);
>> +}
>> +
>> +static int arm_cmn_find_free_wp_idx(struct arm_cmn *cmn, struct
>> arm_cmn_dtm *dtm,
>> + struct perf_event *event)
>> +{
>> + int wp_idx = CMN_EVENT_EVENTID(event);
>> +
>> + if (dtm->wp_event[wp_idx] >= 0)
>> + if (dtm->wp_event[++wp_idx] >= 0)
>> + return -ENOSPC;
>> +
>> + return wp_idx;
>> +}
>> +
>> +static int arm_cmn_get_assigned_wp_idx(struct arm_cmn *cmn,
>> + struct arm_cmn_node *xp,
>> + struct perf_event *event,
>> + struct arm_cmn_hw_event *hw)
>> +{
>> + int xp_idx = arm_cmn_get_xp_idx(cmn, xp);
>> +
>> + if (test_bit(2 * xp_idx, hw->wp_cfg))
>> + return CMN_EVENT_EVENTID(event);
>> + else if (test_bit(2 * xp_idx + 1, hw->wp_cfg))
>> + return CMN_EVENT_EVENTID(event) + 1;
>> +
>> + dev_err(cmn->dev, "Could't find the assigned wp_cfg\n");
>> + return -EINVAL;
>> +}
>
> ...and so for this we would only need more of a mild tweak to the existing
> design, something like:
>
> static int arm_cmn_get_wp_idx(struct perf_event *event, int pos)
> {
> struct arm_cmn_hw_event *hw = to_cmn_hw(event);
>
> return CMN_EVENT_EVENTID(event) + test_bit(&hw->wp_idx, pos);
> }
Yep, it simplifies it quite a bit.
>
>> +
>> +static void arm_cmn_claim_wp_idx(struct arm_cmn *cmn,
>> + struct arm_cmn_dtm *dtm,
>> + struct perf_event *event,
>> + struct arm_cmn_node *xp,
>> + int wp_idx, unsigned int dtc)
>> +{
>> + struct arm_cmn_hw_event *hw = to_cmn_hw(event);
>> + int xp_idx = arm_cmn_get_xp_idx(cmn, xp);
>> +
>> + dtm->wp_event[wp_idx] = hw->dtc_idx[dtc];
>> + set_bit(2 * xp_idx + (wp_idx & 1), hw->wp_cfg);
>
> This is recalculating way more than it needs to. It's only ever used within
> for_each_hw_dn(), which already has all the information to hand already -
> again, look at how hw->dtm_idx is managed. Furthermore I'd also prefer to
> similarly not conflate management of the per-event state with that of the DTM
> state (i.e. just have an arm_cmn_set_wp_idx() for updating the event data).
Right, I somehow forgot that hw->dn points to the right type of the node
and I can simply use the index from for_each_hw_dn().
>
>> }
>> static u32 arm_cmn_wp_config(struct perf_event *event)
>> @@ -1519,12 +1568,16 @@ static void arm_cmn_event_start(struct perf_event
>> *event, int flags)
>> writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base +
>> CMN_DT_PMCCNTR);
>> cmn->dtc[i].cc_active = true;
>> } else if (type == CMN_TYPE_WP) {
>> - int wp_idx = arm_cmn_wp_idx(event);
>> u64 val = CMN_EVENT_WP_VAL(event);
>> u64 mask = CMN_EVENT_WP_MASK(event);
>> for_each_hw_dn(hw, dn, i) {
>> void __iomem *base = dn->pmu_base +
>> CMN_DTM_OFFSET(hw->dtm_offset);
>> + int wp_idx;
>> +
>> + wp_idx = arm_cmn_get_assigned_wp_idx(cmn, dn, event,
>> hw);
>> + if (wp_idx < 0)
>> + return;
>> writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
>> writeq_relaxed(mask, base +
>> CMN_DTM_WPn_MASK(wp_idx));
>> @@ -1549,10 +1602,13 @@ static void arm_cmn_event_stop(struct perf_event
>> *event, int flags)
>> i = hw->dtc_idx[0];
>> cmn->dtc[i].cc_active = false;
>> } else if (type == CMN_TYPE_WP) {
>> - int wp_idx = arm_cmn_wp_idx(event);
>> -
>> for_each_hw_dn(hw, dn, i) {
>> void __iomem *base = dn->pmu_base +
>> CMN_DTM_OFFSET(hw->dtm_offset);
>> + int wp_idx;
>> +
>> + wp_idx = arm_cmn_get_assigned_wp_idx(cmn, dn, event,
>> hw);
>> + if (wp_idx < 0)
>> + continue;
>> writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
>> writeq_relaxed(~0ULL, base +
>> CMN_DTM_WPn_VAL(wp_idx));
>> @@ -1574,8 +1630,20 @@ struct arm_cmn_val {
>> bool cycles;
>> };
>> -static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct
>> arm_cmn_val *val,
>> - struct perf_event *event)
>> +static int arm_cmn_val_find_free_wp_config(struct perf_event *event,
>> + struct arm_cmn_val *val, int dtm)
>> +{
>> + int wp_idx = CMN_EVENT_EVENTID(event);
>> +
>> + if (val->wp[dtm][wp_idx])
>> + if (val->wp[dtm][++wp_idx])
>> + return -ENOSPC;
>> +
>> + return wp_idx;
>> +}
>> +
>> +static int arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val
>> *val,
>> + struct perf_event *event)
>
> This must never fail - the purpose of val_add_event is to fill in the val
> structure with the combination of leader and sibling events which have
> *already* passed their own event_init calls been declared valid as a group.
> The body of validate_group then does the "what if?" version to test whether
> the group would remain valid if the *current* event were to be added.
Makes perfectly sense. I fix it.
>
> The trick with the offset combine value relies on direct indexing to work, so
> I think we need to rejig the structure slightly to track distinct wp_count
> and wp_combine values (per direction) - that then becomes nicely consistent
> with the relationship between dtm_count and occupid, too.
I'm not sure if it's necessary but I do get the consistency reason though
>
>> {
>> struct arm_cmn_hw_event *hw = to_cmn_hw(event);
>> struct arm_cmn_node *dn;
>> @@ -1583,12 +1651,12 @@ static void arm_cmn_val_add_event(struct arm_cmn
>> *cmn, struct arm_cmn_val *val,
>> int i;
>> if (is_software_event(event))
>> - return;
>> + return 0;
>> type = CMN_EVENT_TYPE(event);
>> if (type == CMN_TYPE_DTC) {
>> val->cycles = true;
>> - return;
>> + return 0;
>> }
>> for_each_hw_dtc_idx(hw, dtc, idx)
>> @@ -1605,9 +1673,14 @@ static void arm_cmn_val_add_event(struct arm_cmn
>> *cmn, struct arm_cmn_val *val,
>> if (type != CMN_TYPE_WP)
>> continue;
>> - wp_idx = arm_cmn_wp_idx(event);
>> + wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
>> + if (wp_idx < 0)
>> + return -ENOSPC;
>> +
>> val->wp[dtm][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
>> }
>> +
>> + return 0;
>> }
>> static int arm_cmn_validate_group(struct arm_cmn *cmn, struct
>> perf_event *event)
>> @@ -1629,9 +1702,15 @@ static int arm_cmn_validate_group(struct arm_cmn
>> *cmn, struct perf_event *event)
>> if (!val)
>> return -ENOMEM;
>> - arm_cmn_val_add_event(cmn, val, leader);
>> - for_each_sibling_event(sibling, leader)
>> - arm_cmn_val_add_event(cmn, val, sibling);
>> + ret = arm_cmn_val_add_event(cmn, val, leader);
>> + if (ret)
>> + goto done;
>> +
>> + for_each_sibling_event(sibling, leader) {
>> + ret = arm_cmn_val_add_event(cmn, val, sibling);
>> + if (ret)
>> + goto done;
>> + }
>> type = CMN_EVENT_TYPE(event);
>> if (type == CMN_TYPE_DTC) {
>> @@ -1656,8 +1735,8 @@ static int arm_cmn_validate_group(struct arm_cmn
>> *cmn, struct perf_event *event)
>> if (type != CMN_TYPE_WP)
>> continue;
>> - wp_idx = arm_cmn_wp_idx(event);
>> - if (val->wp[dtm][wp_idx])
>> + wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
>> + if (wp_idx < 0)
>> goto done;
>> wp_cmb = val->wp[dtm][wp_idx ^ 1];
>> @@ -1772,8 +1851,11 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn,
>> struct perf_event *event,
>> struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] +
>> hw->dtm_offset;
>> unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
>> - if (type == CMN_TYPE_WP)
>> - dtm->wp_event[arm_cmn_wp_idx(event)] = -1;
>> + if (type == CMN_TYPE_WP) {
>> + int wp_idx = arm_cmn_get_assigned_wp_idx(cmn,
>> &hw->dn[i], event, hw);
>> +
>> + dtm->wp_event[wp_idx] = -1;
>> + }
>> if (hw->filter_sel > SEL_NONE)
>> hw->dn[i].occupid[hw->filter_sel].count--;
>> @@ -1782,6 +1864,7 @@ static void arm_cmn_event_clear(struct arm_cmn *cmn,
>> struct perf_event *event,
>> writel_relaxed(dtm->pmu_config_low, dtm->base +
>> CMN_DTM_PMU_CONFIG);
>> }
>> memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
>> + bitmap_zero(hw->wp_cfg, 2 * CMN_MAX_XPS);
>
> Nit: I'd rather do this in terms of sizeof() so it's harder to break in
> future. And since it's going to end up being a memset() anyway I'd then
> probably just open-code that rather than mucking about with bytes-to-bits
> calculations.
I change it.
>
>> for_each_hw_dtc_idx(hw, j, idx)
>> cmn->dtc[j].counters[idx] = NULL;
>> @@ -1835,10 +1918,11 @@ static int arm_cmn_event_add(struct perf_event
>> *event, int flags)
>> if (type == CMN_TYPE_XP) {
>> input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
>> } else if (type == CMN_TYPE_WP) {
>> - int tmp, wp_idx = arm_cmn_wp_idx(event);
>> + int tmp, wp_idx;
>> u32 cfg = arm_cmn_wp_config(event);
>> - if (dtm->wp_event[wp_idx] >= 0)
>> + wp_idx = arm_cmn_find_free_wp_idx(cmn, dtm, event);
>> + if (wp_idx < 0)
>
> TBH I'm not convinced it's even worth factoring out the "allocator" here,
> since inline it can be as simple as:
>
> int tmp, wp_idx = CMN_EVENT_EVENTID(event);
> ...
> if (dtm->wp_event[wp_idx] && dtm->wp_event[++wp_idx])
>
> (or perhaps follow the same while/if shape as for dtm_idx further up, if you
> think it's worth being more clear than concise)
I'd rather keep them in their own functions to be more consistent and
slghtly clearer.
Cheers, Ilkka
>
> Thanks,
> Robin.
>
>> goto free_dtms;
>> tmp = dtm->wp_event[wp_idx ^ 1];
>> @@ -1847,7 +1931,8 @@ static int arm_cmn_event_add(struct perf_event
>> *event, int flags)
>> goto free_dtms;
>> input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
>> - dtm->wp_event[wp_idx] = hw->dtc_idx[d];
>> +
>> + arm_cmn_claim_wp_idx(cmn, dtm, event, dn, wp_idx, d);
>> writel_relaxed(cfg, dtm->base +
>> CMN_DTM_WPn_CONFIG(wp_idx));
>> } else {
>> struct arm_cmn_nodeid nid = arm_cmn_nid(cmn, dn->id);
>
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^ permalink raw reply
* Re: [PATCH V8 00/12] soc: imx8mp: Add support for HDMI
From: Laurent Pinchart @ 2024-03-25 22:03 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Adam Ford, linux-arm-kernel, marex, alexander.stein,
frieder.schrempf, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Philipp Zabel, Vinod Koul, Kishon Vijay Abraham I,
Catalin Marinas, Will Deacon, Liu Ying, Ulf Hansson, Lucas Stach,
dri-devel, devicetree, linux-kernel, linux-phy, linux-pm
In-Reply-To: <ZgHxSHDAt7ytqDC1@tom-HP-ZBook-Fury-15-G7-Mobile-Workstation>
Hi Tommaso,
On Mon, Mar 25, 2024 at 10:48:56PM +0100, Tommaso Merciai wrote:
> Hi Adam, Lucas,
> Thanks for this series.
>
> This series make HDMI work on evk.
> All is working properly on my side.
>
> Tested on: Linux imx8mp-lpddr4-evk 6.9.0-rc1.
> Hope this help.
>
> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
The DRM side has been merged already. The only missing patches are for
the PHY, and the latest version can be found in
https://lore.kernel.org/linux-phy/20240227220444.77566-1-aford173@gmail.com/.
You can test that series and send a Tested-by tag. I'm crossing my
fingers and hoping it will be merged in v6.10.
> On Sat, Feb 03, 2024 at 10:52:40AM -0600, Adam Ford wrote:
> > The i.MX8M Plus has an HDMI controller, but it depends on two
> > other systems, the Parallel Video Interface (PVI) and the
> > HDMI PHY from Samsung. The LCDIF controller generates the display
> > and routes it to the PVI which converts passes the parallel video
> > to the HDMI bridge. The HDMI system has a corresponding power
> > domain controller whose driver was partially written, but the
> > device tree for it was never applied, so some changes to the
> > power domain should be harmless because they've not really been
> > used yet.
> >
> > This series is adapted from multiple series from Lucas Stach with
> > edits and suggestions from feedback from various series, but it
> > since it's difficult to use and test them independently,
> > I merged them into on unified series. The version history is a
> > bit ambiguous since different components were submitted at different
> > times and had different amount of retries. In an effort to merge them
> > I used the highest version attempt.
> >
> > Adam Ford (3):
> > dt-bindings: soc: imx: add missing clock and power-domains to
> > imx8mp-hdmi-blk-ctrl
> > pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix
> > domain
> > arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module
> >
> > Lucas Stach (9):
> > dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
> > phy: freescale: add Samsung HDMI PHY
> > arm64: dts: imx8mp: add HDMI power-domains
> > arm64: dts: imx8mp: add HDMI irqsteer
> > dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
> > drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
> > dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
> > drm/bridge: imx: add bridge wrapper driver for i.MX8MP DWC HDMI
> > arm64: dts: imx8mp: add HDMI display pipeline
> >
> > .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++
> > .../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 84 ++
> > .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 62 +
> > .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 22 +-
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 145 +++
> > arch/arm64/configs/defconfig | 1 +
> > drivers/gpu/drm/bridge/imx/Kconfig | 18 +
> > drivers/gpu/drm/bridge/imx/Makefile | 2 +
> > drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c | 207 ++++
> > drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 154 +++
> > drivers/phy/freescale/Kconfig | 6 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1075 +++++++++++++++++
> > drivers/pmdomain/imx/imx8mp-blk-ctrl.c | 10 +-
> > 14 files changed, 1876 insertions(+), 13 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
> > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> > create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> > create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> > create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* Re: [PATCH V8 00/12] soc: imx8mp: Add support for HDMI
From: Tommaso Merciai @ 2024-03-25 21:48 UTC (permalink / raw)
To: Adam Ford
Cc: linux-arm-kernel, marex, alexander.stein, frieder.schrempf,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Philipp Zabel, Vinod Koul, Kishon Vijay Abraham I,
Catalin Marinas, Will Deacon, Liu Ying, Ulf Hansson, Lucas Stach,
dri-devel, devicetree, linux-kernel, linux-phy, linux-pm
In-Reply-To: <20240203165307.7806-1-aford173@gmail.com>
Hi Adam, Lucas,
Thanks for this series.
This series make HDMI work on evk.
All is working properly on my side.
Tested on: Linux imx8mp-lpddr4-evk 6.9.0-rc1.
Hope this help.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Thanks & Regards,
Tommaso
On Sat, Feb 03, 2024 at 10:52:40AM -0600, Adam Ford wrote:
> The i.MX8M Plus has an HDMI controller, but it depends on two
> other systems, the Parallel Video Interface (PVI) and the
> HDMI PHY from Samsung. The LCDIF controller generates the display
> and routes it to the PVI which converts passes the parallel video
> to the HDMI bridge. The HDMI system has a corresponding power
> domain controller whose driver was partially written, but the
> device tree for it was never applied, so some changes to the
> power domain should be harmless because they've not really been
> used yet.
>
> This series is adapted from multiple series from Lucas Stach with
> edits and suggestions from feedback from various series, but it
> since it's difficult to use and test them independently,
> I merged them into on unified series. The version history is a
> bit ambiguous since different components were submitted at different
> times and had different amount of retries. In an effort to merge them
> I used the highest version attempt.
>
> Adam Ford (3):
> dt-bindings: soc: imx: add missing clock and power-domains to
> imx8mp-hdmi-blk-ctrl
> pmdomain: imx8mp-blk-ctrl: imx8mp_blk: Add fdcc clock to hdmimix
> domain
> arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module
>
> Lucas Stach (9):
> dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
> phy: freescale: add Samsung HDMI PHY
> arm64: dts: imx8mp: add HDMI power-domains
> arm64: dts: imx8mp: add HDMI irqsteer
> dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI
> drm/bridge: imx: add driver for HDMI TX Parallel Video Interface
> dt-bindings: display: imx: add binding for i.MX8MP HDMI TX
> drm/bridge: imx: add bridge wrapper driver for i.MX8MP DWC HDMI
> arm64: dts: imx8mp: add HDMI display pipeline
>
> .../display/bridge/fsl,imx8mp-hdmi-tx.yaml | 102 ++
> .../display/imx/fsl,imx8mp-hdmi-pvi.yaml | 84 ++
> .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 62 +
> .../soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml | 22 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 145 +++
> arch/arm64/configs/defconfig | 1 +
> drivers/gpu/drm/bridge/imx/Kconfig | 18 +
> drivers/gpu/drm/bridge/imx/Makefile | 2 +
> drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c | 207 ++++
> drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 154 +++
> drivers/phy/freescale/Kconfig | 6 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 1075 +++++++++++++++++
> drivers/pmdomain/imx/imx8mp-blk-ctrl.c | 10 +-
> 14 files changed, 1876 insertions(+), 13 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
> create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
> create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
> create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c
>
> --
> 2.43.0
>
>
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Boqun Feng @ 2024-03-25 21:37 UTC (permalink / raw)
To: Kent Overstreet
Cc: Linus Torvalds, Philipp Stanner, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <gewmacbbjxwsn4h54w2jfvbiq5iwr2zdm56pc3pv3rctxyd4lt@sqqa544ezmez>
On Mon, Mar 25, 2024 at 05:14:41PM -0400, Kent Overstreet wrote:
> On Mon, Mar 25, 2024 at 12:44:34PM -0700, Linus Torvalds wrote:
> > On Mon, 25 Mar 2024 at 11:59, Kent Overstreet <kent.overstreet@linux.dev> wrote:
> > >
> > > To be fair, "volatile" dates from an era when we didn't have the haziest
> > > understanding of what a working memory model for C would look like or
> > > why we'd even want one.
> >
> > I don't disagree, but I find it very depressing that now that we *do*
> > know about memory models etc, the C++ memory model basically doubled
> > down on the same "object" model.
> >
> > > The way the kernel uses volatile in e.g. READ_ONCE() is fully in line
> > > with modern thinking, just done with the tools available at the time. A
> > > more modern version would be just
> > >
> > > __atomic_load_n(ptr, __ATOMIC_RELAXED)
Note that Rust does have something similiar:
https://doc.rust-lang.org/std/ptr/fn.read_volatile.html
pub unsafe fn read_volatile<T>(src: *const T) -> T
(and also write_volatile()). So they made a good design putting the
volatile on the accesses rather than the type. However, per the current
Rust memory model these two primitives will be UB when data races happen
:-(
I mean, sure, if I use read_volatile() on an enum (whose valid values
are only 0, 1, 2), and I get a value 3, and the compiler says "you have
a logic bug and I refuse to compile the program correctly", I'm OK. But
if I use read_volatile() to read something like a u32, and I know it's
racy so my program actually handle that, I don't know any sane compiler
would miss-compile, so I don't know why that has to be a UB.
> >
> > Yes. Again, that's the *right* model in many ways, where you mark the
> > *access*, not the variable. You make it completely and utterly clear
> > that this is a very explicit access to memory.
> >
> > But that's not what C++ actually did. They went down the same old
> > "volatile object" road, and instead of marking the access, they mark
> > the object, and the way you do the above is
> >
> > std::atomic_int value;
> >
> > and then you just access 'value' and magic happens.
> >
> > EXACTLY the same way that
> >
> > volatile int value;
> >
> > works, in other words. With exactly the same downsides.
>
> Yeah that's crap. Unfortunate too, because this does need to be a type
> system thing and we have all the tools to do it correctly now.
>
> What we need is for loads and stores to be explict, and that absolutely
> can and should be a type system thing.
>
> In Rust terminology, what we want is
>
> Volatile<T>
>
> where T is any type that fits in a machine word, and the only operations
> it supports are get(), set(), xchg() and cmpxchG().
>
> You DO NOT want it to be possible to transparantly use Volatile<T> in
> place of a regular T - in exactly the same way as an atomic_t can't be
> used in place of a regular integer.
Yes, this is useful. But no it's not that useful, how could you use that
to read another CPU's stack during some debug functions in a way you
know it's racy?
Regards,
Boqun
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^ permalink raw reply
* [PATCH v6 1/1] ARM: dts: imx: Add UNI-T UTi260B thermal camera board
From: Sebastian Reichel @ 2024-03-25 21:19 UTC (permalink / raw)
To: Sebastian Reichel, Shawn Guo, Sascha Hauer, Fabio Estevam
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Pengutronix Kernel Team, imx, linux-arm-kernel, devicetree,
linux-kernel, Stefan Wahren
In-Reply-To: <20240325212402.150906-1-sre@kernel.org>
Add DT for the UNI-T UTi260B handheld thermal camera.
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
arch/arm/boot/dts/nxp/imx/Makefile | 1 +
arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts | 566 ++++++++++++++++++
2 files changed, 567 insertions(+)
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index 4052cad859fa..598361d0632e 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -355,6 +355,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-tarragon-slavext.dtb \
imx6ull-tqma6ull2-mba6ulx.dtb \
imx6ull-tqma6ull2l-mba6ulx.dtb \
+ imx6ull-uti260b.dtb \
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
new file mode 100644
index 000000000000..e4576d509a5b
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (C) 2022-2024 Sebastian Reichel <sre@kernel.org>
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/imx6ul-clock.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "UNI-T UTi260B Thermal Camera";
+ compatible = "uni-t,uti260b", "fsl,imx6ull";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ panel_backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ enable-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_backlight_enable>;
+ power-supply = <®_vsd>;
+ pwms = <&pwm1 0 50000 0>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ /* generic 26650 battery */
+ device-chemistry = "lithium-ion";
+ charge-full-design-microamp-hours = <5000000>;
+ voltage-max-design-microvolt = <4200000>;
+ voltage-min-design-microvolt = <3300000>;
+ };
+
+ tp5000: charger {
+ compatible = "gpio-charger";
+ charger-type = "usb-sdp";
+ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_charger_stat1>;
+ };
+
+ fuel-gauge {
+ compatible = "adc-battery";
+ charged-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ io-channel-names = "voltage";
+ io-channels = <&adc1 7>;
+ monitored-battery = <&battery>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_charger_stat2>;
+ power-supplies = <&tp5000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_gpio_keys>;
+ autorepeat;
+
+ up-key {
+ label = "Up";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ down-key {
+ label = "Down";
+ gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ left-key {
+ label = "Left";
+ gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LEFT>;
+ };
+
+ right-key {
+ label = "Right";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RIGHT>;
+ };
+
+ ok-key {
+ label = "Ok";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ return-key {
+ label = "Return";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ESC>;
+ };
+
+ play-key {
+ label = "Media";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_MEDIA>;
+ };
+
+ trigger-key {
+ label = "Trigger";
+ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_TRIGGER>;
+ };
+
+ power-key {
+ label = "Power";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+
+ light-key {
+ label = "Light";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LIGHTS_TOGGLE>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_led_ctrl>;
+
+ led {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_FLASH;
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_poweroff>;
+ };
+
+ reg_vref: regulator-vref-4v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VREF_4V2";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ };
+
+ reg_vsd: regulator-vsd {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ #io-channel-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_adc>;
+ vref-supply = <®_vref>;
+ status = "okay";
+};
+
+&csi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_csi>;
+ status = "okay";
+
+ port {
+ parallel_from_gc0308: endpoint {
+ remote-endpoint = <&gc0308_to_parallel>;
+ };
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_spi3>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "inanbo,t28cp45tn89-v17";
+ reg = <0>;
+ backlight = <&panel_backlight>;
+ power-supply = <®_vsd>;
+ spi-cpha;
+ spi-cpol;
+ spi-max-frequency = <1000000>;
+ spi-rx-bus-width = <0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+};
+
+&gpio1 {
+ ir-reset-hog {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ line-name = "ir-reset-gpio";
+ output-low;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_ir_reset>;
+ };
+};
+
+&gpio2 {
+ /* configuring this to output-high results in poweroff */
+ power-en-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "power-en-gpio";
+ output-low;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_poweroff2>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_i2c1>;
+ status = "okay";
+
+ camera@21 {
+ compatible = "galaxycore,gc0308";
+ reg = <0x21>;
+ clocks = <&clks IMX6UL_CLK_CSI>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_gc0308>;
+ powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ vdd28-supply = <®_vsd>;
+
+ port {
+ gc0308_to_parallel: endpoint {
+ remote-endpoint = <¶llel_from_gc0308>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <1>; /* active high */
+ vsync-active = <1>; /* active high */
+ data-active = <1>; /* active high */
+ pclk-sample = <1>; /* sample on rising edge */
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_i2c2>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&lcdif {
+ assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_lcd_data>, <&mux_lcd_ctrl>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_pwm>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_uart>;
+ status = "okay";
+};
+
+&usbotg1 {
+ /* USB-C connector */
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ /* thermal sensor */
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+ fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+ /* MicroSD */
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&mux_sdhc1>, <&mux_sdhc1_cd>;
+ pinctrl-1 = <&mux_sdhc1_100mhz>, <&mux_sdhc1_cd>;
+ pinctrl-2 = <&mux_sdhc1_200mhz>, <&mux_sdhc1_cd>;
+ wakeup-source;
+ vmmc-supply = <®_vsd>;
+ status = "okay";
+};
+
+&usdhc2 {
+ /* eMMC */
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_sdhc2>;
+ wakeup-source;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mux_wdog>;
+};
+
+&iomuxc {
+ mux_adc: adcgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0xb0
+ >;
+ };
+
+ mux_backlight_enable: blenablegrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3008
+ >;
+ };
+
+ mux_charger_stat1: charger1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3008
+ >;
+ };
+
+ mux_charger_stat2: charger2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x3008
+ >;
+ };
+
+ mux_csi: csi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
+ MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
+ MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
+ MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
+ MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
+ MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
+ MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
+ MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
+ MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
+ MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
+ MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
+ >;
+ };
+
+ mux_gc0308: gc0308grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1e038
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b088
+ MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x1b088
+ >;
+ };
+
+ mux_gpio_keys: gpiokeygrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x3008
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x3008
+ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x3008
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x3008
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x3008
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x3008
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x3008
+ MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x3008
+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x3008
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x3008
+ >;
+ };
+
+ mux_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ mux_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8a8
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8a8
+ >;
+ };
+
+ mux_ir_reset: irresetgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3008
+ >;
+ };
+
+ mux_lcd_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ >;
+ };
+
+ mux_lcd_data: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ >;
+ };
+
+ mux_led_ctrl: ledctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x3008
+ >;
+ };
+
+ mux_poweroff: poweroffgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x3008
+ >;
+ };
+
+ mux_poweroff2: poweroff2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x3008
+ >;
+ };
+
+ mux_pwm: pwm1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+ >;
+ };
+
+ mux_sdhc1: sdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ mux_sdhc1_100mhz: sdhc1-100mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ mux_sdhc1_200mhz: sdhc1-200mhz-grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+
+ mux_sdhc1_cd: sdhc1-cd-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ >;
+ };
+
+ mux_sdhc2: sdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
+
+ mux_spi3: ecspi3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1
+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1
+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x3008
+ >;
+ };
+
+ mux_uart: uartgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ mux_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+};
--
2.43.0
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* [PATCH v6 0/1] UNI-T UTi260B support
From: Sebastian Reichel @ 2024-03-25 21:19 UTC (permalink / raw)
To: Sebastian Reichel, Shawn Guo, Sascha Hauer, Fabio Estevam
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Pengutronix Kernel Team, imx, linux-arm-kernel, devicetree,
linux-kernel, Sebastian Reichel
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Hi,
This adds adds support for the i.MX6ULL based UNI-T UTi260B thermal camera.
The DT is based on reverse engineered information. More information about
the device can be found in this presentation from Embedded Recipes 2023:
* https://embedded-recipes.org/2023/wp-content/uploads/2023/10/Running-FOSS-on-a-Thermal-Camera-Sebastian-Reichel-compressed.pdf
* https://www.youtube.com/watch?v=uvObsCG-Cqo
make -j4 CHECK_DTBS=y nxp/imx/imx6ull-uti260b.dtb reports no issues.
I also prepared a branch with these patches (and a minimal kernel config)
and published it here:
https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-misc.git/log/?h=uti260b
Changes since PATCHv5:
* https://lore.kernel.org/all/20240226212740.2019837-1-sre@kernel.org/
- rebase to v6.9-rc1
- drop merged patches (all but DTS)
Changes since PATCHv4:
* https://lore.kernel.org/all/20240224213240.1854709-1-sre@kernel.org/
- drop merged patches
- use new NXP mailing list
- UTi260B board DT: change patch title
- UTi260B board DT: fix node order
Changes since PATCHv3:
* https://lore.kernel.org/all/20240216223654.1312880-1-sre@kernel.org/
- weim binding: use " instead of '
- weim binding: use "if: not: required: - foo" instead of "if: properties: foo: false"
- imx6ull-uti260b.dts: merge ecspi3_csgrp into ecspi3grp
- collect Reviewed-by from Krzysztof Kozlowski
Changes since PATCHv2:
* https://lore.kernel.org/all/20240213010347.1075251-1-sre@kernel.org/
- drop fsl,imx-asrc YAML binding conversion (merged)
- collect a bunch of Reviewed-by/Acked-by tags
- weim DT binding: fix issue with requirements
- xnur-gpio -> xnur-gpios change: Improve patch long description
Changes since PATCHv1:
* https://lore.kernel.org/all/20240210012114.489102-1-sre@kernel.org/
- uni-t,imx6ull-uti260b -> uni-t,uti260b
- add Acked-by for uni-t vendor prefix
- add Acked-by for HDMI audio index fix
- add Acked-by for LCDIF power-domain requirement drop
- anatop DT binding: Fixed indentation in example
- anatop DT binding: Described IRQs
- touchscreen DT binding: change tsc@ to touchscreen@ in example
- touchscreen DT binding: change xnur-gpio to xnur-gpios
- weim DT binding: drop acme,whatever example
- weim DT binding: use flash@ instead of nor@
- weim DT binding: update weim.txt reference in arcx,anybus-controller.txt
- weim DT binding: switch to memory-controller binding
- fsl,imx-asrc DT binding: fix ASoC patch subject prefix
- fsl,imx-asrc DT binding: add constraints
- add new patch fixing xnur-gpio(s) in all i.MX6UL board DT files
- add new patch fixing touchscreen nodename in i.MX6UL SoC DT file
- add new patch fixing weim nodename in all i.MX SoC DT files
- device DTS: use color/functions for the led
- device DTS: increase SPI speed
- device DTS: add comment for SD / eMMC node
Unadressed feedback from PATCHv1:
- anatop phandle vs parent: technically it makes sense to just use the
parent, but this driver is only used by i.MX6. The current code makes
use of the phandle, so we cannot drop it because of backwards
compatibility. So I don't see a point in deprecating this property.
- touchscreen binding: I kept measure-delay-time and pre-charge-time
values in hex, since that is being used everywhere and the unit
is unknown. The values are directly written into HW registers and
the i.MX6UL TRM does not provide any hints about the unit. I do not
have an i.MX6UL device with a touchsreen, so I cannot test either.
- regulator name in DT: I did not rename the regulators to just
"regulator", since the nodename must be unique.
Greetings,
-- Sebastian
Sebastian Reichel (1):
ARM: dts: imx: Add UNI-T UTi260B thermal camera board
arch/arm/boot/dts/nxp/imx/Makefile | 1 +
arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts | 566 ++++++++++++++++++
2 files changed, 567 insertions(+)
create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts
--
2.43.0
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Kent Overstreet @ 2024-03-25 21:14 UTC (permalink / raw)
To: Linus Torvalds
Cc: Philipp Stanner, Boqun Feng, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <CAHk-=wgLGWBXvNODAkzkVHEj7zrrnTq_hzMft62nKNkaL89ZGQ@mail.gmail.com>
On Mon, Mar 25, 2024 at 12:44:34PM -0700, Linus Torvalds wrote:
> On Mon, 25 Mar 2024 at 11:59, Kent Overstreet <kent.overstreet@linux.dev> wrote:
> >
> > To be fair, "volatile" dates from an era when we didn't have the haziest
> > understanding of what a working memory model for C would look like or
> > why we'd even want one.
>
> I don't disagree, but I find it very depressing that now that we *do*
> know about memory models etc, the C++ memory model basically doubled
> down on the same "object" model.
>
> > The way the kernel uses volatile in e.g. READ_ONCE() is fully in line
> > with modern thinking, just done with the tools available at the time. A
> > more modern version would be just
> >
> > __atomic_load_n(ptr, __ATOMIC_RELAXED)
>
> Yes. Again, that's the *right* model in many ways, where you mark the
> *access*, not the variable. You make it completely and utterly clear
> that this is a very explicit access to memory.
>
> But that's not what C++ actually did. They went down the same old
> "volatile object" road, and instead of marking the access, they mark
> the object, and the way you do the above is
>
> std::atomic_int value;
>
> and then you just access 'value' and magic happens.
>
> EXACTLY the same way that
>
> volatile int value;
>
> works, in other words. With exactly the same downsides.
Yeah that's crap. Unfortunate too, because this does need to be a type
system thing and we have all the tools to do it correctly now.
What we need is for loads and stores to be explict, and that absolutely
can and should be a type system thing.
In Rust terminology, what we want is
Volatile<T>
where T is any type that fits in a machine word, and the only operations
it supports are get(), set(), xchg() and cmpxchG().
You DO NOT want it to be possible to transparantly use Volatile<T> in
place of a regular T - in exactly the same way as an atomic_t can't be
used in place of a regular integer.
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* [PATCH v2 4/4] dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-25 21:10 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240325-rtc-yaml-v2-0-ff9f68f43dbc@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.txt | 21 --------
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml | 60 ++++++++++++++++++++++
2 files changed, 60 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
deleted file mode 100644
index 3c97bd180592..000000000000
--- a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-NXP LPC1788 real-time clock
-
-The LPC1788 RTC provides calendar and clock functionality
-together with periodic tick and alarm interrupt support.
-
-Required properties:
-- compatible : must contain "nxp,lpc1788-rtc"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A single interrupt specifier.
-- clocks : Must contain clock specifiers for rtc and register clock
-- clock-names : Must contain "rtc" and "reg"
- See ../clocks/clock-bindings.txt for details.
-
-Example:
-rtc: rtc@40046000 {
- compatible = "nxp,lpc1788-rtc";
- reg = <0x40046000 0x1000>;
- interrupts = <47>;
- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "rtc", "reg";
-};
diff --git a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
new file mode 100644
index 000000000000..db900617f1e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1788 real-time clock
+
+description:
+ The LPC1788 RTC provides calendar and clock functionality
+ together with periodic tick and alarm interrupt support.
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: nxp,lpc1788-rtc
+
+ reg:
+ description:
+ Base address and length of the register region.
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RTC clock
+ - description: Register clock
+
+ clock-names:
+ items:
+ - const: rtc
+ - const: reg
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc18xx-ccu.h>
+
+ rtc@40046000 {
+ compatible = "nxp,lpc1788-rtc";
+ reg = <0x40046000 0x1000>;
+ clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "rtc", "reg";
+ interrupts = <47>;
+ };
--
2.40.1
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* [PATCH v2 3/4] dt-bindings: rtc: digicolor-rtc: move to trivial-rtc
From: Javier Carrasco @ 2024-03-25 21:10 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240325-rtc-yaml-v2-0-ff9f68f43dbc@gmail.com>
Convert existing binding to dtschema to support validation.
This device meets the requirements to be moved to trivial-rtc
(compatible, reg and a single interrupt).
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
Documentation/devicetree/bindings/rtc/digicolor-rtc.txt | 17 -----------------
Documentation/devicetree/bindings/rtc/trivial-rtc.yaml | 2 ++
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt b/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
deleted file mode 100644
index d464986012cd..000000000000
--- a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Conexant Digicolor Real Time Clock controller
-
-This binding currently supports the CX92755 SoC.
-
-Required properties:
-- compatible: should be "cnxt,cx92755-rtc"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: rtc alarm interrupt
-
-Example:
-
- rtc@f0000c30 {
- compatible = "cnxt,cx92755-rtc";
- reg = <0xf0000c30 0x18>;
- interrupts = <25>;
- };
diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
index c9e3c5262c21..a3db41c5207c 100644
--- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml
@@ -24,6 +24,8 @@ properties:
- abracon,abb5zes3
# AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
- abracon,abeoz9
+ # Conexant Digicolor Real Time Clock Controller
+ - cnxt,cx92755-rtc
# I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
- dallas,ds1374
# Dallas DS1672 Real-time Clock
--
2.40.1
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* [PATCH v2 2/4] dt-bindings: rtc: alphascale,asm9260-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-25 21:10 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240325-rtc-yaml-v2-0-ff9f68f43dbc@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../bindings/rtc/alphascale,asm9260-rtc.txt | 19 --------
.../bindings/rtc/alphascale,asm9260-rtc.yaml | 52 ++++++++++++++++++++++
2 files changed, 52 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
deleted file mode 100644
index 76ebca568db9..000000000000
--- a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Alphascale asm9260 SoC Real Time Clock
-
-Required properties:
-- compatible: Should be "alphascale,asm9260-rtc"
-- reg: Physical base address of the controller and length
- of memory mapped region.
-- interrupts: IRQ line for the RTC.
-- clocks: Reference to the clock entry.
-- clock-names: should contain:
- * "ahb" for the SoC RTC clock
-
-Example:
-rtc0: rtc@800a0000 {
- compatible = "alphascale,asm9260-rtc";
- reg = <0x800a0000 0x100>;
- clocks = <&acc CLKID_AHB_RTC>;
- clock-names = "ahb";
- interrupts = <2>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
new file mode 100644
index 000000000000..8acd5e94fd58
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/alphascale,asm9260-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Alphascale asm9260 SoC Real Time Clock
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: alphascale,asm9260-rtc
+
+ reg:
+ description:
+ Base address and length of the register region.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ahb
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/alphascale,asm9260.h>
+
+ rtc@800a0000 {
+ compatible = "alphascale,asm9260-rtc";
+ reg = <0x800a0000 0x100>;
+ clocks = <&acc CLKID_AHB_RTC>;
+ clock-names = "ahb";
+ interrupts = <2>;
+ };
--
2.40.1
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* [PATCH v2 1/4] dt-bindings: rtc: armada-380-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-25 21:10 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240325-rtc-yaml-v2-0-ff9f68f43dbc@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../devicetree/bindings/rtc/armada-380-rtc.txt | 24 ----------
.../bindings/rtc/marvell,armada-380-rtc.yaml | 51 ++++++++++++++++++++++
2 files changed, 51 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
deleted file mode 100644
index c3c9a1226f9a..000000000000
--- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Real Time Clock of the Armada 38x/7K/8K SoCs
-
-RTC controller for the Armada 38x, 7K and 8K SoCs
-
-Required properties:
-- compatible : Should be one of the following:
- "marvell,armada-380-rtc" for Armada 38x SoC
- "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
-- reg: a list of base address and size pairs, one for each entry in
- reg-names
-- reg names: should contain:
- * "rtc" for the RTC registers
- * "rtc-soc" for the SoC related registers and among them the one
- related to the interrupt.
-- interrupts: IRQ line for the RTC.
-
-Example:
-
-rtc@a3800 {
- compatible = "marvell,armada-380-rtc";
- reg = <0xa3800 0x20>, <0x184a0 0x0c>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
new file mode 100644
index 000000000000..adf3ba0cd09f
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RTC controller for the Armada 38x, 7K and 8K SoCs
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - marvell,armada-380-rtc
+ - marvell,armada-8k-rtc
+
+ reg:
+ items:
+ - description: RTC base address size
+ - description: Base address and size of SoC related registers
+
+ reg-names:
+ items:
+ - const: rtc
+ - const: rtc-soc
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtc@a3800 {
+ compatible = "marvell,armada-380-rtc";
+ reg = <0xa3800 0x20>, <0x184a0 0x0c>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.40.1
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* [PATCH v2 0/4] dt-bindings: rtc: convert multiple devices to dtschema
From: Javier Carrasco @ 2024-03-25 21:10 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
This series converts the following existing bindings to dtschema:
- armada-380-rtc
- alphascale,asm9260
- digicolor-rtc (moved to trivial-rtc)
- nxp,lpc1788-rtc
All bindings include at least one compatible that is referenced in the
existing dts (arch/arm). Those dts could be tested against the new
bindings.
It might be worth mentioning that the reference to nxp,lpc1788-rtc in
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi also includes another compatible
called nxp,lpc1850-rtc, which is not documented or supported by existing
drivers. That generates a warning when testing against nxp,lpc1788-rtc.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
Changes in v2:
- General: reference to rtc.yaml
- digicolor-rtc: move to trivial-rtc
- Link to v1: https://lore.kernel.org/r/20240323-rtc-yaml-v1-0-0c5d12b1b89d@gmail.com
---
Javier Carrasco (4):
dt-bindings: rtc: armada-380-rtc: convert to dtschema
dt-bindings: rtc: alphascale,asm9260-rtc: convert to dtschema
dt-bindings: rtc: digicolor-rtc: move to trivial-rtc
dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
.../bindings/rtc/alphascale,asm9260-rtc.txt | 19 -------
.../bindings/rtc/alphascale,asm9260-rtc.yaml | 52 +++++++++++++++++++
.../devicetree/bindings/rtc/armada-380-rtc.txt | 24 ---------
.../devicetree/bindings/rtc/digicolor-rtc.txt | 17 ------
.../bindings/rtc/marvell,armada-380-rtc.yaml | 51 ++++++++++++++++++
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.txt | 21 --------
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml | 60 ++++++++++++++++++++++
.../devicetree/bindings/rtc/trivial-rtc.yaml | 2 +
8 files changed, 165 insertions(+), 81 deletions(-)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240322-rtc-yaml-473335cbf911
Best regards,
--
Javier Carrasco <javier.carrasco.cruz@gmail.com>
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^ permalink raw reply
* Re: [PATCH v5 00/27] Update SMMUv3 to the modern iommu API (part 2/3)
From: Mostafa Saleh @ 2024-03-25 21:06 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <20240325143503.GF110546@nvidia.com>
On Mon, Mar 25, 2024 at 11:35:03AM -0300, Jason Gunthorpe wrote:
> On Sat, Mar 23, 2024 at 01:38:04PM +0000, Mostafa Saleh wrote:
> > Hi Jason,
> >
> > On Mon, Mar 04, 2024 at 07:43:48PM -0400, Jason Gunthorpe wrote:
> > > Continuing the work of part 1 this focuses on the CD, PASID and SVA
> > > components:
> > >
> > > - attach_dev failure does not change the HW configuration.
> > >
> > > - Full PASID API support including:
> > > - S1/SVA domains attached to PASIDs
> >
> > I am still going through the series, but I see at the end the main SMMUv3
> > driver has set_dev_pasid operation, are there any in-tree drivers that
> > use that? (and how can I test it).
>
> Not yet, but some will be coming. Currently only Intel driver supports
> it, but Intel HW has other problems making it unusable..
>
> A big part of the effort here is to enable the platform ecosystem so
> devices and drivers can use it. Moritz has access to a device that
> can exercise this, though we are still working on it.
>
Just out of curiosity, are there plans to upstream that driver?
> > > - IDENTITY/BLOCKED/S1 attached to RID
> > > - Change of the RID domain while PASIDs are attached
> > >
> > > - Streamlined SVA support using the core infrastructure
> > >
> > > - Hitless, whenever possible, change between two domains
> >
> > Can you please clarify what cases are expected to be hitless?
> > From what I see if ASID and TTB0 changes that would break the CD.
>
> Right. For CD it is only the SVA mm release flow, setting EPD0.
>
I see, thanks for confirming, I am still going through the series, but
I now wonder if this case is worth the extra complexity, unlike the STE
where the hitless transition was usefull in many cases.
Thanks,
Mostafa.
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^ permalink raw reply
* Re: [PATCH v5 08/27] iommu/arm-smmu-v3: Move allocation of the cdtable into arm_smmu_get_cd_ptr()
From: Mostafa Saleh @ 2024-03-25 21:03 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <20240325142128.GC110546@nvidia.com>
On Mon, Mar 25, 2024 at 11:21:28AM -0300, Jason Gunthorpe wrote:
> On Fri, Mar 22, 2024 at 07:07:10PM +0000, Mostafa Saleh wrote:
> > Hi Jason,
> >
> > On Mon, Mar 04, 2024 at 07:43:56PM -0400, Jason Gunthorpe wrote:
> > > No reason to force callers to do two steps. Make arm_smmu_get_cd_ptr()
> > > able to return an entry in all cases except OOM
> >
> > I believe the current code is more clear, as it is explicit about which path
> > is expected to allocate.
>
> I think we had this allocate vs no allocate discussion before on
> something else..
>
> It would be good to make *full* allocate/noallocate variants of
> get_cd_ptr() and the cases that must never allocate call the no
> allocate variation. There are some issues with GFP_KERNEL/ATOMIC that
> are a bit hard to understand as well.
>
> This is a bigger issue than just the cd_table, as even the leafs
> should not allocate.
>
> > As there are many callers for arm_smmu_get_cd_ptr() directly and indirectly,
> > and it read-modify-writes the cdtable, it would be a pain to debug not
> > knowing which one could allocate, and this patch only abstracts one
> > allocating call, so it is not much code less.
>
> > For example, (again I don’t know much about SVA) I think there might be a
> > race condition as follows:
> > arm_smmu_attach_dev
> > arm_smmu_domain_finalise() => set domain stage
> > [....]
> > arm_smmu_get_cd_ptr() => RMW master->cd_table
> >
> > arm_smmu_sva_set_dev_pasid
> > __arm_smmu_sva_bind
> > Check stage is valid
> > [...]
> > arm_smmu_write_ctx_desc
> > arm_smmu_get_cd_ptr => RMW master->cd_table
> >
> > If this path is true though, I guess the in current code, we would need some
> > barriers in arm_smmu_get_cd_ptr(), arm_smmu_get_cd_ptr()
>
> Both of those functions are called under the group mutex held by the
> core code.
>
> The only valid condition to change the CD table backing memory is when
> the group mutex is held. We now have iommu_group_mutex_assert() so an
> alloc/noalloc split can call that test on the alloc side which is
> motivation enough to do it, IMHO.
>
> I will split the function and sort it all out, but I will still
> integrate the cd_table allocation into the allocating version of
> get_cd_ptr().
I prefer that, as it makes it clear which paths expect to allocate
and which not.
> Thanks,
> Jason
Thanks,
Mostafa
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* Re: [PATCH v5 06/27] iommu/arm-smmu-v3: Consolidate clearing a CD table entry
From: Mostafa Saleh @ 2024-03-25 21:02 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <20240325141433.GB110546@nvidia.com>
On Mon, Mar 25, 2024 at 11:14:33AM -0300, Jason Gunthorpe wrote:
> On Fri, Mar 22, 2024 at 06:36:17PM +0000, Mostafa Saleh wrote:
> > > +void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid)
> > > +{
> > > + struct arm_smmu_cd target = {};
> > > + struct arm_smmu_cd *cdptr;
> > > +
> > > + if (!master->cd_table.cdtab)
> > > + return;
> > > + cdptr = arm_smmu_get_cd_ptr(master, ssid);
> > > + if (WARN_ON(!cdptr))
> > > + return;
> >
> > I don’t understand the SVA code enough, but AFAICT, arm_smmu_sva_set_dev_pasid
> > can allocate the L2 CD table through arm_smmu_write_ctx_desc.
>
> Yes
>
> > And if it failed
> > before allocating the CD table, then remove_dev_pasid would be
> > called,
>
> If it fails the core code should not call remove_dev_pasid() on a
> domain that was never attached. There is an obscure error unwinding
> issue in the core code Yi is looking to fix regarding multi-device
> PASID groups, but it is not a driver issue..
>
I see, thanks for clarifying.
> > which warns here, the previous code would tolerate that, but that
> > might regress on systems with panic_on_warn, so I am not sure if
> > that is necessary.
>
> Right, if it does hit it signals there is some error unwinding bug in
> the core code that should be resolved.
>
> > Otherwise, Reviewed-by: Mostafa Saleh <smostafa@google.com>
>
> Thanks,
> Jason
Thanks,
Mostafa
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* Re: [PATCH v5 04/27] iommu/arm-smmu-v3: Add an ops indirection to the STE code
From: Mostafa Saleh @ 2024-03-25 21:01 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <20240325141132.GA110546@nvidia.com>
On Mon, Mar 25, 2024 at 11:11:32AM -0300, Jason Gunthorpe wrote:
> On Fri, Mar 22, 2024 at 06:14:24PM +0000, Mostafa Saleh wrote:
> > > @@ -1027,57 +1038,55 @@ static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent,
> > > * unused_update is an intermediate value of entry that has unused bits set to
> > > * their new values.
> > > */
> > > -static u8 arm_smmu_entry_qword_diff(const struct arm_smmu_ste *entry,
> > > - const struct arm_smmu_ste *target,
> > > - struct arm_smmu_ste *unused_update)
> > > +static u8 arm_smmu_entry_qword_diff(struct arm_smmu_entry_writer *writer,
> > > + const __le64 *entry, const __le64 *target,
> > > + __le64 *unused_update)
> > > {
> > > - struct arm_smmu_ste target_used = {};
> > > - struct arm_smmu_ste cur_used = {};
> > > + __le64 target_used[NUM_ENTRY_QWORDS] = {};
> > > + __le64 cur_used[NUM_ENTRY_QWORDS] = {};
> > This is confusing to me, the function was modified to be generic, so its has
> > args are __le64 * instead of struct arm_smmu_ste *.
>
> Right
>
> > But NUM_ENTRY_QWORDS is defined as “(sizeof(struct arm_smmu_ste) / sizeof(u64))”
> > and in the same function writer->ops->num_entry_qwords is used
> > nterchangeably,
>
> Right
>
> > I understand that this not a constant and the compiler would complain.
> > But since for any other num_entry_qwords larger than NUM_ENTRY_QWORDS it fails,
> > and we know STEs and CDs both have the same size, we simplify the code and make
> > it a constant everywhere.
>
> So you say to get rid of num_entry_qwords and just use the constant?
In my opinion, yes, that looks easier to understand, and avoids the MAX
stuff as there is no reason for the extra generalisation.
> > I see in the next patch, that this is redefined to be the max between STE and
> > CD, but again, this hardware and it never changes, so my opinion is to simplify
> > the code, as there is no need to generalize this part.
>
> Yes, we need a constant.
>
> It would look like this, it is a little bit simpler:
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index a54062faccde38..d015f41900d802 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -63,9 +63,9 @@ enum arm_smmu_msi_index {
> ARM_SMMU_MAX_MSIS,
> };
>
> -#define NUM_ENTRY_QWORDS \
> - (max(sizeof(struct arm_smmu_ste), sizeof(struct arm_smmu_cd)) / \
> - sizeof(u64))
> +#define NUM_ENTRY_QWORDS 8
> +static_assert(sizeof(struct arm_smmu_ste) == NUM_ENTRY_QWORDS * sizeof(u64));
> +static_assert(sizeof(struct arm_smmu_cd) == NUM_ENTRY_QWORDS * sizeof(u64));
>
> static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
> [EVTQ_MSI_INDEX] = {
> @@ -1045,7 +1045,7 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu_entry_writer *writer,
> writer->ops->get_used(entry, cur_used);
> writer->ops->get_used(target, target_used);
>
> - for (i = 0; i != writer->ops->num_entry_qwords; i++) {
> + for (i = 0; i != NUM_ENTRY_QWORDS; i++) {
> /*
> * Check that masks are up to date, the make functions are not
> * allowed to set a bit to 1 if the used function doesn't say it
> @@ -1114,7 +1114,6 @@ static bool entry_set(struct arm_smmu_entry_writer *writer, __le64 *entry,
> void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *entry,
> const __le64 *target)
> {
> - unsigned int num_entry_qwords = writer->ops->num_entry_qwords;
> __le64 unused_update[NUM_ENTRY_QWORDS];
> u8 used_qword_diff;
>
> @@ -1137,9 +1136,9 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *entry,
> */
> unused_update[critical_qword_index] =
> entry[critical_qword_index];
> - entry_set(writer, entry, unused_update, 0, num_entry_qwords);
> + entry_set(writer, entry, unused_update, 0, NUM_ENTRY_QWORDS);
> entry_set(writer, entry, target, critical_qword_index, 1);
> - entry_set(writer, entry, target, 0, num_entry_qwords);
> + entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS);
> } else if (used_qword_diff) {
> /*
> * At least two qwords need their inuse bits to be changed. This
> @@ -1148,7 +1147,7 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *entry,
> */
> unused_update[0] = entry[0] & (~writer->ops->v_bit);
> entry_set(writer, entry, unused_update, 0, 1);
> - entry_set(writer, entry, target, 1, num_entry_qwords - 1);
> + entry_set(writer, entry, target, 1, NUM_ENTRY_QWORDS - 1);
> entry_set(writer, entry, target, 0, 1);
> } else {
> /*
> @@ -1157,7 +1156,7 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *entry,
> * compute_qword_diff().
> */
> WARN_ON_ONCE(
> - entry_set(writer, entry, target, 0, num_entry_qwords));
> + entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS));
> }
> }
>
> @@ -1272,7 +1271,6 @@ static const struct arm_smmu_entry_writer_ops arm_smmu_cd_writer_ops = {
> .sync = arm_smmu_cd_writer_sync_entry,
> .get_used = arm_smmu_get_cd_used,
> .v_bit = cpu_to_le64(CTXDESC_CD_0_V),
> - .num_entry_qwords = sizeof(struct arm_smmu_cd) / sizeof(u64),
> };
>
> void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid,
> @@ -1460,7 +1458,6 @@ static const struct arm_smmu_entry_writer_ops arm_smmu_ste_writer_ops = {
> .sync = arm_smmu_ste_writer_sync_entry,
> .get_used = arm_smmu_get_ste_used,
> .v_bit = cpu_to_le64(STRTAB_STE_0_V),
> - .num_entry_qwords = sizeof(struct arm_smmu_ste) / sizeof(u64),
> };
>
> static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid,
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> index 8ba07b00bf6056..5936dc5f76786a 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
> @@ -779,7 +779,6 @@ struct arm_smmu_entry_writer {
> };
>
> struct arm_smmu_entry_writer_ops {
> - unsigned int num_entry_qwords;
> __le64 v_bit;
> void (*get_used)(const __le64 *entry, __le64 *used);
> void (*sync)(struct arm_smmu_entry_writer *writer);
>
Thanks,
Mostafa
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* [PATCH v2 3/5] clk: scmi: Add support for rate change restricted clocks
From: Cristian Marussi @ 2024-03-25 21:00 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, linux-clk
Cc: sudeep.holla, james.quinlan, f.fainelli, vincent.guittot,
peng.fan, michal.simek, quic_sibis, quic_nkela,
souvik.chakravarty, mturquette, sboyd, Cristian Marussi
In-Reply-To: <20240325210025.1448717-1-cristian.marussi@arm.com>
Some exposed SCMI Clocks could be marked as non-supporting rate changes.
Configure a clk_ops descriptors which does not provide the rate change
callbacks for such clocks when registering with CLK framework.
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@kernel.org>
CC: linux-clk@vger.kernel.org
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
---
drivers/clk/clk-scmi.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index fc9603988d91..d20dcc60f9d1 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -19,6 +19,7 @@
enum scmi_clk_feats {
SCMI_CLK_ATOMIC_SUPPORTED,
SCMI_CLK_STATE_CTRL_FORBIDDEN,
+ SCMI_CLK_RATE_CTRL_FORBIDDEN,
SCMI_CLK_MAX_FEATS
};
@@ -248,7 +249,8 @@ scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
ops->recalc_rate = scmi_clk_recalc_rate;
ops->round_rate = scmi_clk_round_rate;
ops->determine_rate = scmi_clk_determine_rate;
- ops->set_rate = scmi_clk_set_rate;
+ if (!(feats_key & BIT(SCMI_CLK_RATE_CTRL_FORBIDDEN)))
+ ops->set_rate = scmi_clk_set_rate;
/* Parent ops */
ops->get_parent = scmi_clk_get_parent;
@@ -296,6 +298,9 @@ scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
if (ci->state_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_STATE_CTRL_FORBIDDEN);
+ if (ci->rate_ctrl_forbidden)
+ feats_key |= BIT(SCMI_CLK_RATE_CTRL_FORBIDDEN);
+
/* Lookup previously allocated ops */
ops = clk_ops_db[feats_key];
if (!ops) {
--
2.44.0
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* [PATCH v2 5/5] clk: scmi: Add support for get/set duty_cycle operations
From: Cristian Marussi @ 2024-03-25 21:00 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, linux-clk
Cc: sudeep.holla, james.quinlan, f.fainelli, vincent.guittot,
peng.fan, michal.simek, quic_sibis, quic_nkela,
souvik.chakravarty, mturquette, sboyd, Cristian Marussi
In-Reply-To: <20240325210025.1448717-1-cristian.marussi@arm.com>
Provide the CLK framework callbacks related to get/set clock duty cycle if
the related SCMI clock supports OEM extended configurations.
CC: Michael Turquette <mturquette@baylibre.com>
CC: Stephen Boyd <sboyd@kernel.org>
CC: linux-clk@vger.kernel.org
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
---
drivers/clk/clk-scmi.c | 49 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index 87e968b6c095..86ef7c553ddd 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -21,6 +21,7 @@ enum scmi_clk_feats {
SCMI_CLK_STATE_CTRL_FORBIDDEN,
SCMI_CLK_RATE_CTRL_FORBIDDEN,
SCMI_CLK_PARENT_CTRL_FORBIDDEN,
+ SCMI_CLK_DUTY_CYCLE_SUPPORTED,
SCMI_CLK_MAX_FEATS
};
@@ -169,6 +170,45 @@ static int scmi_clk_atomic_is_enabled(struct clk_hw *hw)
return !!enabled;
}
+static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
+{
+ int ret;
+ u32 val;
+ struct scmi_clk *clk = to_scmi_clk(hw);
+
+ ret = scmi_proto_clk_ops->config_oem_get(clk->ph, clk->id,
+ SCMI_CLOCK_CFG_DUTY_CYCLE,
+ &val, NULL, false);
+ if (!ret) {
+ duty->num = val;
+ duty->den = 100;
+ } else {
+ dev_warn(clk->dev,
+ "Failed to get duty cycle for clock ID %d\n", clk->id);
+ }
+
+ return ret;
+}
+
+static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
+{
+ int ret;
+ u32 val;
+ struct scmi_clk *clk = to_scmi_clk(hw);
+
+ /* SCMI OEM Duty Cycle is expressed as a percentage */
+ val = (duty->num * 100) / duty->den;
+ ret = scmi_proto_clk_ops->config_oem_set(clk->ph, clk->id,
+ SCMI_CLOCK_CFG_DUTY_CYCLE,
+ val, false);
+ if (ret)
+ dev_warn(clk->dev,
+ "Failed to set duty cycle(%u/%u) for clock ID %d\n",
+ duty->num, duty->den, clk->id);
+
+ return ret;
+}
+
static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
const struct clk_ops *scmi_ops)
{
@@ -258,6 +298,12 @@ scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
if (!(feats_key & BIT(SCMI_CLK_PARENT_CTRL_FORBIDDEN)))
ops->set_parent = scmi_clk_set_parent;
+ /* Duty cycle */
+ if (feats_key & BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED)) {
+ ops->get_duty_cycle = scmi_clk_get_duty_cycle;
+ ops->set_duty_cycle = scmi_clk_set_duty_cycle;
+ }
+
return ops;
}
@@ -306,6 +352,9 @@ scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
if (ci->parent_ctrl_forbidden)
feats_key |= BIT(SCMI_CLK_PARENT_CTRL_FORBIDDEN);
+ if (ci->extended_config)
+ feats_key |= BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED);
+
/* Lookup previously allocated ops */
ops = clk_ops_db[feats_key];
if (!ops) {
--
2.44.0
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