* [PATCH v2 3/6] arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
Define firmware paths and enable the ADSP and CDSP remoteprocs.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index f90bf3518e98..5b267a94a282 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -508,6 +508,16 @@ &qupv3_id_0 {
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs6490/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs6490/cdsp.mbn";
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <32 2>, /* ADSP */
<48 4>; /* NFC */
--
2.25.1
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* [PATCH v2 4/6] arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
The RB3gen2 has a USB redriver on APPS_I2C, enable the bus and introduce
the redriver. The plumbing with other components is kept separate for
clarity.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 5b267a94a282..2f94b1b865e7 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -485,6 +485,20 @@ &gcc {
<GCC_WPSS_RSCP_CLK>;
};
+&i2c1 {
+ status = "okay";
+
+ typec-mux@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l18b_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+ };
+};
+
&mdss {
status = "okay";
};
--
2.25.1
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^ permalink raw reply related
* [PATCH v2 6/6] arm64: defconfig: Enable sc7280 display and gpu clock controllers
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
Enable the SC7280 display and gpu clock controllers to enable display
support on the QCS6490 RB3gen2.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6c45a465a071..a25a28e6117b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1287,6 +1287,7 @@ CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_GCC_404=y
CONFIG_QDU_GCC_1000=y
CONFIG_SC_CAMCC_8280XP=m
+CONFIG_SC_DISPCC_7280=m
CONFIG_SC_DISPCC_8280XP=m
CONFIG_SA_GCC_8775P=y
CONFIG_SA_GPUCC_8775P=m
@@ -1294,6 +1295,7 @@ CONFIG_SC_GCC_7180=y
CONFIG_SC_GCC_7280=y
CONFIG_SC_GCC_8180X=y
CONFIG_SC_GCC_8280XP=y
+CONFIG_SC_GPUCC_7280=m
CONFIG_SC_GPUCC_8280XP=m
CONFIG_SC_LPASSCC_8280XP=m
CONFIG_SDM_CAMCC_845=m
--
2.25.1
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^ permalink raw reply related
* [PATCH v2 5/6] arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Neil Armstrong, Krishna Kurapati PSSNV, Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
With the ADSP remoteproc loaded pmic_glink can be introduced and
together with the redriver wired up to provide role and orientation
switching signals as well as USB Type-C display on the RB3gen2.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-By: Krishna Kurapati PSSNV <quic_kriskura@quicinc.com>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 107 ++++++++++++++++++++++++++-
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 2f94b1b865e7..3cc19ccff90c 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -135,6 +135,49 @@ debug_vm_mem: debug-vm@d0600000 {
};
};
+ pmic-glink {
+ compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_sbu>;
+ };
+ };
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -496,6 +539,36 @@ typec-mux@1c {
retimer-switch;
orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_usb_con_ss: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_phy_con_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ redriver_usb_con_sbu: endpoint {
+ remote-endpoint = <&pmic_glink_sbu_in>;
+ };
+ };
+ };
};
};
@@ -503,6 +576,15 @@ &mdss {
status = "okay";
};
+&mdss_dp {
+ status = "okay";
+};
+
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
&mdss_edp {
status = "okay";
};
@@ -547,7 +629,16 @@ &usb_1 {
};
&usb_1_dwc3 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
&usb_1_hsphy {
@@ -562,9 +653,23 @@ &usb_1_qmpphy {
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p912>;
+ orientation-switch;
+
status = "okay";
};
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_phy_con_ss>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
+&usb_dp_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp_out>;
+};
+
&wifi {
memory-region = <&wlan_fw_mem>;
};
--
2.25.1
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^ permalink raw reply related
* [PATCH v2 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
The RB3Gen2 board comes with a mini DP connector, describe this, enable
MDSS, DP controller and the PHY that drives this.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 40 ++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 63ebe0774f1d..f90bf3518e98 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -39,6 +39,20 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ dp-connector {
+ compatible = "dp-connector";
+ label = "DP";
+ type = "mini";
+
+ hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&mdss_edp_out>;
+ };
+ };
+ };
+
reserved-memory {
xbl_mem: xbl@80700000 {
reg = <0x0 0x80700000 0x0 0x100000>;
@@ -471,6 +485,25 @@ &gcc {
<GCC_WPSS_RSCP_CLK>;
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_edp {
+ status = "okay";
+};
+
+&mdss_edp_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+ remote-endpoint = <&dp_connector_in>;
+};
+
+&mdss_edp_phy {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -511,3 +544,10 @@ &usb_1_qmpphy {
&wifi {
memory-region = <&wlan_fw_mem>;
};
+
+/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
+
+&edp_hot_plug_det {
+ function = "gpio";
+ bias-disable;
+};
--
2.25.1
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* [PATCH v2 1/6] arm64: dts: qcom: sc7280: Enable MDP turbo mode
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Douglas Anderson, Abhinav Kumar, Bjorn Andersson
In-Reply-To: <20240326-rb3gen2-dp-connector-v2-0-a9f1bc32ecaf@quicinc.com>
The max frequency listed in the DPU opp-table is 506MHz, this is not
sufficient to drive a 4k@60 display, resulting in constant underrun.
Add the missing MDP_CLK turbo frequency of 608MHz to the opp-table to
fix this.
Acked-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 41f51d326111..261d2d431faa 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4458,6 +4458,11 @@ opp-506666667 {
opp-hz = /bits/ 64 <506666667>;
required-opps = <&rpmhpd_opp_nom>;
};
+
+ opp-608000000 {
+ opp-hz = /bits/ 64 <608000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
};
};
--
2.25.1
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* [PATCH v2 0/6] arm64: dts: qcom: qcs6490-rb3gen2: Enable two displays
From: Bjorn Andersson @ 2024-03-27 2:04 UTC (permalink / raw)
To: cros-qcom-dts-watchers, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Douglas Anderson, Abhinav Kumar, Bjorn Andersson, Neil Armstrong,
Krishna Kurapati PSSNV
RB3Gen2 is capable of producing DisplayPort output on a dedicated
mini-DP connector and USB Type-C.
Utilize Abel's work for DP vs eDP selection to allow configuring both
controllers in DP-mode, then enable the two output paths.
Tested by driving fbcon to 4k@60 + 4k@30 concurrently.
Depends on 20240324-x1e80100-display-refactor-connector-v4-0-e0ebaea66a78@linaro.org
---
Changes in v2:
- Rebased on Abel's updated implementation
- Dropped DP driver changes, as Abel's new DP/eDP selection mechanism
obsoleted these.
- Squashed the two separate patches adding pmic-glink
- Corrected remoteproc firmware-name paths
- Described the mini-DP connector in DT, and hence no longer use the
internal HPD handler in DP driver
- Link to v1: https://lore.kernel.org/r/20240221-rb3gen2-dp-connector-v1-0-dc0964ef7d96@quicinc.com
---
Bjorn Andersson (6):
arm64: dts: qcom: sc7280: Enable MDP turbo mode
arm64: dts: qcom: qcs6490-rb3gen2: Add DP output
arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp
arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver
arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display
arm64: defconfig: Enable sc7280 display and gpu clock controllers
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 171 ++++++++++++++++++++++++++-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +
arch/arm64/configs/defconfig | 2 +
3 files changed, 177 insertions(+), 1 deletion(-)
---
base-commit: f27830a6a17b722f9dbbccfaae1f3bae8700c672
change-id: 20240209-rb3gen2-dp-connector-bddfb892ff20
Best regards,
--
Bjorn Andersson <quic_bjorande@quicinc.com>
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* Re: [PATCH v1 2/3] arm64: mm: Don't remap pgtables for allocate vs populate
From: kernel test robot @ 2024-03-27 2:05 UTC (permalink / raw)
To: Ryan Roberts, Catalin Marinas, Will Deacon, Mark Rutland,
Ard Biesheuvel, David Hildenbrand, Donald Dutile, Eric Chanudet
Cc: oe-kbuild-all, Ryan Roberts, linux-arm-kernel, linux-kernel
In-Reply-To: <20240326101448.3453626-3-ryan.roberts@arm.com>
Hi Ryan,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.9-rc1 next-20240326]
[cannot apply to arm64/for-next/core arm-perf/for-next/perf arm/for-next arm/fixes kvmarm/next soc/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ryan-Roberts/arm64-mm-Don-t-remap-pgtables-per-cont-pte-pmd-block/20240326-181754
base: linus/master
patch link: https://lore.kernel.org/r/20240326101448.3453626-3-ryan.roberts%40arm.com
patch subject: [PATCH v1 2/3] arm64: mm: Don't remap pgtables for allocate vs populate
config: x86_64-rhel-8.3 (https://download.01.org/0day-ci/archive/20240327/202403270906.zFGZ2FXl-lkp@intel.com/config)
compiler: gcc-12 (Ubuntu 12.3.0-9ubuntu2) 12.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240327/202403270906.zFGZ2FXl-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403270906.zFGZ2FXl-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from include/linux/mm.h:29,
from include/linux/memcontrol.h:21,
from include/linux/swap.h:9,
from include/linux/suspend.h:5,
from arch/x86/kernel/asm-offsets.c:14:
>> include/linux/pgtable.h:87:29: error: redefinition of 'p4d_index'
87 | static inline unsigned long p4d_index(unsigned long address)
| ^~~~~~~~~
In file included from arch/x86/include/asm/tlbflush.h:16,
from arch/x86/include/asm/uaccess.h:17,
from include/linux/uaccess.h:11,
from include/linux/sched/task.h:13,
from include/linux/sched/signal.h:9,
from include/linux/rcuwait.h:6,
from include/linux/percpu-rwsem.h:7,
from include/linux/fs.h:33,
from include/linux/compat.h:17,
from arch/x86/include/asm/ia32.h:7,
from arch/x86/include/asm/elf.h:10,
from include/linux/elf.h:6,
from include/linux/module.h:19,
from include/crypto/aria.h:22,
from arch/x86/kernel/asm-offsets.c:10:
arch/x86/include/asm/pgtable.h:1134:29: note: previous definition of 'p4d_index' with type 'long unsigned int(long unsigned int)'
1134 | static inline unsigned long p4d_index(unsigned long address)
| ^~~~~~~~~
make[3]: *** [scripts/Makefile.build:117: arch/x86/kernel/asm-offsets.s] Error 1
make[3]: Target 'prepare' not remade because of errors.
make[2]: *** [Makefile:1197: prepare0] Error 2
make[2]: Target 'prepare' not remade because of errors.
make[1]: *** [Makefile:240: __sub-make] Error 2
make[1]: Target 'prepare' not remade because of errors.
make: *** [Makefile:240: __sub-make] Error 2
make: Target 'prepare' not remade because of errors.
vim +/p4d_index +87 include/linux/pgtable.h
85
86 #ifndef p4d_index
> 87 static inline unsigned long p4d_index(unsigned long address)
88 {
89 return (address >> P4D_SHIFT) & (PTRS_PER_P4D - 1);
90 }
91 #define p4d_index p4d_index
92 #endif
93
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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* [PATCH v3] staging: media: remove duplicate line
From: coolrrsh @ 2024-03-27 2:33 UTC (permalink / raw)
To: slongerbeam, p.zabel, mchehab, gregkh, shawnguo, s.hauer, kernel,
festevam, linux-imx, linux-media, linux-staging, linux-arm-kernel,
linux-kernel
Cc: linux-kernel-mentees, Rajeshwar R Shinde
From: Rajeshwar R Shinde <coolrrsh@gmail.com>
The kernel configuration VIDEO_DEV is defined twice in Kconfig.
Thus, the redundant code is removed.
Signed-off-by: Rajeshwar R Shinde <coolrrsh@gmail.com>
---
v1->v2
changed the commit message
v2->v3
changed the subject
---
drivers/staging/media/imx/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig
index 21fd79515042..772f49b1fe52 100644
--- a/drivers/staging/media/imx/Kconfig
+++ b/drivers/staging/media/imx/Kconfig
@@ -4,7 +4,6 @@ config VIDEO_IMX_MEDIA
depends on ARCH_MXC || COMPILE_TEST
depends on HAS_DMA
depends on VIDEO_DEV
- depends on VIDEO_DEV
select MEDIA_CONTROLLER
select V4L2_FWNODE
select V4L2_MEM2MEM_DEV
--
2.25.1
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^ permalink raw reply related
* [PATCH] spi: s3c64xx: Use DMA mode from fifo size
From: Jaewon Kim @ 2024-03-27 3:30 UTC (permalink / raw)
To: Andi Shyti, Mark Brown, Krzysztof Kozlowski, Alim Akhtar
Cc: linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
Jaewon Kim
In-Reply-To: <CGME20240327033501epcas2p2bbe21301da5584f7f3a073c51a363c00@epcas2p2.samsung.com>
The SPI data size is smaller than FIFO, it operates in PIO mode,
and if it is larger than FIFO mode, DMA mode is selected.
If the data size is the same as the FIFO size, it operates in PIO mode
and data is separated into two transfer. In order to prevent,
DMA mode must be used from the case of FIFO and data size.
Fixes: 1ee806718d5e ("spi: s3c64xx: support interrupt based pio mode")
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
---
drivers/spi/spi-s3c64xx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 9fcbe040cb2f..81ed5fddf83e 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -430,7 +430,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
if (sdd->rx_dma.ch && sdd->tx_dma.ch)
- return xfer->len > sdd->fifo_depth;
+ return xfer->len >= sdd->fifo_depth;
return false;
}
@@ -826,11 +826,11 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host,
return status;
}
- if (!is_polling(sdd) && (xfer->len > fifo_len) &&
+ if (!is_polling(sdd) && xfer->len >= fifo_len &&
sdd->rx_dma.ch && sdd->tx_dma.ch) {
use_dma = 1;
- } else if (xfer->len >= fifo_len) {
+ } else if (xfer->len > fifo_len) {
tx_buf = xfer->tx_buf;
rx_buf = xfer->rx_buf;
origin_len = xfer->len;
--
2.43.2
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* Re: [PATCH v3 6/8] cpufreq: sun50i: Add H616 support
From: Samuel Holland @ 2024-03-27 3:46 UTC (permalink / raw)
To: Andre Przywara
Cc: linux-pm, devicetree, linux-sunxi, linux-arm-kernel,
Brandon Cheo Fusi, Martin Botka, Martin Botka, Chris Morgan,
Ryan Walklin, Mark Rutland, Lorenzo Pieralisi, Sudeep Holla,
Yangtao Li, Viresh Kumar, Nishanth Menon, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Rafael J . Wysocki
In-Reply-To: <20240326114743.712167-7-andre.przywara@arm.com>
Hi Andre,
On 3/26/24 06:47, Andre Przywara wrote:
> From: Martin Botka <martin.botka@somainline.org>
>
> The Allwinner H616/H618 SoCs have different OPP tables per SoC version
> and die revision. The SoC version is stored in NVMEM, as before, though
> encoded differently. The die revision is in a different register, in the
> SRAM controller. Firmware already exports that value in a standardised
> way, through the SMCCC SoCID mechanism. We need both values, as some chips
> have the same SoC version, but they don't support the same frequencies and
> they get differentiated by the die revision.
>
> Add the new compatible string and tie the new translation function to
> it. This mechanism not only covers the original H616 SoC, but also its
> very close sibling SoCs H618 and H700, so add them to the list as well.
>
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> drivers/cpufreq/sun50i-cpufreq-nvmem.c | 61 ++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> index bd170611c7906..f9e9fc340f848 100644
> --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> @@ -10,6 +10,7 @@
>
> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> +#include <linux/arm-smccc.h>
> #include <linux/cpu.h>
> #include <linux/module.h>
> #include <linux/nvmem-consumer.h>
> @@ -46,14 +47,71 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
> return 0;
> }
>
> +/*
> + * Judging by the OPP tables in the vendor BSP, the quality order of the
> + * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
> + * 0 and 2 seem identical from the OPP tables' point of view.
> + */
> +static u32 sun50i_h616_efuse_xlate(u32 speedbin)
> +{
> + int ver_bits = arm_smccc_get_soc_id_revision();
This needs a Kconfig dependency on ARM_SMCCC_SOC_ID.
Regards,
Samuel
> + u32 value = 0;
> +
> + switch (speedbin & 0xffff) {
> + case 0x2000:
> + value = 0;
> + break;
> + case 0x2400:
> + case 0x7400:
> + case 0x2c00:
> + case 0x7c00:
> + if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) {
> + /* ic version A/B */
> + value = 1;
> + } else {
> + /* ic version C and later version */
> + value = 2;
> + }
> + break;
> + case 0x5000:
> + case 0x5400:
> + case 0x6000:
> + value = 3;
> + break;
> + case 0x5c00:
> + value = 4;
> + break;
> + case 0x5d00:
> + value = 0;
> + break;
> + case 0x6c00:
> + value = 5;
> + break;
> + default:
> + pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",
> + speedbin & 0xffff);
> + value = 0;
> + break;
> + }
> +
> + return value;
> +}
> +
> static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
> .efuse_xlate = sun50i_h6_efuse_xlate,
> };
>
> +static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
> + .efuse_xlate = sun50i_h616_efuse_xlate,
> +};
> +
> static const struct of_device_id cpu_opp_match_list[] = {
> { .compatible = "allwinner,sun50i-h6-operating-points",
> .data = &sun50i_h6_cpufreq_data,
> },
> + { .compatible = "allwinner,sun50i-h616-operating-points",
> + .data = &sun50i_h616_cpufreq_data,
> + },
> {}
> };
>
> @@ -230,6 +288,9 @@ static struct platform_driver sun50i_cpufreq_driver = {
>
> static const struct of_device_id sun50i_cpufreq_match_list[] = {
> { .compatible = "allwinner,sun50i-h6" },
> + { .compatible = "allwinner,sun50i-h616" },
> + { .compatible = "allwinner,sun50i-h618" },
> + { .compatible = "allwinner,sun50i-h700" },
> {}
> };
> MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
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* [PATCH] media: mediatek: jpeg: support 34bits
From: Jianhua Lin @ 2024-03-27 4:01 UTC (permalink / raw)
To: mchehab, matthias.bgg, angelogioacchino.delregno
Cc: linux-media, linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Jianhua Lin
the iommu HW supported 34bits iova space(16GB),
but mediatek jpeg enc/dec driver still is 32bit,
then need to set the bit32/bit33 iova to jpeg HW.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 13 +++-
.../platform/mediatek/jpeg/mtk_jpeg_core.h | 2 +
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 59 +++++++++++++++----
.../platform/mediatek/jpeg/mtk_jpeg_dec_hw.h | 1 +
.../platform/mediatek/jpeg/mtk_jpeg_dec_reg.h | 8 +++
.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 40 +++++++++++--
.../platform/mediatek/jpeg/mtk_jpeg_enc_hw.h | 11 +++-
7 files changed, 115 insertions(+), 19 deletions(-)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index ac48658e2de4..101245030ac6 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1030,6 +1030,7 @@ static void mtk_jpeg_dec_device_run(void *priv)
spin_lock_irqsave(&jpeg->hw_lock, flags);
mtk_jpeg_dec_reset(jpeg->reg_base);
mtk_jpeg_dec_set_config(jpeg->reg_base,
+ jpeg->support_34bit,
&jpeg_src_buf->dec_param,
jpeg_src_buf->bs_size,
&bs,
@@ -1317,6 +1318,14 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
return -EINVAL;
}
+ ret = of_property_read_u32(pdev->dev.of_node, "mediatek,34bits",
+ &jpeg->support_34bit);
+ if (ret != 0) {
+ dev_info(&pdev->dev, "default for 32bits");
+ jpeg->support_34bit = 0;
+ }
+ dev_info(&pdev->dev, "use 34bits: %d", jpeg->support_34bit);
+
if (!jpeg->variant->multi_core) {
ret = mtk_jpeg_single_core_init(pdev, jpeg);
if (ret) {
@@ -1564,7 +1573,8 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg)
src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
- result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);
+ result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
+ ctx->jpeg->support_34bit);
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
buf_state = VB2_BUF_STATE_DONE;
@@ -1764,6 +1774,7 @@ static void mtk_jpegdec_worker(struct work_struct *work)
ctx->total_frame_num++;
mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
+ jpeg->support_34bit,
&jpeg_src_buf->dec_param,
jpeg_src_buf->bs_size,
&bs,
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
index 8ba6e757e11a..8237c07ac743 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h
@@ -209,6 +209,7 @@ struct mtk_jpegdec_comp_dev {
* @reg_decbase: jpg decode register base addr
* @dec_hw_dev: jpg decode hardware device
* @hw_index: jpg hw index
+ * @support_34bit: flag to check if support dma_address 34bit
*/
struct mtk_jpeg_dev {
struct mutex lock;
@@ -231,6 +232,7 @@ struct mtk_jpeg_dev {
void __iomem *reg_decbase[MTK_JPEGDEC_HW_MAX];
struct mtk_jpegdec_comp_dev *dec_hw_dev[MTK_JPEGDEC_HW_MAX];
atomic_t hw_index;
+ u32 support_34bit;
};
/**
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
index 4a6ee211e18f..cedc12a32927 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
@@ -270,7 +270,7 @@ void mtk_jpeg_dec_reset(void __iomem *base)
EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
- u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
+ u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
{
u32 val;
@@ -279,23 +279,43 @@ static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
writel(val, base + JPGDEC_REG_BRZ_FACTOR);
}
-static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y,
- u32 addr_u, u32 addr_v)
+static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 support_34bit,
+ dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
{
+ u32 val;
+
mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);
writel(addr_y, base + JPGDEC_REG_DEST_ADDR0_Y);
mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);
writel(addr_u, base + JPGDEC_REG_DEST_ADDR0_U);
mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);
writel(addr_v, base + JPGDEC_REG_DEST_ADDR0_V);
+ if (support_34bit) {
+ val = upper_32_bits(addr_y) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);
+ val = upper_32_bits(addr_u) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);
+ val = upper_32_bits(addr_v) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);
+ }
}
-static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y,
- u32 addr_u, u32 addr_v)
+static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 support_34bit,
+ dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
{
+ u32 val;
+
writel(addr_y, base + JPGDEC_REG_DEST_ADDR1_Y);
writel(addr_u, base + JPGDEC_REG_DEST_ADDR1_U);
writel(addr_v, base + JPGDEC_REG_DEST_ADDR1_V);
+ if (support_34bit) {
+ val = upper_32_bits(addr_y) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);
+ val = upper_32_bits(addr_u) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);
+ val = upper_32_bits(addr_v) & 0x3;
+ writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);
+ }
}
static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
@@ -322,18 +342,31 @@ static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode)
writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
}
-static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, u32 ptr)
+static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base,
+ u32 support_34bit, dma_addr_t ptr)
{
+ u32 val;
+
mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);
writel(ptr, base + JPGDEC_REG_FILE_BRP);
+ if (support_34bit) {
+ val = upper_32_bits(ptr) & 0x3;
+ writel(val, base + JPGDEC_REG_FILE_BRP_EXT);
+ }
}
-static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 addr, u32 size,
- u32 bitstream_size)
+static void mtk_jpeg_dec_set_bs_info(void __iomem *base, u32 support_34bit,
+ dma_addr_t addr, u32 size, u32 bitstream_size)
{
+ u32 val;
+
mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
writel(addr, base + JPGDEC_REG_FILE_ADDR);
+ if (support_34bit) {
+ val = upper_32_bits(addr) & 0x3;
+ writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);
+ }
writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
}
@@ -404,6 +437,7 @@ static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
}
void mtk_jpeg_dec_set_config(void __iomem *base,
+ u32 support_34bits,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
@@ -413,8 +447,9 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
mtk_jpeg_dec_set_dec_mode(base, 0);
mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
- mtk_jpeg_dec_set_bs_info(base, bs->str_addr, bs->size, bitstream_size);
- mtk_jpeg_dec_set_bs_write_ptr(base, bs->end_addr);
+ mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr,
+ bs->size, bitstream_size);
+ mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr);
mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
(cfg->comp_num == 1) ? 1 : 0);
mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
@@ -432,9 +467,9 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
cfg->mem_stride[1]);
mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
cfg->img_stride[1]);
- mtk_jpeg_dec_set_dst_bank0(base, fb->plane_addr[0],
+ mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0],
fb->plane_addr[1], fb->plane_addr[2]);
- mtk_jpeg_dec_set_dst_bank1(base, 0, 0, 0);
+ mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0);
mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
cfg->dma_last_mcu);
mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
index 8c31c6b12417..14c6e6cb387d 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.h
@@ -71,6 +71,7 @@ int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param);
u32 mtk_jpeg_dec_get_int_status(void __iomem *dec_reg_base);
u32 mtk_jpeg_dec_enum_result(u32 irq_result);
void mtk_jpeg_dec_set_config(void __iomem *base,
+ u32 support_34bits,
struct mtk_jpeg_dec_param *cfg,
u32 bitstream_size,
struct mtk_jpeg_bs *bs,
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
index 27b7711ca341..e94f52de7c69 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_reg.h
@@ -46,5 +46,13 @@
#define JPGDEC_REG_INTERRUPT_STATUS 0x0274
#define JPGDEC_REG_STATUS 0x0278
#define JPGDEC_REG_BIT_STREAM_SIZE 0x0344
+#define JPGDEC_REG_DEST_ADDR0_Y_EXT 0x0360
+#define JPGDEC_REG_DEST_ADDR0_U_EXT 0x0364
+#define JPGDEC_REG_DEST_ADDR0_V_EXT 0x0368
+#define JPGDEC_REG_DEST_ADDR1_Y_EXT 0x036c
+#define JPGDEC_REG_DEST_ADDR1_U_EXT 0x0370
+#define JPGDEC_REG_DEST_ADDR1_V_EXT 0x0374
+#define JPGDEC_REG_FILE_ADDR_EXT 0x0378
+#define JPGDEC_REG_FILE_BRP_EXT 0x037c
#endif /* _MTK_JPEG_REG_H */
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
index f8fa3b841ccf..c0a8730cb108 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
@@ -62,9 +62,14 @@ void mtk_jpeg_enc_reset(void __iomem *base)
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_reset);
-u32 mtk_jpeg_enc_get_file_size(void __iomem *base)
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base, u32 support_34bit)
{
- return readl(base + JPEG_ENC_DMA_ADDR0) -
+ u32 value = 1;
+
+ if (support_34bit)
+ value = 4;
+
+ return readl(base + JPEG_ENC_DMA_ADDR0) * value -
readl(base + JPEG_ENC_DST_ADDR0);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_get_file_size);
@@ -75,6 +80,9 @@ void mtk_jpeg_enc_start(void __iomem *base)
value = readl(base + JPEG_ENC_CTRL);
value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
+ value |= JPEG_ENC_CTRL_RDMA_PADDING_EN;
+ value |= JPEG_ENC_CTRL_RDMA_RIGHT_PADDING_EN;
+ value &= ~JPEG_ENC_CTRL_RDMA_PADDING_0_EN;
writel(value, base + JPEG_ENC_CTRL);
}
EXPORT_SYMBOL_GPL(mtk_jpeg_enc_start);
@@ -84,14 +92,25 @@ void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
{
int i;
dma_addr_t dma_addr;
+ u32 val;
+ u32 support_34bit = ctx->jpeg->support_34bit;
for (i = 0; i < src_buf->num_planes; i++) {
dma_addr = vb2_dma_contig_plane_dma_addr(src_buf, i) +
src_buf->planes[i].data_offset;
- if (!i)
+ if (!i) {
writel(dma_addr, base + JPEG_ENC_SRC_LUMA_ADDR);
- else
+ if (support_34bit) {
+ val = upper_32_bits(dma_addr) & 0x3;
+ writel(val, base + JPEG_ENC_SRC_LUMA_ADDR_EXT);
+ }
+ } else {
writel(dma_addr, base + JPEG_ENC_SRC_CHROMA_ADDR);
+ if (support_34bit) {
+ val = upper_32_bits(dma_addr) & 0x3;
+ writel(val, base + JPEG_ENC_SRC_CHROMA_ADDR_EXT);
+ }
+ }
}
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_src);
@@ -103,6 +122,8 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
size_t size;
u32 dma_addr_offset;
u32 dma_addr_offsetmask;
+ u32 val;
+ u32 support_34bit = ctx->jpeg->support_34bit;
dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
dma_addr_offset = ctx->enable_exif ? MTK_JPEG_MAX_EXIF_SIZE : 0;
@@ -112,7 +133,15 @@ void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
writel(dma_addr_offset & ~0xf, base + JPEG_ENC_OFFSET_ADDR);
writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK);
writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
+ if (support_34bit) {
+ val = upper_32_bits(dma_addr) & 0x3;
+ writel(val, base + JPEG_ENC_DEST_ADDR0_EXT);
+ }
writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
+ if (support_34bit) {
+ val = upper_32_bits(dma_addr + size) & 0x3;
+ writel(val, base + JPEG_ENC_STALL_ADDR0_EXT);
+ }
}
EXPORT_SYMBOL_GPL(mtk_jpeg_set_enc_dst);
@@ -278,7 +307,8 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv)
if (!(irq_status & JPEG_ENC_INT_STATUS_DONE))
dev_warn(jpeg->dev, "Jpg Enc occurs unknown Err.");
- result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base);
+ result_size = mtk_jpeg_enc_get_file_size(jpeg->reg_base,
+ ctx->jpeg->support_34bit);
vb2_set_plane_payload(&dst_buf->vb2_buf, 0, result_size);
buf_state = VB2_BUF_STATE_DONE;
v4l2_m2m_buf_done(src_buf, buf_state);
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
index 61c60e4e58ea..2f03a1a5de98 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.h
@@ -68,6 +68,15 @@
#define JPEG_ENC_DCM_CTRL 0x300
#define JPEG_ENC_CODEC_SEL 0x314
#define JPEG_ENC_ULTRA_THRES 0x318
+#define JPEG_ENC_SRC_LUMA_ADDR_EXT 0x584
+#define JPEG_ENC_SRC_CHROMA_ADDR_EXT 0x588
+#define JPEG_ENC_Q_TBL_ADDR_EXT 0x58C
+#define JPEG_ENC_DEST_ADDR0_EXT 0x590
+#define JPEG_ENC_STALL_ADDR0_EXT 0x594
+
+#define JPEG_ENC_CTRL_RDMA_PADDING_EN (1 << 20)
+#define JPEG_ENC_CTRL_RDMA_RIGHT_PADDING_EN (1 << 29)
+#define JPEG_ENC_CTRL_RDMA_PADDING_0_EN (1 << 30)
/**
* struct mtk_jpeg_enc_qlt - JPEG encoder quality data
@@ -80,7 +89,7 @@ struct mtk_jpeg_enc_qlt {
};
void mtk_jpeg_enc_reset(void __iomem *base);
-u32 mtk_jpeg_enc_get_file_size(void __iomem *base);
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base, u32 support_34bit);
void mtk_jpeg_enc_start(void __iomem *enc_reg_base);
void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx, void __iomem *base,
struct vb2_buffer *src_buf);
--
2.18.0
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^ permalink raw reply related
* Re: [PATCH 4/5] dt-bindings: arm: Add Au-Zone Maivin AI Vision Starter Kit
From: Krzysztof Kozlowski @ 2024-03-27 5:00 UTC (permalink / raw)
To: Laurent Pinchart
Cc: devicetree, imx, linux-arm-kernel, Trevor Zaharichuk, Greg Lytle,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Li Yang
In-Reply-To: <20240327010156.GD14986@pendragon.ideasonboard.com>
On 27/03/2024 02:01, Laurent Pinchart wrote:
> Hi Krzysztof,
>
> On Tue, Mar 26, 2024 at 08:11:34AM +0100, Krzysztof Kozlowski wrote:
>> On 25/03/2024 21:32, Laurent Pinchart wrote:
>>> The Maivin board is an AI vision starter kit sold by Au-Zone
>>> Technologies, developed in collaboration with Toradex and Vision
>>> Components. It is based on a Toradex Verdin i.MX8MP SoM.
>>>
>>> Add a corresponding compatible string.
>>>
>>> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> index 0027201e19f8..d892c4f9fda3 100644
>>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> @@ -1064,6 +1064,13 @@ properties:
>>> - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
>>> - const: fsl,imx8mp
>>>
>>> + - description: Au-Zone Technologies i.MX8MP-based boards
>>> + items:
>>> + - const: au-zone,maivin-starter-kit # Au-Zone Maivin AI Vision Starter Kit
>>> + - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
>>> + - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
>>
>> I think this should be part of existing "Toradex Boards with Verdin
>> iMX8M Plus Modules)", just renamed to "boards using Toradex Verdin ...".
>
> Is this what you have in mind ?
>
Yes.
Best regards,
Krzysztof
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^ permalink raw reply
* RE: [PATCH] drivers: clk: zynqmp: remove clock name dependency
From: Trivedi Manojbhai, Naman @ 2024-03-27 5:47 UTC (permalink / raw)
To: Stephen Boyd, Simek, Michal, robh@kernel.org
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <PH7PR12MB7284F36E51750D47102410448A202@PH7PR12MB7284.namprd12.prod.outlook.com>
Hi Stephen,
I am awaiting your response for the below query. Can you please help me with the same?
Thanks,
Naman
>-----Original Message-----
>From: Trivedi Manojbhai, Naman
>Sent: Thursday, March 7, 2024 11:37 AM
>To: Stephen Boyd <sboyd@kernel.org>; Simek, Michal
><michal.simek@amd.com>; robh@kernel.org
>Cc: linux-clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
>kernel@vger.kernel.org
>Subject: RE: [PATCH] drivers: clk: zynqmp: remove clock name dependency
>
>Hi Stephen,
>
>>-----Original Message-----
>>From: Stephen Boyd <sboyd@kernel.org>
>>Sent: Thursday, January 4, 2024 6:30 AM
>>To: Trivedi Manojbhai, Naman <Naman.TrivediManojbhai@amd.com>;
>>abel.vesa@linaro.org; angelogioacchino.delregno@collabora.com;
>>krzysztof.kozlowski@linaro.org; Simek, Michal <michal.simek@amd.com>;
>>mturquette@baylibre.com; robh@kernel.org
>>Cc: linux-clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>>linux- kernel@vger.kernel.org; Trivedi Manojbhai, Naman
>><Naman.TrivediManojbhai@amd.com>
>>Subject: Re: [PATCH] drivers: clk: zynqmp: remove clock name dependency
>>
>>Caution: This message originated from an External Source. Use proper
>>caution when opening attachments, clicking links, or responding.
>>
>>
>>Quoting Naman Trivedi Manojbhai (2024-01-02 23:20:17)
>>> Currently, from zynqmp_get_parent_list() function the clock driver
>>> references the clock by name instead of its reference from device tree.
>>> This causes problem when the clock name in the device tree is changed.
>>>
>>> Remove hard dependency of clock name and update the logic to use
>>> clock reference from device tree instead of clock name.
>>
>>Please use struct clk_parent_data instead.
>Thanks for review. As per my understanding, you suggest to replace the
>proposed logic, and use "struct clk_parent_data" to get the clock name from
>device tree.
>
>I have gone through other drivers which use the "struct clk_parent_data"
>structure, they have hard coded clock names in the driver. In zynqmp, the
>driver receives clock name from firmware.
>
>Also, the "zynqmp_get_parent_list" function is called before clocks are
>registered. So at this point, we don't have the hw structure which has
>clk_parent_data.
>
>So, I did not get how to use the struct clk_parent_data in this case. Can you
>please provide an example which I can look at as a reference?
>
>Thanks,
>Naman
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^ permalink raw reply
* Re: [PATCH 00/19] amba: store owner from modules with amba_driver_register()
From: Krzysztof Kozlowski @ 2024-03-27 5:57 UTC (permalink / raw)
To: Suzuki K Poulose, Russell King, Mike Leach, James Clark,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Linus Walleij, Andi Shyti, Olivia Mackall, Herbert Xu, Vinod Koul,
Dmitry Torokhov, Miquel Raynal, Michal Simek, Eric Auger,
Alex Williamson
Cc: linux-kernel, coresight, linux-arm-kernel, linux-stm32, linux-i2c,
linux-crypto, dmaengine, linux-input, kvm
In-Reply-To: <3f61d6d3-a0d6-4c49-b094-6ba62d09ab14@arm.com>
On 27/03/2024 00:24, Suzuki K Poulose wrote:
> Hi Krzysztof
>
> On 26/03/2024 20:23, Krzysztof Kozlowski wrote:
>> Merging
>> =======
>> All further patches depend on the first amba patch, therefore please ack
>> and this should go via one tree.
>
> Are you able to provide a stable branch with these patches once you pull
I doubt I will be merging this. I think amba code goes through Russell.
> them in to "one tree" here ? We have changes coming up in the coresight
> tree, which would conflict with the changes here (horribly).
>
You mean conflict with coresight conversion to platform driver? Worst
case it is solveable: just drop .owner.
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH v2 2/3] dt-bindings: power: Add mediatek larb definition
From: yu-chang.lee @ 2024-03-27 5:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, fan.chen,
xiufeng.li, yu-chang.lee
In-Reply-To: <20240327055732.28198-1-yu-chang.lee@mediatek.com>
Add Smart Multimedia Interface Local Arbiter to mediatek
power domain.
Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 8985e2df8a56..228c0dec5253 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -125,6 +125,10 @@ $defs:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range.
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the LARB register range.
+
required:
- reg
--
2.18.0
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^ permalink raw reply related
* [PATCH v2 3/3] pmdomain: mediatek: support smi clamp protection
From: yu-chang.lee @ 2024-03-27 5:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, fan.chen,
xiufeng.li, yu-chang.lee
In-Reply-To: <20240327055732.28198-1-yu-chang.lee@mediatek.com>
In order to avoid power glitch, this patch use smi clamp
to disable/enable smi common port.
Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com>
---
drivers/pmdomain/mediatek/mt8188-pm-domains.h | 41 ++++++-
drivers/pmdomain/mediatek/mtk-pm-domains.c | 109 +++++++++++++-----
drivers/pmdomain/mediatek/mtk-pm-domains.h | 1 +
3 files changed, 115 insertions(+), 36 deletions(-)
diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
index 7bbba4d56a77..39f057dca92c 100644
--- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
@@ -573,6 +573,18 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR(SMI,
+ MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0,
+ MT8188_SMI_COMMON_CLAMP_EN_SET,
+ MT8188_SMI_COMMON_CLAMP_EN_CLR,
+ MT8188_SMI_COMMON_CLAMP_EN_STA),
+ BUS_PROT_WR(SMI,
+ MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1,
+ MT8188_SMI_COMMON_CLAMP_EN_SET,
+ MT8188_SMI_COMMON_CLAMP_EN_CLR,
+ MT8188_SMI_COMMON_CLAMP_EN_STA),
+ },
.reset_smi = {
SMI_RESET_WR(MT8188_SMI_LARB10_RESET,
MT8188_SMI_LARB10_RESET_ADDR),
@@ -585,7 +597,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
SMI_RESET_WR(MT8188_SMI_LARB15_RESET,
MT8188_SMI_LARB15_RESET_ADDR),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_CLAMP_PROTECTION,
},
[MT8188_POWER_DOMAIN_IPE] = {
.name = "ipe",
@@ -595,11 +607,18 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR(SMI,
+ MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1,
+ MT8188_SMI_COMMON_CLAMP_EN_SET,
+ MT8188_SMI_COMMON_CLAMP_EN_CLR,
+ MT8188_SMI_COMMON_CLAMP_EN_STA),
+ },
.reset_smi = {
SMI_RESET_WR(MT8188_SMI_LARB12_RESET,
MT8188_SMI_LARB12_RESET_ADDR),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_CLAMP_PROTECTION,
},
[MT8188_POWER_DOMAIN_CAM_VCORE] = {
.name = "cam_vcore",
@@ -676,13 +695,20 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR(SMI,
+ MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1,
+ MT8188_SMI_COMMON_CLAMP_EN_SET,
+ MT8188_SMI_COMMON_CLAMP_EN_CLR,
+ MT8188_SMI_COMMON_CLAMP_EN_STA),
+ },
.reset_smi = {
SMI_RESET_WR(MT8188_SMI_LARB16A_RESET,
MT8188_SMI_LARB16A_RESET_ADDR),
SMI_RESET_WR(MT8188_SMI_LARB17A_RESET,
MT8188_SMI_LARB17A_RESET_ADDR),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_CLAMP_PROTECTION,
},
[MT8188_POWER_DOMAIN_CAM_SUBB] = {
.name = "cam_subb",
@@ -692,13 +718,20 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .bp_cfg = {
+ BUS_PROT_WR(SMI,
+ MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0,
+ MT8188_SMI_COMMON_CLAMP_EN_SET,
+ MT8188_SMI_COMMON_CLAMP_EN_CLR,
+ MT8188_SMI_COMMON_CLAMP_EN_STA),
+ },
.reset_smi = {
SMI_RESET_WR(MT8188_SMI_LARB16B_RESET,
MT8188_SMI_LARB16B_RESET_ADDR),
SMI_RESET_WR(MT8188_SMI_LARB17B_RESET,
MT8188_SMI_LARB17B_RESET_ADDR),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_CLAMP_PROTECTION,
},
};
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index 9ab6fa105c8c..2a86ff4bf23e 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -47,9 +47,10 @@ struct scpsys_domain {
struct clk_bulk_data *subsys_clks;
struct regmap *infracfg_nao;
struct regmap *infracfg;
- struct regmap *smi;
+ struct regmap **smi;
struct regmap **larb;
int num_larb;
+ int num_smi;
struct regulator *supply;
};
@@ -122,29 +123,19 @@ static int scpsys_sram_disable(struct scpsys_domain *pd)
MTK_POLL_TIMEOUT);
}
-static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *pd,
- const struct scpsys_bus_prot_data *bpd)
-{
- if (bpd->flags & BUS_PROT_COMPONENT_SMI)
- return pd->smi;
- else
- return pd->infracfg;
-}
-
static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_domain *pd,
const struct scpsys_bus_prot_data *bpd)
{
if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO)
return pd->infracfg_nao;
else
- return scpsys_bus_protect_get_regmap(pd, bpd);
+ return pd->infracfg;
}
static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
- const struct scpsys_bus_prot_data *bpd)
+ const struct scpsys_bus_prot_data *bpd,
+ struct regmap *sta_regmap, struct regmap *regmap)
{
- struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
- struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 sta_mask = bpd->bus_prot_sta_mask;
u32 expected_ack;
u32 val;
@@ -165,10 +156,9 @@ static int scpsys_bus_protect_clear(struct scpsys_domain *pd,
}
static int scpsys_bus_protect_set(struct scpsys_domain *pd,
- const struct scpsys_bus_prot_data *bpd)
+ const struct scpsys_bus_prot_data *bpd,
+ struct regmap *sta_regmap, struct regmap *regmap)
{
- struct regmap *sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
- struct regmap *regmap = scpsys_bus_protect_get_regmap(pd, bpd);
u32 sta_mask = bpd->bus_prot_sta_mask;
u32 val;
@@ -182,19 +172,32 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd,
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
-static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
+static int scpsys_clamp_bus_protection_enable(struct scpsys_domain *pd, bool is_smi)
{
+ int smi_count = 0;
+
for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ struct regmap *sta_regmap, *regmap;
+ bool is_smi = bpd->flags & BUS_PROT_COMPONENT_SMI;
int ret;
if (!bpd->bus_prot_set_clr_mask)
break;
+ if (is_smi) {
+ sta_regmap = pd->smi[smi_count];
+ regmap = pd->smi[smi_count];
+ smi_count++;
+ } else {
+ sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
+ regmap = pd->infracfg;
+ }
+
if (bpd->flags & BUS_PROT_INVERTED)
- ret = scpsys_bus_protect_clear(pd, bpd);
+ ret = scpsys_bus_protect_clear(pd, bpd, sta_regmap, regmap);
else
- ret = scpsys_bus_protect_set(pd, bpd);
+ ret = scpsys_bus_protect_set(pd, bpd, sta_regmap, regmap);
if (ret)
return ret;
}
@@ -202,19 +205,32 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
return 0;
}
-static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
+static int scpsys_clamp_bus_protection_disable(struct scpsys_domain *pd, bool is_smi)
{
+ int smi_count = pd->num_smi - 1;
+
for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
+ struct regmap *sta_regmap, *regmap;
+ bool is_smi = bpd->flags & BUS_PROT_COMPONENT_SMI;
int ret;
if (!bpd->bus_prot_set_clr_mask)
continue;
+ if (is_smi) {
+ sta_regmap = pd->smi[smi_count];
+ regmap = pd->smi[smi_count];
+ smi_count--;
+ } else {
+ sta_regmap = scpsys_bus_protect_get_sta_regmap(pd, bpd);
+ regmap = pd->infracfg;
+ }
+
if (bpd->flags & BUS_PROT_INVERTED)
- ret = scpsys_bus_protect_set(pd, bpd);
+ ret = scpsys_bus_protect_set(pd, bpd, sta_regmap, regmap);
else
- ret = scpsys_bus_protect_clear(pd, bpd);
+ ret = scpsys_bus_protect_clear(pd, bpd, sta_regmap, regmap);
if (ret)
return ret;
}
@@ -272,6 +288,12 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
bool tmp;
int ret;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_CLAMP_PROTECTION)) {
+ ret = scpsys_clamp_bus_protection_enable(pd, true);
+ if (ret)
+ return ret;
+ }
+
ret = scpsys_regulator_enable(pd->supply);
if (ret)
return ret;
@@ -318,7 +340,13 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_disable_subsys_clks;
- ret = scpsys_bus_protect_disable(pd);
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_CLAMP_PROTECTION)) {
+ ret = scpsys_clamp_bus_protection_disable(pd, true);
+ if (ret)
+ return ret;
+ }
+
+ ret = scpsys_clamp_bus_protection_disable(pd, false);
if (ret < 0)
goto err_disable_sram;
@@ -332,7 +360,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
return 0;
err_enable_bus_protect:
- scpsys_bus_protect_enable(pd);
+ scpsys_clamp_bus_protection_enable(pd, false);
err_disable_sram:
scpsys_sram_disable(pd);
err_disable_subsys_clks:
@@ -353,7 +381,13 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
bool tmp;
int ret;
- ret = scpsys_bus_protect_enable(pd);
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_CLAMP_PROTECTION)) {
+ ret = scpsys_clamp_bus_protection_enable(pd, true);
+ if (ret)
+ return ret;
+ }
+
+ ret = scpsys_clamp_bus_protection_enable(pd, false);
if (ret < 0)
return ret;
@@ -450,12 +484,23 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
if (IS_ERR(pd->infracfg))
return ERR_CAST(pd->infracfg);
- smi_node = of_parse_phandle(node, "mediatek,smi", 0);
- if (smi_node) {
- pd->smi = device_node_to_regmap(smi_node);
- of_node_put(smi_node);
- if (IS_ERR(pd->smi))
- return ERR_CAST(pd->smi);
+ pd->num_smi = of_count_phandle_with_args(node, "mediatek,smi", NULL);
+ if (pd->num_smi > 0) {
+ pd->smi = devm_kcalloc(scpsys->dev, pd->num_smi, sizeof(*pd->smi), GFP_KERNEL);
+ if (!pd->smi)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; i < pd->num_smi; i++) {
+ smi_node = of_parse_phandle(node, "mediatek,smi", i);
+ if (!smi_node)
+ return ERR_PTR(-EINVAL);
+
+ pd->smi[i] = device_node_to_regmap(smi_node);
+ if (IS_ERR(pd->smi[i]))
+ return ERR_CAST(pd->smi[i]);
+ }
+ } else {
+ pd->num_smi = 0;
}
pd->num_larb = of_count_phandle_with_args(node, "mediatek,larb", NULL);
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index 31c2a1bb500f..e0eb7214719e 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -13,6 +13,7 @@
#define MTK_SCPD_EXT_BUCK_ISO BIT(6)
#define MTK_SCPD_HAS_INFRA_NAO BIT(7)
#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)
+#define MTK_SCPD_CLAMP_PROTECTION BIT(9)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
--
2.18.0
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^ permalink raw reply related
* [PATCH v2 1/3] pmdomain: mediatek: add smi_larb_reset function when power on
From: yu-chang.lee @ 2024-03-27 5:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, fan.chen,
xiufeng.li, yu-chang.lee
In-Reply-To: <20240327055732.28198-1-yu-chang.lee@mediatek.com>
This patch avoid mtcmos power glitch from happening by set and clear
smi larb reset.
Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com>
---
drivers/pmdomain/mediatek/mt8188-pm-domains.h | 28 +++++++++
drivers/pmdomain/mediatek/mtk-pm-domains.c | 59 +++++++++++++++++++
drivers/pmdomain/mediatek/mtk-pm-domains.h | 12 ++++
3 files changed, 99 insertions(+)
diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
index 06834ab6597c..7bbba4d56a77 100644
--- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
@@ -573,6 +573,18 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .reset_smi = {
+ SMI_RESET_WR(MT8188_SMI_LARB10_RESET,
+ MT8188_SMI_LARB10_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB11A_RESET,
+ MT8188_SMI_LARB11A_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB11C_RESET,
+ MT8188_SMI_LARB11C_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB11B_RESET,
+ MT8188_SMI_LARB11B_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB15_RESET,
+ MT8188_SMI_LARB15_RESET_ADDR),
+ },
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_IPE] = {
@@ -583,6 +595,10 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .reset_smi = {
+ SMI_RESET_WR(MT8188_SMI_LARB12_RESET,
+ MT8188_SMI_LARB12_RESET_ADDR),
+ },
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CAM_VCORE] = {
@@ -660,6 +676,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .reset_smi = {
+ SMI_RESET_WR(MT8188_SMI_LARB16A_RESET,
+ MT8188_SMI_LARB16A_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB17A_RESET,
+ MT8188_SMI_LARB17A_RESET_ADDR),
+ },
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
[MT8188_POWER_DOMAIN_CAM_SUBB] = {
@@ -670,6 +692,12 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.pwr_sta2nd_offs = 0x170,
.sram_pdn_bits = BIT(8),
.sram_pdn_ack_bits = BIT(12),
+ .reset_smi = {
+ SMI_RESET_WR(MT8188_SMI_LARB16B_RESET,
+ MT8188_SMI_LARB16B_RESET_ADDR),
+ SMI_RESET_WR(MT8188_SMI_LARB17B_RESET,
+ MT8188_SMI_LARB17B_RESET_ADDR),
+ },
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
},
};
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c
index e274e3315fe7..9ab6fa105c8c 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.c
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c
@@ -48,6 +48,8 @@ struct scpsys_domain {
struct regmap *infracfg_nao;
struct regmap *infracfg;
struct regmap *smi;
+ struct regmap **larb;
+ int num_larb;
struct regulator *supply;
};
@@ -230,6 +232,39 @@ static int scpsys_regulator_disable(struct regulator *supply)
return supply ? regulator_disable(supply) : 0;
}
+static int _scpsys_smi_larb_reset(const struct smi_reset_data bpd,
+ struct regmap *regmap)
+{
+ int ret;
+ u32 mask = bpd.smi_reset_mask;
+
+ if (!mask)
+ return 0;
+
+ ret = regmap_set_bits(regmap, bpd.smi_reset_addr, mask);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(regmap, bpd.smi_reset_addr, mask);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int scpsys_smi_larb_reset(struct scpsys_domain *pd)
+{
+ int ret, i;
+
+ for (i = 0; i < pd->num_larb; i++) {
+ ret = _scpsys_smi_larb_reset(pd->data->reset_smi[i], pd->larb[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd);
@@ -279,6 +314,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_disable_subsys_clks;
+ ret = scpsys_smi_larb_reset(pd);
+ if (ret < 0)
+ goto err_disable_subsys_clks;
+
ret = scpsys_bus_protect_disable(pd);
if (ret < 0)
goto err_disable_sram;
@@ -355,6 +394,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
struct scpsys_domain *pd;
struct device_node *root_node = scpsys->dev->of_node;
struct device_node *smi_node;
+ struct device_node *larb_node;
struct property *prop;
const char *clk_name;
int i, ret, num_clks;
@@ -418,6 +458,25 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no
return ERR_CAST(pd->smi);
}
+ pd->num_larb = of_count_phandle_with_args(node, "mediatek,larb", NULL);
+ if (pd->num_larb > 0) {
+ pd->larb = devm_kcalloc(scpsys->dev, pd->num_larb, sizeof(*pd->larb), GFP_KERNEL);
+ if (!pd->larb)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; i < pd->num_larb; i++) {
+ larb_node = of_parse_phandle(node, "mediatek,larb", i);
+ if (!larb_node)
+ return ERR_PTR(-EINVAL);
+
+ pd->larb[i] = device_node_to_regmap(larb_node);
+ if (IS_ERR(pd->larb[i]))
+ return ERR_CAST(pd->larb[i]);
+ }
+ } else {
+ pd->num_larb = 0;
+ }
+
if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) {
pd->infracfg_nao = syscon_regmap_lookup_by_phandle(node, "mediatek,infracfg-nao");
if (IS_ERR(pd->infracfg_nao))
diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h
index aaba5e6b0536..31c2a1bb500f 100644
--- a/drivers/pmdomain/mediatek/mtk-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h
@@ -43,6 +43,7 @@
#define PWR_STATUS_USB BIT(25)
#define SPM_MAX_BUS_PROT_DATA 6
+#define SPM_MAX_SMI_RESET_DATA 6
enum scpsys_bus_prot_flags {
BUS_PROT_REG_UPDATE = BIT(1),
@@ -79,6 +80,16 @@ enum scpsys_bus_prot_flags {
INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1)
+#define SMI_RESET_WR(_mask, _addr) { \
+ .smi_reset_mask = (_mask), \
+ .smi_reset_addr = _addr, \
+ }
+
+struct smi_reset_data {
+ u32 smi_reset_mask;
+ u32 smi_reset_addr;
+};
+
struct scpsys_bus_prot_data {
u32 bus_prot_set_clr_mask;
u32 bus_prot_set;
@@ -110,6 +121,7 @@ struct scpsys_domain_data {
u32 ext_buck_iso_mask;
u16 caps;
const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];
+ const struct smi_reset_data reset_smi[SPM_MAX_SMI_RESET_DATA];
int pwr_sta_offs;
int pwr_sta2nd_offs;
};
--
2.18.0
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^ permalink raw reply related
* [PATCH v2 0/3] pmdomain: mediatek: solve power domain glitch issue
From: yu-chang.lee @ 2024-03-27 5:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: devicetree, linux-kernel, linux-pm, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, fan.chen,
xiufeng.li, yu-chang.lee
Hi,
This series aims to solve power-off failures and occasional SMI hang issues that
occur during camera stress tests. The issue arises because, when MTCMOS powers on
or off, signal glitches are sometimes produced. This is fairly normal, but the
software must address it to avoid mistaking the glitch for a transaction signal.
The solutions in these patches can be summarized as follows:
1. Disable the sub-common port after turning off the Larb CG and before turning
off the Larb MTCMOS.
2. Use CLAMP to disable/enable the SMI common port.
3. Implement an AXI reset.
For previous discussion on the direction of the code modifications, please refer
to: https://lore.kernel.org/linux-arm-kernel/c476cc48-17ec-4e14-98d8-35bdffb5d296@collabora.com/
Change in v2
- fix commit title to "pmdomain: mediatek:"
- add dt-binding definition
- remove unused function
yu-chang.lee (3):
pmdomain: mediatek: add smi_larb_reset function when power on
dt-bindings: power: Add mediatek larb definition
pmdomain: mediatek: support smi clamp protection
.../power/mediatek,power-controller.yaml | 4 +
drivers/pmdomain/mediatek/mt8188-pm-domains.h | 69 ++++++-
drivers/pmdomain/mediatek/mtk-pm-domains.c | 168 ++++++++++++++----
drivers/pmdomain/mediatek/mtk-pm-domains.h | 13 ++
4 files changed, 218 insertions(+), 36 deletions(-)
--
2.18.0
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^ permalink raw reply
* [PATCH v11 0/8] PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
Hello,
This series is the continuation of previous work by Vidya Sagar [1] to fix the
issues related to accessing DBI register space before completing the core
initialization in some EP platforms like Tegra194/234 and Qcom EP.
Since Vidya is busy, I took over the series based on his consent (off-list
discussion).
NOTE
====
Based on the comments received in v7 [2], I've heavily modified the series
to fix several other issues reported by Bjorn and Niklas. One noticeable
change is getting rid of the 'core_init_notifer' flag added to differentiate
between glue drivers requiring refclk from host and drivers getting refclk
locally.
By getting rid of this flag, now both the DWC EP driver and the EPF drivers
can use a single flow and need not distinguish between the glue drivers.
We can also get rid of the 'link_up_notifier' flag in the future by following
the same convention.
Testing
=======
I've tested the series on Qcom SM8450 based dev board that depends on refclk
from host with EPF_MHI driver. It'd be good to test this series on platforms
that generate refclk locally and also with EPF_TEST driver.
- Mani
[1] https://lore.kernel.org/linux-pci/20221013175712.7539-1-vidyas@nvidia.com/
[2] https://lore.kernel.org/linux-pci/20231120084014.108274-1-manivannan.sadhasivam@linaro.org/
Changes in v11:
- Minor cleanups reported by Niklas
- 'epc->init_complete = false' is set in dw_pcie_ep_cleanup() to avoid
triggering init complete notification before refclk. This will be moved to EPC
core in the following series adding deinit notifier.
- Collected review tags.
- Link to v10: https://lore.kernel.org/r/20240314-pci-dbi-rework-v10-0-14a45c5a938e@linaro.org
Changes in v10:
- Reordered the commits by moving the independent fixes/cleanups first (Niklas)
- Addressed several comments from Niklas
- Moved PTM register setting out of dw_pcie_ep_init_non_sticky_registers() (Niklas)
- Addressed the issue that EPF drivers were missing init notification after the
removal of core_init_notifier (Niklas)
- Dropped a few cleanup patches to be clubbed with the follow up series
- Collected review tags
- Dropped the review tags for patch 8/8 as it got changed
- Link to v9: https://lore.kernel.org/r/20240304-pci-dbi-rework-v9-0-29d433d99cda@linaro.org
Changes in v9:
- Incorporated changes for missing drivers (Niklas)
- Reworded the dw_pcie_ep_cleanup() API kdoc (Niklas)
- Reworded the description of patch 6/10 (Frank)
- Collected reviews
- Link to v8: https://lore.kernel.org/r/20240224-pci-dbi-rework-v8-0-64c7fd0cfe64@linaro.org
Changes in v8:
- Rebased on top of v6.8-rc1
- Removed the deinit callback from struct dw_pcie_ep_ops
- Renamed dw_pcie_ep_exit() to dw_pcie_ep_deinit()
- Introduced dw_pcie_ep_cleanup() API for drivers supporting PERST#
- Renamed dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers()
- Called dw_pcie_ep_init_registers() API directly from all glue drivers
- Removed "core_init_notifier" flag
- Added a generic dw_pcie_ep_linkdown() API to handle LINK_DOWN event and used
it in qcom driver
- Added Kernel-doc comments for DWC EP APIs
Changes in v7:
- Rebased on top of v6.7-rc1
- Kept the current dw_pcie_ep_init_complete() API instead of renaming it to
dw_pcie_ep_init_late(), since changing the name causes a slight ambiguity.
- Splitted the change that moves pci_epc_init_notify() inside
dw_pcie_ep_init_notify() to help bisecting and also to avoid build issue.
- Added a new patch that moves pci_epc_init_notify() inside
dw_pcie_ep_init_notify().
- Took over the authorship and dropped the previous Ack as the patches are
heavily modified.
Changes in v6:
- Rebased on top of pci/next (6e2fca71e187)
- removed ep_init_late() callback as it is no longer necessary
For previous changelog, please refer [1].
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Manivannan Sadhasivam (8):
PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
PCI: dwc: ep: Add Kernel-doc comments for APIs
PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops
PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit()
PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#
PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers()
PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers
PCI: endpoint: Remove "core_init_notifier" flag
drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +
drivers/pci/controller/dwc/pci-dra7xx.c | 9 +
drivers/pci/controller/dwc/pci-imx6.c | 10 +
drivers/pci/controller/dwc/pci-keystone.c | 11 +
drivers/pci/controller/dwc/pci-layerscape-ep.c | 9 +
drivers/pci/controller/dwc/pcie-artpec6.c | 15 +-
drivers/pci/controller/dwc/pcie-designware-ep.c | 238 +++++++++++++++-------
drivers/pci/controller/dwc/pcie-designware-plat.c | 11 +
drivers/pci/controller/dwc/pcie-designware.h | 14 +-
drivers/pci/controller/dwc/pcie-keembay.c | 18 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +-
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 28 ++-
drivers/pci/controller/dwc/pcie-tegra194.c | 5 +-
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 15 +-
drivers/pci/controller/pcie-rcar-ep.c | 2 +
drivers/pci/controller/pcie-rockchip-ep.c | 2 +
drivers/pci/endpoint/functions/pci-epf-test.c | 18 +-
drivers/pci/endpoint/pci-ep-cfs.c | 9 +
drivers/pci/endpoint/pci-epc-core.c | 22 ++
include/linux/pci-epc.h | 7 +-
20 files changed, 338 insertions(+), 111 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240224-pci-dbi-rework-b2e99a62930c
Best regards,
--
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* [PATCH v11 1/8] PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
In-Reply-To: <20240327-pci-dbi-rework-v11-0-6f5259f90673@linaro.org>
The DWC glue drivers requiring an active reference clock from the PCIe host
for initializing their PCIe EP core, set a flag called 'core_init_notifier'
to let DWC driver know that these drivers need a special attention during
initialization. In these drivers, access to the hw registers (like DBI)
before receiving the active refclk from host will result in access failure
and also could cause a whole system hang.
But the current DWC EP driver doesn't honor the requirements of the drivers
setting 'core_init_notifier' flag and tries to access the DBI registers
during dw_pcie_ep_init(). This causes the system hang for glue drivers such
as Tegra194 and Qcom EP as they depend on refclk from host and have set the
above mentioned flag.
To workaround this issue, users of the affected platforms have to maintain
the dependency with the PCIe host by booting the PCIe EP after host boot.
But this won't provide a good user experience, since PCIe EP is _one_ of
the features of those platforms and it doesn't make sense to delay the
whole platform booting due to PCIe requiring active refclk.
So to fix this issue, let's move all the DBI access from
dw_pcie_ep_init() in the DWC EP driver to the dw_pcie_ep_init_complete()
API. This API will only be called by the drivers setting
'core_init_notifier' flag once refclk is received from host. For the rest
of the drivers that gets the refclk locally, this API will be called
within dw_pcie_ep_init().
Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode")
Co-developed-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++++++++++++++----------
1 file changed, 71 insertions(+), 49 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b..c05304eabb89 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -602,11 +602,16 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct dw_pcie_ep_func *ep_func;
+ struct device *dev = pci->dev;
+ struct pci_epc *epc = ep->epc;
unsigned int offset, ptm_cap_base;
unsigned int nbars;
u8 hdr_type;
+ u8 func_no;
+ int i, ret;
+ void *addr;
u32 reg;
- int i;
hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) &
PCI_HEADER_TYPE_MASK;
@@ -617,6 +622,58 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
return -EIO;
}
+ dw_pcie_version_detect(pci);
+
+ dw_pcie_iatu_detect(pci);
+
+ ret = dw_pcie_edma_detect(pci);
+ if (ret)
+ return ret;
+
+ if (!ep->ib_window_map) {
+ ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
+ GFP_KERNEL);
+ if (!ep->ib_window_map)
+ goto err_remove_edma;
+ }
+
+ if (!ep->ob_window_map) {
+ ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
+ GFP_KERNEL);
+ if (!ep->ob_window_map)
+ goto err_remove_edma;
+ }
+
+ if (!ep->outbound_addr) {
+ addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
+ GFP_KERNEL);
+ if (!addr)
+ goto err_remove_edma;
+ ep->outbound_addr = addr;
+ }
+
+ for (func_no = 0; func_no < epc->max_functions; func_no++) {
+
+ ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+ if (ep_func)
+ continue;
+
+ ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
+ if (!ep_func)
+ goto err_remove_edma;
+
+ ep_func->func_no = func_no;
+ ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+
+ list_add_tail(&ep_func->list, &ep->func_list);
+ }
+
+ if (ep->ops->init)
+ ep->ops->init(ep);
+
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
@@ -651,14 +708,17 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
dw_pcie_dbi_ro_wr_dis(pci);
return 0;
+
+err_remove_edma:
+ dw_pcie_edma_remove(pci);
+
+ return ret;
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
{
int ret;
- void *addr;
- u8 func_no;
struct resource *res;
struct pci_epc *epc;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -666,7 +726,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
const struct pci_epc_features *epc_features;
- struct dw_pcie_ep_func *ep_func;
INIT_LIST_HEAD(&ep->func_list);
@@ -684,26 +743,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ep->ops->pre_init)
ep->ops->pre_init(ep);
- dw_pcie_version_detect(pci);
-
- dw_pcie_iatu_detect(pci);
-
- ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
- GFP_KERNEL);
- if (!ep->ib_window_map)
- return -ENOMEM;
-
- ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
- GFP_KERNEL);
- if (!ep->ob_window_map)
- return -ENOMEM;
-
- addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
- GFP_KERNEL);
- if (!addr)
- return -ENOMEM;
- ep->outbound_addr = addr;
-
epc = devm_pci_epc_create(dev, &epc_ops);
if (IS_ERR(epc)) {
dev_err(dev, "Failed to create epc device\n");
@@ -717,23 +756,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
if (ret < 0)
epc->max_functions = 1;
- for (func_no = 0; func_no < epc->max_functions; func_no++) {
- ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL);
- if (!ep_func)
- return -ENOMEM;
-
- ep_func->func_no = func_no;
- ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no,
- PCI_CAP_ID_MSI);
- ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no,
- PCI_CAP_ID_MSIX);
-
- list_add_tail(&ep_func->list, &ep->func_list);
- }
-
- if (ep->ops->init)
- ep->ops->init(ep);
-
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
ep->page_size);
if (ret < 0) {
@@ -749,25 +771,25 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
goto err_exit_epc_mem;
}
- ret = dw_pcie_edma_detect(pci);
- if (ret)
- goto err_free_epc_mem;
-
if (ep->ops->get_features) {
epc_features = ep->ops->get_features(ep);
if (epc_features->core_init_notifier)
return 0;
}
+ /*
+ * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this
+ * step as platforms that implement 'core_init_notifier' feature may
+ * not have the hardware ready (i.e. core initialized) for access
+ * (Ex: tegra194). Any hardware access on such platforms result
+ * in system hang.
+ */
ret = dw_pcie_ep_init_complete(ep);
if (ret)
- goto err_remove_edma;
+ goto err_free_epc_mem;
return 0;
-err_remove_edma:
- dw_pcie_edma_remove(pci);
-
err_free_epc_mem:
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
epc->mem->window.page_size);
--
2.25.1
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^ permalink raw reply related
* [PATCH v11 2/8] PCI: dwc: ep: Add Kernel-doc comments for APIs
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
In-Reply-To: <20240327-pci-dbi-rework-v11-0-6f5259f90673@linaro.org>
All of the APIs are missing the Kernel-doc comments. Hence, add them.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 77 +++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index c05304eabb89..c2a7653b7b9f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -14,6 +14,10 @@
#include <linux/pci-epc.h>
#include <linux/pci-epf.h>
+/**
+ * dw_pcie_ep_linkup - Notify EPF drivers about Link Up event
+ * @ep: DWC EP device
+ */
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
{
struct pci_epc *epc = ep->epc;
@@ -22,6 +26,10 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup);
+/**
+ * dw_pcie_ep_init_notify - Notify EPF drivers about EPC initialization complete
+ * @ep: DWC EP device
+ */
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
{
struct pci_epc *epc = ep->epc;
@@ -30,6 +38,14 @@ void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify);
+/**
+ * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to
+ * the endpoint function
+ * @ep: DWC EP device
+ * @func_no: Function number of the endpoint device
+ *
+ * Return: struct dw_pcie_ep_func if success, NULL otherwise.
+ */
struct dw_pcie_ep_func *
dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
{
@@ -60,6 +76,11 @@ static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
dw_pcie_dbi_ro_wr_dis(pci);
}
+/**
+ * dw_pcie_ep_reset_bar - Reset endpoint BAR
+ * @pci: DWC PCI device
+ * @bar: BAR number of the endpoint
+ */
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
{
u8 func_no, funcs;
@@ -439,6 +460,13 @@ static const struct pci_epc_ops epc_ops = {
.get_features = dw_pcie_ep_get_features,
};
+/**
+ * dw_pcie_ep_raise_intx_irq - Raise INTx IRQ to the host
+ * @ep: DWC EP device
+ * @func_no: Function number of the endpoint
+ *
+ * Return: 0 if success, errono otherwise.
+ */
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -450,6 +478,14 @@ int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
+/**
+ * dw_pcie_ep_raise_msi_irq - Raise MSI IRQ to the host
+ * @ep: DWC EP device
+ * @func_no: Function number of the endpoint
+ * @interrupt_num: Interrupt number to be raised
+ *
+ * Return: 0 if success, errono otherwise.
+ */
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
{
@@ -498,6 +534,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq);
+/**
+ * dw_pcie_ep_raise_msix_irq_doorbell - Raise MSI-X to the host using Doorbell
+ * method
+ * @ep: DWC EP device
+ * @func_no: Function number of the endpoint device
+ * @interrupt_num: Interrupt number to be raised
+ *
+ * Return: 0 if success, errno otherwise.
+ */
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
{
@@ -517,6 +562,14 @@ int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+/**
+ * dw_pcie_ep_raise_msix_irq - Raise MSI-X to the host
+ * @ep: DWC EP device
+ * @func_no: Function number of the endpoint device
+ * @interrupt_num: Interrupt number to be raised
+ *
+ * Return: 0 if success, errno otherwise.
+ */
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
{
@@ -564,6 +617,13 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+/**
+ * dw_pcie_ep_exit - Deinitialize the endpoint device
+ * @ep: DWC EP device
+ *
+ * Deinitialize the endpoint device. EPC device is not destroyed since that will
+ * be taken care by Devres.
+ */
void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -599,6 +659,14 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
return 0;
}
+/**
+ * dw_pcie_ep_init_complete - Complete DWC EP initialization
+ * @ep: DWC EP device
+ *
+ * Complete the initialization of the registers (CSRs) specific to DWC EP. This
+ * API should be called only when the endpoint receives an active refclk (either
+ * from host or generated locally).
+ */
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -716,6 +784,15 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
+/**
+ * dw_pcie_ep_init - Initialize the endpoint device
+ * @ep: DWC EP device
+ *
+ * Initialize the endpoint device. Allocate resources and create the EPC
+ * device with the endpoint framework.
+ *
+ * Return: 0 if success, errno otherwise.
+ */
int dw_pcie_ep_init(struct dw_pcie_ep *ep)
{
int ret;
--
2.25.1
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^ permalink raw reply related
* [PATCH v11 3/8] PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
In-Reply-To: <20240327-pci-dbi-rework-v11-0-6f5259f90673@linaro.org>
deinit() callback was solely introduced for the pcie-rcar-gen4 driver where
it is used to do platform specific resource deallocation. And this callback
is called right at the end of the dw_pcie_ep_exit() API. So it doesn't
matter whether it is called within or outside of dw_pcie_ep_exit() API.
So let's remove this callback and directly call rcar_gen4_pcie_ep_deinit()
in pcie-rcar-gen4 driver to do resource deallocation after the completion
of dw_pcie_ep_exit() API in rcar_gen4_remove_dw_pcie_ep().
This simplifies the DWC layer.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +--------
drivers/pci/controller/dwc/pcie-designware.h | 1 -
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 14 ++++++++------
3 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index c2a7653b7b9f..7d60abe4fef7 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -635,9 +635,6 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
epc->mem->window.page_size);
pci_epc_mem_exit(epc);
-
- if (ep->ops->deinit)
- ep->ops->deinit(ep);
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
@@ -837,7 +834,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->page_size);
if (ret < 0) {
dev_err(dev, "Failed to initialize address space\n");
- goto err_ep_deinit;
+ return ret;
}
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
@@ -874,10 +871,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
err_exit_epc_mem:
pci_epc_mem_exit(epc);
-err_ep_deinit:
- if (ep->ops->deinit)
- ep->ops->deinit(ep);
-
return ret;
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 26dae4837462..ab7431a37209 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -333,7 +333,6 @@ struct dw_pcie_rp {
struct dw_pcie_ep_ops {
void (*pre_init)(struct dw_pcie_ep *ep);
void (*init)(struct dw_pcie_ep *ep);
- void (*deinit)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
unsigned int type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index e9166619b1f9..ac97d594ea47 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -352,11 +352,8 @@ static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
dw_pcie_ep_reset_bar(pci, bar);
}
-static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
+static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
{
- struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
- struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
-
writel(0, rcar->base + PCIEDMAINTSTSEN);
rcar_gen4_pcie_common_deinit(rcar);
}
@@ -408,7 +405,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
static const struct dw_pcie_ep_ops pcie_ep_ops = {
.pre_init = rcar_gen4_pcie_ep_pre_init,
.init = rcar_gen4_pcie_ep_init,
- .deinit = rcar_gen4_pcie_ep_deinit,
.raise_irq = rcar_gen4_pcie_ep_raise_irq,
.get_features = rcar_gen4_pcie_ep_get_features,
.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
@@ -418,18 +414,24 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = {
static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie_ep *ep = &rcar->dw.ep;
+ int ret;
if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))
return -ENODEV;
ep->ops = &pcie_ep_ops;
- return dw_pcie_ep_init(ep);
+ ret = dw_pcie_ep_init(ep);
+ if (ret)
+ rcar_gen4_pcie_ep_deinit(rcar);
+
+ return ret;
}
static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
{
dw_pcie_ep_exit(&rcar->dw.ep);
+ rcar_gen4_pcie_ep_deinit(rcar);
}
/* Common */
--
2.25.1
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* [PATCH v11 4/8] PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit()
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
In-Reply-To: <20240327-pci-dbi-rework-v11-0-6f5259f90673@linaro.org>
dw_pcie_ep_exit() API is undoing what the dw_pcie_ep_init() API has done
already (at least partly). But the API name dw_pcie_ep_exit() is not quite
reflecting that. So let's rename it to dw_pcie_ep_deinit() to make the
purpose of this API clear. This also aligns with the DWC host driver.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7d60abe4fef7..7ff2015736ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -618,13 +618,13 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
}
/**
- * dw_pcie_ep_exit - Deinitialize the endpoint device
+ * dw_pcie_ep_deinit - Deinitialize the endpoint device
* @ep: DWC EP device
*
* Deinitialize the endpoint device. EPC device is not destroyed since that will
* be taken care by Devres.
*/
-void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
+void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
@@ -636,7 +636,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc);
}
-EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
+EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit);
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
{
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ab7431a37209..61465203bb60 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -671,7 +671,7 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
-void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+void dw_pcie_ep_deinit(struct dw_pcie_ep *ep);
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
@@ -701,7 +701,7 @@ static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
{
}
-static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
+static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)
{
}
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index ac97d594ea47..9d9d22e367bb 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -430,7 +430,7 @@ static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
{
- dw_pcie_ep_exit(&rcar->dw.ep);
+ dw_pcie_ep_deinit(&rcar->dw.ep);
rcar_gen4_pcie_ep_deinit(rcar);
}
--
2.25.1
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^ permalink raw reply related
* [PATCH v11 5/8] PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#
From: Manivannan Sadhasivam @ 2024-03-27 6:35 UTC (permalink / raw)
To: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Marek Vasut, Yoshihiro Shimoda, Thierry Reding, Jonathan Hunter,
Kishon Vijay Abraham I, Vidya Sagar, Vignesh Raghavendra,
Richard Zhu, Lucas Stach, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Minghuan Lian, Mingkai Hu, Roy Zang, Kunihiko Hayashi,
Masami Hiramatsu, Kishon Vijay Abraham I, Jesper Nilsson,
Srikanth Thokala, Shawn Lin, Heiko Stuebner
Cc: linux-pci, linux-kernel, linux-renesas-soc, linux-arm-msm,
linux-tegra, linux-omap, linux-arm-kernel, linuxppc-dev,
Niklas Cassel, linux-arm-kernel, linux-rockchip,
Manivannan Sadhasivam, Frank Li
In-Reply-To: <20240327-pci-dbi-rework-v11-0-6f5259f90673@linaro.org>
For DWC glue drivers supporting PERST# (currently Qcom and Tegra194), some
of the DWC resources like eDMA should be cleaned up during the PERST#
assert time.
So let's introduce a dw_pcie_ep_cleanup() API that could be called by these
drivers to cleanup the DWC specific resources. Currently, it just removes
eDMA.
Reported-by: Niklas Cassel <cassel@kernel.org>
Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 19 +++++++++++++++++--
drivers/pci/controller/dwc/pcie-designware.h | 5 +++++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++
4 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7ff2015736ef..7509fa1d1e7d 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -617,6 +617,22 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+/**
+ * dw_pcie_ep_cleanup - Cleanup DWC EP resources after fundamental reset
+ * @ep: DWC EP device
+ *
+ * Cleans up the DWC EP specific resources like eDMA etc... after fundamental
+ * reset like PERST#. Note that this API is only applicable for drivers
+ * supporting PERST# or any other methods of fundamental reset.
+ */
+void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ dw_pcie_edma_remove(pci);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup);
+
/**
* dw_pcie_ep_deinit - Deinitialize the endpoint device
* @ep: DWC EP device
@@ -626,10 +642,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
*/
void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)
{
- struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
- dw_pcie_edma_remove(pci);
+ dw_pcie_ep_cleanup(ep);
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
epc->mem->window.page_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 61465203bb60..351d2fe3ea4d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -672,6 +672,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep);
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
void dw_pcie_ep_deinit(struct dw_pcie_ep *ep);
+void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep);
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
@@ -705,6 +706,10 @@ static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)
{
}
+static inline void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)
+{
+}
+
static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
{
return 0;
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 36e5e80cd22f..59b1c0110288 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -507,6 +507,7 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci)
return;
}
+ dw_pcie_ep_cleanup(&pci->ep);
qcom_pcie_disable_resources(pcie_ep);
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
}
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 7afa9e9aabe2..68bfeed3429b 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1715,6 +1715,8 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
if (ret)
dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
+ dw_pcie_ep_cleanup(&pcie->pci.ep);
+
reset_control_assert(pcie->core_rst);
tegra_pcie_disable_phy(pcie);
--
2.25.1
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