* Re: [PATCH] arm: kasan: clear stale stack poison
From: Boy Wu (吳勃誼) @ 2024-03-29 3:17 UTC (permalink / raw)
To: linux@armlinux.org.uk, matthias.bgg@gmail.com
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
kasan-dev@googlegroups.com,
angelogioacchino.delregno@collabora.com, linux-mm@kvack.org
In-Reply-To: <20231222022741.8223-1-boy.wu@mediatek.com>
Hi Russell:
Kingly ping
Thanks.
Boy.
On Fri, 2023-12-22 at 10:27 +0800, boy.wu wrote:
> From: Boy Wu <boy.wu@mediatek.com>
>
> We found below OOB crash:
>
> [ 33.452494]
> ==================================================================
> [ 33.453513] BUG: KASAN: stack-out-of-bounds in
> refresh_cpu_vm_stats.constprop.0+0xcc/0x2ec
> [ 33.454660] Write of size 164 at addr c1d03d30 by task swapper/0/0
> [ 33.455515]
> [ 33.455767] CPU: 0 PID: 0 Comm: swapper/0 Tainted:
> G O 6.1.25-mainline #1
> [ 33.456880] Hardware name: Generic DT based system
> [ 33.457555] unwind_backtrace from show_stack+0x18/0x1c
> [ 33.458326] show_stack from dump_stack_lvl+0x40/0x4c
> [ 33.459072] dump_stack_lvl from print_report+0x158/0x4a4
> [ 33.459863] print_report from kasan_report+0x9c/0x148
> [ 33.460616] kasan_report from kasan_check_range+0x94/0x1a0
> [ 33.461424] kasan_check_range from memset+0x20/0x3c
> [ 33.462157] memset from
> refresh_cpu_vm_stats.constprop.0+0xcc/0x2ec
> [ 33.463064] refresh_cpu_vm_stats.constprop.0 from
> tick_nohz_idle_stop_tick+0x180/0x53c
> [ 33.464181] tick_nohz_idle_stop_tick from do_idle+0x264/0x354
> [ 33.465029] do_idle from cpu_startup_entry+0x20/0x24
> [ 33.465769] cpu_startup_entry from rest_init+0xf0/0xf4
> [ 33.466528] rest_init from arch_post_acpi_subsys_init+0x0/0x18
> [ 33.467397]
> [ 33.467644] The buggy address belongs to stack of task swapper/0/0
> [ 33.468493] and is located at offset 112 in frame:
> [ 33.469172] refresh_cpu_vm_stats.constprop.0+0x0/0x2ec
> [ 33.469917]
> [ 33.470165] This frame has 2 objects:
> [ 33.470696] [32, 76) 'global_zone_diff'
> [ 33.470729] [112, 276) 'global_node_diff'
> [ 33.471294]
> [ 33.472095] The buggy address belongs to the physical page:
> [ 33.472862] page:3cd72da8 refcount:1 mapcount:0 mapping:00000000
> index:0x0 pfn:0x41d03
> [ 33.473944] flags: 0x1000(reserved|zone=0)
> [ 33.474565] raw: 00001000 ed741470 ed741470 00000000 00000000
> 00000000 ffffffff 00000001
> [ 33.475656] raw: 00000000
> [ 33.476050] page dumped because: kasan: bad access detected
> [ 33.476816]
> [ 33.477061] Memory state around the buggy address:
> [ 33.477732] c1d03c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00
> [ 33.478630] c1d03c80: 00 00 00 00 00 00 00 00 f1 f1 f1 f1 00 00
> 00 00
> [ 33.479526] >c1d03d00: 00 04 f2 f2 f2 f2 00 00 00 00 00 00 f1 f1
> f1 f1
> [ 33.480415] ^
> [ 33.481195] c1d03d80: 00 00 00 00 00 00 00 00 00 00 04 f3 f3 f3
> f3 f3
> [ 33.482088] c1d03e00: f3 f3 f3 f3 00 00 00 00 00 00 00 00 00 00
> 00 00
> [ 33.482978]
> ==================================================================
>
> We find the root cause of this OOB is that arm does not clear stale
> stack
> poison in the case of cpuidle.
>
> This patch refer to arch/arm64/kernel/sleep.S to resolve this issue.
>
> Signed-off-by: Boy Wu <boy.wu@mediatek.com>
> ---
> arch/arm/kernel/sleep.S | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
> index a86a1d4f3461..93afd1005b43 100644
> --- a/arch/arm/kernel/sleep.S
> +++ b/arch/arm/kernel/sleep.S
> @@ -127,6 +127,10 @@ cpu_resume_after_mmu:
> instr_sync
> #endif
> bl cpu_init @ restore the und/abt/irq
> banked regs
> +#if defined(CONFIG_KASAN) && defined(CONFIG_KASAN_STACK)
> + mov r0, sp
> + bl kasan_unpoison_task_stack_below
> +#endif
> mov r0, #0 @ return zero on success
> ldmfd sp!, {r4 - r11, pc}
> ENDPROC(cpu_resume_after_mmu)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v12 0/2] arm64: Add a build target for Flat Image Tree
From: Simon Glass @ 2024-03-29 3:28 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Masahiro Yamada, Ahmad Fatoum, Nicolas Schier, Simon Glass,
Catalin Marinas, Jonathan Corbet, Nathan Chancellor, Nick Terrell,
Will Deacon, linux-doc, linux-kbuild, linux-kernel, workflows
Flat Image Tree (FIT) is a widely used file format for packaging a
kernel and associated devicetree files[1]. It is not specific to any
one bootloader, as it is supported by U-Boot, coreboot, Linuxboot,
Tianocore and Barebox.
This series adds support for building a FIT as part of the kernel
build. This makes it easy to try out the kernel - just load the FIT
onto your tftp server and it will run automatically on any supported
arm64 board.
The script is written in Python, since it is easy to build a FIT using
the Python libfdt bindings. For now, no attempt is made to compress
files in parallel, so building the 900-odd files takes a while, about
6 seconds with my testing.
The series also includes a minor clean-up patch.
[1] https://github.com/open-source-firmware/flat-image-tree
Changes in v12:
- Avoid showing FIT message if V=0
Changes in v11:
- Use dtbslist file in image.fit rule
- Update cmd_fit rule as per Masahiro
- Don't mention ignoring files without a .dtb prefix
- Use argparse fromfile_prefix_chars feature
- Add a -v option and use it for output (with make V=1)
- rename srcdir to dtbs
- Use -o for the output file instead of -f
Changes in v10:
- Make use of dtbs-list file
- Mention dtbs-list and FIT_COMPRESSION
- Update copyright year
- Update cover letter to take account of an applied patch
Changes in v9:
- Move the compression control into Makefile.lib
Changes in v8:
- Drop compatible string in FDT node
- Correct sorting of MAINTAINERS to before ARM64 PORT
- Turn compress part of the make_fit.py comment in to a sentence
- Add two blank lines before parse_args() and setup_fit()
- Use 'image.fit: dtbs' instead of BUILD_DTBS var
- Use '$(<D)/dts' instead of '$(dir $<)dts'
- Add 'mkimage' details Documentation/process/changes.rst
- Allow changing the compression used
- Tweak cover letter since there is only one clean-up patch
Changes in v7:
- Drop the kbuild tag
- Add Image as a dependency of image.fit
- Drop kbuild tag
- Add dependency on dtbs
- Drop unnecessary path separator for dtbs
- Rebase to -next
Changes in v6:
- Drop the unwanted .gz suffix
Changes in v5:
- Drop patch previously applied
- Correct compression rule which was broken in v4
Changes in v4:
- Use single quotes for UIMAGE_NAME
Changes in v3:
- Drop temporary file image.itk
- Drop patch 'Use double quotes for image name'
- Drop double quotes in use of UIMAGE_NAME
- Drop unnecessary CONFIG_EFI_ZBOOT condition for help
- Avoid hard-coding "arm64" for the DT architecture
Changes in v2:
- Drop patch previously applied
- Add .gitignore file
- Move fit rule to Makefile.lib using an intermediate file
- Drop dependency on CONFIG_EFI_ZBOOT
- Pick up .dtb files separately from the kernel
- Correct pylint too-many-args warning for write_kernel()
- Include the kernel image in the file count
- Add a pointer to the FIT spec and mention of its wide industry usage
- Mention the kernel version in the FIT description
Simon Glass (2):
arm64: Add BOOT_TARGETS variable
arm64: boot: Support Flat Image Tree
Documentation/process/changes.rst | 9 +
MAINTAINERS | 7 +
arch/arm64/Makefile | 11 +-
arch/arm64/boot/.gitignore | 1 +
arch/arm64/boot/Makefile | 6 +-
scripts/Makefile.lib | 16 ++
scripts/make_fit.py | 290 ++++++++++++++++++++++++++++++
7 files changed, 337 insertions(+), 3 deletions(-)
create mode 100755 scripts/make_fit.py
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v12 1/2] arm64: Add BOOT_TARGETS variable
From: Simon Glass @ 2024-03-29 3:28 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Masahiro Yamada, Ahmad Fatoum, Nicolas Schier, Simon Glass,
Catalin Marinas, Will Deacon, linux-kernel
In-Reply-To: <20240329032836.141899-1-sjg@chromium.org>
Add a new variable containing a list of possible targets. Mark them as
phony. This matches the approach taken for arch/arm
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v7)
Changes in v7:
- Drop the kbuild tag
Changes in v6:
- Drop the unwanted .gz suffix
arch/arm64/Makefile | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 0e075d3c546b..1217d97998ac 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -154,6 +154,10 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
# Default target when executing plain make
boot := arch/arm64/boot
+BOOT_TARGETS := Image vmlinuz.efi
+
+PHONY += $(BOOT_TARGETS)
+
ifeq ($(CONFIG_EFI_ZBOOT),)
KBUILD_IMAGE := $(boot)/Image.gz
else
@@ -163,7 +167,7 @@ endif
all: $(notdir $(KBUILD_IMAGE))
vmlinuz.efi: Image
-Image vmlinuz.efi: vmlinux
+$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
Image.%: Image
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v12 2/2] arm64: boot: Support Flat Image Tree
From: Simon Glass @ 2024-03-29 3:28 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Masahiro Yamada, Ahmad Fatoum, Nicolas Schier, Simon Glass,
Catalin Marinas, Jonathan Corbet, Nathan Chancellor, Nick Terrell,
Will Deacon, linux-doc, linux-kbuild, linux-kernel, workflows
In-Reply-To: <20240329032836.141899-1-sjg@chromium.org>
Add a script which produces a Flat Image Tree (FIT), a single file
containing the built kernel and associated devicetree files.
Compression defaults to gzip which gives a good balance of size and
performance.
The files compress from about 86MB to 24MB using this approach.
The FIT can be used by bootloaders which support it, such as U-Boot
and Linuxboot. It permits automatic selection of the correct
devicetree, matching the compatible string of the running board with
the closest compatible string in the FIT. There is no need for
filenames or other workarounds.
Add a 'make image.fit' build target for arm64, as well.
The FIT can be examined using 'dumpimage -l'.
This uses the 'dtbs-list' file but processes only .dtb files, ignoring
the overlay .dtbo files.
This features requires pylibfdt (use 'pip install libfdt'). It also
requires compression utilities for the algorithm being used. Supported
compression options are the same as the Image.xxx files. Use
FIT_COMPRESSION to select an algorithm other than gzip.
While FIT supports a ramdisk / initrd, no attempt is made to support
this here, since it must be built separately from the Linux build.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v12:
- Avoid showing FIT message if V=0
Changes in v11:
- Use dtbslist file in image.fit rule
- Update cmd_fit rule as per Masahiro
- Don't mention ignoring files without a .dtb prefix
- Use argparse fromfile_prefix_chars feature
- Add a -v option and use it for output (with make V=1)
- rename srcdir to dtbs
- Use -o for the output file instead of -f
Changes in v10:
- Make use of dtbs-list file
- Mention dtbs-list and FIT_COMPRESSION
- Update copyright year
- Update cover letter to take account of an applied patch
Changes in v9:
- Move the compression control into Makefile.lib
Changes in v8:
- Drop compatible string in FDT node
- Correct sorting of MAINTAINERS to before ARM64 PORT
- Turn compress part of the make_fit.py comment in to a sentence
- Add two blank lines before parse_args() and setup_fit()
- Use 'image.fit: dtbs' instead of BUILD_DTBS var
- Use '$(<D)/dts' instead of '$(dir $<)dts'
- Add 'mkimage' details Documentation/process/changes.rst
- Allow changing the compression used
- Tweak cover letter since there is only one clean-up patch
Changes in v7:
- Add Image as a dependency of image.fit
- Drop kbuild tag
- Add dependency on dtbs
- Drop unnecessary path separator for dtbs
- Rebase to -next
Changes in v5:
- Drop patch previously applied
- Correct compression rule which was broken in v4
Changes in v4:
- Use single quotes for UIMAGE_NAME
Changes in v3:
- Drop temporary file image.itk
- Drop patch 'Use double quotes for image name'
- Drop double quotes in use of UIMAGE_NAME
- Drop unnecessary CONFIG_EFI_ZBOOT condition for help
- Avoid hard-coding "arm64" for the DT architecture
Changes in v2:
- Drop patch previously applied
- Add .gitignore file
- Move fit rule to Makefile.lib using an intermediate file
- Drop dependency on CONFIG_EFI_ZBOOT
- Pick up .dtb files separately from the kernel
- Correct pylint too-many-args warning for write_kernel()
- Include the kernel image in the file count
- Add a pointer to the FIT spec and mention of its wide industry usage
- Mention the kernel version in the FIT description
Documentation/process/changes.rst | 9 +
MAINTAINERS | 7 +
arch/arm64/Makefile | 7 +-
arch/arm64/boot/.gitignore | 1 +
arch/arm64/boot/Makefile | 6 +-
scripts/Makefile.lib | 16 ++
scripts/make_fit.py | 290 ++++++++++++++++++++++++++++++
7 files changed, 333 insertions(+), 3 deletions(-)
create mode 100755 scripts/make_fit.py
diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst
index 7ef8de58f7f8..3a39395bd9d3 100644
--- a/Documentation/process/changes.rst
+++ b/Documentation/process/changes.rst
@@ -62,6 +62,7 @@ Sphinx\ [#f1]_ 2.4.4 sphinx-build --version
cpio any cpio --version
GNU tar 1.28 tar --version
gtags (optional) 6.6.5 gtags --version
+mkimage (optional) 2017.01 mkimage --version
====================== =============== ========================================
.. [#f1] Sphinx is needed only to build the Kernel documentation
@@ -189,6 +190,14 @@ The kernel build requires GNU GLOBAL version 6.6.5 or later to generate
tag files through ``make gtags``. This is due to its use of the gtags
``-C (--directory)`` flag.
+mkimage
+-------
+
+This tool is used when building a Flat Image Tree (FIT), commonly used on ARM
+platforms. The tool is available via the ``u-boot-tools`` package or can be
+built from the U-Boot source code. See the instructions at
+https://docs.u-boot.org/en/latest/build/tools.html#building-tools-for-linux
+
System utilities
****************
diff --git a/MAINTAINERS b/MAINTAINERS
index d36c19c1bf81..d28089145ca8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3079,6 +3079,13 @@ F: drivers/mmc/host/sdhci-of-arasan.c
N: zynq
N: xilinx
+ARM64 FIT SUPPORT
+M: Simon Glass <sjg@chromium.org>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm64/boot/Makefile
+F: scripts/make_fit.py
+
ARM64 PORT (AARCH64 ARCHITECTURE)
M: Catalin Marinas <catalin.marinas@arm.com>
M: Will Deacon <will@kernel.org>
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 1217d97998ac..b8b1d4f4a572 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -154,7 +154,7 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
# Default target when executing plain make
boot := arch/arm64/boot
-BOOT_TARGETS := Image vmlinuz.efi
+BOOT_TARGETS := Image vmlinuz.efi image.fit
PHONY += $(BOOT_TARGETS)
@@ -166,7 +166,9 @@ endif
all: $(notdir $(KBUILD_IMAGE))
-vmlinuz.efi: Image
+image.fit: dtbs
+
+vmlinuz.efi image.fit: Image
$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
@@ -219,6 +221,7 @@ virtconfig:
define archhelp
echo '* Image.gz - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'
echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
+ echo ' image.fit - Flat Image Tree (arch/$(ARCH)/boot/image.fit)'
echo ' install - Install uncompressed kernel'
echo ' zinstall - Install compressed kernel'
echo ' Install using (your) ~/bin/installkernel or'
diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore
index af5dc61f8b43..abaae9de1bdd 100644
--- a/arch/arm64/boot/.gitignore
+++ b/arch/arm64/boot/.gitignore
@@ -2,3 +2,4 @@
Image
Image.gz
vmlinuz*
+image.fit
diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile
index a5a787371117..607a67a649c4 100644
--- a/arch/arm64/boot/Makefile
+++ b/arch/arm64/boot/Makefile
@@ -16,7 +16,8 @@
OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
-targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo Image.zst
+targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo \
+ Image.zst image.fit
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)
@@ -39,6 +40,9 @@ $(obj)/Image.lzo: $(obj)/Image FORCE
$(obj)/Image.zst: $(obj)/Image FORCE
$(call if_changed,zstd)
+$(obj)/image.fit: $(obj)/Image $(obj)/dts/dtbs-list FORCE
+ $(call if_changed,fit)
+
EFI_ZBOOT_PAYLOAD := Image
EFI_ZBOOT_BFD_TARGET := elf64-littleaarch64
EFI_ZBOOT_MACH_TYPE := ARM64
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 743edb09f9c7..1ca2d9982031 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -504,6 +504,22 @@ quiet_cmd_uimage = UIMAGE $@
-a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
-n '$(UIMAGE_NAME)' -d $< $@
+# Flat Image Tree (FIT)
+# This allows for packaging of a kernel and all devicetrees files, using
+# compression.
+# ---------------------------------------------------------------------------
+
+MAKE_FIT := $(srctree)/scripts/make_fit.py
+
+# Use this to override the compression algorithm
+FIT_COMPRESSION ?= gzip
+
+quiet_cmd_fit = FIT $@
+ cmd_fit = $(MAKE_FIT) -o $@ --arch $(UIMAGE_ARCH) --os linux \
+ --name '$(UIMAGE_NAME)' \
+ $(if $(findstring 1,$(KBUILD_VERBOSE)),-v) \
+ --compress $(FIT_COMPRESSION) -k $< @$(word 2,$^)
+
# XZ
# ---------------------------------------------------------------------------
# Use xzkern or xzkern_with_size to compress the kernel image and xzmisc to
diff --git a/scripts/make_fit.py b/scripts/make_fit.py
new file mode 100755
index 000000000000..3de90c5a094b
--- /dev/null
+++ b/scripts/make_fit.py
@@ -0,0 +1,290 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2024 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+"""Build a FIT containing a lot of devicetree files
+
+Usage:
+ make_fit.py -A arm64 -n 'Linux-6.6' -O linux
+ -o arch/arm64/boot/image.fit -k /tmp/kern/arch/arm64/boot/image.itk
+ @arch/arm64/boot/dts/dtbs-list -E -c gzip
+
+Creates a FIT containing the supplied kernel and a set of devicetree files,
+either specified individually or listed in a file (with an '@' prefix).
+
+Use -E to generate an external FIT (where the data is placed after the
+FIT data structure). This allows parsing of the data without loading
+the entire FIT.
+
+Use -c to compress the data, using bzip2, gzip, lz4, lzma, lzo and
+zstd algorithms.
+
+The resulting FIT can be booted by bootloaders which support FIT, such
+as U-Boot, Linuxboot, Tianocore, etc.
+
+Note that this tool does not yet support adding a ramdisk / initrd.
+"""
+
+import argparse
+import collections
+import os
+import subprocess
+import sys
+import tempfile
+import time
+
+import libfdt
+
+
+# Tool extension and the name of the command-line tools
+CompTool = collections.namedtuple('CompTool', 'ext,tools')
+
+COMP_TOOLS = {
+ 'bzip2': CompTool('.bz2', 'bzip2'),
+ 'gzip': CompTool('.gz', 'pigz,gzip'),
+ 'lz4': CompTool('.lz4', 'lz4'),
+ 'lzma': CompTool('.lzma', 'lzma'),
+ 'lzo': CompTool('.lzo', 'lzop'),
+ 'zstd': CompTool('.zstd', 'zstd'),
+}
+
+
+def parse_args():
+ """Parse the program ArgumentParser
+
+ Returns:
+ Namespace object containing the arguments
+ """
+ epilog = 'Build a FIT from a directory tree containing .dtb files'
+ parser = argparse.ArgumentParser(epilog=epilog, fromfile_prefix_chars='@')
+ parser.add_argument('-A', '--arch', type=str, required=True,
+ help='Specifies the architecture')
+ parser.add_argument('-c', '--compress', type=str, default='none',
+ help='Specifies the compression')
+ parser.add_argument('-E', '--external', action='store_true',
+ help='Convert the FIT to use external data')
+ parser.add_argument('-n', '--name', type=str, required=True,
+ help='Specifies the name')
+ parser.add_argument('-o', '--output', type=str, required=True,
+ help='Specifies the output file (.fit)')
+ parser.add_argument('-O', '--os', type=str, required=True,
+ help='Specifies the operating system')
+ parser.add_argument('-k', '--kernel', type=str, required=True,
+ help='Specifies the (uncompressed) kernel input file (.itk)')
+ parser.add_argument('-v', '--verbose', action='store_true',
+ help='Enable verbose output')
+ parser.add_argument('dtbs', type=str, nargs='*',
+ help='Specifies the devicetree files to process')
+
+ return parser.parse_args()
+
+
+def setup_fit(fsw, name):
+ """Make a start on writing the FIT
+
+ Outputs the root properties and the 'images' node
+
+ Args:
+ fsw (libfdt.FdtSw): Object to use for writing
+ name (str): Name of kernel image
+ """
+ fsw.INC_SIZE = 65536
+ fsw.finish_reservemap()
+ fsw.begin_node('')
+ fsw.property_string('description', f'{name} with devicetree set')
+ fsw.property_u32('#address-cells', 1)
+
+ fsw.property_u32('timestamp', int(time.time()))
+ fsw.begin_node('images')
+
+
+def write_kernel(fsw, data, args):
+ """Write out the kernel image
+
+ Writes a kernel node along with the required properties
+
+ Args:
+ fsw (libfdt.FdtSw): Object to use for writing
+ data (bytes): Data to write (possibly compressed)
+ args (Namespace): Contains necessary strings:
+ arch: FIT architecture, e.g. 'arm64'
+ fit_os: Operating Systems, e.g. 'linux'
+ name: Name of OS, e.g. 'Linux-6.6.0-rc7'
+ compress: Compression algorithm to use, e.g. 'gzip'
+ """
+ with fsw.add_node('kernel'):
+ fsw.property_string('description', args.name)
+ fsw.property_string('type', 'kernel_noload')
+ fsw.property_string('arch', args.arch)
+ fsw.property_string('os', args.os)
+ fsw.property_string('compression', args.compress)
+ fsw.property('data', data)
+ fsw.property_u32('load', 0)
+ fsw.property_u32('entry', 0)
+
+
+def finish_fit(fsw, entries):
+ """Finish the FIT ready for use
+
+ Writes the /configurations node and subnodes
+
+ Args:
+ fsw (libfdt.FdtSw): Object to use for writing
+ entries (list of tuple): List of configurations:
+ str: Description of model
+ str: Compatible stringlist
+ """
+ fsw.end_node()
+ seq = 0
+ with fsw.add_node('configurations'):
+ for model, compat in entries:
+ seq += 1
+ with fsw.add_node(f'conf-{seq}'):
+ fsw.property('compatible', bytes(compat))
+ fsw.property_string('description', model)
+ fsw.property_string('fdt', f'fdt-{seq}')
+ fsw.property_string('kernel', 'kernel')
+ fsw.end_node()
+
+
+def compress_data(inf, compress):
+ """Compress data using a selected algorithm
+
+ Args:
+ inf (IOBase): Filename containing the data to compress
+ compress (str): Compression algorithm, e.g. 'gzip'
+
+ Return:
+ bytes: Compressed data
+ """
+ if compress == 'none':
+ return inf.read()
+
+ comp = COMP_TOOLS.get(compress)
+ if not comp:
+ raise ValueError(f"Unknown compression algorithm '{compress}'")
+
+ with tempfile.NamedTemporaryFile() as comp_fname:
+ with open(comp_fname.name, 'wb') as outf:
+ done = False
+ for tool in comp.tools.split(','):
+ try:
+ subprocess.call([tool, '-c'], stdin=inf, stdout=outf)
+ done = True
+ break
+ except FileNotFoundError:
+ pass
+ if not done:
+ raise ValueError(f'Missing tool(s): {comp.tools}\n')
+ with open(comp_fname.name, 'rb') as compf:
+ comp_data = compf.read()
+ return comp_data
+
+
+def output_dtb(fsw, seq, fname, arch, compress):
+ """Write out a single devicetree to the FIT
+
+ Args:
+ fsw (libfdt.FdtSw): Object to use for writing
+ seq (int): Sequence number (1 for first)
+ fmame (str): Filename containing the DTB
+ arch: FIT architecture, e.g. 'arm64'
+ compress (str): Compressed algorithm, e.g. 'gzip'
+
+ Returns:
+ tuple:
+ str: Model name
+ bytes: Compatible stringlist
+ """
+ with fsw.add_node(f'fdt-{seq}'):
+ # Get the compatible / model information
+ with open(fname, 'rb') as inf:
+ data = inf.read()
+ fdt = libfdt.FdtRo(data)
+ model = fdt.getprop(0, 'model').as_str()
+ compat = fdt.getprop(0, 'compatible')
+
+ fsw.property_string('description', model)
+ fsw.property_string('type', 'flat_dt')
+ fsw.property_string('arch', arch)
+ fsw.property_string('compression', compress)
+ fsw.property('compatible', bytes(compat))
+
+ with open(fname, 'rb') as inf:
+ compressed = compress_data(inf, compress)
+ fsw.property('data', compressed)
+ return model, compat
+
+
+def build_fit(args):
+ """Build the FIT from the provided files and arguments
+
+ Args:
+ args (Namespace): Program arguments
+
+ Returns:
+ tuple:
+ bytes: FIT data
+ int: Number of configurations generated
+ size: Total uncompressed size of data
+ """
+ seq = 0
+ size = 0
+ fsw = libfdt.FdtSw()
+ setup_fit(fsw, args.name)
+ entries = []
+
+ # Handle the kernel
+ with open(args.kernel, 'rb') as inf:
+ comp_data = compress_data(inf, args.compress)
+ size += os.path.getsize(args.kernel)
+ write_kernel(fsw, comp_data, args)
+
+ for fname in args.dtbs:
+ # Ignore overlay (.dtbo) files
+ if os.path.splitext(fname)[1] == '.dtb':
+ seq += 1
+ size += os.path.getsize(fname)
+ model, compat = output_dtb(fsw, seq, fname, args.arch, args.compress)
+ entries.append([model, compat])
+
+ finish_fit(fsw, entries)
+
+ # Include the kernel itself in the returned file count
+ return fsw.as_fdt().as_bytearray(), seq + 1, size
+
+
+def run_make_fit():
+ """Run the tool's main logic"""
+ args = parse_args()
+
+ out_data, count, size = build_fit(args)
+ with open(args.output, 'wb') as outf:
+ outf.write(out_data)
+
+ ext_fit_size = None
+ if args.external:
+ mkimage = os.environ.get('MKIMAGE', 'mkimage')
+ subprocess.check_call([mkimage, '-E', '-F', args.output],
+ stdout=subprocess.DEVNULL)
+
+ with open(args.output, 'rb') as inf:
+ data = inf.read()
+ ext_fit = libfdt.FdtRo(data)
+ ext_fit_size = ext_fit.totalsize()
+
+ if args.verbose:
+ comp_size = len(out_data)
+ print(f'FIT size {comp_size:#x}/{comp_size / 1024 / 1024:.1f} MB',
+ end='')
+ if ext_fit_size:
+ print(f', header {ext_fit_size:#x}/{ext_fit_size / 1024:.1f} KB',
+ end='')
+ print(f', {count} files, uncompressed {size / 1024 / 1024:.1f} MB')
+
+
+if __name__ == "__main__":
+ sys.exit(run_make_fit())
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 2/2] ARM: dts: imx6ull: add seeed studio NPi dev board
From: Shawn Guo @ 2024-03-29 4:00 UTC (permalink / raw)
To: Parthiban Nallathambi
Cc: robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer,
kernel, festevam, linux-imx, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240229082337.3090778-2-parthiban@linumiz.com>
On Thu, Feb 29, 2024 at 01:53:37PM +0530, Parthiban Nallathambi wrote:
> Add support for Seed Stuidos NPi i.MX6ULL SoM equipped with
> 512MB RAM and 8GB eMMC or 512MB NAND flash. Development
> board comes with either eMMC or NAND based SoM with peripheral
> interfaces like 2 x ethernet, 2 x USB, LCD, CSI and more.
>
> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
> ---
> arch/arm/boot/dts/nxp/imx/Makefile | 2 +
> .../imx/imx6ull-seeed-npi-dev-board-emmc.dts | 19 +
> .../imx/imx6ull-seeed-npi-dev-board-nand.dts | 19 +
> .../nxp/imx/imx6ull-seeed-npi-dev-board.dtsi | 424 ++++++++++++++++++
> .../boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi | 155 +++++++
> 5 files changed, 619 insertions(+)
> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts
> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts
> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
> create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi
Could you elaborate a bit the point of splitting imx6ull-seeed-npi.dtsi
and imx6ull-seeed-npi-dev-board.dtsi? Why cannot they be a single file?
Shawn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RESEND PATCH] dmaengine: imx-sdma: support dual fifo for DEV_TO_DEV
From: Frank Li @ 2024-03-29 4:18 UTC (permalink / raw)
To: Shengjiu Wang
Cc: vkoul, shawnguo, s.hauer, kernel, festevam, shengjiu.wang,
linux-imx, dmaengine, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <1711682887-15676-1-git-send-email-shengjiu.wang@nxp.com>
On Fri, Mar 29, 2024 at 11:28:07AM +0800, Shengjiu Wang wrote:
> SSI and SPDIF are dual fifo interface, when support ASRC P2P
> with SSI and SPDIF, the src fifo or dst fifo number can be
> two.
>
> The p2p watermark level bit 13 and 14 are designed for
> these use case. This patch is to complete this function
> in driver.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> Signed-off-by: Joy Zou <joy.zou@nxp.com>
> Acked-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This already in my sdma improvement patch list.
https://lore.kernel.org/imx/20240318-sdma_upstream-v3-0-da37ddd44d49@nxp.com/T/#m59e4e03a527103de7bf1a7fe86e8fbc570454970
This have more nice commit message. Can I take one into my patch series to
avoid conflict.
Frank
> ---
> drivers/dma/imx-sdma.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 9b42f5e96b1e..079e6e8f4f59 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -137,7 +137,11 @@
> * 0: Source on AIPS
> * 12 Destination Bit(DP) 1: Destination on SPBA
> * 0: Destination on AIPS
> - * 13-15 --------- MUST BE 0
> + * 13 Source FIFO 1: Source is dual FIFO
> + * 0: Source is single FIFO
> + * 14 Destination FIFO 1: Destination is dual FIFO
> + * 0: Destination is single FIFO
> + * 15 --------- MUST BE 0
> * 16-23 Higher WML HWML
> * 24-27 N Total number of samples after
> * which Pad adding/Swallowing
> @@ -168,6 +172,8 @@
> #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
> #define SDMA_WATERMARK_LEVEL_SP BIT(11)
> #define SDMA_WATERMARK_LEVEL_DP BIT(12)
> +#define SDMA_WATERMARK_LEVEL_SD BIT(13)
> +#define SDMA_WATERMARK_LEVEL_DD BIT(14)
> #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
> #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
> #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
> @@ -1255,6 +1261,16 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
> sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
>
> sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
> +
> + /*
> + * Limitation: The p2p script support dual fifos in maximum,
> + * So when fifo number is larger than 1, force enable dual
> + * fifos.
> + */
> + if (sdmac->n_fifos_src > 1)
> + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD;
> + if (sdmac->n_fifos_dst > 1)
> + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD;
> }
>
> static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [RESEND PATCH] dmaengine: imx-sdma: support dual fifo for DEV_TO_DEV
From: Shengjiu Wang @ 2024-03-29 4:25 UTC (permalink / raw)
To: Frank Li
Cc: Shengjiu Wang, vkoul, shawnguo, s.hauer, kernel, festevam,
linux-imx, dmaengine, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <ZgZBH/HsO8YmgFZx@lizhi-Precision-Tower-5810>
On Fri, Mar 29, 2024 at 12:18 PM Frank Li <Frank.li@nxp.com> wrote:
>
> On Fri, Mar 29, 2024 at 11:28:07AM +0800, Shengjiu Wang wrote:
> > SSI and SPDIF are dual fifo interface, when support ASRC P2P
> > with SSI and SPDIF, the src fifo or dst fifo number can be
> > two.
> >
> > The p2p watermark level bit 13 and 14 are designed for
> > these use case. This patch is to complete this function
> > in driver.
> >
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > Signed-off-by: Joy Zou <joy.zou@nxp.com>
> > Acked-by: Iuliana Prodan <iuliana.prodan@nxp.com>
>
> This already in my sdma improvement patch list.
>
> https://lore.kernel.org/imx/20240318-sdma_upstream-v3-0-da37ddd44d49@nxp.com/T/#m59e4e03a527103de7bf1a7fe86e8fbc570454970
>
> This have more nice commit message. Can I take one into my patch series to
> avoid conflict.
Yes, please.
best regards
wang shengjiu
>
> Frank
>
> > ---
> > drivers/dma/imx-sdma.c | 18 +++++++++++++++++-
> > 1 file changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> > index 9b42f5e96b1e..079e6e8f4f59 100644
> > --- a/drivers/dma/imx-sdma.c
> > +++ b/drivers/dma/imx-sdma.c
> > @@ -137,7 +137,11 @@
> > * 0: Source on AIPS
> > * 12 Destination Bit(DP) 1: Destination on SPBA
> > * 0: Destination on AIPS
> > - * 13-15 --------- MUST BE 0
> > + * 13 Source FIFO 1: Source is dual FIFO
> > + * 0: Source is single FIFO
> > + * 14 Destination FIFO 1: Destination is dual FIFO
> > + * 0: Destination is single FIFO
> > + * 15 --------- MUST BE 0
> > * 16-23 Higher WML HWML
> > * 24-27 N Total number of samples after
> > * which Pad adding/Swallowing
> > @@ -168,6 +172,8 @@
> > #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
> > #define SDMA_WATERMARK_LEVEL_SP BIT(11)
> > #define SDMA_WATERMARK_LEVEL_DP BIT(12)
> > +#define SDMA_WATERMARK_LEVEL_SD BIT(13)
> > +#define SDMA_WATERMARK_LEVEL_DD BIT(14)
> > #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
> > #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
> > #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
> > @@ -1255,6 +1261,16 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
> > sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
> >
> > sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
> > +
> > + /*
> > + * Limitation: The p2p script support dual fifos in maximum,
> > + * So when fifo number is larger than 1, force enable dual
> > + * fifos.
> > + */
> > + if (sdmac->n_fifos_src > 1)
> > + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD;
> > + if (sdmac->n_fifos_dst > 1)
> > + sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD;
> > }
> >
> > static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
> > --
> > 2.34.1
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2] pmdomain: mediatek: Add MT8188 buck isolation setting
From: Fei Shao @ 2024-03-29 4:38 UTC (permalink / raw)
To: Ulf Hansson
Cc: Johnson Wang, Fei Shao, AngeloGioacchino Del Regno,
Matthias Brugger, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-pm
From: Johnson Wang <johnson.wang@mediatek.com>
From: Johnson Wang <johnson.wang@mediatek.com>
Add buck isolation setting to ADSP_AO, CAM_VCORE and IMG_VCORE power
domains in MT8188 for proper buck isolation control in power domain
on/off.
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Signed-off-by: Fei Shao <fshao@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Changes in v2:
[1] was reviewed but didn't get accepted at the time.
This rebases [1] on next-20240327 with revised commit message.
[1]: https://lore.kernel.org/all/20230315114505.25144-1-johnson.wang@mediatek.com/
drivers/pmdomain/mediatek/mt8188-pm-domains.h | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/pmdomain/mediatek/mt8188-pm-domains.h b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
index 06834ab6597c..007235be9efe 100644
--- a/drivers/pmdomain/mediatek/mt8188-pm-domains.h
+++ b/drivers/pmdomain/mediatek/mt8188-pm-domains.h
@@ -175,6 +175,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x35C,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
+ .ext_buck_iso_offs = 0x3EC,
+ .ext_buck_iso_mask = BIT(10),
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
@@ -187,7 +189,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
MT8188_TOP_AXI_PROT_EN_2_CLR,
MT8188_TOP_AXI_PROT_EN_2_STA),
},
- .caps = MTK_SCPD_ALWAYS_ON,
+ .caps = MTK_SCPD_ALWAYS_ON | MTK_SCPD_EXT_BUCK_ISO,
},
[MT8188_POWER_DOMAIN_ADSP_INFRA] = {
.name = "adsp_infra",
@@ -524,6 +526,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A4,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
+ .ext_buck_iso_offs = 0x3EC,
+ .ext_buck_iso_mask = BIT(12),
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
@@ -541,7 +545,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY |
+ MTK_SCPD_EXT_BUCK_ISO,
},
[MT8188_POWER_DOMAIN_IMG_MAIN] = {
.name = "img_main",
@@ -591,6 +596,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
.ctl_offs = 0x3A0,
.pwr_sta_offs = 0x16C,
.pwr_sta2nd_offs = 0x170,
+ .ext_buck_iso_offs = 0x3EC,
+ .ext_buck_iso_mask = BIT(11),
.bp_cfg = {
BUS_PROT_WR(INFRA,
MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
@@ -618,7 +625,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
MT8188_TOP_AXI_PROT_EN_MM_2_STA),
},
- .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY |
+ MTK_SCPD_EXT_BUCK_ISO,
},
[MT8188_POWER_DOMAIN_CAM_MAIN] = {
.name = "cam_main",
--
2.44.0.478.gd926399ef9-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH net-next RESEND v6 0/7] Fix missing PHY-to-MAC RX clock
From: patchwork-bot+netdevbpf @ 2024-03-29 5:10 UTC (permalink / raw)
To: Romain Gantois
Cc: linux, andrew, hkallweit1, davem, edumazet, kuba, pabeni,
alexandre.torgue, joabreu, mcoquelin.stm32, clement.leger,
maxime.chevallier, miquel.raynal, thomas.petazzoni, netdev,
linux-stm32, linux-arm-kernel, linux-renesas-soc, rmk+kernel,
xiaoning.wang
In-Reply-To: <20240326-rxc_bugfix-v6-0-24a74e5c761f@bootlin.com>
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Tue, 26 Mar 2024 14:32:06 +0100 you wrote:
> Hello everyone,
>
> This is version six of my series that addresses the issue with some MAC/PHY
> combinations.
>
> Notable changes in v6:
> - Corrected trailers
>
> [...]
Here is the summary with links:
- [RESEND,net-next,v6,1/7] net: phylink: add PHY_F_RXC_ALWAYS_ON to PHY dev flags
https://git.kernel.org/netdev/net-next/c/21d9ba5bc551
- [RESEND,net-next,v6,2/7] net: phylink: add rxc_always_on flag to phylink_pcs
https://git.kernel.org/netdev/net-next/c/dceb393a0a8e
- [RESEND,net-next,v6,3/7] net: stmmac: don't rely on lynx_pcs presence to check for a PHY
https://git.kernel.org/netdev/net-next/c/10658e99d952
- [RESEND,net-next,v6,4/7] net: stmmac: Support a generic PCS field in mac_device_info
https://git.kernel.org/netdev/net-next/c/f7bff228a616
- [RESEND,net-next,v6,5/7] net: stmmac: Signal to PHY/PCS drivers to keep RX clock on
https://git.kernel.org/netdev/net-next/c/58329b03a595
- [RESEND,net-next,v6,6/7] net: phy: qcom: at803x: Avoid hibernating if MAC requires RX clock
https://git.kernel.org/netdev/net-next/c/30dc5873967e
- [RESEND,net-next,v6,7/7] net: pcs: rzn1-miic: Init RX clock early if MAC requires it
https://git.kernel.org/netdev/net-next/c/0f671b3b6edf
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v6 3/5] arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases for it
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Jayesh Choudhary, Chintan Vankar
In-Reply-To: <20240329053130.2822129-1-c-vankar@ti.com>
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Enable MAIN CPSW2G and add alias for it to enable Linux to fetch
MAC Address for the port directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-4-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 1f390c22844e..637c8223b561 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -28,6 +28,7 @@ aliases {
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
ethernet0 = &mcu_cpsw_port1;
+ ethernet1 = &main_cpsw1_port1;
};
memory@80000000 {
@@ -281,6 +282,30 @@ &wkup_gpio0 {
&main_pmx0 {
bootph-all;
+ main_cpsw2g_default_pins: main-cpsw2g-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+ J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+ J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+ J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+ J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+ J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+ J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+ J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+ J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+
+ main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
main_uart8_pins_default: main-uart8-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -833,6 +858,31 @@ &mcu_cpsw_port1 {
phy-handle = <&mcu_phy0>;
};
+&main_cpsw1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_default_pins>;
+ status = "okay";
+};
+
+&main_cpsw1_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_mdio_default_pins>;
+ status = "okay";
+
+ main_cpsw1_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw1_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw1_phy0>;
+ status = "okay";
+};
+
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v6 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
In-Reply-To: <20240329053130.2822129-1-c-vankar@ti.com>
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII
mode with the Add-On Ethernet Card connected to the ENET Expansion
1 slot on the EVM.
Add support to reset the PHY from kernel by using gpio-hog and
gpio-reset.
Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-5-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/Makefile | 7 +-
.../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 9a722c2473fb..f8e47278df43 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -145,6 +146,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
+k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-quad-port-eth-exp1.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
@@ -165,7 +168,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am69-sk-csi2-dual-imx219-dtbs \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-sk-csi2-dual-imx219-dtbs \
- k3-j721s2-evm-pcie1-ep.dtb
+ k3-j721s2-evm-pcie1-ep.dtb \
+ k3-j784s4-evm-quad-port-eth-exp1.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
@@ -181,3 +185,4 @@ DTC_FLAGS_k3-am69-sk += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721e-sk += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@
+DTC_FLAGS_k3-j784s4-evm += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
new file mode 100644
index 000000000000..dcd2c7c39ec3
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
+ * board.
+ *
+ * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
+ *
+ * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-pinctrl.h"
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
+ ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
+ ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
+ ethernet5 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ status = "okay";
+};
+
+&main_cpsw0_port5 {
+ phy-handle = <&cpsw9g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port6 {
+ phy-handle = <&cpsw9g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port7 {
+ phy-handle = <&cpsw9g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_port8 {
+ phy-handle = <&cpsw9g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+};
+
+&main_cpsw0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_default_pins>;
+ bus_freq = <1000000>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ cpsw9g_phy0: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw9g_phy1: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw9g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw9g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ /* Power-up ENET1 EXPANDER PHY. */
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ /* Toggle MUX2 for MDIO lines */
+ mux-sel-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
+&main_pmx0 {
+ mdio0_default_pins: mdio0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
+ J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
+ >;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
+};
+
+&serdes_wiz2 {
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ serdes2_qsgmii_link: phy@0 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz2 3>;
+ };
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v6 1/5] arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
In-Reply-To: <20240329053130.2822129-1-c-vankar@ti.com>
Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address
for the port directly from U-Boot.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-2-c-vankar@ti.com/
Changes from v5 to v6:
- No changes in v6.
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 81fd7afac8c5..1f390c22844e 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -27,6 +27,7 @@ aliases {
mmc1 = &main_sdhci1;
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
+ ethernet0 = &mcu_cpsw_port1;
};
memory@80000000 {
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v6 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
In-Reply-To: <20240329053130.2822129-1-c-vankar@ti.com>
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode
with MAC Ports 1 and 2 of the instance, which are connected to ENET
Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through
the Serdes2 instance of the SERDES.
Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode
at 5 Gbps each.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-6-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
arch/arm64/boot/dts/ti/Makefile | 6 +-
.../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++
2 files changed, 86 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index f8e47278df43..2d798ef415e4 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
@@ -148,6 +149,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \
k3-j784s4-evm-quad-port-eth-exp1.dtbo
+k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \
+ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
@@ -169,7 +172,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-sk-csi2-dual-imx219-dtbs \
k3-j721s2-evm-pcie1-ep.dtb \
- k3-j784s4-evm-quad-port-eth-exp1.dtb
+ k3-j784s4-evm-quad-port-eth-exp1.dtb \
+ k3-j784s4-evm-usxgmii-exp1-exp2.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
new file mode 100644
index 000000000000..d5f8c8531923
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/**
+ * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
+ * and ENET-2 Expansion slots of J784S4 EVM.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "k3-serdes.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+ ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_cpsw0 {
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&main_cpsw0_port1 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&main_cpsw0_port2 {
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "okay";
+ fixed-link {
+ speed = <5000>;
+ full-duplex;
+ };
+};
+
+&serdes_wiz2 {
+ assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
+ status = "okay";
+};
+
+&serdes2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ serdes2_usxgmii_link: phy@2 {
+ reg = <2>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
+ resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4] staging: media: imx: Remove duplicate Kconfig dependency
From: coolrrsh @ 2024-03-29 5:44 UTC (permalink / raw)
To: slongerbeam, p.zabel, mchehab, gregkh, shawnguo, s.hauer, kernel,
festevam, linux-imx, linux-media, linux-staging, linux-arm-kernel,
linux-kernel
Cc: linux-kernel-mentees, Rajeshwar R Shinde
From: Rajeshwar R Shinde <coolrrsh@gmail.com>
The kernel configuration VIDEO_DEV is defined twice in Kconfig.
Thus, the duplicate Kconfig dependency is removed.
Signed-off-by: Rajeshwar R Shinde <coolrrsh@gmail.com>
---
v1->v2
changed the commit message
v2->v3
changed the subject
v3->v4
changed the commit message and subject
---
drivers/staging/media/imx/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig
index 21fd79515042..772f49b1fe52 100644
--- a/drivers/staging/media/imx/Kconfig
+++ b/drivers/staging/media/imx/Kconfig
@@ -4,7 +4,6 @@ config VIDEO_IMX_MEDIA
depends on ARCH_MXC || COMPILE_TEST
depends on HAS_DMA
depends on VIDEO_DEV
- depends on VIDEO_DEV
select MEDIA_CONTROLLER
select V4L2_FWNODE
select V4L2_MEM2MEM_DEV
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH] spi: s3c64xx: Use DMA mode from fifo size
From: Jaewon Kim @ 2024-03-29 5:53 UTC (permalink / raw)
To: Sam Protsenko
Cc: Andi Shyti, Mark Brown, Krzysztof Kozlowski, Alim Akhtar,
linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel
In-Reply-To: <CAPLW+4k4qh4ZYBufZoGbUZN0yxSE2X8bOdkEQVw1Zg9YUVpbug@mail.gmail.com>
Hi Sam,
Thanks for your review.
On 3/29/24 02:58, Sam Protsenko wrote:
> On Tue, Mar 26, 2024 at 10:35 PM Jaewon Kim<jaewon02.kim@samsung.com> wrote:
>> The SPI data size is smaller than FIFO, it operates in PIO mode,
> Spelling: "The" -> "If the"
Thanks, I will fix it v2.
>> and if it is larger than FIFO mode, DMA mode is selected.
>>
>> If the data size is the same as the FIFO size, it operates in PIO mode
>> and data is separated into two transfer. In order to prevent,
> Nit: "transfer" -> "transfers", "prevent" -> "prevent it"
Thanks, I will fix it v2.
>> DMA mode must be used from the case of FIFO and data size.
>>
> You probably mean this code (it occurs two times in the driver):
>
> xfer->len = fifo_len - 1;
>
> Can you please elaborate on why it's done this way? Why can't we just
> do "xfer->len = fifo_len" and use the whole FIFO for the transfer
> instead? I don't understand the necessity to split the transfer into
> two chunks if its size is of FIFO length -- wouldn't it fit into FIFO
> in that case? (I'm pretty sure this change is correct, just want to
> understand how exactly it works).
In IRQ mode(S3C64XX_SPI_MODE_RX_RDY_LVL enable), TxOverrun/RxUnderrun
irq occurs when FIFO is full.
To avoid FIFO full, it is transmitted in a smaller size than
fifo_len.(fifo-len - 1)
However, in case of "fifo_len == data size" "fifo_len - 1" byte + "1"
byte were transmitted separately.
This problem can be solved by starting DMA transmission start size from
fifo_len.
>> Fixes: 1ee806718d5e ("spi: s3c64xx: support interrupt based pio mode")
> Just wonder if that fixes some throughput regression, or something
> worse (like failed transfers when the transfer size is the same as
> FIFO size)?
It is not a critical issue, but When I look at the actual waveform, it
seems strange that only the last 1-byte is transmitted separately.
I thought it was "Fixes", but if not, I will remove it.
>> Signed-off-by: Jaewon Kim<jaewon02.kim@samsung.com>
>> ---
>> drivers/spi/spi-s3c64xx.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>> index 9fcbe040cb2f..81ed5fddf83e 100644
>> --- a/drivers/spi/spi-s3c64xx.c
>> +++ b/drivers/spi/spi-s3c64xx.c
>> @@ -430,7 +430,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
>> struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
>>
>> if (sdd->rx_dma.ch && sdd->tx_dma.ch)
>> - return xfer->len > sdd->fifo_depth;
>> + return xfer->len >= sdd->fifo_depth;
>>
>> return false;
>> }
>> @@ -826,11 +826,11 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host,
>> return status;
>> }
>>
>> - if (!is_polling(sdd) && (xfer->len > fifo_len) &&
>> + if (!is_polling(sdd) && xfer->len >= fifo_len &&
>> sdd->rx_dma.ch && sdd->tx_dma.ch) {
>> use_dma = 1;
>>
> Would be nice to remove this empty line, while at it.
Good, I will remove it also.
>> - } else if (xfer->len >= fifo_len) {
>> + } else if (xfer->len > fifo_len) {
> Below in the same function I can see similar code:
>
> if (target_len >= fifo_len)
> xfer->len = fifo_len - 1;
>
> Shouldn't that 'if' condition be fixed too? Or it's ok as it is? (Just
> noticed it by searching, not sure myself, hence asking).
You are correct. This 'if' condition should not have been modified.
>> tx_buf = xfer->tx_buf;
>> rx_buf = xfer->rx_buf;
>> origin_len = xfer->len;
>> --
>> 2.43.2
>>
>>
Thanks
Jaewon Kim
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] spi: s3c64xx: Use DMA mode from fifo size
From: Sam Protsenko @ 2024-03-29 6:01 UTC (permalink / raw)
To: Jaewon Kim
Cc: Andi Shyti, Mark Brown, Krzysztof Kozlowski, Alim Akhtar,
linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel
In-Reply-To: <63355869-e679-7226-7719-36b62169db7e@samsung.com>
On Fri, Mar 29, 2024 at 12:53 AM Jaewon Kim <jaewon02.kim@samsung.com> wrote:
>
> Hi Sam,
>
> Thanks for your review.
>
>
> On 3/29/24 02:58, Sam Protsenko wrote:
> > On Tue, Mar 26, 2024 at 10:35 PM Jaewon Kim<jaewon02.kim@samsung.com> wrote:
> >> The SPI data size is smaller than FIFO, it operates in PIO mode,
> > Spelling: "The" -> "If the"
>
> Thanks, I will fix it v2.
>
> >> and if it is larger than FIFO mode, DMA mode is selected.
> >>
> >> If the data size is the same as the FIFO size, it operates in PIO mode
> >> and data is separated into two transfer. In order to prevent,
> > Nit: "transfer" -> "transfers", "prevent" -> "prevent it"
>
> Thanks, I will fix it v2.
>
> >> DMA mode must be used from the case of FIFO and data size.
> >>
> > You probably mean this code (it occurs two times in the driver):
> >
> > xfer->len = fifo_len - 1;
> >
> > Can you please elaborate on why it's done this way? Why can't we just
> > do "xfer->len = fifo_len" and use the whole FIFO for the transfer
> > instead? I don't understand the necessity to split the transfer into
> > two chunks if its size is of FIFO length -- wouldn't it fit into FIFO
> > in that case? (I'm pretty sure this change is correct, just want to
> > understand how exactly it works).
>
> In IRQ mode(S3C64XX_SPI_MODE_RX_RDY_LVL enable), TxOverrun/RxUnderrun
> irq occurs when FIFO is full.
>
> To avoid FIFO full, it is transmitted in a smaller size than
> fifo_len.(fifo-len - 1)
>
> However, in case of "fifo_len == data size" "fifo_len - 1" byte + "1"
> byte were transmitted separately.
>
> This problem can be solved by starting DMA transmission start size from
> fifo_len.
>
Thanks for the explanation! Please feel free to add:
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
> >> Fixes: 1ee806718d5e ("spi: s3c64xx: support interrupt based pio mode")
> > Just wonder if that fixes some throughput regression, or something
> > worse (like failed transfers when the transfer size is the same as
> > FIFO size)?
>
> It is not a critical issue, but When I look at the actual waveform, it
> seems strange that only the last 1-byte is transmitted separately.
>
> I thought it was "Fixes", but if not, I will remove it.
>
No no, I was just curious. "Fixes" is fine with me.
> >> Signed-off-by: Jaewon Kim<jaewon02.kim@samsung.com>
> >> ---
> >> drivers/spi/spi-s3c64xx.c | 6 +++---
> >> 1 file changed, 3 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> >> index 9fcbe040cb2f..81ed5fddf83e 100644
> >> --- a/drivers/spi/spi-s3c64xx.c
> >> +++ b/drivers/spi/spi-s3c64xx.c
> >> @@ -430,7 +430,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host,
> >> struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
> >>
> >> if (sdd->rx_dma.ch && sdd->tx_dma.ch)
> >> - return xfer->len > sdd->fifo_depth;
> >> + return xfer->len >= sdd->fifo_depth;
> >>
> >> return false;
> >> }
> >> @@ -826,11 +826,11 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host,
> >> return status;
> >> }
> >>
> >> - if (!is_polling(sdd) && (xfer->len > fifo_len) &&
> >> + if (!is_polling(sdd) && xfer->len >= fifo_len &&
> >> sdd->rx_dma.ch && sdd->tx_dma.ch) {
> >> use_dma = 1;
> >>
> > Would be nice to remove this empty line, while at it.
> Good, I will remove it also.
> >> - } else if (xfer->len >= fifo_len) {
> >> + } else if (xfer->len > fifo_len) {
> > Below in the same function I can see similar code:
> >
> > if (target_len >= fifo_len)
> > xfer->len = fifo_len - 1;
> >
> > Shouldn't that 'if' condition be fixed too? Or it's ok as it is? (Just
> > noticed it by searching, not sure myself, hence asking).
>
> You are correct. This 'if' condition should not have been modified.
>
> >> tx_buf = xfer->tx_buf;
> >> rx_buf = xfer->rx_buf;
> >> origin_len = xfer->len;
> >> --
> >> 2.43.2
> >>
> >>
>
> Thanks
>
> Jaewon Kim
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [RESEND PATCH] dmaengine: imx-sdma: support dual fifo for DEV_TO_DEV
From: Shengjiu Wang @ 2024-03-29 3:28 UTC (permalink / raw)
To: vkoul, shawnguo, s.hauer, kernel, festevam, shengjiu.wang,
linux-imx, dmaengine, imx
Cc: linux-arm-kernel, linux-kernel
SSI and SPDIF are dual fifo interface, when support ASRC P2P
with SSI and SPDIF, the src fifo or dst fifo number can be
two.
The p2p watermark level bit 13 and 14 are designed for
these use case. This patch is to complete this function
in driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Acked-by: Iuliana Prodan <iuliana.prodan@nxp.com>
---
drivers/dma/imx-sdma.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9b42f5e96b1e..079e6e8f4f59 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -137,7 +137,11 @@
* 0: Source on AIPS
* 12 Destination Bit(DP) 1: Destination on SPBA
* 0: Destination on AIPS
- * 13-15 --------- MUST BE 0
+ * 13 Source FIFO 1: Source is dual FIFO
+ * 0: Source is single FIFO
+ * 14 Destination FIFO 1: Destination is dual FIFO
+ * 0: Destination is single FIFO
+ * 15 --------- MUST BE 0
* 16-23 Higher WML HWML
* 24-27 N Total number of samples after
* which Pad adding/Swallowing
@@ -168,6 +172,8 @@
#define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
#define SDMA_WATERMARK_LEVEL_SP BIT(11)
#define SDMA_WATERMARK_LEVEL_DP BIT(12)
+#define SDMA_WATERMARK_LEVEL_SD BIT(13)
+#define SDMA_WATERMARK_LEVEL_DD BIT(14)
#define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
#define SDMA_WATERMARK_LEVEL_LWE BIT(28)
#define SDMA_WATERMARK_LEVEL_HWE BIT(29)
@@ -1255,6 +1261,16 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
+
+ /*
+ * Limitation: The p2p script support dual fifos in maximum,
+ * So when fifo number is larger than 1, force enable dual
+ * fifos.
+ */
+ if (sdmac->n_fifos_src > 1)
+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SD;
+ if (sdmac->n_fifos_dst > 1)
+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DD;
}
static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2)
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
NVIDIA's Tegra241 (Grace) SoC has a CMDQ-Virtualization (CMDQV) hardware
that extends standard ARM SMMUv3 to support multiple command queues with
virtualization capabilities. Though this is similar to the ECMDQ in SMMU
v3.3, CMDQV provides additional Virtual Interfaces (VINTFs) allowing VMs
to have their own VINTFs and Virtual Command Queues (VCMDQs). The VCMDQs
can only execute a limited set of commands, mainly invalidation commands
when exclusively used by the VMs, compared to the standard SMMUv3 CMDQ.
Thus, there are two parts of patch series to add its support: the basic
in-kernel support as part 1, and the user-space support as part 2.
The in-kernel support is to detect/configure the CMDQV hardware and then
allocate a VINTF with some VCMDQs for the kernel/hypervisor to use. Like
ECMDQ, CMDQV also allows the kernel to use multiple VCMDQs, giving some
limited performance improvement: up to 20% reduction of TLB invalidation
time was measured by a multi-threaded DMA unmap benchmark, compared to a
single queue.
The user-space support is to provide uAPIs (via IOMMUFD) for hypervisors
in user space to passthrough VCMDQs to VMs, allowing these VMs to access
the VCMDQs directly without trappings, i.e. no VM Exits. This gives huge
performance improvements: 70% to 90% reductions of TLB invalidation time
were measured by various DMA unmap tests running in a guest OS, compared
to a nested SMMU CMDQ (with trappings).
This is the part-1 series:
- Preparatory changes to share the existing SMMU functions
- A new CMDQV driver and extending the SMMUv3 driver to interact with
the new driver
- Limit the commands for a guest kernel.
It's available on Github:
https://github.com/nicolinc/iommufd/commits/vcmdq_in_kernel-v1
And the part-2 series is currently WIP, with a pair of drafts available:
https://github.com/nicolinc/linux-nvidia-6.5/commits/iommufd_nesting-vcmdq/
https://github.com/nicolinc/qemu/commits/wip/iommufd_vcmdq/
It's planned to send for review after nested SMMU kernel patches.
Note that this in-kernel support isn't confined to host kernels running
on Grace-powered servers, but is also used by guest kernels running on
VMs virtualized on those servers. So, those VMs must install the driver,
ideally before the part 2 is merged. So, later those servers would only
need to upgrade their host kernels without bothering the VMs.
Thank you!
Changelog
v4:
* Rebased on v6.9-rc1
* Renamed to "tegra241-cmdqv", following other Grace kernel patches
* Added a set of print and MMIO helpers
* Reworked the guest limitation patch
v3:
https://lore.kernel.org/all/20211119071959.16706-1-nicolinc@nvidia.com/
* Dropped VMID and mdev patches to redesign later based on IOMMUFD
* Separated HYP_OWN part for guest support into a new patch
* Added new preparatory changes
v2:
https://lore.kernel.org/all/20210831025923.15812-1-nicolinc@nvidia.com/
* Added mdev interface support for hypervisor and VMs
* Added preparatory changes for mdev interface implementation
* PATCH-12 Changed ->issue_cmdlist() to ->get_cmdq() for a better
integration with recently merged ECMDQ-related changes
v1:
https://lore.kernel.org/all/20210723193140.9690-1-nicolinc@nvidia.com/
Nate Watterson (1):
iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace)
CMDQV
Nicolin Chen (5):
iommu/arm-smmu-v3: Add CS_NONE quirk
iommu/arm-smmu-v3: Make arm_smmu_cmdq_init reusable
iommu/arm-smmu-v3: Make __arm_smmu_cmdq_skip_err reusable
iommu/arm-smmu-v3: Pass in cmdq pointer to
arm_smmu_cmdq_issue_cmdlist()
iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF
MAINTAINERS | 1 +
drivers/iommu/Kconfig | 12 +
drivers/iommu/arm/arm-smmu-v3/Makefile | 1 +
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 46 ++
.../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 665 ++++++++++++++++++
6 files changed, 772 insertions(+), 27 deletions(-)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 2/6] iommu/arm-smmu-v3: Make arm_smmu_cmdq_init reusable
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
The CMDQV extension in NVIDIA Tegra241 SoC resues the arm_smmu_cmdq
structure while the queue location isn't same as smmu->cmdq.
Add a cmdq argument to arm_smmu_cmdq_init() function and shares its
define in the header for CMDQV driver to use.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index da3957ad95be..44fcc0c0a149 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3135,9 +3135,9 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
return 0;
}
-static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu)
+int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq)
{
- struct arm_smmu_cmdq *cmdq = &smmu->cmdq;
unsigned int nents = 1 << cmdq->q.llq.max_n_shift;
atomic_set(&cmdq->owner_prod, 0);
@@ -3162,7 +3162,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
if (ret)
return ret;
- ret = arm_smmu_cmdq_init(smmu);
+ ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq);
if (ret)
return ret;
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index b95d9a9ae0a8..4af0976a2338 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -758,6 +758,9 @@ bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd);
int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid,
unsigned long iova, size_t size);
+int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq);
+
#ifdef CONFIG_ARM_SMMU_V3_SVA
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
bool arm_smmu_master_sva_supported(struct arm_smmu_master *master);
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 3/6] iommu/arm-smmu-v3: Make __arm_smmu_cmdq_skip_err reusable
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
Allow __arm_smmu_cmdq_skip_err function to be reused by NVIDIA Tegra241
CMDQV unit since it will use the same data structure for q.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 +++++++++-------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 44fcc0c0a149..6cb20bff5a8a 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -379,8 +379,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,
arm_smmu_cmdq_build_cmd(cmd, &ent);
}
-static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,
- struct arm_smmu_queue *q)
+void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q)
{
static const char * const cerror_str[] = {
[CMDQ_ERR_CERROR_NONE_IDX] = "No error",
@@ -397,12 +396,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,
.opcode = CMDQ_OP_CMD_SYNC,
};
- dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons,
+ dev_err(dev, "CMDQ error (cons 0x%08x): %s\n", cons,
idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown");
switch (idx) {
case CMDQ_ERR_CERROR_ABT_IDX:
- dev_err(smmu->dev, "retrying command fetch\n");
+ dev_err(dev, "retrying command fetch\n");
return;
case CMDQ_ERR_CERROR_NONE_IDX:
return;
@@ -424,9 +423,12 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,
* not to touch any of the shadow cmdq state.
*/
queue_read(cmd, Q_ENT(q, cons), q->ent_dwords);
- dev_err(smmu->dev, "skipping command in error state:\n");
+ dev_err(dev, "skipping command in error state:\n");
for (i = 0; i < ARRAY_SIZE(cmd); ++i)
- dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
+ dev_err(dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
+
+ if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)
+ cmd_sync.sync.cs_none = true;
/* Convert the erroneous command into a CMD_SYNC */
arm_smmu_cmdq_build_cmd(cmd, &cmd_sync);
@@ -436,7 +438,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,
static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
{
- __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q);
+ __arm_smmu_cmdq_skip_err(smmu->dev, &smmu->cmdq.q);
}
/*
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 4af0976a2338..3046c1028e66 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -760,6 +760,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid,
int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,
struct arm_smmu_cmdq *cmdq);
+void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q);
#ifdef CONFIG_ARM_SMMU_V3_SVA
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 4/6] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_issue_cmdlist()
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
The driver currently calls arm_smmu_get_cmdq() helper in different places,
although they are all called from the arm_smmu_cmdq_issue_cmdlist().
Allow to pass in the cmdq pointer, instead of calling arm_smmu_get_cmdq()
every time.
This will also help CMDQV extension in NVIDIA Tegra241 SoC, as its driver
will maintain its own cmdq pointers, then need to redirect arm_smmu->cmdq
to one of its vcmdqs upon seeing a supported command.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 6cb20bff5a8a..7630c1dd5235 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -603,11 +603,11 @@ static void arm_smmu_cmdq_poll_valid_map(struct arm_smmu_cmdq *cmdq,
/* Wait for the command queue to become non-full */
static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq,
struct arm_smmu_ll_queue *llq)
{
unsigned long flags;
struct arm_smmu_queue_poll qp;
- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu);
int ret = 0;
/*
@@ -638,11 +638,11 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu,
* Must be called with the cmdq lock held in some capacity.
*/
static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq,
struct arm_smmu_ll_queue *llq)
{
int ret = 0;
struct arm_smmu_queue_poll qp;
- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu);
u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod));
queue_poll_init(smmu, &qp);
@@ -662,10 +662,10 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu,
* Must be called with the cmdq lock held in some capacity.
*/
static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq,
struct arm_smmu_ll_queue *llq)
{
struct arm_smmu_queue_poll qp;
- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu);
u32 prod = llq->prod;
int ret = 0;
@@ -712,13 +712,14 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu,
}
static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu,
+ struct arm_smmu_cmdq *cmdq,
struct arm_smmu_ll_queue *llq)
{
if (smmu->options & ARM_SMMU_OPT_MSIPOLL &&
!(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY))
- return __arm_smmu_cmdq_poll_until_msi(smmu, llq);
+ return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq);
- return __arm_smmu_cmdq_poll_until_consumed(smmu, llq);
+ return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq);
}
static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds,
@@ -775,7 +776,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
while (!queue_has_space(&llq, n + sync)) {
local_irq_restore(flags);
- if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq))
+ if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq))
dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
local_irq_save(flags);
}
@@ -851,7 +852,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
/* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */
if (sync) {
llq.prod = queue_inc_prod_n(&llq, n);
- ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq);
+ ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq);
if (ret) {
dev_err_ratelimited(smmu->dev,
"CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n",
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 6/6] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
When VCMDQs are assigned to a VINTF owned by a guest (HYP_OWN bit unset),
only TLB and ATC invalidation commands are supported by the VCMDQ HW. So,
add a new helper to scan the input cmds to make sure every single command
is supported when selecting a queue.
Note that the guest VM shouldn't have HYP_OWN bit being set regardless of
guest kernel driver writing it or not, i.e. the hypervisor running in the
host OS should wire this bit to zero when trapping a write access to this
VINTF_CONFIG register from a guest kernel.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +--
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 ++-
.../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 44 ++++++++++++++++++-
3 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index d12e048ddd93..5cc31cdf1ab7 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -352,10 +352,11 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
return 0;
}
-static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu)
+static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu,
+ u64 *cmds, int n)
{
if (smmu->tegra241_cmdqv)
- return tegra241_cmdqv_get_cmdq(smmu);
+ return tegra241_cmdqv_get_cmdq(smmu, cmds, n);
return &smmu->cmdq;
}
@@ -765,7 +766,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
u32 prod;
unsigned long flags;
bool owner;
- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu);
+ struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu, cmds, n);
struct arm_smmu_ll_queue llq, head;
int ret = 0;
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 22270de3aed7..495c80579c8e 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -834,7 +834,8 @@ static inline void arm_smmu_sva_remove_dev_pasid(struct iommu_domain *domain,
struct tegra241_cmdqv *
tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id);
int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu);
-struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu);
+struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,
+ u64 *cmds, int n);
#else /* CONFIG_TEGRA241_CMDQV */
static inline struct tegra241_cmdqv *
tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id)
@@ -848,7 +849,7 @@ static inline int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu)
}
static inline struct arm_smmu_cmdq *
-tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu)
+tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, u64 *cmds, int n)
{
return NULL;
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
index 4bfddeb658e2..7816ec8e6075 100644
--- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
+++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
@@ -213,6 +213,7 @@ struct tegra241_vintf {
u16 idx;
bool enabled;
+ bool hyp_own;
atomic_t error;
struct tegra241_cmdqv *cmdqv;
@@ -330,7 +331,33 @@ static int tegra241_cmdqv_init_one_vcmdq(struct tegra241_vcmdq *vcmdq)
return arm_smmu_cmdq_init(cmdqv->smmu, cmdq);
}
-struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu)
+static bool tegra241_vintf_support_cmds(struct tegra241_vintf *vintf,
+ u64 *cmds, int n)
+{
+ int i;
+
+ /* VINTF owned by hypervisor can execute any command */
+ if (vintf->hyp_own)
+ return true;
+
+ /* Guest-owned VINTF must Check against the list of supported CMDs */
+ for (i = 0; i < n; i++) {
+ switch (FIELD_GET(CMDQ_0_OP, cmds[i * CMDQ_ENT_DWORDS])) {
+ case CMDQ_OP_TLBI_NH_ASID:
+ case CMDQ_OP_TLBI_NH_VA:
+ case CMDQ_OP_ATC_INV:
+ continue;
+ default:
+ return false;
+ }
+ }
+
+ return true;
+}
+
+struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,
+ u64 *cmds, int n)
+
{
struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv;
struct tegra241_vintf *vintf = cmdqv->vintf[0];
@@ -344,6 +371,10 @@ struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu)
if (atomic_read(&vintf->error))
return &smmu->cmdq;
+ /* Unsupported CMDs go for smmu->cmdq pathway */
+ if (!tegra241_vintf_support_cmds(vintf, cmds, n))
+ return &smmu->cmdq;
+
/*
* Select a vcmdq to use. Here we use a temporal solution to
* balance out traffic on cmdq issuing: each cmdq has its own
@@ -405,12 +436,23 @@ int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu)
atomic_set(&vintf->error, 0);
vintf->base = cmdqv->base + TEGRA241_VINTF(0);
+ /*
+ * Note that HYP_OWN bit is wired to zero when running in guest kernel
+ * regardless of enabling it here, as !HYP_OWN cmdqs have a restricted
+ * set of supported commands, by following the HW design.
+ */
regval = FIELD_PREP(VINTF_HYP_OWN, 1);
vintf_writel(regval, CONFIG);
regval |= FIELD_PREP(VINTF_EN, 1);
vintf_writel(regval, CONFIG);
+ /*
+ * As being mentioned above, HYP_OWN bit is wired to zero for a guest
+ * kernel, so read it back from HW to ensure that reflects in hyp_own
+ */
+ vintf->hyp_own = !!FIELD_GET(VINTF_HYP_OWN, vintf_readl(CONFIG));
+
ret = readl_relaxed_poll_timeout(vintf->base + TEGRA241_VINTF_STATUS,
regval, regval & VINTF_ENABLED,
1, ARM_SMMU_POLL_TIMEOUT_US);
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 1/6] iommu/arm-smmu-v3: Add CS_NONE quirk
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the
CS field of CMD_SYNC. Add a quirk flag to accommodate that.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++--
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 5ed036225e69..da3957ad95be 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -334,7 +334,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag);
break;
case CMDQ_OP_CMD_SYNC:
- if (ent->sync.msiaddr) {
+ if (ent->sync.cs_none) {
+ cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE);
+ } else if (ent->sync.msiaddr) {
cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);
cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK;
} else {
@@ -371,6 +373,9 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,
q->ent_dwords * 8;
}
+ if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)
+ ent.sync.cs_none = true;
+
arm_smmu_cmdq_build_cmd(cmd, &ent);
}
@@ -707,7 +712,8 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu,
static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu,
struct arm_smmu_ll_queue *llq)
{
- if (smmu->options & ARM_SMMU_OPT_MSIPOLL)
+ if (smmu->options & ARM_SMMU_OPT_MSIPOLL &&
+ !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY))
return __arm_smmu_cmdq_poll_until_msi(smmu, llq);
return __arm_smmu_cmdq_poll_until_consumed(smmu, llq);
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 23baf117e7e4..b95d9a9ae0a8 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -509,6 +509,7 @@ struct arm_smmu_cmdq_ent {
#define CMDQ_OP_CMD_SYNC 0x46
struct {
u64 msiaddr;
+ bool cs_none;
} sync;
};
};
@@ -541,6 +542,9 @@ struct arm_smmu_queue {
u32 __iomem *prod_reg;
u32 __iomem *cons_reg;
+
+#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */
+ u32 quirks;
};
struct arm_smmu_queue_poll {
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v4 5/6] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV
From: Nicolin Chen @ 2024-03-29 6:14 UTC (permalink / raw)
To: will, robin.murphy
Cc: joro, jgg, thierry.reding, vdumpa, jonathanh, linux-kernel, iommu,
linux-arm-kernel, linux-tegra
In-Reply-To: <cover.1711690673.git.nicolinc@nvidia.com>
From: Nate Watterson <nwatterson@nvidia.com>
NVIDIA's Tegra241 Soc has a CMDQ-Virtualization (CMDQV) hardware, extending
the standard ARM SMMU v3 IP to support multiple VCMDQs with virtualization
capabilities. In terms of command queue, they are very like a standard SMMU
CMDQ (or ECMDQs), but only support CS_NONE in the CS field of CMD_SYNC.
Add a new tegra241-cmdqv driver, and insert its structure pointer into the
existing arm_smmu_device, and then add related function calls in the SMMUv3
driver to interact with the CMDQV driver.
In the CMDQV driver, add a minimal part for the in-kernel support: reserve
VINTF0 for in-kernel use, and assign some of the VCMDQs to the VINTF0, and
select one VCMDQ based on the current CPU ID to execute supported commands.
This multi-queue design for in-kernel use gives some limited improvements:
up to 20% reduction of invalidation time was measured by a multi-threaded
DMA unmap benchmark, compared to a single queue.
The other part of the CMDQV driver will be user-space support that gives a
hypervisor running on the host OS to talk to the driver for virtualization
use cases, allowing VMs to use VCMDQs without trappings, i.e. no VM Exits.
This is currently WIP based on IOMMUFD, and will be sent for review after
SMMU nesting patches are getting merged. This part will provide a guest OS
a bigger improvement: 70% to 90% reductions of TLB invalidation time were
measured by DMA unmap tests running in a guest OS, compared to nested SMMU
CMDQ (with trappings).
However, it is very important for this in-kernel support to get merged and
installed to VMs running on Grace-powered servers as soon as possible. So,
later those servers would only need to upgrade their host kernels for the
user-space support.
As the initial version, the CMDQV driver only supports ACPI configurations.
Signed-off-by: Nate Watterson <nwatterson@nvidia.com>
Co-developed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
MAINTAINERS | 1 +
drivers/iommu/Kconfig | 12 +
drivers/iommu/arm/arm-smmu-v3/Makefile | 1 +
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 37 ++
.../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 623 ++++++++++++++++++
6 files changed, 690 insertions(+), 6 deletions(-)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa3b947fb080..ebe8f720fffc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21719,6 +21719,7 @@ M: Thierry Reding <thierry.reding@gmail.com>
R: Krishna Reddy <vdumpa@nvidia.com>
L: linux-tegra@vger.kernel.org
S: Supported
+F: drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
F: drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
F: drivers/iommu/tegra*
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 0af39bbbe3a3..82e557de31e3 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -410,6 +410,18 @@ config ARM_SMMU_V3_SVA
Say Y here if your system supports SVA extensions such as PCIe PASID
and PRI.
+config TEGRA241_CMDQV
+ bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"
+ depends on ARM_SMMU_V3
+ depends on ACPI
+ help
+ Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The
+ CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues
+ support, except with virtualization capabilities.
+
+ Say Y here if your system is NVIDIA Tegra241 (Grace) or it has the same
+ CMDQ-V extension.
+
config S390_IOMMU
def_bool y if S390 && PCI
depends on S390 && PCI
diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile
index 54feb1ecccad..8dff2bc4c7f3 100644
--- a/drivers/iommu/arm/arm-smmu-v3/Makefile
+++ b/drivers/iommu/arm/arm-smmu-v3/Makefile
@@ -2,4 +2,5 @@
obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
arm_smmu_v3-objs-y += arm-smmu-v3.o
arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
+arm_smmu_v3-objs-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o
arm_smmu_v3-objs := $(arm_smmu_v3-objs-y)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 7630c1dd5235..d12e048ddd93 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -354,6 +354,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu)
{
+ if (smmu->tegra241_cmdqv)
+ return tegra241_cmdqv_get_cmdq(smmu);
+
return &smmu->cmdq;
}
@@ -3095,12 +3098,10 @@ static struct iommu_ops arm_smmu_ops = {
};
/* Probing and initialisation functions */
-static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
- struct arm_smmu_queue *q,
- void __iomem *page,
- unsigned long prod_off,
- unsigned long cons_off,
- size_t dwords, const char *name)
+int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
+ struct arm_smmu_queue *q, void __iomem *page,
+ unsigned long prod_off, unsigned long cons_off,
+ size_t dwords, const char *name)
{
size_t qsz;
@@ -3635,6 +3636,12 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
return ret;
}
+ if (smmu->tegra241_cmdqv) {
+ ret = tegra241_cmdqv_device_reset(smmu);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -3928,6 +3935,9 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE)
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
+ smmu->tegra241_cmdqv =
+ tegra241_cmdqv_acpi_probe(smmu, node->identifier);
+
return 0;
}
#else
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 3046c1028e66..22270de3aed7 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -625,6 +625,8 @@ struct arm_smmu_strtab_cfg {
u32 strtab_base_cfg;
};
+struct tegra241_cmdqv;
+
/* An SMMUv3 instance */
struct arm_smmu_device {
struct device *dev;
@@ -687,6 +689,12 @@ struct arm_smmu_device {
struct rb_root streams;
struct mutex streams_mutex;
+
+ /*
+ * Pointer to NVIDIA Tegra241 CMDQ-Virtualization Extension support,
+ * similar to v3.3 ECMDQ except with virtualization capabilities.
+ */
+ struct tegra241_cmdqv *tegra241_cmdqv;
};
struct arm_smmu_stream {
@@ -761,6 +769,10 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid,
int arm_smmu_cmdq_init(struct arm_smmu_device *smmu,
struct arm_smmu_cmdq *cmdq);
void __arm_smmu_cmdq_skip_err(struct device *dev, struct arm_smmu_queue *q);
+int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
+ struct arm_smmu_queue *q, void __iomem *page,
+ unsigned long prod_off, unsigned long cons_off,
+ size_t dwords, const char *name);
#ifdef CONFIG_ARM_SMMU_V3_SVA
bool arm_smmu_sva_supported(struct arm_smmu_device *smmu);
@@ -817,4 +829,29 @@ static inline void arm_smmu_sva_remove_dev_pasid(struct iommu_domain *domain,
{
}
#endif /* CONFIG_ARM_SMMU_V3_SVA */
+
+#ifdef CONFIG_TEGRA241_CMDQV
+struct tegra241_cmdqv *
+tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id);
+int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu);
+struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu);
+#else /* CONFIG_TEGRA241_CMDQV */
+static inline struct tegra241_cmdqv *
+tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id)
+{
+ return NULL;
+}
+
+static inline int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu)
+{
+ return -ENODEV;
+}
+
+static inline struct arm_smmu_cmdq *
+tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu)
+{
+ return NULL;
+}
+#endif /* CONFIG_TEGRA241_CMDQV */
+
#endif /* _ARM_SMMU_V3_H */
diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
new file mode 100644
index 000000000000..4bfddeb658e2
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2021-2024 NVIDIA CORPORATION & AFFILIATES. */
+
+#define dev_fmt(fmt) "tegra241_cmdqv: " fmt
+
+#include <linux/acpi.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/iommu.h>
+#include <linux/iopoll.h>
+
+#include <acpi/acpixf.h>
+
+#include "arm-smmu-v3.h"
+
+#define TEGRA241_CMDQV_HID "NVDA200C"
+
+/* CMDQV register page base and size defines */
+#define TEGRA241_CMDQV_CONFIG_BASE (0)
+#define TEGRA241_CMDQV_CONFIG_SIZE (SZ_64K)
+#define TEGRA241_VCMDQ_PAGE0_BASE (TEGRA241_CMDQV_CONFIG_BASE + SZ_64K)
+#define TEGRA241_VCMDQ_PAGE1_BASE (TEGRA241_VCMDQ_PAGE0_BASE + SZ_64K)
+#define TEGRA241_VINTF_VCMDQ_BASE (TEGRA241_VCMDQ_PAGE1_BASE + SZ_64K)
+
+/* CMDQV global config regs */
+#define TEGRA241_CMDQV_CONFIG 0x0000
+#define CMDQV_EN BIT(0)
+
+#define TEGRA241_CMDQV_PARAM 0x0004
+#define CMDQV_NUM_VINTF_LOG2 GENMASK(11, 8)
+#define CMDQV_NUM_VCMDQ_LOG2 GENMASK(7, 4)
+
+#define TEGRA241_CMDQV_STATUS 0x0008
+#define CMDQV_STATUS GENMASK(2, 1)
+#define CMDQV_ENABLED BIT(0)
+
+#define TEGRA241_CMDQV_VINTF_ERR_MAP 0x0014
+#define TEGRA241_CMDQV_VINTF_INT_MASK 0x001C
+#define TEGRA241_CMDQV_VCMDQ_ERR_MAP0 0x0024
+#define TEGRA241_CMDQV_VCMDQ_ERR_MAP(i) (0x0024 + 0x4*(i))
+
+#define TEGRA241_CMDQV_CMDQ_ALLOC(q) (0x0200 + 0x4*(q))
+#define CMDQV_CMDQ_ALLOC_VINTF GENMASK(20, 15)
+#define CMDQV_CMDQ_ALLOC_LVCMDQ GENMASK(7, 1)
+#define CMDQV_CMDQ_ALLOCATED BIT(0)
+
+/* VINTF config regs */
+#define TEGRA241_VINTF(v) (0x1000 + 0x100*(v))
+
+#define TEGRA241_VINTF_CONFIG 0x0000
+#define VINTF_HYP_OWN BIT(17)
+#define VINTF_VMID GENMASK(16, 1)
+#define VINTF_EN BIT(0)
+
+#define TEGRA241_VINTF_STATUS 0x0004
+#define VINTF_STATUS GENMASK(3, 1)
+#define VINTF_ENABLED BIT(0)
+
+#define TEGRA241_VINTF_CMDQ_ERR_MAP(m) (0x00C0 + 0x4*(m))
+
+/* VCMDQ config regs */
+/* -- PAGE0 -- */
+#define TEGRA241_VCMDQ_PAGE0(q) (TEGRA241_VCMDQ_PAGE0_BASE + 0x80*(q))
+
+#define TEGRA241_VCMDQ_CONS 0x00000
+#define VCMDQ_CONS_ERR GENMASK(30, 24)
+
+#define TEGRA241_VCMDQ_PROD 0x00004
+
+#define TEGRA241_VCMDQ_CONFIG 0x00008
+#define VCMDQ_EN BIT(0)
+
+#define TEGRA241_VCMDQ_STATUS 0x0000C
+#define VCMDQ_ENABLED BIT(0)
+
+#define TEGRA241_VCMDQ_GERROR 0x00010
+#define TEGRA241_VCMDQ_GERRORN 0x00014
+
+/* -- PAGE1 -- */
+#define TEGRA241_VCMDQ_PAGE1(q) (TEGRA241_VCMDQ_PAGE1_BASE + 0x80*(q))
+#define VCMDQ_ADDR GENMASK(47, 5)
+#define VCMDQ_LOG2SIZE GENMASK(4, 0)
+
+#define TEGRA241_VCMDQ_BASE 0x00000
+#define TEGRA241_VCMDQ_CONS_INDX_BASE 0x00008
+
+/* VINTF logical-VCMDQ pages */
+#define TEGRA241_VINTFi_PAGE0(i) (TEGRA241_VINTF_VCMDQ_BASE + SZ_128K*(i))
+#define TEGRA241_VINTFi_PAGE1(i) (TEGRA241_VINTFi_PAGE0(i) + SZ_64K)
+#define TEGRA241_VINTFi_VCMDQ_PAGE0(i, q) \
+ (TEGRA241_VINTFi_PAGE0(i) + 0x80*(q))
+#define TEGRA241_VINTFi_VCMDQ_PAGE1(i, q) \
+ (TEGRA241_VINTFi_PAGE1(i) + 0x80*(q))
+
+/* MMIO helpers */
+#define cmdqv_readl(reg) \
+ readl(cmdqv->base + TEGRA241_CMDQV_##reg)
+#define cmdqv_readl_relaxed(reg) \
+ readl_relaxed(cmdqv->base + TEGRA241_CMDQV_##reg)
+#define cmdqv_write(val, reg) \
+ writel((val), cmdqv->base + TEGRA241_CMDQV_##reg)
+#define cmdqv_writel_relaxed(val, reg) \
+ writel_relaxed((val), cmdqv->base + TEGRA241_CMDQV_##reg)
+
+#define vintf_readl(reg) \
+ readl(vintf->base + TEGRA241_VINTF_##reg)
+#define vintf_readl_relaxed(reg) \
+ readl_relaxed(vintf->base + TEGRA241_VINTF_##reg)
+#define vintf_writel(val, reg) \
+ writel((val), vintf->base + TEGRA241_VINTF_##reg)
+#define vintf_writel_relaxed(val, reg) \
+ writel_relaxed((val), vintf->base + TEGRA241_VINTF_##reg)
+
+#define vcmdq_page0_readl(reg) \
+ readl(vcmdq->page0 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page0_readl_relaxed(reg) \
+ readl_relaxed(vcmdq->page0 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page0_writel(val, reg) \
+ writel((val), vcmdq->page0 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page0_writel_relaxed(val, reg) \
+ writel_relaxed((val), vcmdq->page0 + TEGRA241_VCMDQ_##reg)
+
+#define vcmdq_page1_readl(reg) \
+ readl(vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page1_readl_relaxed(reg) \
+ readl_relaxed(vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page1_writel(val, reg) \
+ writel((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page1_writel_relaxed(val, reg) \
+ writel_relaxed((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page1_writeq(val, reg) \
+ writeq((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+#define vcmdq_page1_writeq_relaxed(val, reg) \
+ writeq_relaxed((val), vcmdq->page1 + TEGRA241_VCMDQ_##reg)
+
+/* Logging helpers */
+#define cmdqv_warn(fmt, ...) \
+ dev_warn(cmdqv->dev, fmt, ##__VA_ARGS__)
+#define cmdqv_err(fmt, ...) \
+ dev_err(cmdqv->dev, fmt, ##__VA_ARGS__)
+#define cmdqv_info(fmt, ...) \
+ dev_info(cmdqv->dev, fmt, ##__VA_ARGS__)
+#define cmdqv_dbg(fmt, ...) \
+ dev_dbg(cmdqv->dev, fmt, ##__VA_ARGS__)
+
+#define vintf_warn(fmt, ...) \
+ dev_warn(cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__)
+#define vintf_err(fmt, ...) \
+ dev_err(cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__)
+#define vintf_info(fmt, ...) \
+ dev_info(cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__)
+#define vintf_dbg(fmt, ...) \
+ dev_dbg(cmdqv->dev, "VINTF%u: " fmt, vintf->idx, ##__VA_ARGS__)
+
+#define vcmdq_warn(fmt, ...) \
+ do { \
+ if (vcmdq->vintf) \
+ vintf_warn("VCMDQ%u/LVCMDQ%u: " fmt, \
+ vcmdq->idx, vcmdq->logical_idx, \
+ ##__VA_ARGS__); \
+ else \
+ dev_warn(cmdqv->dev, "VCMDQ%u: " fmt, \
+ vcmdq->idx, ##__VA_ARGS__); \
+ } while (0)
+#define vcmdq_err(fmt, ...) \
+ do { \
+ if (vcmdq->vintf) \
+ vintf_err("VCMDQ%u/LVCMDQ%u: " fmt, \
+ vcmdq->idx, vcmdq->logical_idx, \
+ ##__VA_ARGS__); \
+ else \
+ dev_err(cmdqv->dev, "VCMDQ%u: " fmt, \
+ vcmdq->idx, ##__VA_ARGS__); \
+ } while (0)
+#define vcmdq_info(fmt, ...) \
+ do { \
+ if (vcmdq->vintf) \
+ vintf_info("VCMDQ%u/LVCMDQ%u: " fmt, \
+ vcmdq->idx, vcmdq->logical_idx, \
+ ##__VA_ARGS__); \
+ else \
+ dev_info(cmdqv->dev, "VCMDQ%u: " fmt, \
+ vcmdq->idx, ##__VA_ARGS__); \
+ } while (0)
+#define vcmdq_dbg(fmt, ...) \
+ do { \
+ if (vcmdq->vintf) \
+ vintf_dbg("VCMDQ%u/LVCMDQ%u: " fmt, \
+ vcmdq->idx, vcmdq->logical_idx, \
+ ##__VA_ARGS__); \
+ else \
+ dev_dbg(cmdqv->dev, "VCMDQ%u: " fmt, \
+ vcmdq->idx, ##__VA_ARGS__); \
+ } while (0)
+
+static bool disable_cmdqv;
+module_param(disable_cmdqv, bool, 0444);
+MODULE_PARM_DESC(disable_cmdqv,
+ "This allows to disable CMDQV and use default SMMU internal CMDQ.");
+
+struct tegra241_vcmdq {
+ u16 idx;
+ u16 logical_idx;
+
+ struct arm_smmu_cmdq cmdq;
+ struct tegra241_vintf *vintf;
+
+ void __iomem *page0;
+ void __iomem *page1;
+};
+
+struct tegra241_vintf {
+ u16 idx;
+
+ bool enabled;
+ atomic_t error;
+
+ struct tegra241_cmdqv *cmdqv;
+ struct tegra241_vcmdq **vcmdqs;
+
+ void __iomem *base;
+};
+
+struct tegra241_cmdqv {
+ struct arm_smmu_device *smmu;
+
+ struct device *dev;
+ struct resource res;
+ void __iomem *base;
+ int irq;
+
+ /* CMDQV Hardware Params */
+ u16 num_total_vintfs;
+ u16 num_total_vcmdqs;
+ u16 num_vcmdqs_per_vintf;
+
+ struct xarray vcmdqs;
+ struct xarray vintfs;
+
+ struct tegra241_vintf **vintf;
+};
+
+static void tegra241_cmdqv_handle_vintf0_error(struct tegra241_cmdqv *cmdqv)
+{
+ struct tegra241_vintf *vintf = cmdqv->vintf[0];
+ bool error;
+ int i;
+
+ /* Cache error status to bypass VCMDQs until error is recovered */
+ error = !!FIELD_GET(VINTF_STATUS, vintf_readl_relaxed(STATUS));
+ atomic_set(&vintf->error, error);
+
+ for (i = 0; i < 4; i++) {
+ u32 lvcmdq_err_map = vintf_readl_relaxed(CMDQ_ERR_MAP(i));
+
+ while (lvcmdq_err_map) {
+ int qidx = ffs(lvcmdq_err_map) - 1;
+ struct tegra241_vcmdq *vcmdq = vintf->vcmdqs[qidx];
+ u32 gerrorn, gerror;
+
+ lvcmdq_err_map &= ~BIT(qidx);
+
+ __arm_smmu_cmdq_skip_err(cmdqv->dev, &vcmdq->cmdq.q);
+
+ gerrorn = vcmdq_page0_readl_relaxed(GERRORN);
+ gerror = vcmdq_page0_readl_relaxed(GERROR);
+
+ vcmdq_page0_writel(gerror, GERRORN);
+ }
+ }
+
+ /* Now error status should be clean, cache it again */
+ error = !!FIELD_GET(VINTF_STATUS, vintf_readl_relaxed(STATUS));
+ atomic_set(&vintf->error, error);
+}
+
+static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid)
+{
+ struct tegra241_cmdqv *cmdqv = (struct tegra241_cmdqv *)devid;
+ u32 vintf_errs[2];
+ u32 vcmdq_errs[4];
+
+ vintf_errs[0] = cmdqv_readl_relaxed(VINTF_ERR_MAP);
+ vintf_errs[1] = cmdqv_readl_relaxed(VINTF_ERR_MAP + 0x4);
+
+ vcmdq_errs[0] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(0));
+ vcmdq_errs[1] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(1));
+ vcmdq_errs[2] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(2));
+ vcmdq_errs[3] = cmdqv_readl_relaxed(VCMDQ_ERR_MAP(3));
+
+ cmdqv_warn("unexpected cmdqv error reported\n");
+ cmdqv_warn(" vintf_map: 0x%08X%08X\n", vintf_errs[1], vintf_errs[0]);
+ cmdqv_warn(" vcmdq_map: 0x%08X%08X%08X%08X\n",
+ vcmdq_errs[3], vcmdq_errs[2], vcmdq_errs[1], vcmdq_errs[0]);
+
+ /* Handle VINTF0 and its VCMDQs */
+ if (vintf_errs[0] & 0x1)
+ tegra241_cmdqv_handle_vintf0_error(cmdqv);
+
+ return IRQ_HANDLED;
+}
+
+/* Adapt struct arm_smmu_cmdq init sequences from arm-smmu-v3.c for VCMDQs */
+static int tegra241_cmdqv_init_one_vcmdq(struct tegra241_vcmdq *vcmdq)
+{
+ struct tegra241_cmdqv *cmdqv = vcmdq->vintf->cmdqv;
+ struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq;
+ struct arm_smmu_queue *q = &cmdq->q;
+ char name[16];
+ int ret;
+
+ sprintf(name, "vcmdq%u", vcmdq->idx);
+
+ q->llq.max_n_shift = ilog2(SZ_64K >> CMDQ_ENT_SZ_SHIFT);
+
+ /* Use the common helper to init the VCMDQ, and then... */
+ ret = arm_smmu_init_one_queue(cmdqv->smmu, q, vcmdq->page0,
+ TEGRA241_VCMDQ_PROD, TEGRA241_VCMDQ_CONS,
+ CMDQ_ENT_DWORDS, name);
+ if (ret)
+ return ret;
+
+ /* ...override q_base to write VCMDQ_BASE registers */
+ q->q_base = q->base_dma & VCMDQ_ADDR;
+ q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift);
+
+ /* All VCMDQs support CS_NONE only for CMD_SYNC */
+ q->quirks = CMDQ_QUIRK_SYNC_CS_NONE_ONLY;
+
+ return arm_smmu_cmdq_init(cmdqv->smmu, cmdq);
+}
+
+struct arm_smmu_cmdq *tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu)
+{
+ struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv;
+ struct tegra241_vintf *vintf = cmdqv->vintf[0];
+ u16 qidx;
+
+ /* Use SMMU CMDQ if vintf[0] is uninitialized */
+ if (!vintf->enabled)
+ return &smmu->cmdq;
+
+ /* Use SMMU CMDQ if vintf[0] has error status */
+ if (atomic_read(&vintf->error))
+ return &smmu->cmdq;
+
+ /*
+ * Select a vcmdq to use. Here we use a temporal solution to
+ * balance out traffic on cmdq issuing: each cmdq has its own
+ * lock, if all cpus issue cmdlist using the same cmdq, only
+ * one CPU at a time can enter the process, while the others
+ * will be spinning at the same lock.
+ */
+ qidx = smp_processor_id() % cmdqv->num_vcmdqs_per_vintf;
+ return &vintf->vcmdqs[qidx]->cmdq;
+}
+
+static int tegra241_vintf0_init_vcmdq(struct tegra241_vcmdq *vcmdq)
+{
+ struct tegra241_vintf *vintf = vcmdq->vintf;
+ struct tegra241_cmdqv *cmdqv = vintf->cmdqv;
+ u32 regval;
+ int ret;
+
+ /* Setup struct arm_smmu_cmdq data members */
+ tegra241_cmdqv_init_one_vcmdq(vcmdq);
+
+ /* Configure and enable the vcmdq */
+ vcmdq_page0_writel_relaxed(0, PROD);
+ vcmdq_page0_writel_relaxed(0, CONS);
+
+ vcmdq_page1_writeq_relaxed(vcmdq->cmdq.q.q_base, BASE);
+ vcmdq_page0_writel_relaxed(VCMDQ_EN, CONFIG);
+
+ ret = readl_poll_timeout(vcmdq->page0 + TEGRA241_VCMDQ_STATUS,
+ regval, regval == VCMDQ_ENABLED,
+ 1, ARM_SMMU_POLL_TIMEOUT_US);
+ if (ret) {
+ u32 gerror = vcmdq_page0_readl_relaxed(GERROR);
+ u32 gerrorn = vcmdq_page0_readl_relaxed(GERRORN);
+ u32 cons = vcmdq_page0_readl_relaxed(CONS);
+
+ vcmdq_err("failed to enable\n");
+ vcmdq_err(" GERROR=0x%X\n", gerror);
+ vcmdq_err(" GERRORN=0x%X\n", gerrorn);
+ vcmdq_err(" CONS=0x%X\n", cons);
+ return ret;
+ }
+
+ vcmdq_info("inited\n");
+ return 0;
+}
+
+int tegra241_cmdqv_device_reset(struct arm_smmu_device *smmu)
+{
+ struct tegra241_cmdqv *cmdqv = smmu->tegra241_cmdqv;
+ struct tegra241_vintf *vintf = cmdqv->vintf[0];
+ u32 regval;
+ u16 qidx;
+ int ret;
+
+ /* Setup vintf[0] for host kernel */
+ vintf->idx = 0;
+ vintf->cmdqv = cmdqv;
+ atomic_set(&vintf->error, 0);
+ vintf->base = cmdqv->base + TEGRA241_VINTF(0);
+
+ regval = FIELD_PREP(VINTF_HYP_OWN, 1);
+ vintf_writel(regval, CONFIG);
+
+ regval |= FIELD_PREP(VINTF_EN, 1);
+ vintf_writel(regval, CONFIG);
+
+ ret = readl_relaxed_poll_timeout(vintf->base + TEGRA241_VINTF_STATUS,
+ regval, regval & VINTF_ENABLED,
+ 1, ARM_SMMU_POLL_TIMEOUT_US);
+ if (ret) {
+ vintf_err("failed to enable: STATUS = 0x%08X\n", regval);
+ return ret;
+ }
+
+ vintf->enabled = true;
+
+ /* Allocate vcmdqs to vintf */
+ for (qidx = 0; qidx < cmdqv->num_vcmdqs_per_vintf; qidx++) {
+ regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, vintf->idx);
+ regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, qidx);
+ regval |= CMDQV_CMDQ_ALLOCATED;
+ cmdqv_writel_relaxed(regval, CMDQ_ALLOC(qidx));
+ }
+
+ /* Build an arm_smmu_cmdq for each vcmdq allocated to vintf */
+ vintf->vcmdqs = devm_kcalloc(cmdqv->dev, cmdqv->num_vcmdqs_per_vintf,
+ sizeof(*vintf->vcmdqs), GFP_KERNEL);
+ if (!vintf->vcmdqs)
+ return -ENOMEM;
+
+ for (qidx = 0; qidx < cmdqv->num_vcmdqs_per_vintf; qidx++) {
+ struct tegra241_vcmdq *vcmdq;
+
+ vcmdq = devm_kzalloc(cmdqv->dev, sizeof(*vcmdq), GFP_KERNEL);
+ if (!vcmdq)
+ return -ENOMEM;
+ vcmdq->vintf = vintf;
+ vcmdq->idx = vcmdq->logical_idx = qidx;
+ vcmdq->page0 = cmdqv->base + TEGRA241_VCMDQ_PAGE0(qidx);
+ vcmdq->page1 = cmdqv->base + TEGRA241_VCMDQ_PAGE1(qidx);
+ ret = tegra241_vintf0_init_vcmdq(vcmdq);
+ if (ret)
+ return ret;
+ vintf->vcmdqs[qidx] = vcmdq;
+ }
+
+ /* Reserve vintf[0] for kernel and hypervisor use */
+ xa_init_flags(&cmdqv->vintfs, XA_FLAGS_ALLOC1 | XA_FLAGS_ACCOUNT);
+ xa_init_flags(&cmdqv->vcmdqs, XA_FLAGS_ALLOC | XA_FLAGS_ACCOUNT);
+
+ if (cmdqv->vintf && cmdqv->vintf[0])
+ cmdqv->vintf[0] = vintf;
+
+ return 0;
+}
+
+static int tegra241_cmdqv_acpi_is_memory(struct acpi_resource *res, void *data)
+{
+ struct resource_win win;
+
+ return !acpi_dev_resource_address_space(res, &win);
+}
+
+static int tegra241_cmdqv_acpi_get_irqs(struct acpi_resource *ares, void *data)
+{
+ struct resource r;
+ int *irq = data;
+
+ if (*irq <= 0 && acpi_dev_resource_interrupt(ares, 0, &r))
+ *irq = r.start;
+ return 1; /* No need to add resource to the list */
+}
+
+static struct tegra241_cmdqv *
+tegra241_cmdqv_find_resource(struct arm_smmu_device *smmu, int id)
+{
+ struct tegra241_cmdqv *cmdqv = NULL;
+ struct device *dev = smmu->dev;
+ struct list_head resource_list;
+ struct resource_entry *rentry;
+ struct acpi_device *adev;
+ const char *match_uid;
+ int ret;
+
+ if (acpi_disabled)
+ return NULL;
+
+ /* Look for a device in the DSDT whose _UID matches the SMMU node ID */
+ match_uid = kasprintf(GFP_KERNEL, "%u", id);
+ adev = acpi_dev_get_first_match_dev(TEGRA241_CMDQV_HID, match_uid, -1);
+ kfree(match_uid);
+
+ if (!adev)
+ return NULL;
+
+ dev_info(dev, "found companion CMDQV device, %s\n",
+ dev_name(&adev->dev));
+
+ INIT_LIST_HEAD(&resource_list);
+ ret = acpi_dev_get_resources(adev, &resource_list,
+ tegra241_cmdqv_acpi_is_memory, NULL);
+ if (ret < 0) {
+ dev_err(dev, "failed to get memory resource: %d\n", ret);
+ goto put_dev;
+ }
+
+ cmdqv = devm_kzalloc(dev, sizeof(*cmdqv), GFP_KERNEL);
+ if (!cmdqv)
+ goto free_list;
+
+ cmdqv->dev = dev;
+ cmdqv->smmu = smmu;
+
+ rentry = list_first_entry_or_null(&resource_list,
+ struct resource_entry, node);
+ if (!rentry) {
+ cmdqv_err("failed to get memory resource entry\n");
+ goto free_cmdqv;
+ }
+
+ cmdqv->res = *(rentry->res);
+
+ cmdqv->base = devm_ioremap_resource(smmu->dev, rentry->res);
+ if (IS_ERR(cmdqv->base)) {
+ cmdqv_err("failed to ioremap: %ld\n", PTR_ERR(cmdqv->base));
+ goto free_cmdqv;
+ }
+
+ acpi_dev_free_resource_list(&resource_list);
+
+ INIT_LIST_HEAD(&resource_list);
+
+ ret = acpi_dev_get_resources(adev, &resource_list,
+ tegra241_cmdqv_acpi_get_irqs, &cmdqv->irq);
+ if (ret < 0 || cmdqv->irq <= 0) {
+ cmdqv_warn("no cmdqv interrupt. errors will not be reported\n");
+ } else {
+ ret = devm_request_irq(smmu->dev, cmdqv->irq,
+ tegra241_cmdqv_isr, 0,
+ "tegra241-cmdqv", cmdqv);
+ if (ret) {
+ cmdqv_err("failed to request irq (%d): %d\n",
+ cmdqv->irq, ret);
+ goto iounmap;
+ }
+ }
+
+ goto free_list;
+
+iounmap:
+ devm_iounmap(cmdqv->dev, cmdqv->base);
+free_cmdqv:
+ devm_kfree(cmdqv->dev, cmdqv);
+ cmdqv = NULL;
+free_list:
+ acpi_dev_free_resource_list(&resource_list);
+put_dev:
+ put_device(&adev->dev);
+
+ return cmdqv;
+}
+
+struct tegra241_cmdqv *
+tegra241_cmdqv_acpi_probe(struct arm_smmu_device *smmu, int id)
+{
+ struct tegra241_cmdqv *cmdqv;
+ u32 regval;
+
+ cmdqv = tegra241_cmdqv_find_resource(smmu, id);
+ if (!cmdqv)
+ return NULL;
+
+ regval = cmdqv_readl_relaxed(CONFIG);
+ if (disable_cmdqv) {
+ cmdqv_info("disable_cmdqv=true. Falling back to SMMU CMDQ\n");
+ cmdqv_writel_relaxed(regval & ~CMDQV_EN, CONFIG);
+ goto free_res;
+ }
+
+ cmdqv_writel_relaxed(regval | CMDQV_EN, CONFIG);
+
+ regval = cmdqv_readl_relaxed(STATUS);
+ if (!FIELD_GET(CMDQV_ENABLED, regval) ||
+ FIELD_GET(CMDQV_STATUS, regval)) {
+ cmdqv_err("CMDQV h/w not ready: CMDQV_STATUS=0x%08X\n", regval);
+ goto free_res;
+ }
+
+ regval = cmdqv_readl_relaxed(PARAM);
+ cmdqv->num_total_vintfs = 1 << FIELD_GET(CMDQV_NUM_VINTF_LOG2, regval);
+ cmdqv->num_total_vcmdqs = 1 << FIELD_GET(CMDQV_NUM_VCMDQ_LOG2, regval);
+ cmdqv->num_vcmdqs_per_vintf =
+ cmdqv->num_total_vcmdqs / cmdqv->num_total_vintfs;
+
+ cmdqv->vintf = devm_kcalloc(cmdqv->dev, cmdqv->num_total_vintfs,
+ sizeof(*cmdqv->vintf), GFP_KERNEL);
+ if (!cmdqv->vintf)
+ goto free_res;
+
+ cmdqv->vintf[0] = devm_kzalloc(cmdqv->dev, sizeof(*(cmdqv->vintf[0])),
+ GFP_KERNEL);
+ if (!cmdqv->vintf[0])
+ goto free_vintf;
+
+ return cmdqv;
+
+free_vintf:
+ devm_kfree(cmdqv->dev, cmdqv->vintf);
+free_res:
+ if (cmdqv->irq > 0)
+ devm_free_irq(smmu->dev, cmdqv->irq, cmdqv);
+ devm_iounmap(smmu->dev, cmdqv->base);
+ devm_kfree(smmu->dev, cmdqv);
+
+ return NULL;
+}
--
2.43.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v6 0/5] Add CPSW2G and CPSW9G nodes for J784S4
From: Chintan Vankar @ 2024-03-29 5:31 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Rob Herring, Tero Kristo,
Vignesh Raghavendra, Nishanth Menon
Cc: linux-kernel, devicetree, linux-arm-kernel, s-vadapalli,
Chintan Vankar
This series adds device-tree nodes for CPSW2G and CPSW9G instance
of the CPSW Ethernet Switch on TI's J784S4 SoC. Additionally,
two device-tree overlays are also added:
1. QSGMII mode with the CPSW9G instance via the ENET EXPANSION 1
connector.
2. USXGMII mode with MAC Ports 1 and 2 of the CPSW9G instance via
ENET EXPANSION 1 and 2 connectors, configured in fixed-link
mode of operation at 5Gbps link speed.
Link to v5:
https://lore.kernel.org/r/20240314072129.1520475-1-c-vankar@ti.com/
Changes from v5 to v6:
- Updated order of properties in Device Nodes based on
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-properties-in-device-node
Chintan Vankar (1):
arm64: dts: ti: k3-j784s4-evm: Add alias for MCU CPSW2G
Siddharth Vadapalli (4):
arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes
arm64: dts: ti: k3-j784s4-evm: Enable Main CPSW2G node and add aliases
for it
arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with
CPSW9G
arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode
arch/arm64/boot/dts/ti/Makefile | 11 +-
.../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++
.../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 ++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 51 +++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 187 ++++++++++++++++++
5 files changed, 476 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox