* [RFC 6/8] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This adds required field details for ID_AA64DFR1_EL1, and also drops dummy
ftr_raz[] array which is now redundant. These register fields will be used
to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9
later.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
cc: Mark Brown <broonie@kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 56583677c1f2..128f2836fc1e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -527,6 +527,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_id_aa64dfr1[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABL_CMPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DPFZS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EBEP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ITE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABLE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PMICNTR_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SPMU_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CTX_CMPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WRPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BRPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SYSPMUID_SHIFT, 8, 0),
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_mvfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
@@ -705,10 +720,6 @@ static const struct arm64_ftr_bits ftr_single32[] = {
ARM64_FTR_END,
};
-static const struct arm64_ftr_bits ftr_raz[] = {
- ARM64_FTR_END,
-};
-
#define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
.sys_id = id, \
.reg = &(struct arm64_ftr_reg){ \
@@ -781,7 +792,7 @@ static const struct __ftr_reg_entry {
/* Op1 = 0, CRn = 0, CRm = 5 */
ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
- ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
+ ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1),
/* Op1 = 0, CRn = 0, CRm = 6 */
ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
--
2.25.1
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* [RFC 8/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
Currently there can be maximum 16 breakpoints, and 16 watchpoints available
on a given platform - as detected from ID_AA64DFR0_EL1.[BRPs|WRPs] register
fields. But these breakpoint, and watchpoints can be extended further up to
64 via a new arch feature FEAT_Debugv8p9.
This first enables banked access for the breakpoint and watchpoint register
set via MDSELR_EL1, extended exceptions via MDSCR_EL1.EMBWE and determining
available breakpoints and watchpoints in the platform from ID_AA64DFR1_EL1,
when FEAT_Debugv8p9 is enabled.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/debug-monitors.h | 2 +-
arch/arm64/include/asm/hw_breakpoint.h | 46 +++++++++++++++++++------
arch/arm64/kernel/debug-monitors.c | 16 ++++++---
arch/arm64/kernel/hw_breakpoint.c | 33 ++++++++++++++++++
4 files changed, 82 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index 13d437bcbf58..75eedba2abbe 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -19,7 +19,7 @@
/* MDSCR_EL1 enabling bits */
#define DBG_MDSCR_KDE (1 << 13)
#define DBG_MDSCR_MDE (1 << 15)
-#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
+#define DBG_MDSCR_EMBWE (1UL << 32)
#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index bd81cf17744a..6b9822140f71 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -79,8 +79,8 @@ static inline void decode_ctrl_reg(u32 reg,
* Limits.
* Changing these will require modifications to the register accessors.
*/
-#define ARM_MAX_BRP 16
-#define ARM_MAX_WRP 16
+#define ARM_MAX_BRP 64
+#define ARM_MAX_WRP 64
/* Virtual debug register bases. */
#define AARCH64_DBG_REG_BVR 0
@@ -135,22 +135,48 @@ static inline void ptrace_hw_copy_thread(struct task_struct *task)
}
#endif
+static inline bool is_debug_v8p9_enabled(void)
+{
+ u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+ int dver = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_DebugVer_SHIFT);
+
+ return dver == ID_AA64DFR0_EL1_DebugVer_V8P9;
+}
+
/* Determine number of BRP registers available. */
static inline int get_num_brps(void)
{
- u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
- return 1 +
- cpuid_feature_extract_unsigned_field(dfr0,
- ID_AA64DFR0_EL1_BRPs_SHIFT);
+ u64 dfr0, dfr1;
+ int dver, brps;
+
+ dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+ dver = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_DebugVer_SHIFT);
+ if (dver == ID_AA64DFR0_EL1_DebugVer_V8P9) {
+ dfr1 = read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1);
+ brps = cpuid_feature_extract_unsigned_field_width(dfr1,
+ ID_AA64DFR1_EL1_BRPs_SHIFT, 8);
+ } else {
+ brps = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_BRPs_SHIFT);
+ }
+ return 1 + brps;
}
/* Determine number of WRP registers available. */
static inline int get_num_wrps(void)
{
- u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
- return 1 +
- cpuid_feature_extract_unsigned_field(dfr0,
- ID_AA64DFR0_EL1_WRPs_SHIFT);
+ u64 dfr0, dfr1;
+ int dver, wrps;
+
+ dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
+ dver = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_DebugVer_SHIFT);
+ if (dver == ID_AA64DFR0_EL1_DebugVer_V8P9) {
+ dfr1 = read_sanitised_ftr_reg(SYS_ID_AA64DFR1_EL1);
+ wrps = cpuid_feature_extract_unsigned_field_width(dfr1,
+ ID_AA64DFR1_EL1_WRPs_SHIFT, 8);
+ } else {
+ wrps = cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_WRPs_SHIFT);
+ }
+ return 1 + wrps;
}
#ifdef CONFIG_CPU_PM
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 64f2ecbdfe5c..3299d1e8dc61 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -23,6 +23,7 @@
#include <asm/debug-monitors.h>
#include <asm/system_misc.h>
#include <asm/traps.h>
+#include <asm/hw_breakpoint.h>
/* Determine debug architecture. */
u8 debug_monitors_arch(void)
@@ -34,7 +35,7 @@ u8 debug_monitors_arch(void)
/*
* MDSCR access routines.
*/
-static void mdscr_write(u32 mdscr)
+static void mdscr_write(u64 mdscr)
{
unsigned long flags;
flags = local_daif_save();
@@ -43,7 +44,7 @@ static void mdscr_write(u32 mdscr)
}
NOKPROBE_SYMBOL(mdscr_write);
-static u32 mdscr_read(void)
+static u64 mdscr_read(void)
{
return read_sysreg(mdscr_el1);
}
@@ -76,10 +77,11 @@ early_param("nodebugmon", early_debug_disable);
*/
static DEFINE_PER_CPU(int, mde_ref_count);
static DEFINE_PER_CPU(int, kde_ref_count);
+static DEFINE_PER_CPU(int, embwe_ref_count);
void enable_debug_monitors(enum dbg_active_el el)
{
- u32 mdscr, enable = 0;
+ u64 mdscr, enable = 0;
WARN_ON(preemptible());
@@ -90,6 +92,9 @@ void enable_debug_monitors(enum dbg_active_el el)
this_cpu_inc_return(kde_ref_count) == 1)
enable |= DBG_MDSCR_KDE;
+ if (is_debug_v8p9_enabled() && this_cpu_inc_return(embwe_ref_count) == 1)
+ enable |= DBG_MDSCR_EMBWE;
+
if (enable && debug_enabled) {
mdscr = mdscr_read();
mdscr |= enable;
@@ -100,7 +105,7 @@ NOKPROBE_SYMBOL(enable_debug_monitors);
void disable_debug_monitors(enum dbg_active_el el)
{
- u32 mdscr, disable = 0;
+ u64 mdscr, disable = 0;
WARN_ON(preemptible());
@@ -111,6 +116,9 @@ void disable_debug_monitors(enum dbg_active_el el)
this_cpu_dec_return(kde_ref_count) == 0)
disable &= ~DBG_MDSCR_KDE;
+ if (is_debug_v8p9_enabled() && this_cpu_dec_return(embwe_ref_count) == 0)
+ disable &= ~DBG_MDSCR_EMBWE;
+
if (disable) {
mdscr = mdscr_read();
mdscr &= disable;
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index 2f5755192c2b..7b9169535b76 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -103,10 +103,40 @@ int hw_breakpoint_slots(int type)
WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \
WRITE_WB_REG_CASE(OFF, 15, REG, VAL)
+static int set_bank_index(int n)
+{
+ int mdsel_bank;
+ int bank = n / 16, index = n % 16;
+
+ switch (bank) {
+ case 0:
+ mdsel_bank = MDSELR_EL1_BANK_BANK_0;
+ break;
+ case 1:
+ mdsel_bank = MDSELR_EL1_BANK_BANK_1;
+ break;
+ case 2:
+ mdsel_bank = MDSELR_EL1_BANK_BANK_2;
+ break;
+ case 3:
+ mdsel_bank = MDSELR_EL1_BANK_BANK_3;
+ break;
+ default:
+ pr_warn("Unknown register bank %d\n", bank);
+ return -EINVAL;
+ }
+ write_sysreg_s(mdsel_bank << MDSELR_EL1_BANK_SHIFT, SYS_MDSELR_EL1);
+ isb();
+ return index;
+}
+
static u64 read_wb_reg(int reg, int n)
{
u64 val = 0;
+ if (is_debug_v8p9_enabled())
+ n = set_bank_index(n);
+
switch (reg + n) {
GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
@@ -122,6 +152,9 @@ NOKPROBE_SYMBOL(read_wb_reg);
static void write_wb_reg(int reg, int n, u64 val)
{
+ if (is_debug_v8p9_enabled())
+ n = set_bank_index(n);
+
switch (reg + n) {
GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val);
GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val);
--
2.25.1
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* [RFC 7/8] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel, linux-doc
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
Fine grained trap control for MDSELR_EL1 register needs to be configured in
HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
is also present. This adds a new helper __init_el2_fgt2() initializing this
new FEAT_FGT2 based fine grained registers.
MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
This updates __init_el2_debug() as required for FEAT_Debugv8p9.
While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.linux.dev
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++
arch/arm64/include/asm/el2_setup.h | 27 +++++++++++++++++++++++++++
arch/arm64/include/asm/kvm_arm.h | 1 +
3 files changed, 47 insertions(+)
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index b57776a68f15..e69d972018cf 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
+ For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present:
+
+ - If EL3 is present and the kernel is entered at EL2:
+
+ - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
+
For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
- If EL3 is present and the kernel is entered at EL2:
@@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditions must be met:
- ZCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
+ For CPUs with FEAT_Debugv8p9 extension present:
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+ - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
+ - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
+ - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
+
+ - If EL3 is present:
+
+ - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
+ - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1
+
For CPUs with the Scalable Matrix Extension (FEAT_SME):
- If EL3 is present:
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index b7afaa026842..0425067a93d9 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -96,6 +96,14 @@
// to own it.
.Lskip_trace_\@:
+ mrs x1, id_aa64dfr0_el1
+ ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
+ cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
+ b.lt .Lskip_dbg_v8p9_\@
+
+ mov x0, #MDCR_EL2_EBWE
+ orr x2, x2, x0
+.Lskip_dbg_v8p9_\@:
msr mdcr_el2, x2 // Configure debug traps
.endm
@@ -203,6 +211,24 @@
.Lskip_fgt_\@:
.endm
+.macro __init_el2_fgt2
+ mrs x1, id_aa64mmfr0_el1
+ ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
+ cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2
+ b.lt .Lskip_fgt2_\@
+
+ mrs x1, id_aa64dfr0_el1
+ ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
+ cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
+ b.lt .Lskip_dbg_v8p9_\@
+
+ mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1
+ msr_s SYS_HDFGWTR2_EL2, x0
+ msr_s SYS_HDFGRTR2_EL2, x0
+.Lskip_dbg_v8p9_\@:
+.Lskip_fgt2_\@:
+.endm
+
.macro __init_el2_nvhe_prepare_eret
mov x0, #INIT_PSTATE_EL1
msr spsr_el2, x0
@@ -228,6 +254,7 @@
__init_el2_nvhe_idregs
__init_el2_cptr
__init_el2_fgt
+ __init_el2_fgt2
.endm
#ifndef __KVM_NVHE_HYPERVISOR__
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index e01bb5ca13b7..9d77dfc43e08 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -306,6 +306,7 @@
BIT(11))
/* Hyp Debug Configuration Register bits */
+#define MDCR_EL2_EBWE (UL(1) << 43)
#define MDCR_EL2_E2TB_MASK (UL(0x3))
#define MDCR_EL2_E2TB_SHIFT (UL(24))
#define MDCR_EL2_HPMFZS (UL(1) << 36)
--
2.25.1
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* Re: [PATCH] arm64: dts: mediatek: mt2712: fix validation errors
From: AngeloGioacchino Del Regno @ 2024-04-05 8:02 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rafał Miłecki
Cc: AngeloGioacchino Del Regno, Sam Shih, Lorenzo Bianconi,
David S . Miller, Daniel Golle, Frank Wunderlich, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Rafał Miłecki
In-Reply-To: <20240301074741.8362-1-zajec5@gmail.com>
On Fri, 01 Mar 2024 08:47:41 +0100, Rafał Miłecki wrote:
> 1. Fixup infracfg clock controller binding
> It also acts as reset controller so #reset-cells is required.
> 2. Use -pins suffix for pinctrl
>
> This fixes:
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: syscon@10001000: '#reset-cells' is a required property
> from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: pinctrl@1000b000: 'eth_default', 'eth_sleep', 'usb0_iddig', 'usb1_iddig' do not match any of the regexes: 'pinctrl-[0-9]+', 'pins$'
> from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
>
> [...]
Applied to v6.9-fixes/dts64, thanks!
[1/1] arm64: dts: mediatek: mt2712: fix validation errors
commit: 3baac7291effb501c4d52df7019ebf52011e5772
Cheers,
Angelo
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* Re: [PATCH 1/3] arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
From: AngeloGioacchino Del Regno @ 2024-04-05 8:02 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rafał Miłecki
Cc: AngeloGioacchino Del Regno, Sam Shih, Lorenzo Bianconi,
David S . Miller, Daniel Golle, Frank Wunderlich, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Rafał Miłecki
In-Reply-To: <20240213053739.14387-1-zajec5@gmail.com>
On Tue, 13 Feb 2024 06:37:37 +0100, Rafał Miłecki wrote:
> Mediatek ethsys controller / syscon binding doesn't allow any subnodes
> so "#address-cells" and "#size-cells" are redundant (actually:
> disallowed).
>
> This fixes:
> arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtb: syscon@15000000: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
>
> [...]
Applied to v6.9-fixes/dts64, thanks!
[1/3] arm64: dts: mediatek: mt7986: drop invalid properties from ethsys
commit: 3b449bfd2ff6c5d3ceecfcb18528ff8e1b4ac2fd
[2/3] arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller
commit: 9bd88afc94c3570289a0f1c696578b3e1f4e3169
[3/3] arm64: dts: mediatek: mt7986: drop invalid thermal block clock
commit: 970f8b01bd7719a22e577ba6c78e27f9ccf22783
Cheers,
Angelo
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^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
From: AngeloGioacchino Del Regno @ 2024-04-05 8:02 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rafał Miłecki
Cc: AngeloGioacchino Del Regno, Sam Shih, Lorenzo Bianconi,
David S . Miller, Daniel Golle, Frank Wunderlich, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Rafał Miłecki
In-Reply-To: <20240213061459.17917-1-zajec5@gmail.com>
On Tue, 13 Feb 2024 07:14:59 +0100, Rafał Miłecki wrote:
> This fixes:
> arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtb: thermal-zones: cpu-thermal:cooling-maps: 'cpu-active-high', 'cpu-active-low', 'cpu-active-med' do not match any of the regexes: '^map[-a-zA-Z0-9]*$', 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/thermal/thermal-zones.yaml#
>
>
Applied to v6.9-fixes/dts64, thanks!
[1/1] arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-"
commit: f8c65a5e4560781f2ea175d8f26cd75ac98e8d78
Cheers,
Angelo
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^ permalink raw reply
* Re: (subset) [PATCH 1/2] dt-bindings: usb: mtk-xhci: add compatible for MT7988
From: AngeloGioacchino Del Regno @ 2024-04-05 8:02 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rafał Miłecki
Cc: AngeloGioacchino Del Regno, Chunfeng Yun, Greg Kroah-Hartman,
Daniel Golle, linux-usb, linux-arm-kernel, linux-mediatek,
devicetree, linux-kernel, Rafał Miłecki
In-Reply-To: <20240213130044.1976-1-zajec5@gmail.com>
On Tue, 13 Feb 2024 14:00:43 +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> MT7988 SoC contains two on-SoC XHCI controllers. Add proper binding.
>
>
Applied to v6.9-next/dts64, thanks!
[2/2] arm64: dts: mediatek: mt7988: add XHCI controllers
commit: 4ee20d528b0487f879f789e010fe2269bc1b2f71
Cheers,
Angelo
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^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: mt7981: add watchdog & WiFi controllers
From: AngeloGioacchino Del Regno @ 2024-04-05 8:02 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Rafał Miłecki
Cc: AngeloGioacchino Del Regno, Chunfeng Yun, Greg Kroah-Hartman,
Daniel Golle, linux-usb, linux-arm-kernel, linux-mediatek,
devicetree, linux-kernel, Rafał Miłecki
In-Reply-To: <20240221085547.27840-1-zajec5@gmail.com>
On Wed, 21 Feb 2024 09:55:47 +0100, Rafał Miłecki wrote:
> MT7981 (Filogic 820) is a low cost version of MT7986 (Filogic 830) with
> the same watchdog controller. It also comes with on-SoC 802.11ax
> wireless.
>
>
Applied to v6.9-next/dts64, thanks!
[1/1] arm64: dts: mediatek: mt7981: add watchdog & WiFi controllers
commit: 452f39543ce4cebda3471931b0efc6a46e765458
Cheers,
Angelo
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^ permalink raw reply
* [PATCH v5] dt-bindings: serial: actions,owl-uart: convert to dtschema
From: Kanak Shilledar @ 2024-04-05 8:02 UTC (permalink / raw)
Cc: daniel.baluta, Kanak Shilledar, Krzysztof Kozlowski,
Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andreas Färber, Manivannan Sadhasivam,
linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-actions
From: Kanak Shilledar <kanakshilledar111@protonmail.com>
Convert the Actions Semi Owl UART to newer DT schema.
Created DT schema based on the .txt file which had
`compatible`, `reg` and `interrupts` as the
required properties. This binding is used by Actions S500, S700
and S900 SoC. S700 and S900 use the same UART compatible string.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kanak Shilledar <kanakshilledar111@protonmail.com>
---
Changes in v5
- rebased the patch
- sent to all the maintainers
Changes in v4
- updated commit message
- `clocks` property is removed from the required section.
- remove disabled status from example devicetree
---
.../bindings/serial/actions,owl-uart.txt | 16 -------
.../bindings/serial/actions,owl-uart.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.txt
create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
deleted file mode 100644
index aa873eada02d..000000000000
--- a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Actions Semi Owl UART
-
-Required properties:
-- compatible : "actions,s500-uart", "actions,owl-uart" for S500
- "actions,s900-uart", "actions,owl-uart" for S900
-- reg : Offset and length of the register set for the device.
-- interrupts : Should contain UART interrupt.
-
-
-Example:
-
- uart3: serial@b0126000 {
- compatible = "actions,s500-uart", "actions,owl-uart";
- reg = <0xb0126000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
new file mode 100644
index 000000000000..ab1c4514ae93
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/actions,owl-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl UART
+
+maintainers:
+ - Kanak Shilledar <kanakshilledar111@protonmail.com>
+
+allOf:
+ - $ref: serial.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - actions,s500-uart
+ - actions,s900-uart
+ - const: actions,owl-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/actions,s500-cmu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ uart0: serial@b0126000 {
+ compatible = "actions,s500-uart", "actions,owl-uart";
+ reg = <0xb0126000 0x1000>;
+ clocks = <&cmu CLK_UART0>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH] media: verisilicon: Fix auxiliary buffers allocation size
From: Benjamin Gaignard @ 2024-04-05 8:13 UTC (permalink / raw)
To: Nicolas Dufresne, ezequiel, p.zabel, mchehab, heiko
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
kernel
In-Reply-To: <c8de69fc6cb6029e96f3e6b6c1eeb1de9304ccff.camel@ndufresne.ca>
Le 04/04/2024 à 20:00, Nicolas Dufresne a écrit :
> Hi,
>
> Le jeudi 28 mars 2024 à 10:34 +0100, Benjamin Gaignard a écrit :
>> Use v4l2_av1_tile_info->tile_cols to know the number of colons
>> in the frame. This made auxiliary buffers meory size computation
>> more accurate.
> Seems like this is potentially going to impact some conformance tests. Anything
> to report from fluster results ?
Flusters AV1 score is the same.
Maybe we have been lucky when allocating memory until now.
That said the test stream have 8 tile columns which is unusual but admitted by AV1 specifications.
Benjamin
>
> Nicolas
>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>> Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder")
>> ---
>> .../media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>> index cc4483857489..65e8f2d07400 100644
>> --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>> +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
>> @@ -257,7 +257,8 @@ static int rockchip_vpu981_av1_dec_tiles_reallocate(struct hantro_ctx *ctx)
>> struct hantro_dev *vpu = ctx->dev;
>> struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
>> struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
>> - unsigned int num_tile_cols = 1 << ctrls->tile_group_entry->tile_col;
>> + const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info;
>> + unsigned int num_tile_cols = tile_info->tile_cols;
>> unsigned int height = ALIGN(ctrls->frame->frame_height_minus_1 + 1, 64);
>> unsigned int height_in_sb = height / 64;
>> unsigned int stripe_num = ((height + 8) + 63) / 64;
>
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* Re: [PATCH RESEND v3 2/2] Input: atmel_mxt_ts - support poweroff in suspend
From: Stefan Eichenberger @ 2024-04-05 8:15 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: devicetree, alexandre.belloni, nick, linux-kernel, linus.walleij,
linux-input, conor+dt, Stefan Eichenberger, robh+dt,
krzysztof.kozlowski+dt, claudiu.beznea, francesco.dolcini,
linux-arm-kernel
In-Reply-To: <ZfSYp6aV6bRhlPUJ@google.com>
Hi Dmitry,
Thanks for the feedback, I had a first look at the changes and I'm not
sure if we would break some use cases. Therfore, here some questions.
On Fri, Mar 15, 2024 at 11:51:19AM -0700, Dmitry Torokhov wrote:
> > diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
> > index 542a31448c8f..2d5655385702 100644
> > --- a/drivers/input/touchscreen/atmel_mxt_ts.c
> > +++ b/drivers/input/touchscreen/atmel_mxt_ts.c
> > @@ -317,6 +317,7 @@ struct mxt_data {
> > struct gpio_desc *reset_gpio;
> > struct gpio_desc *wake_gpio;
> > bool use_retrigen_workaround;
> > + bool poweroff_sleep;
> >
> > /* Cached parameters from object table */
> > u16 T5_address;
> > @@ -2799,15 +2800,18 @@ static int mxt_configure_objects(struct mxt_data *data,
> > dev_warn(dev, "Error %d updating config\n", error);
> > }
> >
> > - if (data->multitouch) {
> > - error = mxt_initialize_input_device(data);
> > - if (error)
> > - return error;
> > - } else {
> > - dev_warn(dev, "No touch object detected\n");
> > - }
> > + /* If input device is not already registered */
> > + if (!data->input_dev) {
> > + if (data->multitouch) {
> > + error = mxt_initialize_input_device(data);
> > + if (error)
> > + return error;
> > + } else {
> > + dev_warn(dev, "No touch object detected\n");
> > + }
> >
> > - mxt_debug_init(data);
> > + mxt_debug_init(data);
> > + }
> >
> > return 0;
> > }
> > @@ -3325,6 +3329,8 @@ static int mxt_probe(struct i2c_client *client)
> > msleep(MXT_RESET_INVALID_CHG);
> > }
> >
> > + data->poweroff_sleep = device_property_read_bool(&client->dev,
> > + "atmel,poweroff-sleep");
> > /*
> > * Controllers like mXT1386 have a dedicated WAKE line that could be
> > * connected to a GPIO or to I2C SCL pin, or permanently asserted low.
> > @@ -3387,12 +3393,21 @@ static int mxt_suspend(struct device *dev)
> > if (!input_dev)
> > return 0;
> >
> > - mutex_lock(&input_dev->mutex);
> > + if (!device_may_wakeup(dev) && data->poweroff_sleep) {
> > + if (data->reset_gpio)
> > + gpiod_set_value(data->reset_gpio, 1);
> >
> > - if (input_device_enabled(input_dev))
> > - mxt_stop(data);
> > + regulator_bulk_disable(ARRAY_SIZE(data->regulators),
> > + data->regulators);
> > + data->T44_address = 0;
> > + } else {
> > + mutex_lock(&input_dev->mutex);
> > +
> > + if (input_device_enabled(input_dev))
> > + mxt_stop(data);
> >
> > - mutex_unlock(&input_dev->mutex);
> > + mutex_unlock(&input_dev->mutex);
> > + }
>
> This all should go into mxt_stop(), so that if device is closed, or
> inhibited, you power it down as well (if you can).
We would then have to power it up during probe to see if the device is
threre, read the configuration and power it down again afterwards until
the device is opened. If the device is in bootloader mode we would most
likely have to keep the power on all the time and never turn it off,
right?
>
> >
> > disable_irq(data->irq);
> >
> > @@ -3408,14 +3423,37 @@ static int mxt_resume(struct device *dev)
> > if (!input_dev)
> > return 0;
> >
> > - enable_irq(data->irq);
> > + if (!device_may_wakeup(dev) && data->poweroff_sleep) {
> > + int ret;
> >
> > - mutex_lock(&input_dev->mutex);
> > + ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
> > + data->regulators);
> > + if (ret) {
> > + dev_err(dev, "failed to enable regulators: %d\n",
> > + ret);
> > + return ret;
> > + }
> > + msleep(MXT_BACKUP_TIME);
> >
> > - if (input_device_enabled(input_dev))
> > - mxt_start(data);
> > + if (data->reset_gpio) {
> > + /* Wait a while and then de-assert the RESET GPIO line */
> > + msleep(MXT_RESET_GPIO_TIME);
> > + gpiod_set_value(data->reset_gpio, 0);
> > + msleep(MXT_RESET_INVALID_CHG);
> > + }
> >
> > - mutex_unlock(&input_dev->mutex);
> > + /* This also enables the irq again */
> > + mxt_initialize(data);
>
> And this needs to go into mxt_start(). Also, we should make sure that
> once resume operation completes the device is fully operational. That
> means you should not request the firmware asynchronously in
> mxt_initialize() in case you are in the resume path. I think you should
> also unwind mxt_initialize() and mxt_configure_objects() to make it
> clear what is the part of initial initialization and what is part of
> re-initializing during resume. The configuration that is exposed to
> userspace (resolution, number of objects, other properties) should stay
> the same, the configuration of the chip itself (power mode, etc) should
> be restored.
Here we would most likely have to load the firmware (configuration)
synchronously all the time if the poweroff_sleep flag is set. Ths makes
sure that the device is ready when we open the device. Would this delay
be acceptable when opening the input device? Normally the configuration
is not that big and should load quite fast.
Regards,
Stefan
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* Re: [PATCH 4/4] clk: en7523: add EN7581 support
From: Lorenzo Bianconi @ 2024-04-05 8:17 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-clk, mturquette, sboyd, linux-arm-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, nbd, john, devicetree, dd,
catalin.marinas, will, upstream, lorenzo.bianconi83
In-Reply-To: <0297a8ab-2f62-4f03-b2ed-87180a47c57c@collabora.com>
[-- Attachment #1.1: Type: text/plain, Size: 9826 bytes --]
> Il 03/04/24 18:20, Lorenzo Bianconi ha scritto:
> > Introduce EN7581 clock support to clk-en7523 driver.
> >
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> > drivers/clk/clk-en7523.c | 130 +++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 125 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> > index c7def87b74c6..51a6c0cc7f58 100644
> > --- a/drivers/clk/clk-en7523.c
> > +++ b/drivers/clk/clk-en7523.c
> > @@ -4,13 +4,16 @@
> > #include <linux/clk-provider.h>
> > #include <linux/io.h>
> > #include <linux/of.h>
> > +#include <linux/of_device.h>
> > #include <linux/platform_device.h>
> > #include <dt-bindings/clock/en7523-clk.h>
> > #define REG_PCI_CONTROL 0x88
> > #define REG_PCI_CONTROL_PERSTOUT BIT(29)
> > #define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
> > +#define REG_PCI_CONTROL_REFCLK_EN0 BIT(23)
> > #define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
> > +#define REG_PCI_CONTROL_PERSTOUT2 BIT(16)
> > #define REG_GSW_CLK_DIV_SEL 0x1b4
> > #define REG_EMI_CLK_DIV_SEL 0x1b8
> > #define REG_BUS_CLK_DIV_SEL 0x1bc
> > @@ -18,10 +21,25 @@
> > #define REG_SPI_CLK_FREQ_SEL 0x1c8
> > #define REG_NPU_CLK_DIV_SEL 0x1fc
> > #define REG_CRYPTO_CLKSRC 0x200
> > -#define REG_RESET_CONTROL 0x834
> > +#define REG_RESET_CONTROL2 0x830
>
> Wait what? The RESET2 register comes before RESET1 ?!?!
>
> Is this a typo? :-)
actually not :)
>
> > +#define REG_RESET2_CONTROL_PCIE2 BIT(27)
> > +#define REG_RESET_CONTROL1 0x834
> > #define REG_RESET_CONTROL_PCIEHB BIT(29)
> > #define REG_RESET_CONTROL_PCIE1 BIT(27)
> > #define REG_RESET_CONTROL_PCIE2 BIT(26)
> > +/* EN7581 */
> > +#define REG_PCIE0_MEM 0x00
> > +#define REG_PCIE0_MEM_MASK 0x04
> > +#define REG_PCIE1_MEM 0x08
> > +#define REG_PCIE1_MEM_MASK 0x0c
> > +#define REG_PCIE2_MEM 0x10
> > +#define REG_PCIE2_MEM_MASK 0x14
> > +#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
> > +#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
> > +#define REG_NP_SCU_PCIC 0x88
> > +#define REG_NP_SCU_SSTR 0x9c
> > +#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
> > +#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
> > struct en_clk_desc {
> > int id;
> > @@ -207,14 +225,14 @@ static int en7523_pci_prepare(struct clk_hw *hw)
> > usleep_range(1000, 2000);
> > /* Reset to default */
> > - val = readl(np_base + REG_RESET_CONTROL);
> > + val = readl(np_base + REG_RESET_CONTROL1);
> > mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
> > REG_RESET_CONTROL_PCIEHB;
> > - writel(val & ~mask, np_base + REG_RESET_CONTROL);
> > + writel(val & ~mask, np_base + REG_RESET_CONTROL1);
> > usleep_range(1000, 2000);
> > - writel(val | mask, np_base + REG_RESET_CONTROL);
> > + writel(val | mask, np_base + REG_RESET_CONTROL1);
> > msleep(100);
> > - writel(val & ~mask, np_base + REG_RESET_CONTROL);
> > + writel(val & ~mask, np_base + REG_RESET_CONTROL1);
> > usleep_range(5000, 10000);
> > /* Release device */
> > @@ -262,6 +280,64 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
> > return &cg->hw;
> > }
> > +static int en7581_pci_is_enabled(struct clk_hw *hw)
> > +{
> > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
> > + u32 val, mask;
> > +
> > + mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
> > + val = readl(cg->base + REG_PCI_CONTROL);
> > + return (val & mask) == mask;
> > +}
> > +
> > +static int en7581_pci_prepare(struct clk_hw *hw)
> > +{
> > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
> > + void __iomem *np_base = cg->base;
> > + u32 val, mask;
> > +
> > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
> > + REG_RESET_CONTROL_PCIEHB;
> > + val = readl(np_base + REG_RESET_CONTROL1);
> > + writel(val & ~mask, np_base + REG_RESET_CONTROL1);
> > + val = readl(np_base + REG_RESET_CONTROL2);
> > + writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
> > + usleep_range(5000, 10000);
> > +
> > + mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
> > + REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
> > + REG_PCI_CONTROL_PERSTOUT;
>
> I'm not sure that this is actually something to control in a clock driver...
>
> the right thing to do would be to add a reset controller to this clock driver
> and then assert/deassert reset in the PCIe PHY/MAC driver.
>
> Perhaps REFCLK_EN0/EN1 can be manipulated in a .enable() callback, treating
> this really just as what it appears to really be: a gate clock! (hint: check
> clk-gate.c)
ack, I will look into it.
>
> > + val = readl(np_base + REG_PCI_CONTROL);
> > + writel(val | mask, np_base + REG_PCI_CONTROL);
> > + msleep(250);
> > +
> > + return 0;
> > +}
> > +
> > +static void en7581_pci_unprepare(struct clk_hw *hw)
> > +{
> > + struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
> > + void __iomem *np_base = cg->base;
> > + u32 val, mask;
> > +
> > + mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
>
> ...and this should be a clk-gate .disable() callback, I guess :-)
ack, I will look into it.
>
> > + REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
> > + REG_PCI_CONTROL_PERSTOUT;
> > + val = readl(np_base + REG_PCI_CONTROL);
> > + writel(val & ~mask, np_base + REG_PCI_CONTROL);
> > + usleep_range(1000, 2000);
> > +
> > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
> > + REG_RESET_CONTROL_PCIEHB;
> > + val = readl(np_base + REG_RESET_CONTROL1);
> > + writel(val | mask, np_base + REG_RESET_CONTROL1);
> > + mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
> > + writel(val | mask, np_base + REG_RESET_CONTROL1);
> > + val = readl(np_base + REG_RESET_CONTROL2);
> > + writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
> > + msleep(100);
> > +}
> > +
> > static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
> > void __iomem *base, void __iomem *np_base)
> > {
> > @@ -291,6 +367,37 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
> > clk_data->num = EN7523_NUM_CLOCKS;
> > }
> > +static int en7581_clk_hw_init(struct platform_device *pdev,
> > + void __iomem *base,
> > + void __iomem *np_base)
> > +{
> > + void __iomem *pb_base;
> > + u32 val;
> > +
> > + pb_base = devm_platform_ioremap_resource(pdev, 2);
> > + if (IS_ERR(pb_base))
> > + return PTR_ERR(pb_base);
> > +
> > + val = readl(np_base + REG_NP_SCU_SSTR);
> > + val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
> > + writel(val, np_base + REG_NP_SCU_SSTR);
> > + val = readl(np_base + REG_NP_SCU_PCIC);
> > + writel(val | 3, np_base + REG_NP_SCU_PCIC);
>
> What is 3?
>
> #define SOMETHING 3 ??
actullay I do not know what it means since write in the pcie_ctrl subfield of
REG_NP_SCU_PCIC but it is a GENMASK(7, 0) and I do not have any more info
about it.
>
> > +
> > + writel(0x20000000, pb_base + REG_PCIE0_MEM);
> > + writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
> > + writel(0x24000000, pb_base + REG_PCIE1_MEM);
> > + writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
> > + writel(0x28000000, pb_base + REG_PCIE2_MEM);
> > + writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
>
> And... this is .. some BIT() and some GENMASK() as far as I understand...
> do we have any clue about what you're setting to those registers?
same as above, they seems undocumented.
@airoha folks: any input about them?
>
> Can MediaTek/Airoha help with this, please?
>
> #define SOMETHING BIT(29) /* this is 0x20000000 */
> #define SOME_MASK GENMASK(31, 26) /* this is 0xfc00000 */
>
> > +
> > + val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
> > + writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
> > + base + REG_PCIE_RESET_OPEN_DRAIN);
> > +
> > + return 0;
> > +}
> > +
> > static int en7523_clk_probe(struct platform_device *pdev)
> > {
> > struct device_node *node = pdev->dev.of_node;
> > @@ -306,6 +413,12 @@ static int en7523_clk_probe(struct platform_device *pdev)
> > if (IS_ERR(np_base))
> > return PTR_ERR(np_base);
> > + if (of_device_is_compatible(node, "airoha,en7581-scu")) {
> > + r = en7581_clk_hw_init(pdev, base, np_base);
> > + if (r)
> > + return r;
> > + }
> > +
> > clk_data = devm_kzalloc(&pdev->dev,
> > struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
> > GFP_KERNEL);
> > @@ -329,8 +442,15 @@ static const struct clk_ops en7523_pcie_ops = {
> > .unprepare = en7523_pci_unprepare,
> > };
>
> static const struct clk_en7523_pdata en7581_pdata = {
> .init = en7581_clk_hw_init, /* if (pdata->init) pdata->init(x, y, z) */
> .ops = en7581_pcie_ops,
> };
>
> or, alternatively:
>
> static const struct .... = {
> .init = ...,
> .ops = (const struct clk_ops) {
> .is_enabled = en7581_pci_is_enabled,
> .... etc
> }
ack, I will fix it.
Regards,
Lorenzo
> };
>
> Cheers,
> Angelo
>
> > +static const struct clk_ops en7581_pcie_ops = {
> > + .is_enabled = en7581_pci_is_enabled,
> > + .prepare = en7581_pci_prepare,
> > + .unprepare = en7581_pci_unprepare,
> > +};
> > +
> > static const struct of_device_id of_match_clk_en7523[] = {
> > { .compatible = "airoha,en7523-scu", .data = &en7523_pcie_ops },
> > + { .compatible = "airoha,en7581-scu", .data = &en7581_pcie_ops },
> > { /* sentinel */ }
> > };
>
> -
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^ permalink raw reply
* Re: [PATCH] media: verisilicon: AV1: Be more fexible on postproc capabilities
From: Benjamin Gaignard @ 2024-04-05 8:17 UTC (permalink / raw)
To: Nicolas Dufresne, ezequiel, p.zabel, mchehab, heiko
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
kernel
In-Reply-To: <e4d01c27aa976c44e0b7122e39111be062a4deb4.camel@ndufresne.ca>
Le 04/04/2024 à 19:59, Nicolas Dufresne a écrit :
> Hi,
>
> Le jeudi 28 mars 2024 à 10:34 +0100, Benjamin Gaignard a écrit :
>> RK3588 post-processor block is able to convert 10 bits streams
>> into 8 bits pixels format.
> Does it come with any HDR to SDR capabilities ? cause stripping off 2 bits means
> that tone mapping will cause a lot of banding as it won't have the expected
> precision. I'm simply trying to make up the big portrait so we don't just offer
> yet another foot gun. But perhaps its fine to offer this, its just that we don't
> have a mechanism to report which pixel format in the selection will cause data
> lost.
No it just to enable post-processor capabilities like we have already for G2/HEVC.
Since it is a post-processor pixel format it will be enumerated after V4L2_PIX_FMT_NV15_4L4
so it will update to userland to decide to use it or not.
Benjamin
>
> Nicolas
>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>> Fixes: 003afda97c65 ("media: verisilicon: Enable AV1 decoder on rk3588")
>> ---
>> drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
>> index f97527670783..964122e7c355 100644
>> --- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
>> +++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
>> @@ -82,7 +82,6 @@ static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
>> {
>> .fourcc = V4L2_PIX_FMT_NV12,
>> .codec_mode = HANTRO_MODE_NONE,
>> - .match_depth = true,
>> .postprocessed = true,
>> .frmsize = {
>> .min_width = ROCKCHIP_VPU981_MIN_SIZE,
>
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^ permalink raw reply
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Pratham Patel @ 2024-04-05 8:32 UTC (permalink / raw)
To: Saravana Kannan
Cc: Dragan Simic, sebastian.reichel, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, regressions, stable
In-Reply-To: <D0A2ZL6S8UG6.2BQKIBQWYB36D@thefossguy.com>
On Wednesday, April 3rd, 2024 at 06:33, Pratham Patel <prathampatel@thefossguy.com> wrote:
>
>
> On Wed Apr 3, 2024 at 6:16 AM IST, Saravana Kannan wrote:
>
> > On Tue, Apr 2, 2024 at 4:32 PM Pratham Patel
> > prathampatel@thefossguy.com wrote:
> >
> > > On Tue Apr 2, 2024 at 4:54 AM IST, Saravana Kannan wrote:
> > >
> > > > On Sat, Mar 23, 2024 at 10:10 AM Dragan Simic dsimic@manjaro.org wrote:
> > > >
> > > > > Hello Pratham,
> > > > >
> > > > > On 2024-03-23 18:02, Pratham Patel wrote:
> > > > >
> > > > > > I looked at the patch and tried several things, neither resulted in
> > > > > > anything that would point me to the core issue. Then I tried this:
> > > > >
> > > > > Could you, please, clarify a bit what's the actual issue you're
> > > > > experiencing on your Rock 5B?
> > > >
> > > > Pratham, can you reply to this please? I don't really understand what
> > > > your issue is for me to be able to help.
> > >
> > > Hi,
> > >
> > > I apologize for not replying. Somehow, I did not notice the reply from
> > > Dragan. :(
> > >
> > > Since this patch was applied, an issue in the Rock 5B's DT has been
> > > unearthed which now results in the kernel being unable to boot properly.
> > >
> > > Following is the relevant call trace from the UART capture:
> > >
> > > [ 21.595068] Call trace:
> > > [ 21.595288] smp_call_function_many_cond+0x174/0x5f8
> > > [ 21.595728] on_each_cpu_cond_mask+0x2c/0x40
> > > [ 21.596109] cpuidle_register_driver+0x294/0x318
> > > [ 21.596524] cpuidle_register+0x24/0x100
> > > [ 21.596875] psci_cpuidle_probe+0x2e4/0x490
> > > [ 21.597247] platform_probe+0x70/0xd0
> > > [ 21.597575] really_probe+0x18c/0x3d8
> > > [ 21.597905] __driver_probe_device+0x84/0x180
> > > [ 21.598294] driver_probe_device+0x44/0x120
> > > [ 21.598669] __device_attach_driver+0xc4/0x168
> > > [ 21.599063] bus_for_each_drv+0x8c/0xf0
> > > [ 21.599408] __device_attach+0xa4/0x1c0
> > > [ 21.599748] device_initial_probe+0x1c/0x30
> > > [ 21.600118] bus_probe_device+0xb4/0xc0
> > > [ 21.600462] device_add+0x68c/0x888
> > > [ 21.600775] platform_device_add+0x19c/0x270
> > > [ 21.601154] platform_device_register_full+0xdc/0x178
> > > [ 21.601602] psci_idle_init+0xa0/0xc8
> > > [ 21.601934] do_one_initcall+0x60/0x290
> > > [ 21.602275] kernel_init_freeable+0x20c/0x3e0
> > > [ 21.602664] kernel_init+0x2c/0x1f8
> > > [ 21.602979] ret_from_fork+0x10/0x20
> >
> > This doesn't make a lot of sense. "remote-endpoint" shouldn't be
> > related to anything to do with psci cpuidle. I'm guessing something
> > else is failing much earlier in boot that's indirectly causing this
> > somehow? Can you please take a look at what's failing earlier and let
> > us know? Or see what driver probe is failing up to this point but used
> > to work in the good case.
>
>
> I'm pretty new to this, "just starting". I'm not sure how to do that,
> since the kernel doesn't really "move forward". I will verify if
> a8037ceb8964 fixes it or not and get back by the end of this week.
>
> > Also, where is the dts file that corresponds to this board in upstream? Is it
> > arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
>
>
> Yes.
>
> > > > Also, can you give the output of <debugfs>/devices_deferred for the
> > > > good vs bad case?
> > >
> > > I can't provide you with requested output from the bad case, since the
> > > kernel never moves past this to an initramfs rescue shell, but following
> > > is the output from v6.8.1 (with aforementioned patch reverted).
> > >
> > > # cat /sys/kernel/debug/devices_deferred
> > > fc400000.usb platform: wait for supplier /phy@fed90000/usb3-port
> > > 1-0022 typec_fusb302: cannot register tcpm port
> > > fc000000.usb platform: wait for supplier /phy@fed80000/usb3-port
> > >
> > > It seems that v6.8.2 works without needing to revert the patch. I will
> > > have to look into this sometime this week but it seems like
> > > a8037ceb8964 (arm64: dts: rockchip: drop rockchip,trcm-sync-tx-only from rk3588 i2s)
> > > seems to be the one that fixed the root issue. I will have to test it
> > > sometime later this week.
> >
> > Ok, once you find the patch that fixes things, let me know too.
I confirm that a8037ceb8964 fixed this issue for me. Now, v6.8.2+ boots on my Rock 5B,
with my distro's config and the arm64 defconfig.
-- Pratham Patel
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^ permalink raw reply
* Re: [PATCH v2 02/18] PCI: endpoint: Introduce pci_epc_map_align()
From: Dan Carpenter @ 2024-04-05 8:38 UTC (permalink / raw)
To: oe-kbuild, Damien Le Moal, Manivannan Sadhasivam,
Lorenzo Pieralisi, Kishon Vijay Abraham I, Shawn Lin,
Krzysztof Wilczyński, Bjorn Helgaas, Heiko Stuebner,
linux-pci, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree
Cc: lkp, oe-kbuild-all, linux-rockchip, linux-arm-kernel,
Rick Wertenbroek, Wilfred Mallawa, Niklas Cassel
In-Reply-To: <20240330041928.1555578-3-dlemoal@kernel.org>
Hi Damien,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Damien-Le-Moal/PCI-endpoint-Introduce-pci_epc_function_is_valid/20240330-122311
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20240330041928.1555578-3-dlemoal%40kernel.org
patch subject: [PATCH v2 02/18] PCI: endpoint: Introduce pci_epc_map_align()
config: parisc-randconfig-r071-20240405 (https://download.01.org/0day-ci/archive/20240405/202404051508.hvNRDVZq-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 13.2.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202404051508.hvNRDVZq-lkp@intel.com/
smatch warnings:
drivers/pci/endpoint/pci-epc-core.c:493 pci_epc_map_align() error: we previously assumed 'features' could be null (see line 487)
vim +/features +493 drivers/pci/endpoint/pci-epc-core.c
9d2f10d2ace040 Damien Le Moal 2024-03-30 458 int pci_epc_map_align(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
9d2f10d2ace040 Damien Le Moal 2024-03-30 459 u64 pci_addr, size_t size, struct pci_epc_map *map)
9d2f10d2ace040 Damien Le Moal 2024-03-30 460 {
9d2f10d2ace040 Damien Le Moal 2024-03-30 461 const struct pci_epc_features *features;
9d2f10d2ace040 Damien Le Moal 2024-03-30 462 size_t mask;
9d2f10d2ace040 Damien Le Moal 2024-03-30 463 int ret;
9d2f10d2ace040 Damien Le Moal 2024-03-30 464
9d2f10d2ace040 Damien Le Moal 2024-03-30 465 if (!pci_epc_function_is_valid(epc, func_no, vfunc_no))
9d2f10d2ace040 Damien Le Moal 2024-03-30 466 return -EINVAL;
9d2f10d2ace040 Damien Le Moal 2024-03-30 467
9d2f10d2ace040 Damien Le Moal 2024-03-30 468 if (!size || !map)
9d2f10d2ace040 Damien Le Moal 2024-03-30 469 return -EINVAL;
9d2f10d2ace040 Damien Le Moal 2024-03-30 470
9d2f10d2ace040 Damien Le Moal 2024-03-30 471 memset(map, 0, sizeof(*map));
9d2f10d2ace040 Damien Le Moal 2024-03-30 472 map->pci_addr = pci_addr;
9d2f10d2ace040 Damien Le Moal 2024-03-30 473 map->pci_size = size;
9d2f10d2ace040 Damien Le Moal 2024-03-30 474
9d2f10d2ace040 Damien Le Moal 2024-03-30 475 if (epc->ops->map_align) {
9d2f10d2ace040 Damien Le Moal 2024-03-30 476 mutex_lock(&epc->lock);
9d2f10d2ace040 Damien Le Moal 2024-03-30 477 ret = epc->ops->map_align(epc, func_no, vfunc_no, map);
9d2f10d2ace040 Damien Le Moal 2024-03-30 478 mutex_unlock(&epc->lock);
9d2f10d2ace040 Damien Le Moal 2024-03-30 479 return ret;
9d2f10d2ace040 Damien Le Moal 2024-03-30 480 }
9d2f10d2ace040 Damien Le Moal 2024-03-30 481
9d2f10d2ace040 Damien Le Moal 2024-03-30 482 /*
9d2f10d2ace040 Damien Le Moal 2024-03-30 483 * Assume a fixed alignment constraint as specified by the controller
9d2f10d2ace040 Damien Le Moal 2024-03-30 484 * features.
9d2f10d2ace040 Damien Le Moal 2024-03-30 485 */
9d2f10d2ace040 Damien Le Moal 2024-03-30 486 features = pci_epc_get_features(epc, func_no, vfunc_no);
9d2f10d2ace040 Damien Le Moal 2024-03-30 @487 if (!features || !features->align) {
^^^^^^^^^
Check for NULL
9d2f10d2ace040 Damien Le Moal 2024-03-30 488 map->map_pci_addr = pci_addr;
9d2f10d2ace040 Damien Le Moal 2024-03-30 489 map->map_size = size;
9d2f10d2ace040 Damien Le Moal 2024-03-30 490 map->map_ofst = 0;
Missing return 0?
9d2f10d2ace040 Damien Le Moal 2024-03-30 491 }
9d2f10d2ace040 Damien Le Moal 2024-03-30 492
9d2f10d2ace040 Damien Le Moal 2024-03-30 @493 mask = features->align - 1;
^^^^^^^^^^
9d2f10d2ace040 Damien Le Moal 2024-03-30 494 map->map_pci_addr = map->pci_addr & ~mask;
9d2f10d2ace040 Damien Le Moal 2024-03-30 495 map->map_ofst = map->pci_addr & mask;
9d2f10d2ace040 Damien Le Moal 2024-03-30 496 map->map_size = ALIGN(map->map_ofst + map->pci_size, features->align);
9d2f10d2ace040 Damien Le Moal 2024-03-30 497
9d2f10d2ace040 Damien Le Moal 2024-03-30 498 return 0;
9d2f10d2ace040 Damien Le Moal 2024-03-30 499 }
--
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https://github.com/intel/lkp-tests/wiki
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* [PATCH 0/4] A new selftests/ directory for arm compatibility testing
From: Dev Jain @ 2024-04-05 8:44 UTC (permalink / raw)
To: shuah, linux-arm-kernel
Cc: linux-kselftest, linux-kernel, Anshuman.Khandual, suzuki.poulose,
ryan.roberts, rob.herring, Catalin.Marinas, broonie, will,
mark.rutland, Dev Jain
This series introduces the selftests/arm directory, which tests 32 and 64-bit
kernel compatibility with 32-bit ELFs running on the Aarch platform.
The need for this bucket of tests is that 32 bit applications built on legacy
ARM architecture must not break on the new Aarch64 platforms and the 64-bit
kernel. The kernel must emulate the data structures, system calls and the
registers according to Aarch32, when running a 32-bit process; this directory
fills that testing requirement.
One may find similarity between this directory and selftests/arm64; it is
advisable to refer to that since a lot has been copied from there itself.
The mm directory includes a test for checking 4GB limit of the virtual
address space of a process.
The signal directory contains two tests, following a common theme: mangle
with arm_cpsr, dumped by the kernel to user space while invoking the signal
handler; kernel must spot this illegal attempt and terminate the program by
SEGV.
The elf directory includes a test for checking the 32-bit status of the ELF.
The series has been tested on 6.9.0-rc2, on Aarch64 platform. Testing remains
to be done on Aaarch32.
Dev Jain (4):
selftests/arm: Add mm test
selftests/arm: Add signal tests
selftests/arm: Add elf test
selftests: Add build infrastructure along with README
tools/testing/selftests/Makefile | 1 +
tools/testing/selftests/arm/Makefile | 57 ++++
tools/testing/selftests/arm/README | 31 +++
tools/testing/selftests/arm/elf/Makefile | 6 +
tools/testing/selftests/arm/elf/parse_elf.c | 75 +++++
tools/testing/selftests/arm/mm/Makefile | 6 +
tools/testing/selftests/arm/mm/compat_va.c | 94 +++++++
tools/testing/selftests/arm/signal/Makefile | 30 ++
.../selftests/arm/signal/test_signals.c | 27 ++
.../selftests/arm/signal/test_signals.h | 74 +++++
.../selftests/arm/signal/test_signals_utils.c | 257 ++++++++++++++++++
.../selftests/arm/signal/test_signals_utils.h | 128 +++++++++
.../signal/testcases/mangle_cpsr_aif_bits.c | 33 +++
.../mangle_cpsr_invalid_compat_toggle.c | 29 ++
14 files changed, 848 insertions(+)
create mode 100644 tools/testing/selftests/arm/Makefile
create mode 100644 tools/testing/selftests/arm/README
create mode 100644 tools/testing/selftests/arm/elf/Makefile
create mode 100644 tools/testing/selftests/arm/elf/parse_elf.c
create mode 100644 tools/testing/selftests/arm/mm/Makefile
create mode 100644 tools/testing/selftests/arm/mm/compat_va.c
create mode 100644 tools/testing/selftests/arm/signal/Makefile
create mode 100644 tools/testing/selftests/arm/signal/test_signals.c
create mode 100644 tools/testing/selftests/arm/signal/test_signals.h
create mode 100644 tools/testing/selftests/arm/signal/test_signals_utils.c
create mode 100644 tools/testing/selftests/arm/signal/test_signals_utils.h
create mode 100644 tools/testing/selftests/arm/signal/testcases/mangle_cpsr_aif_bits.c
create mode 100644 tools/testing/selftests/arm/signal/testcases/mangle_cpsr_invalid_compat_toggle.c
--
2.39.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 2/4] selftests/arm: Add signal tests
From: Dev Jain @ 2024-04-05 8:44 UTC (permalink / raw)
To: shuah, linux-arm-kernel
Cc: linux-kselftest, linux-kernel, Anshuman.Khandual, suzuki.poulose,
ryan.roberts, rob.herring, Catalin.Marinas, broonie, will,
mark.rutland, Dev Jain
In-Reply-To: <20240405084410.256788-1-dev.jain@arm.com>
This patch introduces two signal tests, and generic test wrappers similar to
selftests/arm64/signal directory, along with the mangling testcases found
therein. arm_cpsr, dumped by the kernel to user space in the ucontext structure
to the signal handler, is mangled with. The kernel must spot this illegal
attempt and the testcases are expected to terminate via SEGV.
Signed-off-by: Dev Jain <dev.jain@arm.com>
---
.../selftests/arm/signal/test_signals.c | 27 ++
.../selftests/arm/signal/test_signals.h | 74 +++++
.../selftests/arm/signal/test_signals_utils.c | 257 ++++++++++++++++++
.../selftests/arm/signal/test_signals_utils.h | 128 +++++++++
.../signal/testcases/mangle_cpsr_aif_bits.c | 33 +++
.../mangle_cpsr_invalid_compat_toggle.c | 29 ++
6 files changed, 548 insertions(+)
create mode 100644 tools/testing/selftests/arm/signal/test_signals.c
create mode 100644 tools/testing/selftests/arm/signal/test_signals.h
create mode 100644 tools/testing/selftests/arm/signal/test_signals_utils.c
create mode 100644 tools/testing/selftests/arm/signal/test_signals_utils.h
create mode 100644 tools/testing/selftests/arm/signal/testcases/mangle_cpsr_aif_bits.c
create mode 100644 tools/testing/selftests/arm/signal/testcases/mangle_cpsr_invalid_compat_toggle.c
diff --git a/tools/testing/selftests/arm/signal/test_signals.c b/tools/testing/selftests/arm/signal/test_signals.c
new file mode 100644
index 000000000000..1ecf1e9f041c
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/test_signals.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 ARM Limited
+ *
+ * Generic test wrapper for arm signal tests.
+ *
+ * Each test provides its own tde struct tdescr descriptor to link with
+ * this wrapper. Framework provides common helpers.
+ */
+#include <kselftest.h>
+
+#include "test_signals.h"
+#include "test_signals_utils.h"
+
+struct tdescr *current = &tde;
+
+int main(int argc, char *argv[])
+{
+ ksft_print_msg("%s :: %s\n", current->name, current->descr);
+ if (test_setup(current) && test_init(current)) {
+ test_run(current);
+ test_cleanup(current);
+ }
+ test_result(current);
+
+ return current->result;
+}
diff --git a/tools/testing/selftests/arm/signal/test_signals.h b/tools/testing/selftests/arm/signal/test_signals.h
new file mode 100644
index 000000000000..bbd147127d66
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/test_signals.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2024 ARM Limited */
+
+#ifndef __TEST_SIGNALS_H__
+#define __TEST_SIGNALS_H__
+
+#include <signal.h>
+#include <stdbool.h>
+#include <ucontext.h>
+
+/*
+ * Using ARCH specific and sanitized Kernel headers from the tree.
+ */
+#include <asm/ptrace.h>
+#include <asm/hwcap.h>
+
+/*
+ * A descriptor used to describe and configure a test case.
+ * Fields with a non-trivial meaning are described inline in the following.
+ */
+struct tdescr {
+ /* KEEP THIS FIELD FIRST for easier lookup from assembly */
+ void *token;
+ /* when disabled token based sanity checking is skipped in handler */
+ bool sanity_disabled;
+ /* just a name for the test-case; manadatory field */
+ char *name;
+ char *descr;
+
+ bool initialized;
+ unsigned int minsigstksz;
+ /* signum used as a test trigger. Zero if no trigger-signal is used */
+ int sig_trig;
+ /*
+ * signum considered as a successful test completion.
+ * Zero when no signal is expected on success
+ */
+ int sig_ok;
+ /* signum expected on unsupported CPU features. */
+ int sig_unsupp;
+ /* a timeout in second for test completion */
+ unsigned int timeout;
+ bool triggered;
+ bool pass;
+ unsigned int result;
+ /* optional sa_flags for the installed handler */
+ int sa_flags;
+ ucontext_t saved_uc;
+ /* used by get_current_ctx() */
+ size_t live_sz;
+ ucontext_t *live_uc;
+ volatile sig_atomic_t live_uc_valid;
+ /* optional test private data */
+ void *priv;
+
+ /* a custom setup: called alternatively to default_setup */
+ int (*setup)(struct tdescr *td);
+ /* a custom init: called by default test init after test_setup */
+ bool (*init)(struct tdescr *td);
+ /* a custom cleanup function called before test exits */
+ void (*cleanup)(struct tdescr *td);
+ /* an optional function to be used as a trigger for starting test */
+ int (*trigger)(struct tdescr *td);
+ /*
+ * the actual test-core: invoked differently depending on the
+ * presence of the trigger function above; this is mandatory
+ */
+ int (*run)(struct tdescr *td, siginfo_t *si, ucontext_t *uc);
+ /* an optional function for custom results' processing */
+ void (*check_result)(struct tdescr *td);
+};
+
+extern struct tdescr tde;
+#endif
diff --git a/tools/testing/selftests/arm/signal/test_signals_utils.c b/tools/testing/selftests/arm/signal/test_signals_utils.c
new file mode 100644
index 000000000000..96aeb11de151
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/test_signals_utils.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2024 ARM Limited */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <string.h>
+#include <unistd.h>
+#include <assert.h>
+#include <sys/auxv.h>
+#include <linux/auxvec.h>
+#include <ucontext.h>
+
+#include <asm/unistd.h>
+
+#include <kselftest.h>
+
+#include "test_signals.h"
+#include "test_signals_utils.h"
+
+
+extern struct tdescr *current;
+
+static int sig_copyctx = SIGTRAP;
+
+static void unblock_signal(int signum)
+{
+ sigset_t sset;
+
+ sigemptyset(&sset);
+ sigaddset(&sset, signum);
+ sigprocmask(SIG_UNBLOCK, &sset, NULL);
+}
+
+static void default_result(struct tdescr *td, bool force_exit)
+{
+ if (td->result == KSFT_SKIP) {
+ fprintf(stderr, "==>> completed. SKIP.\n");
+ } else if (td->pass) {
+ fprintf(stderr, "==>> completed. PASS(1)\n");
+ td->result = KSFT_PASS;
+ } else {
+ fprintf(stdout, "==>> completed. FAIL(0)\n");
+ td->result = KSFT_FAIL;
+ }
+
+ if (force_exit)
+ exit(td->result);
+}
+
+/*
+ * The following handle_signal_* helpers are used by main default_handler
+ * and are meant to return true when signal is handled successfully:
+ * when false is returned instead, it means that the signal was somehow
+ * unexpected in that context and it was NOT handled; default_handler will
+ * take care of such unexpected situations.
+ */
+
+static bool handle_signal_unsupported(struct tdescr *td,
+ siginfo_t *si, void *uc)
+{
+
+ /* Mangling PC to avoid loops on original SIGILL */
+ ((ucontext_t *)uc)->uc_mcontext.arm_pc += 4;
+
+ if (!td->initialized) {
+ fprintf(stderr,
+ "Got SIG_UNSUPP @test_init. Ignore.\n");
+ } else {
+ fprintf(stderr,
+ "-- RX SIG_UNSUPP on unsupported feat...OK\n");
+ td->pass = 1;
+ default_result(current, 1);
+ }
+
+ return true;
+}
+
+static bool handle_signal_trigger(struct tdescr *td,
+ siginfo_t *si, void *uc)
+{
+ td->triggered = 1;
+
+ /* ->run was asserted NON-NULL in test_setup() already */
+ td->run(td, si, uc);
+
+ return true;
+}
+
+static bool handle_signal_ok(struct tdescr *td,
+ siginfo_t *si, void *uc)
+{
+
+ /*
+ * it's a bug in the test code when this assert fail:
+ * if sig_trig was defined, it must have been used before getting here.
+ */
+ assert(!td->sig_trig || td->triggered);
+ fprintf(stderr,
+ "SIG_OK -- SP:0x%lX si_addr@:%p si_code:%d token@:%p offset:%d\n",
+ ((ucontext_t *)uc)->uc_mcontext.arm_sp,
+ si->si_addr, si->si_code, td->token, td->token - si->si_addr);
+
+ /*
+ * Trying to narrow down the SEGV to the ones generated by Kernel itself
+ * via arm64_notify_segfault(). This is a best-effort check anyway, and
+ * the si_code check may need to change if this aspect of the kernel
+ * ABI changes.
+ */
+ if (td->sig_ok == SIGSEGV && si->si_code != SEGV_ACCERR) {
+ fprintf(stdout,
+ "si_code != SEGV_ACCERR...test is probably broken!\n");
+ abort();
+ }
+ td->pass = 1;
+ /*
+ * Some tests can lead to SEGV loops: in such a case we want to
+ * terminate immediately exiting straight away; some others are not
+ * supposed to outlive the signal handler code, due to the content of
+ * the fake sigframe which caused the signal itself.
+ */
+ default_result(current, 1);
+
+ return true;
+}
+
+static void default_handler(int signum, siginfo_t *si, void *uc)
+{
+ if (current->sig_unsupp && signum == current->sig_unsupp &&
+ handle_signal_unsupported(current, si, uc)) {
+ fprintf(stderr, "Handled SIG_UNSUPP\n");
+ } else if (current->sig_trig && signum == current->sig_trig &&
+ handle_signal_trigger(current, si, uc)) {
+ fprintf(stderr, "Handled SIG_TRIG\n");
+ } else if (current->sig_ok && signum == current->sig_ok &&
+ handle_signal_ok(current, si, uc)) {
+ fprintf(stderr, "Handled SIG_OK\n");
+ } else if (signum == sig_copyctx && current->live_uc) {
+ fprintf(stderr, "Handled SIG_COPYCTX\n");
+ } else {
+ if (signum == SIGALRM && current->timeout) {
+ fprintf(stderr, "-- Timeout !\n");
+ } else {
+ fprintf(stderr,
+ "-- RX UNEXPECTED SIGNAL: %d code %d address %p\n",
+ signum, si->si_code, si->si_addr);
+ }
+ default_result(current, 1);
+ }
+}
+
+static int default_setup(struct tdescr *td)
+{
+ struct sigaction sa;
+
+ sa.sa_sigaction = default_handler;
+ sa.sa_flags = SA_SIGINFO | SA_RESTART;
+ sa.sa_flags |= td->sa_flags;
+ sigemptyset(&sa.sa_mask);
+ /* uncatchable signals naturally skipped ... */
+ for (int sig = 1; sig < 32; sig++)
+ sigaction(sig, &sa, NULL);
+ /*
+ * RT Signals default disposition is Term but they cannot be
+ * generated by the Kernel in response to our tests; so just catch
+ * them all and report them as UNEXPECTED signals.
+ */
+ for (int sig = SIGRTMIN; sig <= SIGRTMAX; sig++)
+ sigaction(sig, &sa, NULL);
+
+ /* just in case...unblock explicitly all we need */
+ if (td->sig_trig)
+ unblock_signal(td->sig_trig);
+ if (td->sig_ok)
+ unblock_signal(td->sig_ok);
+ if (td->sig_unsupp)
+ unblock_signal(td->sig_unsupp);
+
+ if (td->timeout) {
+ unblock_signal(SIGALRM);
+ alarm(td->timeout);
+ }
+ fprintf(stderr, "Registered handlers for all signals.\n");
+
+ return 1;
+}
+
+static inline int default_trigger(struct tdescr *td)
+{
+ return !raise(td->sig_trig);
+}
+
+int test_init(struct tdescr *td)
+{
+ if (td->sig_trig == sig_copyctx) {
+ fprintf(stdout,
+ "Signal %d is RESERVED, cannot be used as a trigger. Aborting\n",
+ sig_copyctx);
+ return 0;
+ }
+ /* just in case */
+ unblock_signal(sig_copyctx);
+
+ td->minsigstksz = getauxval(AT_MINSIGSTKSZ);
+ if (!td->minsigstksz)
+ td->minsigstksz = MINSIGSTKSZ;
+ fprintf(stderr, "Detected MINSTKSIGSZ:%d\n", td->minsigstksz);
+
+ /* Perform test specific additional initialization */
+ if (td->init && !td->init(td)) {
+ fprintf(stderr, "FAILED Testcase initialization.\n");
+ return 0;
+ }
+ td->initialized = 1;
+ fprintf(stderr, "Testcase initialized.\n");
+
+ return 1;
+}
+
+int test_setup(struct tdescr *td)
+{
+ /* assert core invariants symptom of a rotten testcase */
+ assert(current);
+ assert(td);
+ assert(td->name);
+ assert(td->run);
+
+ /* Default result is FAIL if test setup fails */
+ td->result = KSFT_FAIL;
+ if (td->setup)
+ return td->setup(td);
+ else
+ return default_setup(td);
+}
+
+int test_run(struct tdescr *td)
+{
+ if (td->trigger)
+ return td->trigger(td);
+ else if (td->sig_trig)
+ return default_trigger(td);
+ else
+ return td->run(td, NULL, NULL);
+}
+
+void test_result(struct tdescr *td)
+{
+ if (td->initialized && td->result != KSFT_SKIP && td->check_result)
+ td->check_result(td);
+ default_result(td, 0);
+}
+
+void test_cleanup(struct tdescr *td)
+{
+ if (td->cleanup)
+ td->cleanup(td);
+}
diff --git a/tools/testing/selftests/arm/signal/test_signals_utils.h b/tools/testing/selftests/arm/signal/test_signals_utils.h
new file mode 100644
index 000000000000..386dcc6c268d
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/test_signals_utils.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2024 ARM Limited */
+
+#ifndef __TEST_SIGNALS_UTILS_H__
+#define __TEST_SIGNALS_UTILS_H__
+
+#include <assert.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <linux/compiler.h>
+#include "test_signals.h"
+
+int test_init(struct tdescr *td);
+int test_setup(struct tdescr *td);
+void test_cleanup(struct tdescr *td);
+int test_run(struct tdescr *td);
+void test_result(struct tdescr *td);
+
+/*
+ * Obtaining a valid and full-blown ucontext_t from userspace is tricky:
+ * libc getcontext does() not save all the regs and messes with some of
+ * them (pstate value in particular is not reliable).
+ *
+ * Here we use a service signal to grab the ucontext_t from inside a
+ * dedicated signal handler, since there, it is populated by Kernel
+ * itself in setup_sigframe(). The grabbed context is then stored and
+ * made available in td->live_uc.
+ *
+ * As service-signal is used a SIGTRAP induced by a 'brk' instruction,
+ * because here we have to avoid syscalls to trigger the signal since
+ * they would cause any SVE sigframe content (if any) to be removed.
+ *
+ * Anyway this function really serves a dual purpose:
+ *
+ * 1. grab a valid sigcontext into td->live_uc for result analysis: in
+ * such case it returns 1.
+ *
+ * 2. detect if, somehow, a previously grabbed live_uc context has been
+ * used actively with a sigreturn: in such a case the execution would have
+ * magically resumed in the middle of this function itself (seen_already==1):
+ * in such a case return 0, since in fact we have not just simply grabbed
+ * the context.
+ *
+ * This latter case is useful to detect when a fake_sigreturn test-case has
+ * unexpectedly survived without hitting a SEGV.
+ *
+ * Note that the case of runtime dynamically sized sigframes (like in SVE
+ * context) is still NOT addressed: sigframe size is supposed to be fixed
+ * at sizeof(ucontext_t).
+ */
+static __always_inline bool get_current_context(struct tdescr *td,
+ ucontext_t *dest_uc,
+ size_t dest_sz)
+{
+ static volatile bool seen_already;
+ int i;
+ char *uc = (char *)dest_uc;
+
+ assert(td && dest_uc);
+ /* it's a genuine invocation..reinit */
+ seen_already = 0;
+ td->live_uc_valid = 0;
+ td->live_sz = dest_sz;
+
+ /*
+ * This is a memset() but we don't want the compiler to
+ * optimise it into either instructions or a library call
+ * which might be incompatible with streaming mode.
+ */
+ for (i = 0; i < td->live_sz; i++) {
+ uc[i] = 0;
+ OPTIMIZER_HIDE_VAR(uc[0]);
+ }
+
+ td->live_uc = dest_uc;
+ /*
+ * Grab ucontext_t triggering a SIGTRAP.
+ *
+ * Note that:
+ * - live_uc_valid is declared volatile sig_atomic_t in
+ * struct tdescr since it will be changed inside the
+ * sig_copyctx handler
+ * - the additional 'memory' clobber is there to avoid possible
+ * compiler's assumption on live_uc_valid and the content
+ * pointed by dest_uc, which are all changed inside the signal
+ * handler
+ * - BRK causes a debug exception which is handled by the Kernel
+ * and finally causes the SIGTRAP signal to be delivered to this
+ * test thread. Since such delivery happens on the ret_to_user()
+ * /do_notify_resume() debug exception return-path, we are sure
+ * that the registered SIGTRAP handler has been run to completion
+ * before the execution path is restored here: as a consequence
+ * we can be sure that the volatile sig_atomic_t live_uc_valid
+ * carries a meaningful result. Being in a single thread context
+ * we'll also be sure that any access to memory modified by the
+ * handler (namely ucontext_t) will be visible once returned.
+ * - note that since we are using a breakpoint instruction here
+ * to cause a SIGTRAP, the ucontext_t grabbed from the signal
+ * handler would naturally contain a PC pointing exactly to this
+ * BRK line, which means that, on return from the signal handler,
+ * or if we place the ucontext_t on the stack to fake a sigreturn,
+ * we'll end up in an infinite loop of BRK-SIGTRAP-handler.
+ * For this reason we take care to artificially move forward the
+ * PC to the next instruction while inside the signal handler.
+ */
+ asm volatile ("brk #666"
+ : "+m" (*dest_uc)
+ :
+ : "memory");
+
+ /*
+ * If we get here with seen_already==1 it implies the td->live_uc
+ * context has been used to get back here....this probably means
+ * a test has failed to cause a SEGV...anyway live_uc does not
+ * point to a just acquired copy of ucontext_t...so return 0
+ */
+ if (seen_already) {
+ fprintf(stdout,
+ "Unexpected successful sigreturn detected: live_uc is stale !\n");
+ return 0;
+ }
+ seen_already = 1;
+
+ return td->live_uc_valid;
+}
+
+#endif
diff --git a/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_aif_bits.c b/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_aif_bits.c
new file mode 100644
index 000000000000..f422cd11ccf2
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_aif_bits.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 ARM Limited
+ *
+ * Try to mangle the ucontext from inside a signal handler, mangling the
+ * AIF bits in an illegal manner: this attempt must be spotted by Kernel
+ * and the test case is expected to be terminated via SEGV.
+ *
+ */
+
+#include "test_signals_utils.h"
+
+static int mangle_invalid_cpsr_run(struct tdescr *td, siginfo_t *si,
+ ucontext_t *uc)
+{
+
+ /*
+ * This config should trigger a SIGSEGV by Kernel when it checks
+ * the sigframe consistency in valid_user_regs() routine.
+ */
+ uc->uc_mcontext.arm_cpsr |= PSR_A_BIT | PSR_I_BIT | PSR_F_BIT;
+
+ return 1;
+}
+
+struct tdescr tde = {
+ .sanity_disabled = true,
+ .name = "MANGLE_CPSR_INVALID_AIF_BITS",
+ .descr = "Mangling uc_mcontext with INVALID AIF_BITS",
+ .sig_trig = SIGUSR1,
+ .sig_ok = SIGSEGV,
+ .run = mangle_invalid_cpsr_run,
+};
diff --git a/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_invalid_compat_toggle.c b/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_invalid_compat_toggle.c
new file mode 100644
index 000000000000..cb7eb8aec7f2
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/testcases/mangle_cpsr_invalid_compat_toggle.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 ARM Limited
+ *
+ * Try to mangle the ucontext from inside a signal handler, toggling
+ * the execution state bit: this attempt must be spotted by Kernel and
+ * the test case is expected to be terminated via SEGV.
+ */
+
+#include "test_signals_utils.h"
+
+static int mangle_invalid_cpsr_run(struct tdescr *td, siginfo_t *si,
+ ucontext_t *uc)
+{
+
+ /* This config should trigger a SIGSEGV by Kernel */
+ uc->uc_mcontext.arm_cpsr ^= MODE32_BIT;
+
+ return 1;
+}
+
+struct tdescr tde = {
+ .sanity_disabled = true,
+ .name = "MANGLE_CPSR_INVALID_STATE_TOGGLE",
+ .descr = "Mangling uc_mcontext with INVALID STATE_TOGGLE",
+ .sig_trig = SIGUSR1,
+ .sig_ok = SIGSEGV,
+ .run = mangle_invalid_cpsr_run,
+};
--
2.39.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 4/4] selftests: Add build infrastructure along with README
From: Dev Jain @ 2024-04-05 8:44 UTC (permalink / raw)
To: shuah, linux-arm-kernel
Cc: linux-kselftest, linux-kernel, Anshuman.Khandual, suzuki.poulose,
ryan.roberts, rob.herring, Catalin.Marinas, broonie, will,
mark.rutland, Dev Jain
In-Reply-To: <20240405084410.256788-1-dev.jain@arm.com>
Add arm target, individual Makefile targets, and instructions to build the
tests.
Signed-off-by: Dev Jain <dev.jain@arm.com>
---
tools/testing/selftests/Makefile | 1 +
tools/testing/selftests/arm/Makefile | 57 +++++++++++++++++++++
tools/testing/selftests/arm/README | 31 +++++++++++
tools/testing/selftests/arm/elf/Makefile | 6 +++
tools/testing/selftests/arm/mm/Makefile | 6 +++
tools/testing/selftests/arm/signal/Makefile | 30 +++++++++++
6 files changed, 131 insertions(+)
create mode 100644 tools/testing/selftests/arm/Makefile
create mode 100644 tools/testing/selftests/arm/README
create mode 100644 tools/testing/selftests/arm/elf/Makefile
create mode 100644 tools/testing/selftests/arm/mm/Makefile
create mode 100644 tools/testing/selftests/arm/signal/Makefile
diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile
index 15b6a111c3be..8478d94cda4c 100644
--- a/tools/testing/selftests/Makefile
+++ b/tools/testing/selftests/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
TARGETS += alsa
TARGETS += amd-pstate
+TARGETS += arm
TARGETS += arm64
TARGETS += bpf
TARGETS += breakpoints
diff --git a/tools/testing/selftests/arm/Makefile b/tools/testing/selftests/arm/Makefile
new file mode 100644
index 000000000000..039224bc006e
--- /dev/null
+++ b/tools/testing/selftests/arm/Makefile
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# When ARCH not overridden for crosscompiling, lookup machine
+ARCH ?= $(shell uname -m 2>/dev/null || echo not)
+
+ifneq (,$(filter $(ARCH),aarch64 arm64 arm armv7l armv8l))
+ARM_SUBTARGETS ?= mm signal elf
+else
+ARM_SUBTARGETS :=
+endif
+
+CFLAGS := -Wall -O2 -g -static
+
+# A proper top_srcdir is needed by KSFT(lib.mk)
+top_srcdir = $(realpath ../../../../)
+
+# Additional include paths needed by kselftest.h and local headers
+CFLAGS += -I$(top_srcdir)/tools/testing/selftests/
+
+CFLAGS += -I$(top_srcdir)/tools/include
+
+export CFLAGS
+export top_srcdir
+
+all:
+ @for DIR in $(ARM_SUBTARGETS); do \
+ BUILD_TARGET=$(OUTPUT)/$$DIR; \
+ mkdir -p $$BUILD_TARGET; \
+ make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \
+ done
+
+install: all
+ @for DIR in $(ARM_SUBTARGETS); do \
+ BUILD_TARGET=$(OUTPUT)/$$DIR; \
+ make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \
+ done
+
+run_tests: all
+ @for DIR in $(ARM_SUBTARGETS); do \
+ BUILD_TARGET=$(OUTPUT)/$$DIR; \
+ make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \
+ done
+
+# Avoid any output on non arm on emit_tests
+emit_tests:
+ @for DIR in $(ARM_SUBTARGETS); do \
+ BUILD_TARGET=$(OUTPUT)/$$DIR; \
+ make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \
+ done
+
+clean:
+ @for DIR in $(ARM_SUBTARGETS); do \
+ BUILD_TARGET=$(OUTPUT)/$$DIR; \
+ make OUTPUT=$$BUILD_TARGET -C $$DIR $@; \
+ done
+
+.PHONY: all clean install run_tests emit_tests
diff --git a/tools/testing/selftests/arm/README b/tools/testing/selftests/arm/README
new file mode 100644
index 000000000000..1a05c043d7ee
--- /dev/null
+++ b/tools/testing/selftests/arm/README
@@ -0,0 +1,31 @@
+KSelfTest ARM
+===============
+
+- This is a series of compatibility tests, wherein the source files are
+ built statically into a 32 bit ELF; they should pass on both 32 and 64
+ bit kernels. They are not built or run but just skipped completely when
+ env-variable ARCH is found to be different than 'arm64' or 'arm' and
+ `uname -m` reports other than 'aarch64', 'armv7l' or 'armv8l'.
+
+- Please ensure that the test kernel is built with CONFIG_COMPAT enabled.
+
+- Holding true the above, ARM KSFT tests can be run within the KSelfTest
+ framework using standard Linux top-level-makefile targets. Please set
+ $(CROSS_COMPILE) to 'arm-linux-gnueabi-' or 'arm-linux-gnueabihf-'.
+
+ $ make TARGETS=arm kselftest-clean
+ $ make $(CROSS_COMPILE) TARGETS=arm kselftest
+
+ or
+
+ $ make $(CROSS_COMPILE) -C tools/testing/selftests TARGETS=arm \
+ INSTALL_PATH=<your-installation-path> install
+
+ or, alternatively, only specific arm/ subtargets can be picked:
+
+ $ make $(CROSS_COMPILE) -C tools/testing/selftests TARGETS=arm \
+ ARM_SUBTARGETS="signal" INSTALL_PATH=<your-installation-path> \
+ install
+
+ Further details on building and running KFST can be found in:
+ Documentation/dev-tools/kselftest.rst
diff --git a/tools/testing/selftests/arm/elf/Makefile b/tools/testing/selftests/arm/elf/Makefile
new file mode 100644
index 000000000000..86636fe02994
--- /dev/null
+++ b/tools/testing/selftests/arm/elf/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2024 ARM Limited
+
+TEST_GEN_PROGS := parse_elf
+
+include ../../lib.mk
diff --git a/tools/testing/selftests/arm/mm/Makefile b/tools/testing/selftests/arm/mm/Makefile
new file mode 100644
index 000000000000..d8bfa45df98c
--- /dev/null
+++ b/tools/testing/selftests/arm/mm/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2024 ARM Limited
+
+TEST_GEN_PROGS := compat_va
+
+include ../../lib.mk
diff --git a/tools/testing/selftests/arm/signal/Makefile b/tools/testing/selftests/arm/signal/Makefile
new file mode 100644
index 000000000000..3540a25de75a
--- /dev/null
+++ b/tools/testing/selftests/arm/signal/Makefile
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2024 ARM Limited
+
+# Additional include paths needed by kselftest.h and local headers
+CFLAGS += -D_GNU_SOURCE -std=gnu99 -I.
+
+SRCS := $(filter-out testcases/testcases.c,$(wildcard testcases/*.c))
+PROGS := $(patsubst %.c,%,$(SRCS))
+
+# Generated binaries to be installed by top KSFT script
+TEST_GEN_PROGS := $(notdir $(PROGS))
+
+# Get Kernel headers installed and use them.
+
+# Including KSFT lib.mk here will also mangle the TEST_GEN_PROGS list
+# to account for any OUTPUT target-dirs optionally provided by
+# the toplevel makefile
+include ../../lib.mk
+
+$(TEST_GEN_PROGS): $(PROGS)
+ cp $(PROGS) $(OUTPUT)/
+
+# Common test-unit targets to build common-layout test-cases executables
+# Needs secondary expansion to properly include the testcase c-file in pre-reqs
+COMMON_SOURCES := test_signals.c test_signals_utils.c
+COMMON_HEADERS := test_signals.h test_signals_utils.h
+
+.SECONDEXPANSION:
+$(PROGS): $$@.c ${COMMON_SOURCES} ${COMMON_HEADERS}
+ $(CC) $(CFLAGS) ${@}.c ${COMMON_SOURCES} -o $@
--
2.39.2
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^ permalink raw reply related
* [PATCH 0/3] Fix reg ranges for dma-controller node
From: Jayesh Choudhary @ 2024-04-05 8:52 UTC (permalink / raw)
To: nm, vigneshr, bb, devicetree, j-choudhary
Cc: kristo, robh, krzk+dt, conor+dt, linux-kernel, linux-arm-kernel
The dma-controller node 'main_pktdma' has few memory regions with
wrong sizes.
DMASS0_PKTDMA_RINGRT is marked as 4MB region when it is actually a 2MB
region. Similarly, DMASS0_PKTDMA_TCHANRT is marked as 256KB region but
the actual size is 128KB as shown in TRM in the section for Main Memory
Map (Table 2-1)
Fix these region across AM62, AM62A and AM62P (which is also used in
J722S)
TRM:
AM625: <https://www.ti.com/lit/pdf/spruiv7>
AM62A7: <https://www.ti.com/lit/pdf/spruj16>
AM62P: <https://www.ti.com/lit/pdf/spruj83>
J722S: <https://www.ti.com/lit/zip/sprujb3>
Jayesh Choudhary (3):
arm64: dts: ti: k3-am62-main: Fix the reg-range for dma-controller
arm64: dts: ti: k3-am62a-main: Fix the reg-range for dma-controller
arm64: dts: ti: k3-am62p-main: Fix the reg-range for dma-controller
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ++--
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++--
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
--
2.25.1
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^ permalink raw reply
* [PATCH 1/3] arm64: dts: ti: k3-am62-main: Fix the reg-range for dma-controller
From: Jayesh Choudhary @ 2024-04-05 8:52 UTC (permalink / raw)
To: nm, vigneshr, bb, devicetree, j-choudhary
Cc: kristo, robh, krzk+dt, conor+dt, linux-kernel, linux-arm-kernel
In-Reply-To: <20240405085208.32227-1-j-choudhary@ti.com>
The TX Channel Realtime Registers region 'tchanrt' is 128KB and Ring
Realtime Registers region 'ringrt' is 2MB as shown in memory map in
the TRM[0]. So fix ranges for those reg-regions.
[0]: <https://www.ti.com/lit/pdf/spruiv7>
Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
index e9cffca073ef..e10cc9fc0b10 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi
@@ -141,8 +141,8 @@ main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
--
2.25.1
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^ permalink raw reply related
* [PATCH 3/3] arm64: dts: ti: k3-am62p-main: Fix the reg-range for dma-controller
From: Jayesh Choudhary @ 2024-04-05 8:52 UTC (permalink / raw)
To: nm, vigneshr, bb, devicetree, j-choudhary
Cc: kristo, robh, krzk+dt, conor+dt, linux-kernel, linux-arm-kernel
In-Reply-To: <20240405085208.32227-1-j-choudhary@ti.com>
The TX Channel Realtime Registers region 'tchanrt' is 128KB and Ring
Realtime Registers region 'ringrt' is 2MB as shown in memory map in
the TRM[0]. So fix ranges for those reg-regions.
[0]: <https://www.ti.com/lit/pdf/spruj83>
Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 7337a9e13535..514c201bd5c9 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -123,8 +123,8 @@ main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
--
2.25.1
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^ permalink raw reply related
* [PATCH 2/3] arm64: dts: ti: k3-am62a-main: Fix the reg-range for dma-controller
From: Jayesh Choudhary @ 2024-04-05 8:52 UTC (permalink / raw)
To: nm, vigneshr, bb, devicetree, j-choudhary
Cc: kristo, robh, krzk+dt, conor+dt, linux-kernel, linux-arm-kernel
In-Reply-To: <20240405085208.32227-1-j-choudhary@ti.com>
The TX Channel Realtime Registers region 'tchanrt' is 128KB and Ring
Realtime Registers region 'ringrt' is 2MB as shown in memory map in
the TRM[0]. So fix ranges for those reg-regions.
[0]: <https://www.ti.com/lit/pdf/spruj16>
Fixes: 3dad70def7ff ("arm64: dts: ti: k3-am62a-main: Add more peripheral nodes")
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index aa1e057082f0..5a4cb0536c6f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -120,8 +120,8 @@ main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
--
2.25.1
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^ permalink raw reply related
* Re: [PATCH 14/19] i2c: nomadik: drop owner assignment
From: Wolfram Sang @ 2024-04-05 8:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Russell King, Suzuki K Poulose, Mike Leach, James Clark,
Alexander Shishkin, Maxime Coquelin, Alexandre Torgue,
Linus Walleij, Andi Shyti, Olivia Mackall, Herbert Xu, Vinod Koul,
Dmitry Torokhov, Miquel Raynal, Michal Simek, Eric Auger,
Alex Williamson, linux-kernel, coresight, linux-arm-kernel,
linux-stm32, linux-i2c, linux-crypto, dmaengine, linux-input, kvm
In-Reply-To: <20240326-module-owner-amba-v1-14-4517b091385b@linaro.org>
[-- Attachment #1.1: Type: text/plain, Size: 277 bytes --]
On Tue, Mar 26, 2024 at 09:23:44PM +0100, Krzysztof Kozlowski wrote:
> Amba bus core already sets owner, so driver does not need to.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* Re: [PATCH v12 2/7] clk: meson: add vclk driver
From: Jerome Brunet @ 2024-04-05 7:00 UTC (permalink / raw)
To: neil.armstrong
Cc: Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Martin Blumenstingl, Kevin Hilman, Michael Turquette,
Stephen Boyd, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Daniel Vetter, Jagan Teki, Nicolas Belin,
devicetree, linux-kernel, linux-amlogic, linux-clk,
linux-arm-kernel, dri-devel
In-Reply-To: <2cf79f07-0ae1-4267-ac08-fe40366d87d4@linaro.org>
On Thu 04 Apr 2024 at 18:59, Neil Armstrong <neil.armstrong@linaro.org> wrote:
> On 04/04/2024 10:13, Jerome Brunet wrote:
>> On Wed 03 Apr 2024 at 09:46, Neil Armstrong <neil.armstrong@linaro.org>
>> wrote:
>>
>>> The VCLK and VCLK_DIV clocks have supplementary bits.
>>>
>>> The VCLK gate has a "SOFT RESET" bit to toggle after the whole
>>> VCLK sub-tree rate has been set, this is implemented in
>>> the gate enable callback.
>>>
>>> The VCLK_DIV clocks as enable and reset bits used to disable
>>> and reset the divider, associated with CLK_SET_RATE_GATE it ensures
>>> the rate is set while the divider is disabled and in reset mode.
>>>
>>> The VCLK_DIV enable bit isn't implemented as a gate since it's part
>>> of the divider logic and vendor does this exact sequence to ensure
>>> the divider is correctly set.
>> The checkpatch warning is still there. Is it a choice or a mistake ?
>> Documentation says "GPL v2" exists for historic reason which seems to
>> hint "GPL" is preferred, and I suppose this is why checkpatch warns for
>> it.
>
> Well I didn't see this warning, this is what I fixed:
>
> $ scripts/checkpatch.pl --strict drivers/clk/meson/vclk.c
> CHECK: Alignment should match open parenthesis
> #63: FILE: drivers/clk/meson/vclk.c:63:
> +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
> + unsigned long prate)
>
> CHECK: Alignment should match open parenthesis
> #73: FILE: drivers/clk/meson/vclk.c:73:
> +static int meson_vclk_div_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
>
> CHECK: Alignment should match open parenthesis
> #83: FILE: drivers/clk/meson/vclk.c:83:
> +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
>
I would not ask a respin solely for this. It's nice to fix it but I was
mostly after the warning TBH.
> <snip>
>
> It seems that checking a commit triggers an extra check....
>
> $ scripts/checkpatch.pl --strict -G 1bac9f6aa3c3
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #58:
> new file mode 100644
>
> <snip>
>
> WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity")
> #203: FILE: drivers/clk/meson/vclk.c:141:
> +MODULE_LICENSE("GPL v2");
Hum, I'm running checkpatch against the mail itself, not the commit. I
still get the warning
>
> <snip>
>
> Neil
>
>>
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>> drivers/clk/meson/Kconfig | 4 ++
>>> drivers/clk/meson/Makefile | 1 +
>>> drivers/clk/meson/vclk.c | 141 +++++++++++++++++++++++++++++++++++++++++++++
>>> drivers/clk/meson/vclk.h | 51 ++++++++++++++++
>>> 4 files changed, 197 insertions(+)
>>>
>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>> index 29ffd14d267b..8a9823789fa3 100644
>>> --- a/drivers/clk/meson/Kconfig
>>> +++ b/drivers/clk/meson/Kconfig
>>> @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV
>>> tristate
>>> select COMMON_CLK_MESON_REGMAP
>>> +config COMMON_CLK_MESON_VCLK
>>> + tristate
>>> + select COMMON_CLK_MESON_REGMAP
>>> +
>>> config COMMON_CLK_MESON_CLKC_UTILS
>>> tristate
>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>> index 9ee4b954c896..9ba43fe7a07a 100644
>>> --- a/drivers/clk/meson/Makefile
>>> +++ b/drivers/clk/meson/Makefile
>>> @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
>>> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
>>> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
>>> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
>>> +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
>>> # Amlogic Clock controllers
>>> diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c
>>> new file mode 100644
>>> index 000000000000..45dc216941ea
>>> --- /dev/null
>>> +++ b/drivers/clk/meson/vclk.c
>>> @@ -0,0 +1,141 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>>> + */
>>> +
>>> +#include <linux/module.h>
>>> +#include "vclk.h"
>>> +
>>> +/* The VCLK gate has a supplementary reset bit to pulse after ungating */
>>> +
>>> +static inline struct meson_vclk_gate_data *
>>> +clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
>>> +{
>>> + return (struct meson_vclk_gate_data *)clk->data;
>>> +}
>>> +
>>> +static int meson_vclk_gate_enable(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>>> +
>>> + meson_parm_write(clk->map, &vclk->enable, 1);
>>> +
>>> + /* Do a reset pulse */
>>> + meson_parm_write(clk->map, &vclk->reset, 1);
>>> + meson_parm_write(clk->map, &vclk->reset, 0);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_vclk_gate_disable(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>>> +
>>> + meson_parm_write(clk->map, &vclk->enable, 0);
>>> +}
>>> +
>>> +static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>>> +
>>> + return meson_parm_read(clk->map, &vclk->enable);
>>> +}
>>> +
>>> +const struct clk_ops meson_vclk_gate_ops = {
>>> + .enable = meson_vclk_gate_enable,
>>> + .disable = meson_vclk_gate_disable,
>>> + .is_enabled = meson_vclk_gate_is_enabled,
>>> +};
>>> +EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
>>> +
>>> +/* The VCLK Divider has supplementary reset & enable bits */
>>> +
>>> +static inline struct meson_vclk_div_data *
>>> +clk_get_meson_vclk_div_data(struct clk_regmap *clk)
>>> +{
>>> + return (struct meson_vclk_div_data *)clk->data;
>>> +}
>>> +
>>> +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
>>> + unsigned long prate)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> +
>>> + return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
>>> + vclk->table, vclk->flags, vclk->div.width);
>>> +}
>>> +
>>> +static int meson_vclk_div_determine_rate(struct clk_hw *hw,
>>> + struct clk_rate_request *req)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> +
>>> + return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
>>> + vclk->flags);
>>> +}
>>> +
>>> +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
>>> + unsigned long parent_rate)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> + int ret;
>>> +
>>> + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
>>> + vclk->flags);
>>> + if (ret < 0)
>>> + return ret;
>>> +
>>> + meson_parm_write(clk->map, &vclk->div, ret);
>>> +
>>> + return 0;
>>> +};
>>> +
>>> +static int meson_vclk_div_enable(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> +
>>> + /* Unreset the divider when ungating */
>>> + meson_parm_write(clk->map, &vclk->reset, 0);
>>> + meson_parm_write(clk->map, &vclk->enable, 1);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_vclk_div_disable(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> +
>>> + /* Reset the divider when gating */
>>> + meson_parm_write(clk->map, &vclk->enable, 0);
>>> + meson_parm_write(clk->map, &vclk->reset, 1);
>>> +}
>>> +
>>> +static int meson_vclk_div_is_enabled(struct clk_hw *hw)
>>> +{
>>> + struct clk_regmap *clk = to_clk_regmap(hw);
>>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>>> +
>>> + return meson_parm_read(clk->map, &vclk->enable);
>>> +}
>>> +
>>> +const struct clk_ops meson_vclk_div_ops = {
>>> + .recalc_rate = meson_vclk_div_recalc_rate,
>>> + .determine_rate = meson_vclk_div_determine_rate,
>>> + .set_rate = meson_vclk_div_set_rate,
>>> + .enable = meson_vclk_div_enable,
>>> + .disable = meson_vclk_div_disable,
>>> + .is_enabled = meson_vclk_div_is_enabled,
>>> +};
>>> +EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
>>> +
>>> +MODULE_DESCRIPTION("Amlogic vclk clock driver");
>>> +MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
>>> +MODULE_LICENSE("GPL v2");
>>> diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h
>>> new file mode 100644
>>> index 000000000000..20b0b181db09
>>> --- /dev/null
>>> +++ b/drivers/clk/meson/vclk.h
>>> @@ -0,0 +1,51 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>>> + */
>>> +
>>> +#ifndef __VCLK_H
>>> +#define __VCLK_H
>>> +
>>> +#include "clk-regmap.h"
>>> +#include "parm.h"
>>> +
>>> +/**
>>> + * struct meson_vclk_gate_data - vclk_gate regmap backed specific data
>>> + *
>>> + * @enable: vclk enable field
>>> + * @reset: vclk reset field
>>> + * @flags: hardware-specific flags
>>> + *
>>> + * Flags:
>>> + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
>>> + */
>>> +struct meson_vclk_gate_data {
>>> + struct parm enable;
>>> + struct parm reset;
>>> + u8 flags;
>>> +};
>>> +
>>> +extern const struct clk_ops meson_vclk_gate_ops;
>>> +
>>> +/**
>>> + * struct meson_vclk_div_data - vclk_div regmap back specific data
>>> + *
>>> + * @div: divider field
>>> + * @enable: vclk divider enable field
>>> + * @reset: vclk divider reset field
>>> + * @table: array of value/divider pairs, last entry should have div = 0
>>> + *
>>> + * Flags:
>>> + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
>>> + */
>>> +struct meson_vclk_div_data {
>>> + struct parm div;
>>> + struct parm enable;
>>> + struct parm reset;
>>> + const struct clk_div_table *table;
>>> + u8 flags;
>>> +};
>>> +
>>> +extern const struct clk_ops meson_vclk_div_ops;
>>> +
>>> +#endif /* __VCLK_H */
>>
--
Jerome
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* [RFC 1/8] arm64/sysreg: Add register fields for MDSELR_EL1
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This adds register fields for MDSELR_EL1 as per the definitions based
on DDI0601 2023-12.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/tools/sysreg | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a4c1dd4741a4..4c58fd7a70e6 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -93,6 +93,17 @@ Res0 63:32
Field 31:0 DTRTX
EndSysreg
+Sysreg MDSELR_EL1 2 0 0 4 2
+Res0 63:6
+Enum 5:4 BANK
+ 0b00 BANK_0
+ 0b01 BANK_1
+ 0b10 BANK_2
+ 0b11 BANK_3
+EndEnum
+Res0 3:0
+EndSysreg
+
Sysreg OSECCR_EL1 2 0 0 6 2
Res0 63:32
Field 31:0 EDECCR
--
2.25.1
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