* [PATCH 1/2] dt-bindings: mmc: hisilicon,hi3660-dw-mshc: Convert to DT schema
From: Bhargav Joshi @ 2026-03-23 19:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, zhangfei.gao, linux-mmc
Cc: daniel.baluta, simona.toaca, d-gole, m-chawdhry, rougueprince47
In-Reply-To: <20260323194400.22886-1-rougueprince47@gmail.com>
Convert the Hisilicon DesignWare Mobile Storage Host Controller
(dw-mshc) bindings from text format to DT schema.
As part of this conversion, the binding file is renamed from
k3-dw-mshc.txt to hisilicon,hi3660-dw-mshc.yaml to align with compatible
string naming conventions.
Examples have been updated to pass schema validation.
Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
---
.../mmc/hisilicon,hi3660-dw-mshc.yaml | 111 ++++++++++++++++++
.../devicetree/bindings/mmc/k3-dw-mshc.txt | 73 ------------
2 files changed, 111 insertions(+), 73 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
diff --git a/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
new file mode 100644
index 000000000000..6ba1a42a27ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/hisilicon,hi3660-dw-mshc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon specific extensions to the Synopsys Designware Mobile Storage Host Controller
+
+maintainers:
+ - Zhangfei Gao <zhangfei.gao@linaro.org>
+
+description:
+ The Synopsys designware mobile storage host controller is used to interface
+ a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+ differences between the core Synopsys dw mshc controller properties described
+ by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
+ extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+allOf:
+ - $ref: /schemas/mmc/synopsys-dw-mshc-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: hisilicon,hi3660-dw-mshc
+ - items:
+ - const: hisilicon,hi3670-dw-mshc
+ - const: hisilicon,hi3660-dw-mshc
+ - const: hisilicon,hi4511-dw-mshc
+ - const: hisilicon,hi6220-dw-mshc
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: card interface unit clock
+ - description: bus interface unit clock
+
+ clock-names:
+ items:
+ - const: ciu
+ - const: biu
+
+ hisilicon,peripheral-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle of syscon used to control peripheral.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/hi3620-clock.h>
+
+ mmc@fcd03000 {
+ compatible = "hisilicon,hi4511-dw-mshc";
+ reg = <0xfcd03000 0x1000>;
+ interrupts = <0 16 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
+ clock-names = "ciu", "biu";
+ vmmc-supply = <&ldo12>;
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
+ bus-width = <4>;
+ disable-wp;
+ cd-gpios = <&gpio10 3 0>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ - |
+ #include <dt-bindings/clock/hi6220-clock.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mmc@f723e000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ bus-width = <0x4>;
+ disable-wp;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ card-detect-delay = <200>;
+ hisilicon,peripheral-syscon = <&ao_ctrl>;
+ reg = <0x0 0xf723e000 0x0 0x1000>;
+ interrupts = <0x0 0x49 0x4>;
+ clocks = <&clock_sys HI6220_MMC1_CIUCLK>,
+ <&clock_sys HI6220_MMC1_CLK>;
+ clock-names = "ciu", "biu";
+ cd-gpios = <&gpio1 0 1>;
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
+ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
+ vqmmc-supply = <&ldo7>;
+ vmmc-supply = <&ldo10>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
deleted file mode 100644
index 36c4bea675d5..000000000000
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-* Hisilicon specific extensions to the Synopsys Designware Mobile
- Storage Host Controller
-
-Read synopsys-dw-mshc.txt for more details
-
-The Synopsys designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core Synopsys dw mshc controller properties described
-by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
-extensions to the Synopsys Designware Mobile Storage Host Controller.
-
-Required Properties:
-
-* compatible: should be one of the following.
- - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
- - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
- with hi3670 specific extensions.
- - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
- - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
-
-Optional Properties:
-- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
-
-Example:
-
- /* for Hi3620 */
-
- /* SoC portion */
- dwmmc_0: dwmmc0@fcd03000 {
- compatible = "hisilicon,hi4511-dw-mshc";
- reg = <0xfcd03000 0x1000>;
- interrupts = <0 16 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
- clock-names = "ciu", "biu";
- };
-
- /* Board portion */
- dwmmc0@fcd03000 {
- vmmc-supply = <&ldo12>;
- fifo-depth = <0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
- bus-width = <4>;
- disable-wp;
- cd-gpios = <&gpio10 3 0>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- };
-
- /* for Hi6220 */
-
- dwmmc_1: dwmmc1@f723e000 {
- compatible = "hisilicon,hi6220-dw-mshc";
- bus-width = <0x4>;
- disable-wp;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- card-detect-delay = <200>;
- hisilicon,peripheral-syscon = <&ao_ctrl>;
- reg = <0x0 0xf723e000 0x0 0x1000>;
- interrupts = <0x0 0x49 0x4>;
- clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
- clock-names = "ciu", "biu";
- cd-gpios = <&gpio1 0 1>;
- pinctrl-names = "default", "idle";
- pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
- pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
- vqmmc-supply = <&ldo7>;
- vmmc-supply = <&ldo10>;
- };
--
2.53.0
^ permalink raw reply related
* [PATCH 0/2] mmc: hisilicon: Convert dw-mshc bindings and fix dtbs
From: Bhargav Joshi @ 2026-03-23 19:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, zhangfei.gao, linux-mmc
Cc: daniel.baluta, simona.toaca, d-gole, m-chawdhry, rougueprince47
This series converts the Hisilicon dw-mshc text bindings to DT schema
format and cleans up legacy node names in Hisilicon board files.
While testing the new YAML schema, dtbs_check flagged the hi3660,
hi3670, and hi6220 SoC files for using the non-standard 'dwmmc' node
name prefix. resulting in warnings.
Patch 1 Convert to DT schema
Patch 2 updates the Hisilicon dtsi files to use standard 'mmc'
node name.
Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
---
Note: this patch is part of the process for applying to GSoC device
tree bindings conversion project #
https://github.com/LinuxFoundationGSoC/ProjectIdeas/wiki/GSoC-2026-Device-Tree-Bindings
- The file is enabled by arm64 defconfig (CONFIG_MMC_DW_K3=y)
- It is used in following
/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
-included by /arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
-included by /arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
Bhargav Joshi (2):
dt-bindings: mmc: hisilicon,hi3660-dw-mshc: Convert to DT schema
arm64: dts: hisilicon: Rename dwmmc nodes to mmc
.../mmc/hisilicon,hi3660-dw-mshc.yaml | 111 ++++++++++++++++++
.../devicetree/bindings/mmc/k3-dw-mshc.txt | 73 ------------
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 +-
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 +-
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 +-
5 files changed, 118 insertions(+), 80 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
--
2.53.0
^ permalink raw reply
* Re: [PATCH v5 08/17] spi: rockchip-sfc: Simplify clock handling with devm_clk_get_enabled()
From: Mark Brown @ 2026-03-23 19:43 UTC (permalink / raw)
To: Pei Xiao
Cc: linux-spi, linux-arm-kernel, linux-kernel, imx, openbmc,
linux-rockchip, linux-riscv, linux-mediatek, linux-stm32,
Frank.Li, amelie.delaunay
In-Reply-To: <863ab1ddc4f3b9a25c0bf79e1581b65359cef6c3.1773885292.git.xiaopei01@kylinos.cn>
[-- Attachment #1: Type: text/plain, Size: 395 bytes --]
On Thu, Mar 19, 2026 at 10:04:04AM +0800, Pei Xiao wrote:
> Replace devm_clk_get() followed by clk_prepare_enable() with
> devm_clk_get_enabled() for both the interface clock "clk_sfc" and the
> AHB clock "hclk_sfc". This reduces boilerplate code and error handling,
> as the managed API automatically disables the clocks when the device is
> removed or if probe fails.
More runtime PM clocks.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
From: nick.hawkins @ 2026-03-23 19:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean-Marie Verdun,
devicetree, linux-arm-kernel, linux-kernel, Nick Hawkins
In-Reply-To: <20260323194223.683487-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add the HPE GSC ARM64 BMC SoC compatibles to the existing
hpe,gxp.yaml binding.
The initial board compatible is hpe,gsc-dl340gen12 for the DL340 Gen12
server platform.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
Documentation/devicetree/bindings/arm/hpe,gxp.yaml | 7 ++++++-
MAINTAINERS | 7 +++++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
index 224bbcb93f95..6f057cd58571 100644
--- a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
+++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: HPE BMC GXP platforms
+title: HPE BMC GXP and GSC platforms
maintainers:
- Nick Hawkins <nick.hawkins@hpe.com>
@@ -18,6 +18,11 @@ properties:
- enum:
- hpe,gxp-dl360gen10
- const: hpe,gxp
+ - description: GSC Based Boards
+ items:
+ - enum:
+ - hpe,gsc-dl340gen12
+ - const: hpe,gsc
required:
- compatible
diff --git a/MAINTAINERS b/MAINTAINERS
index 2265e2c9bfbe..33e4357f9011 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2859,6 +2859,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git
F: arch/arm/mach-sa1100/include/mach/jornada720.h
F: arch/arm/mach-sa1100/jornada720.c
+ARM64/HPE GSC ARCHITECTURE
+M: Nick Hawkins <nick.hawkins@hpe.com>
+S: Maintained
+F: Documentation/devicetree/bindings/arm/hpe,gxp.yaml
+F: arch/arm64/Kconfig.platforms
+F: arch/arm64/boot/dts/hpe/
+
ARM/HPE GXP ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
M: Nick Hawkins <nick.hawkins@hpe.com>
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
From: nick.hawkins @ 2026-03-23 19:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean-Marie Verdun,
devicetree, linux-arm-kernel, linux-kernel, Nick Hawkins
In-Reply-To: <20260323194223.683487-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU
cluster, GIC v3 interrupt controller, ARM64 generic timer, and console
UART.
Add the board-level DTS for the HPE DL340 Gen12, which includes
gsc.dtsi and adds memory and chosen nodes.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
arch/arm64/boot/dts/hpe/Makefile | 2 +
arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++
arch/arm64/boot/dts/hpe/gsc.dtsi | 106 +++++++++++++++++++++
3 files changed, 126 insertions(+)
create mode 100644 arch/arm64/boot/dts/hpe/Makefile
create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Makefile
new file mode 100644
index 000000000000..804f7c54e9b6
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_ARCH_HPE_GSC) += gsc-dl340gen12.dtb
diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
new file mode 100644
index 000000000000..42cfeac99029
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "gsc.dtsi"
+
+/ {
+ compatible = "hpe,gsc-dl340gen12", "hpe,gsc";
+ model = "HPE ProLiant DL340 Gen12";
+
+ chosen {
+ stdout-path = &uartc;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc.dtsi
new file mode 100644
index 000000000000..3433c4a18512
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GSC
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0xa0008048>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0xa0008048>;
+ };
+ };
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <33333333>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gic>;
+ };
+
+ ahb: ahb@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x80000000>;
+ ranges;
+
+ gic: gic@ce000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x20000>;
+ #redistributor-regions = <1>;
+ reg = <0xce000000 0x10000>,
+ <0xce060000 0x40000>,
+ <0xce200000 0x40000>;
+ };
+
+ uartc: serial@c00000f0 {
+ compatible = "ns16550a";
+ reg = <0xc00000f0 0x8>;
+ interrupts = <0 19 4>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uarta: serial@c00000e0 {
+ compatible = "ns16550a";
+ reg = <0xc00000e0 0x8>;
+ interrupts = <0 17 4>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartb: serial@c00000e8 {
+ compatible = "ns16550a";
+ reg = <0xc00000e8 0x8>;
+ interrupts = <0 18 4>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uarte: serial@c00003e0 {
+ compatible = "ns16550a";
+ reg = <0xc00003e0 0x8>;
+ interrupts = <0 12 4>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/3] arm64: Add HPE GSC platform support
From: nick.hawkins @ 2026-03-23 19:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean-Marie Verdun,
devicetree, linux-arm-kernel, linux-kernel, Nick Hawkins
From: Nick Hawkins <nick.hawkins@hpe.com>
This series adds base platform support for the HPE GSC ARM64
BMC SoC used on HPE servers.
Patch 1 extends the existing hpe,gxp.yaml DT binding to cover GSC-based
boards (per DT maintainer guidance: one binding file per vendor).
Patch 2 adds the ARCH_HPE_GSC Kconfig entry to arm64/Kconfig.platforms.
Patch 3 adds the minimal SoC DTSI and DL340 Gen12 board DTS. The
full peripheral set (i3c, ethernet, etc.) will follow in a later
series after the relevant subsystem drivers are accepted upstream.
v1 was submitted as a single patch containing only the DT binding.
Based on review feedback from Krzysztof Kozlowski, this v2 expands to
a proper series covering the full base platform introduction.
Changes in v2:
- Drop hpe,gsc.yaml; extend existing hpe,gxp.yaml instead
(per Krzysztof Kozlowski review: one binding per vendor)
- Split into three patches: binding, Kconfig, and DTS
- Add gsc.dtsi + gsc-dl340gen12.dts
- Add ARCH_HPE_GSC to arm64/Kconfig.platforms
Nick Hawkins (3):
dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
arm64: Kconfig: Add ARCH_HPE_GSC platform
arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
.../devicetree/bindings/arm/hpe,gxp.yaml | 11 ++-
MAINTAINERS | 5 ++
arch/arm64/Kconfig.platforms | 18 +++++
arch/arm64/boot/dts/hpe/Makefile | 2 +
arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 +++++
arch/arm64/boot/dts/hpe/gsc.dtsi | 73 +++++++++++++++++++
6 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/hpe/Makefile
create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
base-commit: 3f4a08e64442340f4807de63e30aef22cc308830
--
2.34.1
^ permalink raw reply
* [PATCH v2 2/3] arm64: Kconfig: Add ARCH_HPE_GSC platform
From: nick.hawkins @ 2026-03-23 19:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jean-Marie Verdun,
devicetree, linux-arm-kernel, linux-kernel, Nick Hawkins
In-Reply-To: <20260323194223.683487-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add the ARCH_HPE menuconfig group and ARCH_HPE_GSC config for the
HPE GSC ARM64 BMC SoC.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
arch/arm64/Kconfig.platforms | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 54eb1d7fd419..4bbc27bb9b7b 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -168,6 +168,29 @@ config ARCH_HISI
help
This enables support for Hisilicon ARMv8 SoC family
+
+menuconfig ARCH_HPE
+ bool "HPE SoC Support"
+ help
+ This enables support for HPE ARM-based SoC chips used
+ on HPE servers. HPE SoCs serve as the Baseboard
+ Management Controller (BMC) providing out-of-band server
+ management.
+
+if ARCH_HPE
+
+config ARCH_HPE_GSC
+ bool "HPE GSC SoC"
+ select PINCTRL
+ select GENERIC_IRQ_CHIP
+ select CLKSRC_MMIO
+ help
+ Support for the HPE GSC ARM64 BMC SoC used on HPE servers.
+ The GSC provides hardware management, power control, remote
+ access, and server health monitoring capabilities for HPE
+ Gen12 and later server platforms.
+
+endif
config ARCH_KEEMBAY
bool "Keem Bay SoC"
help
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v5 07/17] spi: orion: Simplify clock handling with devm_clk_get_enabled()
From: Mark Brown @ 2026-03-23 19:42 UTC (permalink / raw)
To: Pei Xiao
Cc: linux-spi, linux-arm-kernel, linux-kernel, imx, openbmc,
linux-rockchip, linux-riscv, linux-mediatek, linux-stm32,
Frank.Li, amelie.delaunay
In-Reply-To: <387f2fa1b3e1a356c524bb36eab07e1b431b6382.1773885292.git.xiaopei01@kylinos.cn>
[-- Attachment #1: Type: text/plain, Size: 360 bytes --]
On Thu, Mar 19, 2026 at 10:04:03AM +0800, Pei Xiao wrote:
> Replace devm_clk_get() followed by clk_prepare_enable() with
> devm_clk_get_enabled() for the "axi" clock. This reduces
> boilerplate code and error handling, as the managed API automatically
> disables the clock when the device is removed or if probe fails.
Another runtime PM clock managment one.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v5 05/17] spi: imx: Simplify clock handling with devm_clk_get_enabled()
From: Mark Brown @ 2026-03-23 19:41 UTC (permalink / raw)
To: Pei Xiao
Cc: linux-spi, linux-arm-kernel, linux-kernel, imx, openbmc,
linux-rockchip, linux-riscv, linux-mediatek, linux-stm32,
Frank.Li, amelie.delaunay
In-Reply-To: <9d0fa929a4158e7f4e9adec21dd351e6cdd2984d.1773885292.git.xiaopei01@kylinos.cn>
[-- Attachment #1: Type: text/plain, Size: 364 bytes --]
On Thu, Mar 19, 2026 at 10:04:01AM +0800, Pei Xiao wrote:
> Replace devm_clk_get() followed by clk_prepare_enable() with
> devm_clk_get_enabled() for both "ipg" and "per" clocks. This reduces
> boilerplate code and error handling, as the managed API automatically
> disables the clocks when the device is removed or if probe fails.
This one also uses runtime PM.
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^ permalink raw reply
* Re: [PATCH v5 04/17] spi: img-spfi: Simplify clock handling with devm_clk_get_enabled()
From: Mark Brown @ 2026-03-23 19:40 UTC (permalink / raw)
To: Pei Xiao
Cc: linux-spi, linux-arm-kernel, linux-kernel, imx, openbmc,
linux-rockchip, linux-riscv, linux-mediatek, linux-stm32,
Frank.Li, amelie.delaunay
In-Reply-To: <c6a5cf59294d754389dfdd8837b596c52976e198.1773885292.git.xiaopei01@kylinos.cn>
[-- Attachment #1: Type: text/plain, Size: 390 bytes --]
On Thu, Mar 19, 2026 at 10:04:00AM +0800, Pei Xiao wrote:
> Replace devm_clk_get() followed by clk_prepare_enable() with
> devm_clk_get_enabled() for both "sys" and "spfi" clocks. This reduces
> boilerplate code and error handling, as the managed API automatically
> disables the clocks when the device is removed or if probe fails.
This is another driver using runtime PM for the clocks.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v3 2/9] dt-bindings: mmc: amlogic: Add compatible for T7 mmc
From: Conor Dooley @ 2026-03-23 19:38 UTC (permalink / raw)
To: Ronald Claveau
Cc: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Johannes Berg, van Spriel, linux-arm-kernel, linux-amlogic,
devicetree, linux-kernel, linux-mmc, linux-wireless
In-Reply-To: <20260323-add-emmc-t7-vim4-v3-2-5159d90a984c@aliel.fr>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v5 01/17] spi: axiado: Simplify clock management with devm_clk_get_enabled()
From: Mark Brown @ 2026-03-23 19:38 UTC (permalink / raw)
To: Pei Xiao
Cc: linux-spi, linux-arm-kernel, linux-kernel, imx, openbmc,
linux-rockchip, linux-riscv, linux-mediatek, linux-stm32,
Frank.Li, amelie.delaunay
In-Reply-To: <52f7e0ebd2f0ece71929384444e1ae87506e5e2d.1773885292.git.xiaopei01@kylinos.cn>
[-- Attachment #1: Type: text/plain, Size: 448 bytes --]
On Thu, Mar 19, 2026 at 10:03:57AM +0800, Pei Xiao wrote:
> Replace devm_clk_get() followed by clk_prepare_enable() with
> devm_clk_get_enabled() for both the "pclk" and "ref" clocks. This
> reduces boilerplate code and error handling, as the managed API
> automatically disables the clocks when the device is removed or if
> probe fails.
This driver is doing runtime management of the clocks via runtime
suspend/resume so this isn't appropriate.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v3 8/9] dt-bindings: net: wireless: brcm: Add compatible for bcm43752
From: Conor Dooley @ 2026-03-23 19:37 UTC (permalink / raw)
To: Ronald Claveau
Cc: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Johannes Berg, van Spriel, linux-arm-kernel, linux-amlogic,
devicetree, linux-kernel, linux-mmc, linux-wireless
In-Reply-To: <20260323-add-emmc-t7-vim4-v3-8-5159d90a984c@aliel.fr>
[-- Attachment #1: Type: text/plain, Size: 250 bytes --]
On Mon, Mar 23, 2026 at 10:55:33AM +0100, Ronald Claveau wrote:
> Add bcm43752 compatible with its bcm4329 compatible fallback.
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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^ permalink raw reply
* Re: [PATCH v3 2/6] dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support
From: Conor Dooley @ 2026-03-23 19:35 UTC (permalink / raw)
To: Ciprian Costea
Cc: Marc Kleine-Budde, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Fabio Estevam, Pengutronix Kernel Team, linux-can, devicetree,
linux-kernel, imx, linux-arm-kernel, NXP S32 Linux Team,
Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Eric Chanudet,
Andra-Teodora Ilie, Larisa Grigore
In-Reply-To: <20260323135827.2129371-3-ciprianmarian.costea@oss.nxp.com>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v2 1/2] media: dt-bindings: rockchip,rk3568-mipi-csi2: add rk3588 compatible
From: Rob Herring (Arm) @ 2026-03-23 19:35 UTC (permalink / raw)
To: Michael Riesch
Cc: Mauro Carvalho Chehab, Conor Dooley, linux-media,
linux-arm-kernel, linux-kernel, devicetree, Laurent Pinchart,
Kever Yang, linux-rockchip, Sakari Ailus, Collabora Kernel Team,
Heiko Stuebner, Krzysztof Kozlowski, Frank Li
In-Reply-To: <20260305-rk3588-csi2rx-v2-1-79d01b615486@collabora.com>
On Fri, 13 Mar 2026 12:08:45 +0100, Michael Riesch wrote:
> The RK3588 MIPI CSI-2 receivers are compatible to the ones found in
> the RK3568.
> Introduce a list of compatible variants and add the RK3588 variant to
> it.
>
> Signed-off-by: Michael Riesch <michael.riesch@collabora.com>
> ---
> .../devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: remoteproc: imx-rproc: Support i.MX94
From: Rob Herring (Arm) @ 2026-03-23 19:16 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Conor Dooley, linux-arm-kernel, Fabio Estevam, Bjorn Andersson,
Krzysztof Kozlowski, Pengutronix Kernel Team, linux-remoteproc,
Peng Fan, imx, linux-kernel, Sascha Hauer, Mathieu Poirier,
devicetree, Frank Li
In-Reply-To: <20260312-imx943-rproc-v1-2-3e66596592a8@nxp.com>
On Thu, 12 Mar 2026 20:36:57 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add compatible string for:
> Cortex-M7 core[0,1] in i.MX94
> Cortex-M33 Sync core in i.MX94
>
> To i.MX94, Cortex-M7 core0 and core1 have different memory view from
> Cortex-A55 core, so different compatible string is used.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: remoteproc: imx-rproc: Introduce fsl,reset-vector-mask
From: Rob Herring @ 2026-03-23 19:15 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Bjorn Andersson, Mathieu Poirier, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, linux-remoteproc, devicetree, imx,
linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20260312-imx943-rproc-v1-1-3e66596592a8@nxp.com>
On Thu, Mar 12, 2026 at 08:36:56PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Cortex-M[7,33] processors use a fixed reset vector table format:
>
> 0x00 Initial SP value
> 0x04 Reset vector
> 0x08 NMI
> 0x0C ...
> ...
> IRQ[n]
>
> In ELF images, the corresponding layout is:
>
> reset_vectors: --> hardware reset address
> .word __stack_end__
> .word Reset_Handler
> .word NMI_Handler
> .word HardFault_Handler
> ...
> .word UART_IRQHandler
> .word SPI_IRQHandler
> ...
>
> Reset_Handler: --> ELF entry point address
> ...
>
> The hardware fetches the first two words from reset_vectors and populates
> SP with __stack_end__ and PC with Reset_Handler. Execution proceeds from
> Reset_Handler.
>
> However, the ELF entry point does not always match the hardware reset
> address. For example, on i.MX94 CM33S:
>
> ELF entry point: 0x0ffc211d
> CM33S hardware reset base: 0x0ffc0000
>
> To derive the correct hardware reset address, the unused lower bits must
> be masked off. The boot code should apply a SoC‑specific mask before
> programming the reset address registers, e.g.:
>
> reset_address = entry & reset-vector-mask
>
> This reset address derivation method is also applicable to i.MX8M
> Cortex-M7/4 cores.
>
> Introduces the optional DT property `fsl,reset-vector-mask` to specify the
> mask used for deriving the hardware reset address from
> the ELF entry point.
Why can't you fix the ELF image to have the right address?
Or just imply the reset address from the compatible? It's fixed per SoC,
right?
Rob
^ permalink raw reply
* Re: [PATCH 0/6] media: synopsys: Add imx93 support
From: Frank Li @ 2026-03-23 19:10 UTC (permalink / raw)
To: Michael Riesch, Mauro Carvalho Chehab, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus
Cc: linux-media, linux-kernel, devicetree, linux-arm-kernel,
linux-rockchip, Guoniu Zhou, Laurent Pinchart, imx
In-Reply-To: <20260210-imx93-dw-csi2-v1-0-69667bb86bfa@nxp.com>
On Tue, Feb 10, 2026 at 12:11:07PM -0500, Frank Li wrote:
> This 3rd time try to support DW CSI2RX support for imx93.
>
Laurent Pinchart and Sakari Ailus:
I am not who will take care this patch?
original drivers/media/platform/synopsys/dw-mipi-csi2rx.c picked
by Sakari Ailus
Frank
> 1st: Create new dw csi2 driver
> https://lore.kernel.org/all/20250701-95_cam-v1-5-c5172bab387b@nxp.com/
>
> 2nd: Based on legacy imx6's DW CSI2 constroller.
> https://lore.kernel.org/imx/20250821-95_cam-v3-0-c9286fbb34b9@nxp.com/
>
> Now rockchip create a common DW CSI2RX driver at
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c
>
> This time base on rockchip's implement.
>
> i.MX93's version is newer than rockchip one. i.MX6's is more similar with
> rockchips.
>
> But i.MX6 is too old. So start at i.MX93 firstly even it has bigger
> difference.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Frank Li (6):
> media: synopsys: use devm_reset_control_get_optional_exclusive()
> media: synopsys: only check errors from devm_clk_bulk_get_all()
> media: synopsys: implement .get_frame_desc() callback
> media: synopsys: use struct dw_mipi_csi2rx_regs to describe register offsets
> media: dt-bindings: add NXP i.MX93 compatible string
> media: synopsys: add i.MX93 support
>
> .../bindings/media/rockchip,rk3568-mipi-csi2.yaml | 47 +++-
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 280 ++++++++++++++++++---
> 2 files changed, 293 insertions(+), 34 deletions(-)
> ---
> base-commit: ada3fa02f7a95623b724dfe300fce6f49cc2d75a
> change-id: 20260128-imx93-dw-csi2-b472ddcb176a
>
> Best regards,
> --
> Frank Li <Frank.Li@nxp.com>
>
^ permalink raw reply
* Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: aspeed: Add AST2700-A2 support
From: Rob Herring @ 2026-03-23 19:07 UTC (permalink / raw)
To: Ryan Chen
Cc: Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Thomas Gleixner, linux-kernel, devicetree, linux-arm-kernel,
linux-aspeed, linux-riscv
In-Reply-To: <20260306-irqchip-v2-1-f8512c09be63@aspeedtech.com>
On Fri, Mar 06, 2026 at 04:07:23PM +0800, Ryan Chen wrote:
> Introduce a new binding describing the AST2700 interrupt controller
> architecture implemented in the A2 production silicon.
>
> The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
> prior to mass production. The interrupt architecture was substantially
> reworked after the A0 revision for A1, and the A1 design is retained
> unchanged in the A2 production silicon.
>
> The existing AST2700 interrupt controller binding was written against
> the pre-production A0 design. That binding does not accurately describe
> the interrupt hierarchy and routing model present in A1/A2, where
> interrupts can be routed to multiple processor-local interrupt
> controllers (Primary Service Processor (PSP) GIC, Secondary Service
> Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU
> APLIC) depending on the execution context.
Unless you intend to maintain both bindings for some period, then you
should just squash the removal here. If both are going to be maintained
then patch 5 should not be applied yet.
>
> Hardware connectivity between interrupt controllers is expressed using
> the aspeed,interrupt-ranges property.
>
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
>
> ---
> Changes in v2:
> - Describe AST2700 A0/A1/A2 design evolution.
> - Drop the redundant '-ic' suffix from compatible strings.
> - Expand commit message to match the series cover letter context.
> - fix ascii diagram
> - remove intc0 label
> - remove spaces before >
> - drop intc1 example
> ---
> .../aspeed,ast2700-interrupt.yaml | 189 +++++++++++++++++++++
> 1 file changed, 189 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml
> new file mode 100644
> index 000000000000..13398ff8be12
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml
> @@ -0,0 +1,189 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1)
> +
> +description: |
> + The ASPEED AST2700 SoC integrates two interrupt controller designs:
> +
> + - INTC0: Primary controller that routes interrupt sources to upstream,
> + processor-specific interrupt controllers
> +
> + - INTC1: Secondary controller whose interrupt outputs feed into
> + INTC0
Wrap lines at 80 char.
> +
> + The SoC contains four processors to which interrupts can be routed:
> +
> + - PSP: Primary Service Processor (Cortex-A35)
> + - SSP: Secondary Service Processor (Cortex-M4)
> + - TSP: Tertiary Sevice Processor (Cortex-M4)
> + - BMCU: Boot MCU (a RISC-V microcontroller)
> +
> + The following diagram illustrates the overall architecture of the
> + ASPEED AST2700 interrupt controllers:
> +
> + +-----------+ +-----------+
> + | INTC0 | | INTC1(0) |
> + +-----------+ +-----------+
> + | Router | +-----------+ | Router |
> + | out int | +Peripheral + | out int |
> + +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+
> + |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral +
> + +-----------+ | . . | | . . | +Controllers+
> + +-----------+ | . . | | . . | +-----------+
> + |SSP NVIC <-|---+ . . <----------------+ . . |
> + +-----------+ | . . | | . . |
> + +-----------+ | . . <-------- | . . |
> + |TSP NVIC <-|---+ . . | | ----+ . . |
> + +-----------+ | . . | | | | O P |
> + | . . | | | +-----------+
> + | . . <---- | --------------------
> + | . . | | | +-----------+ |
> + | M N | | ---------+ INTC1(1) | |
> + +-----------+ | +-----------+ |
> + | . |
> + | +-----------+ |
> + -------------+ INTC1(N) | |
> + +-----------+ |
> + +--------------+ |
> + + BMCU APLIC <-+---------------------------------------------
> + +--------------+
> +
> + INTC0 supports:
> + - 128 local peripheral interrupt inputs
> + - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM)
> + - Local peripheral interrupt outputs
> + - Merged interrupt outputs
> + - Software interrupt outputs (SWINT)
> + - Configurable interrupt routes targeting the PSP, SSP, and TSP
> +
> + INTC1 supports:
> + - 192 local peripheral interrupt inputs
> + - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank)
> + - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU
> +
> + One INTC1 instance is always present, on the SoC's IO die. A further two
> + instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS
> + Tunneling Protocol & Interface).
> +
> + Interrupt numbering model
> + -------------------------
> + The binding uses a controller-local numbering model. Peripheral device
> + nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or
> + 'interrupts-extended' properties.
> +
> + For AST2700, INTC0 exposes the following (inclusive) input ranges:
> +
> + - 000..479: Independent interrupts
> + - 480..489: INTM0-INTM9
> + - 490..499: INTM10-INTM19
> + - 500..509: INTM20-INTM29
> + - 510..519: INTM30-INTM39
> + - 520..529: INTM40-INTM49
> +
> + INTC0's (inclusive) output ranges are as follows:
> +
> + - 000..127: 1:1 local peripheral interrupt output to PSP
> + - 144..151: Software interrupts from the SSP output to PSP
> + - 152..159: Software interrupts from the TSP output to PSP
> + - 192..201: INTM0-INTM9 banked outputs to PSP
> + - 208..217: INTM30-INTM39 banked outputs to PSP
> + - 224..233: INTM40-INTM49 banked outputs to PSP
> + - 256..383: 1:1 local peripheral interrupt output to SSP
> + - 384..393: INTM10-INTM19 banked outputs to SSP
> + - 400..407: Software interrupts from the PSP output to SSP
> + - 408..415: Software interrupts from the TSP output to SSP
> + - 426..553: 1:1 local peripheral interrupt output to TSP
> + - 554..563: INTM20-INTM29 banked outputs to TSP
> + - 570..577: Software interrupts from the PSP output to TSP
> + - 578..585: Software interrupts from the SSP output to TSP
> +
> + Inputs and outputs for INTC1 instances are context-dependent. However, for the
> + first instance of INTC1, the (inclusive) output ranges are:
> +
> + - 00..05: INTM0-INTM5
> + - 10..15: INTM10-INTM15
> + - 20..25: INTM20-INTM25
> + - 30..35: INTM30-INTM35
> + - 40..45: INTM40-INTM45
> + - 50..50: BootMCU
> +
> +maintainers:
> + - ryan_chen@aspeedtech.com
> + - andrew@codeconstruct.com.au
Name and email address please.
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2700-intc0
> + - aspeed,ast2700-intc1
> +
> + reg:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 1
> + description: Single cell encoding the INTC local interrupt number (hwirq).
> +
> + aspeed,interrupt-ranges:
> + description: |
> + Describes how ranges of controller output pins are routed to a parent
> + interrupt controller.
> +
> + Each range entry is encoded as:
> +
> + <out count phandle parent-specifier...>
> +
> + where:
> + - out: First controller interrupt output index in the range.
> + - count: Number of consecutive controller interrupt outputs and parent
> + interrupt inputs in this range.
> + - phandle: Phandle to the parent interrupt controller node.
> + - parent-specifier: Interrupt specifier, as defined by the parent
> + interrupt controller binding.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 3
> + items:
> + description: Range descriptors with a parent interrupt specifier.
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-controller
> + - '#interrupt-cells'
> + - aspeed,interrupt-ranges
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + interrupt-controller@12100000 {
> + compatible = "aspeed,ast2700-intc0";
> + reg = <0x12100000 0x3b00>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + aspeed,interrupt-ranges =
> + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
> + <256 128 &ssp_nvic 0 0>,
> + <384 10 &ssp_nvic 160 0>,
> + <400 8 &ssp_nvic 144 0>,
> + <408 8 &ssp_nvic 152 0>,
> + <426 128 &tsp_nvic 0 0>,
> + <554 10 &tsp_nvic 160 0>,
> + <570 8 &tsp_nvic 144 0>,
> + <578 8 &tsp_nvic 152 0>;
> + };
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v6] mmc: sdhci-esdhc-imx: remove redundant mx25 handling and consolidate soc data
From: Frank Li @ 2026-03-23 19:04 UTC (permalink / raw)
To: Adrián García Casado
Cc: Ulf Hansson, Haibo Chen, Sascha Hauer, linux-mmc, imx,
linux-arm-kernel, linux-kernel, Miguel Ojeda
In-Reply-To: <20260319173832.15543-1-adriangarciacasado42@gmail.com>
On Thu, Mar 19, 2026 at 06:38:32PM +0100, Adrián García Casado wrote:
> Remove the is_imx25_esdhc check and redundant mx25-specific handling as it's no longer necessary since the new_soc initialization. Consolidate the drive data structs for imx25/35.
wrap commit message at 75 column.
Frank
>
> Signed-off-by: Adrián García Casado <adriangarciacasado42@gmail.com>
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 21 +++++----------------
> 1 file changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a7a5df673b0f6..3dc43f1e517aa 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -256,11 +256,7 @@ struct esdhc_soc_data {
> u32 quirks;
> };
>
> -static const struct esdhc_soc_data esdhc_imx25_data = {
> - .flags = ESDHC_FLAG_ERR004536,
> -};
> -
> -static const struct esdhc_soc_data esdhc_imx35_data = {
> +static const struct esdhc_soc_data esdhc_imx25_35_data = {
> .flags = ESDHC_FLAG_ERR004536,
> };
>
> @@ -391,8 +387,8 @@ struct pltfm_imx_data {
> };
>
> static const struct of_device_id imx_esdhc_dt_ids[] = {
> - { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
> - { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
> + { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_35_data, },
> + { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx25_35_data, },
> { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
> { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
> { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
> @@ -412,10 +408,6 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
> };
> MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
>
> -static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
> -{
> - return data->socdata == &esdhc_imx25_data;
> -}
>
> static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
> {
> @@ -873,11 +865,8 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
> new_val = val & SDHCI_CTRL_LED;
> /* ensure the endianness */
> new_val |= ESDHC_HOST_CONTROL_LE;
> - /* bits 8&9 are reserved on mx25 */
> - if (!is_imx25_esdhc(imx_data)) {
> - /* DMA mode bits are shifted */
> - new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
> - }
> + /* DMA mode bits are shifted */
> + new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
>
> /*
> * Do not touch buswidth bits here. This is done in
>
> base-commit: f338e77383789c0cae23ca3d48adcc5e9e137e3c
> prerequisite-patch-id: bf56dcdce62cb97741b7aa11b04c7a9648fb2d6a
> prerequisite-patch-id: bb57e0fd9cad8c81bcf7a6389f3cb294bbe1eb52
> --
> 2.47.3
>
^ permalink raw reply
* [GIT PULL 1/2] Broadcom devicetree changes for 7.1
From: Florian Fainelli @ 2026-03-23 19:02 UTC (permalink / raw)
To: soc
Cc: Rosen Penev, Florian Fainelli, Rob Herring, Linus Walleij,
Linus Walleij, William Zhang, Miquel Raynal,
Rafał Miłecki, linux-arm-kernel, arnd, khilman,
bcm-kernel-feedback-list
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://github.com/Broadcom/stblinux.git tags/arm-soc/for-7.1/devicetree
for you to fetch changes up to 220bdfcb4b4788f57faa2c28454d8b2dd3bcab6c:
ARM: dts: BCM5301X: EA9200: specify partitions (2026-03-20 16:57:31 -0700)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 7.1, please pull the following:
- Rafal provides a complete description of the PCIe Root Complex nodes
in order to silence a number of dtc warnings
- Rosen provides the necessary NVMEM properties to allow describing the
WAN device MAC address from NVRAM, also adds better LEDs, USB GPIOs
and Wi-Fi buttons for the Linksys EA9200 router
- Linus completes the BCA devices description by adding the I2C block
and fixing interrupts for the DMA block on 63138 and 6878
----------------------------------------------------------------
Linus Walleij (7):
ARM: dts: bcm6878: Fix PL081 DMA block IRQ
ARM: dts: bcm63138: Fix DMA IRQ
ARM: dts: bcm6846: Add I2C bus block
ARM: dts: bcm6855: Add I2C bus blocks
ARM: dts: bcm6878: Add I2C bus block
ARM: dts: bcm63138: Add I2C block
ARM: dts: bcm63148: Add I2C block
Miquel Raynal (1):
ARM: dts: BCM5301X: Drop extra NAND controller compatible
Rafał Miłecki (1):
ARM: dts: BCM5301X: Describe PCIe controllers fully
Rob Herring (Arm) (1):
ARM: dts: broadcom: bcm2835-rpi: Move non simple-bus nodes to root level
Rosen Penev (9):
ARM: dts: BCM5301X: add root pcie bridges
ARM: dts: BCM5301X: EA9200: set WAN MAC from nvram
ARM: dts: BCM5301X: panamera: set WAN MAC from nvram
ARM: dts: BCM5301X: AC3100: set WAN MAC from nvram
ARM: dts: BCM5301X: AC5300: set WAN MAC from nvram
ARM: dts: BCM5301X: EA9200: add WiFi button
ARM: dts: BCM5301X: EA9200: add USB GPIOs
ARM: dts: BCM5301X: EA9200: add LEDs
ARM: dts: BCM5301X: EA9200: specify partitions
arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 58 +++++++++++-
arch/arm/boot/dts/broadcom/bcm2835-common.dtsi | 7 +-
arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 16 ++--
.../boot/dts/broadcom/bcm4709-linksys-ea9200.dts | 100 +++++++++++++++++++++
.../boot/dts/broadcom/bcm4709-netgear-r8000.dts | 73 +++++++--------
.../boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi | 7 ++
.../boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts | 3 +
.../dts/broadcom/bcm47094-linksys-panamera.dts | 7 ++
.../boot/dts/broadcom/bcm47094-luxul-xap-1610.dts | 36 ++------
.../dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts | 36 ++------
arch/arm/boot/dts/broadcom/bcm63138.dtsi | 11 ++-
arch/arm/boot/dts/broadcom/bcm63148.dtsi | 11 ++-
arch/arm/boot/dts/broadcom/bcm6846.dtsi | 9 ++
arch/arm/boot/dts/broadcom/bcm6855.dtsi | 18 ++++
arch/arm/boot/dts/broadcom/bcm6878.dtsi | 11 ++-
15 files changed, 289 insertions(+), 114 deletions(-)
^ permalink raw reply
* [GIT PULL 2/2] Broadcom devicetree-arm64 changes for 7.1
From: Florian Fainelli @ 2026-03-23 19:02 UTC (permalink / raw)
To: soc
Cc: Rob Herring, Florian Fainelli, Gregor Herburger, Maíra Canal,
Stefan Wahren, linux-arm-kernel, arnd, khilman,
bcm-kernel-feedback-list
In-Reply-To: <20260323190239.1890505-1-florian.fainelli@broadcom.com>
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://github.com/Broadcom/stblinux.git tags/arm-soc/for-7.1/devicetree-arm64
for you to fetch changes up to 0acb1de2b4df426a62dba33bcd80f3939636f97b:
arm64: dts: broadcom: bcm2712: Move non simple-bus nodes to root level (2026-03-20 10:17:30 -0700)
----------------------------------------------------------------
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 7.1, please pull the following:
- Maira adds the V3D DT node to the 2712 (Raspberry Pi 5) SoC
- Gergor adds the I2C controller, CSI (camera), ISP (image signal
processor), fixes the pinctrl node and updates the UART10 interrupt
for the RP1 sister chip to the 2712 (Raspberry Pi 5)
- Rob moves the firmware and GPU to the root level to fix DTC warnings
----------------------------------------------------------------
Gregor Herburger (6):
arm64: dts: broadcom: rp1: add i2c controller
arm64: dts: broadcom: rp1: add csi nodes
arm64: dts: broadcom: bcm2712: add camera backend node pispbe
arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs
arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon
arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt
Maíra Canal (1):
arm64: dts: broadcom: bcm2712: Add V3D device node
Rob Herring (Arm) (1):
arm64: dts: broadcom: bcm2712: Move non simple-bus nodes to root level
arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts | 14 +++
.../boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi | 55 +++++------
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 24 +++++
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 29 +++++-
arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 105 +++++++++++++++++++++
5 files changed, 196 insertions(+), 31 deletions(-)
^ permalink raw reply
* [PATCH v6 5/7] firmware: arm_scmi: Allow PINCTRL_REQUEST to return EOPNOTSUPP
From: Dan Carpenter @ 2026-03-23 19:01 UTC (permalink / raw)
To: Sudeep Holla, AKASHI Takahiro
Cc: Cristian Marussi, arm-scmi, linux-arm-kernel, linux-kernel,
Andy Shevchenko, Linus Walleij, Bartosz Golaszewski, linux-gpio,
Vincent Guittot, Khaled Ali Ahmed, Michal Simek
In-Reply-To: <cover.1774283146.git.dan.carpenter@linaro.org>
The SCMI protocol specification says that the PINCTRL_REQUEST and
PINCTRL_RELEASE commands are optional. So if the SCMI server returns
-EOPNOTSUPP, then treat that as success and continue.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Sudeep Holla <sudeep.holla@kernel.org>
---
v5: fix subsytem prefix
v4: add r-b tags
v3: new patch
drivers/firmware/arm_scmi/pinctrl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/firmware/arm_scmi/pinctrl.c b/drivers/firmware/arm_scmi/pinctrl.c
index a020e23d7c49..42cb1aef1fe1 100644
--- a/drivers/firmware/arm_scmi/pinctrl.c
+++ b/drivers/firmware/arm_scmi/pinctrl.c
@@ -578,6 +578,8 @@ static int scmi_pinctrl_request_free(const struct scmi_protocol_handle *ph,
tx->flags = cpu_to_le32(type);
ret = ph->xops->do_xfer(ph, t);
+ if (ret == -EOPNOTSUPP)
+ ret = 0;
ph->xops->xfer_put(ph, t);
return ret;
--
2.53.0
^ permalink raw reply related
* [PATCH v6 3/7] pinctrl: scmi: Delete PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS support
From: Dan Carpenter @ 2026-03-23 19:01 UTC (permalink / raw)
To: Sudeep Holla, AKASHI Takahiro
Cc: Cristian Marussi, Linus Walleij, arm-scmi, linux-arm-kernel,
linux-gpio, linux-kernel, Andy Shevchenko, Bartosz Golaszewski,
Vincent Guittot, Khaled Ali Ahmed, Michal Simek, Peng Fan
In-Reply-To: <cover.1774283146.git.dan.carpenter@linaro.org>
The argument for PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS is supposed to
be expressed in terms of ohms. But the pinctrl-scmi driver was
implementing it the same as PIN_CONFIG_OUTPUT and writing either a
zero or one to the pin.
The SCMI protocol doesn't have an support configuration type so just
delete this code instead of replacing it.
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
v5: fix subystem prefix
v4: add r-b tags
v3: new patch
drivers/pinctrl/pinctrl-scmi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c
index 5d347e6b2e4c..de8c113bc61d 100644
--- a/drivers/pinctrl/pinctrl-scmi.c
+++ b/drivers/pinctrl/pinctrl-scmi.c
@@ -254,9 +254,6 @@ static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param,
case PIN_CONFIG_OUTPUT_ENABLE:
*type = SCMI_PIN_OUTPUT_MODE;
break;
- case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
- *type = SCMI_PIN_OUTPUT_VALUE;
- break;
case PIN_CONFIG_POWER_SOURCE:
*type = SCMI_PIN_POWER_SOURCE;
break;
--
2.53.0
^ permalink raw reply related
* [PATCH v6 4/7] pinctrl: scmi: ignore PIN_CONFIG_PERSIST_STATE
From: Dan Carpenter @ 2026-03-23 19:01 UTC (permalink / raw)
To: Sudeep Holla, AKASHI Takahiro
Cc: Cristian Marussi, Linus Walleij, arm-scmi, linux-arm-kernel,
linux-gpio, linux-kernel, Andy Shevchenko, Bartosz Golaszewski,
Vincent Guittot, Khaled Ali Ahmed, Michal Simek
In-Reply-To: <cover.1774283146.git.dan.carpenter@linaro.org>
The PIN_CONFIG_PERSIST_STATE setting ensures that the pin state persists
across a sleep or controller reset. The SCMI spec does not have an
equivalent command to this so just ignore it.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
---
v5: fix subsystem prefix
v4: Add r-b tags
v3: No change
drivers/pinctrl/pinctrl-scmi.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c
index de8c113bc61d..f22be6b7b82a 100644
--- a/drivers/pinctrl/pinctrl-scmi.c
+++ b/drivers/pinctrl/pinctrl-scmi.c
@@ -361,7 +361,7 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev,
unsigned long *configs,
unsigned int num_configs)
{
- int i, ret;
+ int i, cnt, ret;
struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
u32 config_value[SCMI_NUM_CONFIGS];
@@ -377,17 +377,21 @@ static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev,
if (ret)
return ret;
+ cnt = 0;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
- ret = pinctrl_scmi_map_pinconf_type_set(param, &p_config_type[i]);
+ if (param == PIN_CONFIG_PERSIST_STATE)
+ continue;
+ ret = pinctrl_scmi_map_pinconf_type_set(param, &p_config_type[cnt]);
if (ret) {
dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
goto free_config;
}
- p_config_value[i] = pinconf_to_config_argument(configs[i]);
+ p_config_value[cnt] = pinconf_to_config_argument(configs[i]);
+ cnt++;
}
- ret = pinctrl_ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
+ ret = pinctrl_ops->settings_conf(pmx->ph, pin, PIN_TYPE, cnt,
p_config_type, p_config_value);
if (ret)
dev_err(pmx->dev, "Error parsing config %d\n", ret);
--
2.53.0
^ permalink raw reply related
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