* Re: [PATCH v6 39/40] arm_mpam: Quirk CMN-650's CSU NRDY behaviour
From: Gavin Shan @ 2026-03-24 4:21 UTC (permalink / raw)
To: Ben Horgan
Cc: amitsinght, baisheng.gao, baolin.wang, carl, dave.martin, david,
dfustini, fenghuay, james.morse, jonathan.cameron, kobak,
lcherian, linux-arm-kernel, linux-kernel, peternewman,
punit.agrawal, quic_jiles, reinette.chatre, rohit.mathew, scott,
sdonthineni, tan.shaopeng, xhao, catalin.marinas, will, corbet,
maz, oupton, joey.gouly, suzuki.poulose, kvmarm, zengheng4,
linux-doc
In-Reply-To: <20260313144617.3420416-40-ben.horgan@arm.com>
On 3/14/26 12:46 AM, Ben Horgan wrote:
> From: James Morse <james.morse@arm.com>
>
> CMN-650 is afflicted with an erratum where the CSU NRDY bit never clears.
> This tells us the monitor never finishes scanning the cache. The erratum
> document says to wait the maximum time, then ignore the field.
>
> Add a flag to indicate whether this is the final attempt to read the
> counter, and when this quirk is applied, ignore the NRDY field.
>
> This means accesses to this counter will always retry, even if the counter
> was previously programmed to the same values.
>
> The counter value is not expected to be stable, it drifts up and down with
> each allocation and eviction. The CSU register provides the value for a
> point in time.
>
> Reviewed-by: Zeng Heng <zengheng4@huawei.com>
> Signed-off-by: James Morse <james.morse@arm.com>
> Signed-off-by: Ben Horgan <ben.horgan@arm.com>
> ---
> Changes since v3:
> parentheses in macro
> ---
> Documentation/arch/arm64/silicon-errata.rst | 3 +++
> drivers/resctrl/mpam_devices.c | 12 ++++++++++++
> drivers/resctrl/mpam_internal.h | 6 ++++++
> 3 files changed, 21 insertions(+)
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply
* Re: [PATCH v5 phy-next 10/27] scsi: ufs: qcom: keep parallel track of PHY power state
From: Manivannan Sadhasivam @ 2026-03-24 5:30 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, James E.J. Bottomley, Martin K. Petersen,
Nitin Rawat
In-Reply-To: <20260319223241.1351137-11-vladimir.oltean@nxp.com>
On Fri, Mar 20, 2026 at 12:32:24AM +0200, Vladimir Oltean wrote:
> As explained in the similar ufs-exynos.c change, PHY consumer drivers
> should not look at the phy->power_count, because in the general case
> there might also be other consumers who have called phy_power_on() too,
> so the fact that the power_count is non-zero does not mean that we did.
>
> Moreover, struct phy will become opaque soon, so the qcom UFS driver
> will not be able to apply this pattern. Keep parallel track of the PHY
> power state, instead of looking at a field which will become unavailable
> (phy->power_count).
>
> About treating the phy_power_off() return code: from an API perspective,
> this should have probably returned void, otherwise consumers would be
> stuck in a state they can't escape. The provider, phy-qcom-qmp-ufs.c,
> does return 0 in its power_off() implementation. I consider it safe to
> discard potential errors from phy_power_off() instead of complicating
> the phy_powered_on logic.
>
You could even simplify the code by getting rid of the 'phy_powered_on' check
altogether. There is no real need to track the PHY power state in this driver.
It is safe to call phy_power_off() without any checks.
- Mani
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
> Cc: Nitin Rawat <quic_nitirawa@quicinc.com>
>
> v4->v5: patch is new
> ---
> drivers/ufs/host/ufs-qcom.c | 9 +++++++--
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 375fd24ba458..3b8bd9968235 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -508,9 +508,10 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> if (ret)
> return ret;
>
> - if (phy->power_count)
> + if (host->phy_powered_on) {
> phy_power_off(phy);
> -
> + host->phy_powered_on = false;
> + }
>
> /* phy initialization - calibrate the phy */
> ret = phy_init(phy);
> @@ -531,6 +532,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> __func__, ret);
> goto out_disable_phy;
> }
> + host->phy_powered_on = true;
>
> ret = phy_calibrate(phy);
> if (ret) {
> @@ -1268,6 +1270,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
> return err;
> }
> + host->phy_powered_on = false;
> }
> break;
> case POST_CHANGE:
> @@ -1277,6 +1280,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
> dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
> return err;
> }
> + host->phy_powered_on = true;
>
> /* enable the device ref clock for HS mode*/
> if (ufshcd_is_hs_mode(&hba->pwr_info))
> @@ -1467,6 +1471,7 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
>
> ufs_qcom_disable_lane_clks(host);
> phy_power_off(host->generic_phy);
> + host->phy_powered_on = false;
> phy_exit(host->generic_phy);
> }
>
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 1111ab34da01..72ce0687fa42 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -282,6 +282,7 @@ struct ufs_qcom_host {
> struct clk_bulk_data *clks;
> u32 num_clks;
> bool is_lane_clks_enabled;
> + bool phy_powered_on;
>
> struct icc_path *icc_ddr;
> struct icc_path *icc_cpu;
> --
> 2.43.0
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* [PATCH RESEND 0/2] regulator: mt6315: add regulator supplies
From: Chen-Yu Tsai @ 2026-03-24 5:30 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-arm-kernel, linux-mediatek, devicetree
(Resent with correct subject on cover letter)
Hi,
This series is part of a broader collection of regulator related
cleanups for MediaTek Chromebooks. This one covers the MT6315 PMIC.
Patch 1 adds the names of the power supply inputs to the binding.
Patch 2 adds the supply names from the DT binding change in patch 1
to the regulator descriptions in the driver. This patch has a
checkpatch.pl warnings, but I wonder if it's because the context size
for checking complex macros is not large enough.
Device tree changes will be sent separately. The goal is to get the
regulator tree as complete as possible. This includes adding supply
names to other regulator DT bindings, and adding all the supply links
to the existing DTs.
Please have a look.
Thanks
ChenYu
Chen-Yu Tsai (2):
regulator: dt-bindings: mt6315: Add regulator supplies
regulator: mt6315: Add regulator supplies
.../bindings/regulator/mt6315-regulator.yaml | 13 +++++++++++++
drivers/regulator/mt6315-regulator.c | 11 ++++++-----
2 files changed, 19 insertions(+), 5 deletions(-)
--
2.53.0.983.g0bb29b3bc5-goog
^ permalink raw reply
* [PATCH RESEND 1/2] regulator: dt-bindings: mt6315: Add regulator supplies
From: Chen-Yu Tsai @ 2026-03-24 5:30 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-arm-kernel, linux-mediatek, devicetree
In-Reply-To: <20260324053030.4077453-1-wenst@chromium.org>
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a
separate supply.
Add these supplies to the device tree binding.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
.../bindings/regulator/mt6315-regulator.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
index fa6743bb269d..ba99a0d02bc7 100644
--- a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
@@ -29,6 +29,16 @@ properties:
type: object
description: List of regulators and its properties
+ properties:
+ pvdd1-supply:
+ description: Supply for vbuck1
+ pvdd2-supply:
+ description: Supply for vbuck2
+ pvdd3-supply:
+ description: Supply for vbuck3
+ pvdd4-supply:
+ description: Supply for vbuck4
+
patternProperties:
"^vbuck[1-4]$":
type: object
@@ -51,6 +61,9 @@ examples:
reg = <0x6 0>;
regulators {
+ pvdd1-supply = <&pp4200_z2>;
+ pvdd3-supply = <&pp4200_z2>;
+
vbuck1 {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
--
2.53.0.983.g0bb29b3bc5-goog
^ permalink raw reply related
* [PATCH RESEND 2/2] regulator: mt6315: Add regulator supplies
From: Chen-Yu Tsai @ 2026-03-24 5:30 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-arm-kernel, linux-mediatek, devicetree
In-Reply-To: <20260324053030.4077453-1-wenst@chromium.org>
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a
separate supply.
Add these supplies to the driver.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/regulator/mt6315-regulator.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/regulator/mt6315-regulator.c b/drivers/regulator/mt6315-regulator.c
index d3f93aae0fc5..231e64fb0596 100644
--- a/drivers/regulator/mt6315-regulator.c
+++ b/drivers/regulator/mt6315-regulator.c
@@ -31,10 +31,11 @@ struct mt6315_chip {
struct regmap *regmap;
};
-#define MT_BUCK(_name, _bid, _vsel) \
+#define MT_BUCK(_name, _bid, _supply, _vsel) \
[_bid] = { \
.desc = { \
.name = _name, \
+ .supply_name = _supply, \
.of_match = of_match_ptr(_name), \
.regulators_node = "regulators", \
.ops = &mt6315_volt_range_ops, \
@@ -190,10 +191,10 @@ static const struct regulator_ops mt6315_volt_range_ops = {
};
static const struct mt6315_regulator_info mt6315_regulators[MT6315_VBUCK_MAX] = {
- MT_BUCK("vbuck1", MT6315_VBUCK1, MT6315_BUCK_TOP_ELR0),
- MT_BUCK("vbuck2", MT6315_VBUCK2, MT6315_BUCK_TOP_ELR2),
- MT_BUCK("vbuck3", MT6315_VBUCK3, MT6315_BUCK_TOP_ELR4),
- MT_BUCK("vbuck4", MT6315_VBUCK4, MT6315_BUCK_TOP_ELR6),
+ MT_BUCK("vbuck1", MT6315_VBUCK1, "pvdd1", MT6315_BUCK_TOP_ELR0),
+ MT_BUCK("vbuck2", MT6315_VBUCK2, "pvdd2", MT6315_BUCK_TOP_ELR2),
+ MT_BUCK("vbuck3", MT6315_VBUCK3, "pvdd3", MT6315_BUCK_TOP_ELR4),
+ MT_BUCK("vbuck4", MT6315_VBUCK4, "pvdd4", MT6315_BUCK_TOP_ELR6),
};
static const struct regmap_config mt6315_regmap_config = {
--
2.53.0.983.g0bb29b3bc5-goog
^ permalink raw reply related
* Re: [PATCH v5 phy-next 08/27] PCI: Remove device links to PHY
From: Manivannan Sadhasivam @ 2026-03-24 5:35 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Vignesh Raghavendra,
Siddharth Vadapalli
In-Reply-To: <20260319223241.1351137-9-vladimir.oltean@nxp.com>
On Fri, Mar 20, 2026 at 12:32:22AM +0200, Vladimir Oltean wrote:
> This is practically a full revert of commit
> 7a4db656a635 ("PCI: dra7xx: Create functional dependency between PCIe and PHY")
> and a partial revert of the device link pieces from commits
> dfb80534692d ("PCI: cadence: Add generic PHY support to host and EP drivers")
> 49229238ab47 ("PCI: keystone: Cleanup PHY handling")
>
> The trouble with these commits is that they dereference fields inside
> struct phy from a consumer driver, which will become no longer possible.
>
> Since commit 987351e1ea77 ("phy: core: Add consumer device link
> support") from 2019, the PHY core also adds a device link to order PHY
> provider and consumer suspend/resume operations. All reverted commits
> are from 2017-2018, and what they do should actually be redundant now.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
- Mani
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Siddharth Vadapalli <s-vadapalli@ti.com>
>
> v3->v5: none
> v2->v3:
> - remove dangling set but unused phy_count local variable in
> cdns_plat_pcie_probe()
> v1->v2:
> - fully remove struct device link **link from struct cdns_pcie and from
> cdns_plat_pcie_probe() error path
> - collect tag
> - adjust commit title
> ---
> .../controller/cadence/pcie-cadence-plat.c | 4 ---
> drivers/pci/controller/cadence/pcie-cadence.c | 16 +---------
> drivers/pci/controller/cadence/pcie-cadence.h | 2 --
> drivers/pci/controller/dwc/pci-dra7xx.c | 16 ----------
> drivers/pci/controller/dwc/pci-keystone.c | 31 +++----------------
> 5 files changed, 5 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> index b067a3296dd3..fc39c01b7964 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
> @@ -41,7 +41,6 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
> struct pci_host_bridge *bridge;
> struct cdns_pcie_ep *ep;
> struct cdns_pcie_rc *rc;
> - int phy_count;
> bool is_rc;
> int ret;
>
> @@ -122,9 +121,6 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
> pm_runtime_put_sync(dev);
> pm_runtime_disable(dev);
> cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
> - phy_count = cdns_plat_pcie->pcie->phy_count;
> - while (phy_count--)
> - device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
>
> return 0;
> }
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
> index a1eada56edba..0ac980249941 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
> @@ -222,7 +222,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> struct device_node *np = dev->of_node;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> int i;
> int ret;
> const char *name;
> @@ -238,10 +237,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < phy_count; i++) {
> of_property_read_string_index(np, "phy-names", i, &name);
> phy[i] = devm_phy_get(dev, name);
> @@ -249,17 +244,10 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> ret = PTR_ERR(phy[i]);
> goto err_phy;
> }
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - devm_phy_put(dev, phy[i]);
> - ret = -EINVAL;
> - goto err_phy;
> - }
> }
>
> pcie->phy_count = phy_count;
> pcie->phy = phy;
> - pcie->link = link;
>
> ret = cdns_pcie_enable_phy(pcie);
> if (ret)
> @@ -268,10 +256,8 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> return 0;
>
> err_phy:
> - while (--i >= 0) {
> - device_link_del(link[i]);
> + while (--i >= 0)
> devm_phy_put(dev, phy[i]);
> - }
>
> return ret;
> }
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 443033c607d7..35b0b33bc6fb 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -82,7 +82,6 @@ struct cdns_plat_pcie_of_data {
> * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
> * @phy_count: number of supported PHY devices
> * @phy: list of pointers to specific PHY control blocks
> - * @link: list of pointers to corresponding device link representations
> * @ops: Platform-specific ops to control various inputs from Cadence PCIe
> * wrapper
> * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
> @@ -95,7 +94,6 @@ struct cdns_pcie {
> bool is_rc;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> const struct cdns_pcie_ops *ops;
> const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
> };
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index d5d26229063f..b91ab37845c9 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -9,7 +9,6 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/device.h>
> #include <linux/err.h>
> #include <linux/interrupt.h>
> #include <linux/irq.h>
> @@ -683,7 +682,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> int i;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> void __iomem *base;
> struct dw_pcie *pci;
> struct dra7xx_pcie *dra7xx;
> @@ -731,10 +729,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> dra7xx->clk = devm_clk_get_optional(dev, NULL);
> if (IS_ERR(dra7xx->clk))
> return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
> @@ -749,12 +743,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> phy[i] = devm_phy_get(dev, name);
> if (IS_ERR(phy[i]))
> return PTR_ERR(phy[i]);
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> - }
> }
>
> dra7xx->base = base;
> @@ -856,10 +844,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> dra7xx_pcie_disable_phy(dra7xx);
>
> -err_link:
> - while (--i >= 0)
> - device_link_del(link[i]);
> -
> return ret;
> }
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 642e4c45eefc..07698c645e02 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -130,7 +130,6 @@ struct keystone_pcie {
> int num_lanes;
> u32 num_viewport;
> struct phy **phy;
> - struct device_link **link;
> struct device_node *msi_intc_np;
> struct irq_domain *intx_irq_domain;
> struct device_node *np;
> @@ -1118,7 +1117,6 @@ static int ks_pcie_probe(struct platform_device *pdev)
> enum dw_pcie_device_mode mode;
> struct dw_pcie *pci;
> struct keystone_pcie *ks_pcie;
> - struct device_link **link;
> struct gpio_desc *gpiod;
> struct resource *res;
> void __iomem *base;
> @@ -1189,31 +1187,17 @@ static int ks_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, num_lanes, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < num_lanes; i++) {
> snprintf(name, sizeof(name), "pcie-phy%d", i);
> phy[i] = devm_phy_optional_get(dev, name);
> if (IS_ERR(phy[i])) {
> ret = PTR_ERR(phy[i]);
> - goto err_link;
> - }
> -
> - if (!phy[i])
> - continue;
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> + goto err;
> }
> }
>
> ks_pcie->np = np;
> ks_pcie->pci = pci;
> - ks_pcie->link = link;
> ks_pcie->num_lanes = num_lanes;
> ks_pcie->phy = phy;
>
> @@ -1223,7 +1207,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
> ret = PTR_ERR(gpiod);
> if (ret != -EPROBE_DEFER)
> dev_err(dev, "Failed to get reset GPIO\n");
> - goto err_link;
> + goto err;
> }
>
> /* Obtain references to the PHYs */
> @@ -1238,7 +1222,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
>
> if (ret) {
> dev_err(dev, "failed to enable phy\n");
> - goto err_link;
> + goto err;
> }
>
> platform_set_drvdata(pdev, ks_pcie);
> @@ -1325,25 +1309,18 @@ static int ks_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
>
> -err_link:
> - while (--i >= 0 && link[i])
> - device_link_del(link[i]);
> -
> +err:
> return ret;
> }
>
> static void ks_pcie_remove(struct platform_device *pdev)
> {
> struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
> - struct device_link **link = ks_pcie->link;
> - int num_lanes = ks_pcie->num_lanes;
> struct device *dev = &pdev->dev;
>
> pm_runtime_put(dev);
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
> - while (num_lanes--)
> - device_link_del(link[num_lanes]);
> }
>
> static struct platform_driver ks_pcie_driver = {
> --
> 2.43.0
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* [PATCH v3 0/7] arm64: dts: imx943: various update
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan,
Ranjani Vaidyanathan, Joy Zou, Florin Leotescu
Update pin header
Add V2X/ELE mailbox nodes, more SCMI nodes, thermal nodes, fan node
Add nxp,ctrl-ids.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v3:
- Typo fixes in patch 1 and 3
- Link to v2: https://lore.kernel.org/r/20260320-imx943-dts-v1-v2-0-e6eba6b3a837@nxp.com
Changes in v2:
- Rename ana to ana-thermal
- Rebased to next-20260319 to resolve conflicts
- Link to v1: https://lore.kernel.org/r/20260314-imx943-dts-v1-v1-0-3ba9b426863b@nxp.com
---
Florin Leotescu (1):
arm64: dts: imx943-evk: Add fan node and enable active cooling on A55
Joy Zou (1):
arm64: dts: imx943: Add thermal support
Peng Fan (4):
arm64: dts: imx94: Add V2X/ELE mailbox nodes
arm64: dts: imx94: Add SCMI sensor/lmm/cpu nodes
arm64: dts: imx943-evk: Add nxp,ctrl-ids for scmi_misc
arm64: dts: imx943-evk: Add pf09/53 thermal zone
Ranjani Vaidyanathan (1):
arm64: dts: imx94: Update pin headers
arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 12 +++
arch/arm64/boot/dts/freescale/imx94.dtsi | 56 +++++++++++++
arch/arm64/boot/dts/freescale/imx943-evk.dts | 108 ++++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx943.dtsi | 62 +++++++++++++++
4 files changed, 238 insertions(+)
---
base-commit: 518185e147d184577d14d975642eb4b7add52aef
change-id: 20260313-imx943-dts-v1-7e5b684421cb
Best regards,
--
Peng Fan <peng.fan@nxp.com>
^ permalink raw reply
* [PATCH v3 1/7] arm64: dts: imx94: Update pin headers
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan,
Ranjani Vaidyanathan
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Update the pin headers to include pins that has special mux options:
The MUX value field in the IOMUX table is extended to 16 bits where
the lower 8 bits represent the current IOMUX value and the upper
8 bits represent the new extended mux.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94-pinfunc.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h
index 00255db89185260811c4b6b50ac3980f18e69141..d5056e9171409ed922ea12c559f5cffa94cb9075 100644
--- a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h
@@ -233,6 +233,7 @@
#define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3 0x0054 0x0358 0x0704 0x05 0x01
#define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0 0x0054 0x0358 0x06e4 0x06 0x00
#define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31 0x0054 0x0358 0x08b4 0x07 0x00
+#define IMX94_PAD_GPIO_IO17__XSPI1_IPP_IND_INTFA_B 0x0054 0x0358 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x035c 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x0058 0x035c 0x0738 0x01 0x00
@@ -242,6 +243,7 @@
#define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6 0x0058 0x035c 0x0710 0x05 0x01
#define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1 0x0058 0x035c 0x06d8 0x06 0x00
#define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32 0x0058 0x035c 0x08b8 0x07 0x00
+#define IMX94_PAD_GPIO_IO18__USB1_OTG_OC 0x0058 0x035c 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x0360 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x005c 0x0360 0x0734 0x01 0x00
@@ -251,6 +253,7 @@
#define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9 0x005c 0x0360 0x071c 0x05 0x01
#define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1 0x005c 0x0360 0x06e8 0x06 0x00
#define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33 0x005c 0x0360 0x08bc 0x07 0x00
+#define IMX94_PAD_GPIO_IO19__USB2_OTG_OC 0x005c 0x0360 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0364 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x0060 0x0364 0x0000 0x01 0x00
@@ -413,6 +416,7 @@
#define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2 0x00a4 0x03a8 0x06c0 0x05 0x00
#define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1 0x00a4 0x03a8 0x06a4 0x06 0x00
#define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13 0x00a4 0x03a8 0x0890 0x07 0x00
+#define IMX94_PAD_GPIO_IO37__XSPI1_IPP_IND_INTFA_B 0x00a4 0x03a8 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO38__GPIO3_IO6 0x00a8 0x03ac 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0 0x00a8 0x03ac 0x064c 0x01 0x00
@@ -574,6 +578,7 @@
#define IMX94_PAD_GPIO_IO55__TPM4_CH3 0x00ec 0x03f0 0x083c 0x05 0x01
#define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0 0x00ec 0x03f0 0x0000 0x06 0x00
#define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19 0x00ec 0x03f0 0x08a8 0x07 0x00
+#define IMX94_PAD_GPIO_IO55__XSPI1_IPP_IND_INTFA_B 0x00ec 0x03f0 0x0000 0x0100 0x00
#define IMX94_PAD_GPIO_IO56__GPIO3_IO24 0x00f0 0x03f4 0x0000 0x00 0x00
#define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6 0x00f0 0x03f4 0x0664 0x01 0x00
@@ -592,6 +597,8 @@
#define IMX94_PAD_GPIO_IO57__TPM6_CH3 0x00f4 0x03f8 0x084c 0x05 0x01
#define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1 0x00f4 0x03f8 0x0000 0x06 0x00
#define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT 0x00f4 0x03f8 0x0000 0x07 0x00
+#define IMX94_PAD_GPIO_IO57__XBAR1_XBAR_INOUT21 0x00f4 0x03f8 0x0000 0x0100 0x00
+#define IMX94_PAD_GPIO_IO57__SAI3_RX_SYNC 0x00f4 0x03f8 0x0000 0x0200 0x00
#define IMX94_PAD_CCM_CLKO1__CLKO_1 0x00f8 0x03fc 0x0000 0x00 0x00
#define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8 0x00f8 0x03fc 0x066c 0x01 0x00
@@ -619,6 +626,7 @@
#define IMX94_PAD_CCM_CLKO3__GPIO4_IO2 0x0100 0x0404 0x0000 0x05 0x00
#define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3 0x0100 0x0404 0x0000 0x06 0x00
#define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT 0x0100 0x0404 0x0000 0x07 0x00
+#define IMX94_PAD_CCM_CLKO3__XBAR1_XBAR_INOUT24 0x0100 0x0404 0x0000 0x0105 0x00
#define IMX94_PAD_CCM_CLKO4__CLKO_4 0x0104 0x0408 0x0000 0x00 0x00
#define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11 0x0104 0x0408 0x0000 0x01 0x00
@@ -872,6 +880,7 @@
#define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29 0x017c 0x0480 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1 0x017c 0x0480 0x06f8 0x06 0x02
#define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK 0x017c 0x0480 0x0000 0x07 0x00
+#define IMX94_PAD_ETH4_MDIO_GPIO2__XSPI2_IPP_IND_INTFA_B 0x017c 0x0480 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0180 0x0484 0x0648 0x00 0x00
#define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK 0x0180 0x0484 0x0000 0x01 0x00
@@ -917,6 +926,7 @@
#define IMX94_PAD_ETH4_TXD2__GPIO7_IO2 0x0190 0x0494 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2 0x0190 0x0494 0x06dc 0x06 0x01
#define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK 0x0190 0x0494 0x0000 0x07 0x00
+#define IMX94_PAD_ETH4_TXD2__XBAR1_XBAR_INOUT34 0x0190 0x0494 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x0194 0x0498 0x0000 0x00 0x00
#define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3 0x0194 0x0498 0x0868 0x01 0x01
@@ -965,6 +975,7 @@
#define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8 0x01a8 0x04ac 0x0000 0x05 0x00
#define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT 0x01a8 0x04ac 0x0000 0x06 0x00
#define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6 0x01a8 0x04ac 0x0874 0x07 0x01
+#define IMX94_PAD_ETH4_RX_CTL__XSPI2_IPP_IND_INTFA_B 0x01a8 0x04ac 0x0000 0x0105 0x00
#define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x01ac 0x04b0 0x0630 0x00 0x00
#define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS 0x01ac 0x04b0 0x0000 0x02 0x00
@@ -1344,6 +1355,7 @@
#define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27 0x028c 0x0590 0x0000 0x05 0x00
#define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0 0x028c 0x0590 0x0000 0x06 0x00
#define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK 0x028c 0x0590 0x0000 0x07 0x00
+#define IMX94_PAD_XSPI1_SS1_B__XSPI1_IPP_IND_INTFA_B 0x028c 0x0590 0x0000 0x0105 0x00
#define IMX94_PAD_SD2_CD_B__USDHC2_CD_B 0x0290 0x0594 0x0000 0x00 0x00
#define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL 0x0290 0x0594 0x0634 0x01 0x01
--
2.37.1
^ permalink raw reply related
* [PATCH v3 2/7] arm64: dts: imx94: Add V2X/ELE mailbox nodes
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add V2X and ELE Message Unit nodes for i.MX94.
One extra V2X MU which is dedicated for V2X fast crypto engine is not
included, because it requires a new compatible string.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 38488147a3ef2f3e9c19e0ad14de2b98d85639d2..69ede676fc04ede23faceb8f24cf740697e40d7e 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -1212,6 +1212,48 @@ a55_irqsteer: interrupt-controller@446a0000 {
};
};
+ mailbox@47300000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47310000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47330000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47340000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47340000 0x0 0x10000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47350000 {
+ compatible = "fsl,imx95-mu-v2x";
+ reg = <0x0 0x47350000 0x0 0x10000>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
+ mailbox@47550000 {
+ compatible = "fsl,imx95-mu-ele";
+ reg = <0x0 0x47550000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
aips4: bus@49000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x0 0x49000000 0x0 0x800000>;
--
2.37.1
^ permalink raw reply related
* [PATCH v3 3/7] arm64: dts: imx94: Add SCMI sensor/lmm/cpu nodes
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add SCMI sensor/lmm/cpu nodes to allow Linux use thermal, i.MX System
Manager Logical Machine API and CPU API
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index 69ede676fc04ede23faceb8f24cf740697e40d7e..d779866d5bb2d425a496065d6f7f3f7532f15298 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -94,14 +94,27 @@ scmi_clk: protocol@14 {
#clock-cells = <1>;
};
+ scmi_sensor: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
scmi_iomuxc: protocol@19 {
reg = <0x19>;
};
+ scmi_lmm: protocol@80 {
+ reg = <0x80>;
+ };
+
scmi_bbm: protocol@81 {
reg = <0x81>;
};
+ scmi_cpu: protocol@82 {
+ reg = <0x82>;
+ };
+
scmi_misc: protocol@84 {
reg = <0x84>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v3 4/7] arm64: dts: imx943: Add thermal support
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan,
Joy Zou
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Joy Zou <joy.zou@nxp.com>
Add A55 and ANA thermal including cooling-maps.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx943.dtsi | 62 +++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index d779866d5bb2d425a496065d6f7f3f7532f15298..45dc1905549274bae118156f425ee5daa9ae10bb 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx94-clock.h"
#include "imx94-pinfunc.h"
diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 45b8da758e87771c0775eb799ce2da3aac37c060..5091a5c3d5815d88b7ae94b7e1776de7403b9c00 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -145,4 +145,66 @@ l3_cache: l3-cache {
cache-unified;
};
};
+
+ thermal_zones: thermal-zones {
+ a55-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 1>;
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ ana-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 0>;
+ trips {
+ ana_alert: trip0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ana_crit0: trip1 {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&ana_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
--
2.37.1
^ permalink raw reply related
* [PATCH v3 5/7] arm64: dts: imx943-evk: Add nxp,ctrl-ids for scmi_misc
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add nxp,ctrl-ids for scmi_misc to support wakeup from the peripherals.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx943-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index 1d834379f602dea9eb70381f6fe2ef6e3c938a80..ec728efbe15cf0b97deade68445b23528325b082 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -8,6 +8,12 @@
#include "imx943.dtsi"
#include <dt-bindings/usb/pd.h>
+#define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */
+#define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */
+#define BRD_SM_CTRL_PCIE1_WAKE 0x8002 /*!< PCAL6416A-5 */
+#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6416A-6 */
+#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6416A-7 */
+
/ {
compatible = "fsl,imx943-evk", "fsl,imx94";
model = "NXP i.MX943 EVK board";
@@ -878,6 +884,14 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe
};
};
+&scmi_misc {
+ nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
+ BRD_SM_CTRL_PCIE1_WAKE 1
+ BRD_SM_CTRL_BT_WAKE 1
+ BRD_SM_CTRL_PCIE2_WAKE 1
+ BRD_SM_CTRL_BUTTON 1>;
+};
+
&usb2 {
dr_mode = "otg";
disable-over-current;
--
2.37.1
^ permalink raw reply related
* [PATCH v3 7/7] arm64: dts: imx943-evk: Add pf09/53 thermal zone
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add PF09 and PF53 thermal nodes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx943-evk.dts | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index 7125c7fc6e32999fd279b9d01af0b210d1ab843d..0fd142f19ed2c99c9d555f4f2b9e6b8259131fb9 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -946,6 +946,44 @@ map3 {
};
};
};
+
+ pf09-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 2>;
+ trips {
+ pf09_alert: trip0 {
+ temperature = <140000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pf09_crit: trip1 {
+ temperature = <155000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pf53soc-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&scmi_sensor 3>;
+ trips {
+ pf5302_alert: trip0 {
+ temperature = <140000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pf5302_crit: trip1 {
+ temperature = <155000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
};
&usb2 {
--
2.37.1
^ permalink raw reply related
* [PATCH v3 6/7] arm64: dts: imx943-evk: Add fan node and enable active cooling on A55
From: Peng Fan (OSS) @ 2026-03-24 5:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan,
Florin Leotescu
In-Reply-To: <20260324-imx943-dts-v1-v3-0-b33bf1f1c254@nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
Add pwm fan node and use it for A55 cooling.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx943-evk.dts | 56 ++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index ec728efbe15cf0b97deade68445b23528325b082..7125c7fc6e32999fd279b9d01af0b210d1ab843d 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -7,6 +7,7 @@
#include "imx943.dtsi"
#include <dt-bindings/usb/pd.h>
+#include <dt-bindings/pwm/pwm.h>
#define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */
#define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */
@@ -314,6 +315,20 @@ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
+ fan_controller: pwm@2f {
+ compatible = "microchip,emc2301", "microchip,emc2305";
+ reg = <0x2f>;
+ #pwm-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan0: fan@0 {
+ reg = <0x0>;
+ pwms = <&fan_controller 26000 1 PWM_POLARITY_INVERTED>;
+ #cooling-cells = <2>;
+ };
+ };
+
wm8962: codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
@@ -892,6 +907,47 @@ BRD_SM_CTRL_PCIE2_WAKE 1
BRD_SM_CTRL_BUTTON 1>;
};
+&thermal_zones {
+ a55-thermal {
+ trips {
+ atrip2: trip2 {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ atrip3: trip3 {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ atrip4: trip4 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&atrip2>;
+ cooling-device = <&fan0 4 6>;
+ };
+
+ map2 {
+ trip = <&atrip3>;
+ cooling-device = <&fan0 6 8>;
+ };
+
+ map3 {
+ trip = <&atrip4>;
+ cooling-device = <&fan0 8 10>;
+ };
+ };
+ };
+};
+
&usb2 {
dr_mode = "otg";
disable-over-current;
--
2.37.1
^ permalink raw reply related
* [PATCH] arm64: dts: imx8mp-evk: Specify ADV7535 register addresses
From: Liu Ying @ 2026-03-24 5:52 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Liu Ying
MIPI DSI to HDMI bridge ADV7535 CEC default register address is 0x3c
on an I2C bus. And, OV5640 camera uses the same address on the same
I2C bus. To resolve this conflict, use 0x3b as ADV7535 CEC register
address by specifying all ADV7535 register addresses.
Fixes: 6f6c18cba16f ("arm64: dts: imx8mp-evk: add camera ov5640 and related nodes")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index aedc09937716..d0a2bd975a18 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -602,7 +602,8 @@ ov5640_mipi_0_ep: endpoint {
hdmi@3d {
compatible = "adi,adv7535";
- reg = <0x3d>;
+ reg = <0x3d>, <0x3f>, <0x3b>, <0x38>;
+ reg-names = "main", "edid", "cec", "packet";
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
---
base-commit: 09c0f7f1bcdbc3c37a5a760cbec76bf18f278406
change-id: 20260324-imx8mp-evk-adv7535-cec-reg-addr-2de67760133a
Best regards,
--
Liu Ying <victor.liu@nxp.com>
^ permalink raw reply related
* Re: [PATCH v6 40/40] arm64: mpam: Add initial MPAM documentation
From: Gavin Shan @ 2026-03-24 6:04 UTC (permalink / raw)
To: Ben Horgan
Cc: amitsinght, baisheng.gao, baolin.wang, carl, dave.martin, david,
dfustini, fenghuay, james.morse, jonathan.cameron, kobak,
lcherian, linux-arm-kernel, linux-kernel, peternewman,
punit.agrawal, quic_jiles, reinette.chatre, rohit.mathew, scott,
sdonthineni, tan.shaopeng, xhao, catalin.marinas, will, corbet,
maz, oupton, joey.gouly, suzuki.poulose, kvmarm, zengheng4,
linux-doc, Shaopeng Tan
In-Reply-To: <20260313144617.3420416-41-ben.horgan@arm.com>
On 3/14/26 12:46 AM, Ben Horgan wrote:
> MPAM (Memory Partitioning and Monitoring) is now exposed to user-space via
> resctrl. Add some documentation so the user knows what features to expect.
>
> Reviewed-by: Zeng Heng <zengheng4@huawei.com>
> Reviewed-by: Shaopeng Tan <tan.shaopeng@jp.fujitsu.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: James Morse <james.morse@arm.com>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Ben Horgan <ben.horgan@arm.com>
> ---
> Changes by Ben:
> Some tidying, update for current heuristics
>
> Changes from v4:
> Fix unusual indentation
>
> Changes from v5:
> Drop cdp (under CONFIG_EXPERT) and mbwu (back with abmc)
> ---
> Documentation/arch/arm64/index.rst | 1 +
> Documentation/arch/arm64/mpam.rst | 72 ++++++++++++++++++++++++++++++
> 2 files changed, 73 insertions(+)
> create mode 100644 Documentation/arch/arm64/mpam.rst
>
Reviewed-by: Gavin Shan <gshan@redhat.com>
^ permalink raw reply
* Re: [PATCH v3 1/5] perf kvm stat: Remove use of the arch directory
From: patchwork-bot+linux-riscv @ 2026-03-24 6:07 UTC (permalink / raw)
To: Ian Rogers
Cc: linux-riscv, acme, aditya.b1, adrian.hunter, ajones, ak, alex,
alexander.shishkin, anup, aou, ashelat, atrajeev, blakejones,
ctshao, dapeng1.mi, dvyukov, howardchu95, james.clark,
john.g.garry, jolsa, leo.yan, linux-arm-kernel, linux-kernel,
linux-perf-users, mingo, namhyung, palmer, peterz, pjw,
shimin.guo, swapnil.sapkal, thomas.falcon, will, ysk, zhouquan
In-Reply-To: <20260203182640.3911987-2-irogers@google.com>
Hello:
This series was applied to riscv/linux.git (for-next)
by Arnaldo Carvalho de Melo <acme@redhat.com>:
On Tue, 3 Feb 2026 10:26:36 -0800 you wrote:
> `perf kvm stat` supports record and report options. By using the arch
> directory a report for a different machine type cannot be
> supported. Move the kvm-stat code out of the arch directory and into
> util/kvm-stat-arch following the pattern of perf-regs and
> dwarf-regs. Avoid duplicate symbols by renaming functions to have the
> architecture name within them. For global variables, wrap them in an
> architecture specific function. Selecting the architecture to use with
> `perf kvm stat` is selected by EM_HOST, ie no different than before
> the change. Later the ELF machine can be determined from the session
> or a header feature (ie EM_HOST at the time of the record).
>
> [...]
Here is the summary with links:
- [v3,1/5] perf kvm stat: Remove use of the arch directory
https://git.kernel.org/riscv/c/ceea279f9376
- [v3,2/5] perf kvm: Wire up e_machine
https://git.kernel.org/riscv/c/43af54843677
- [v3,3/5] perf session: Add e_flags to the e_machine helper
https://git.kernel.org/riscv/c/07ad6f31b674
- [v3,4/5] perf header: Add e_machine/e_flags to the header
https://git.kernel.org/riscv/c/c4f4392264b4
- [v3,5/5] perf thread: Don't require machine to compute the e_machine
https://git.kernel.org/riscv/c/84cb36da8141
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH] KVM: Remove subtle "struct kvm_stats_desc" pseudo-overlay
From: patchwork-bot+linux-riscv @ 2026-03-24 6:07 UTC (permalink / raw)
To: Sean Christopherson
Cc: linux-riscv, maz, oupton, zhaotianrui, maobibo, chenhuacai, maddy,
anup, pjw, palmer, aou, borntraeger, frankja, imbrenda, pbonzini,
linux-arm-kernel, kvmarm, kvm, loongarch, linux-mips,
linuxppc-dev, kvm-riscv, linux-kernel, gustavoars
In-Reply-To: <20251205232655.445294-1-seanjc@google.com>
Hello:
This patch was applied to riscv/linux.git (for-next)
by Sean Christopherson <seanjc@google.com>:
On Fri, 5 Dec 2025 15:26:55 -0800 you wrote:
> Remove KVM's internal pseudo-overlay of kvm_stats_desc, which subtly
> aliases the flexible name[] in the uAPI definition with a fixed-size array
> of the same name. The unusual embedded structure results in compiler
> warnings due to -Wflex-array-member-not-at-end, and also necessitates an
> extra level of dereferencing in KVM. To avoid the "overlay", define the
> uAPI structure to have a fixed-size name when building for the kernel.
>
> [...]
Here is the summary with links:
- KVM: Remove subtle "struct kvm_stats_desc" pseudo-overlay
https://git.kernel.org/riscv/c/da142f3d373a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [Patch v3 0/4] Perf tools: perf-regs bug fix and optimization
From: patchwork-bot+linux-riscv @ 2026-03-24 6:07 UTC (permalink / raw)
To: Mi, Dapeng
Cc: linux-riscv, peterz, mingo, acme, namhyung, irogers,
adrian.hunter, alexander.shishkin, john.g.garry, will,
james.clark, mike.leach, guoren, pjw, palmer, aou, alex,
linux-perf-users, linux-arm-kernel, linux-csky, linux-kernel,
zide.chen, thomas.falcon, dapeng1.mi, xudong.hao
In-Reply-To: <20260203024356.444942-1-dapeng1.mi@linux.intel.com>
Hello:
This series was applied to riscv/linux.git (for-next)
by Arnaldo Carvalho de Melo <acme@redhat.com>:
On Tue, 3 Feb 2026 10:43:52 +0800 you wrote:
> Changes:
> v2 -> v3:
> * Fix the abort issue for "-I" or "--user-regs" options. (Patch 1/4)
> * Address Ian's comments.
>
> v1 -> v2:
> * Fixing "PERF_REG_EXTENDED_MASK" redefinition building error by
> changing the "asm/perf_regs.h" header path to relative UAPI path.
> (Patch 1/3)
> * Spliting xxx_reg_mask() and xxx_sdt_arg_parse_op() conversion into 2
> patches.
>
> [...]
Here is the summary with links:
- [v3,1/4] perf regs: Fix abort for "-I" or "--user-regs" options
https://git.kernel.org/riscv/c/c2e28ae2946f
- [v3,2/4] perf arch: Update arch headers to use relative UAPI paths
https://git.kernel.org/riscv/c/e716e69cf67b
- [v3,3/4] perf regs: Remove __weak attributive arch__xxx_reg_mask() functions
(no matching commit)
- [v3,4/4] perf regs: Remove __weak attributive arch_sdt_arg_parse_op() function
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v2] perf regs: Refactor use of arch__sample_reg_masks to perf_reg_name
From: patchwork-bot+linux-riscv @ 2026-03-24 6:07 UTC (permalink / raw)
To: Ian Rogers
Cc: linux-riscv, peterz, mingo, acme, namhyung, jolsa, adrian.hunter,
james.clark, john.g.garry, will, leo.yan, guoren, pjw, palmer,
aou, alex, shimin.guo, atrajeev, stephen.s.brennan, howardchu95,
thomas.falcon, ak, linux, dvyukov, krzysztof.m.lopatowski, ctshao,
aditya.b1, haibo1.xu, slyich, linux-kernel, linux-perf-users,
linux-arm-kernel, linux-csky, dapeng1.mi
In-Reply-To: <20260121021735.3625244-1-irogers@google.com>
Hello:
This patch was applied to riscv/linux.git (for-next)
by Arnaldo Carvalho de Melo <acme@redhat.com>:
On Tue, 20 Jan 2026 18:17:35 -0800 you wrote:
> arch__sample_reg_masks isn't supported on ARM(32), csky, loongarch,
> MIPS, RISC-V and s390. The table returned by the function just has the
> name of a register paired with the corresponding sample_regs_user mask
> value. For a given perf register we can compute the name with
> perf_reg_name and the mask is just 1 left-shifted by the perf register
> number. Change __parse_regs to use this method for finding registers
> rather than arch__sample_reg_masks, thereby adding __parse_regs
> support for ARM(32), csky, loongarch, MIPS, RISC-V and s390. As
> arch__sample_reg_masks is then unused, remove the now unneeded
> declarations.
>
> [...]
Here is the summary with links:
- [v2] perf regs: Refactor use of arch__sample_reg_masks to perf_reg_name
https://git.kernel.org/riscv/c/3d06db9bad1a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
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^ permalink raw reply
* Re: [PATCH v3 00/12] perf annotate arch clean up
From: patchwork-bot+linux-riscv @ 2026-03-24 6:07 UTC (permalink / raw)
To: Ian Rogers
Cc: linux-riscv, peterz, mingo, acme, namhyung, alexander.shishkin,
jolsa, adrian.hunter, james.clark, john.g.garry, will, leo.yan,
guoren, pjw, palmer, aou, alex, nathan, nick.desaulniers+lkml,
morbo, justinstitt, zecheng, tianyou.li, thomas.falcon,
Julia.Lawall, suchitkarunakaran, atrajeev, aditya.b1, howardchu95,
krzysztof.m.lopatowski, linux, shimin.guo, slyich, linux-kernel,
linux-perf-users, linux-arm-kernel, linux-csky
In-Reply-To: <20260122213516.671089-1-irogers@google.com>
Hello:
This series was applied to riscv/linux.git (for-next)
by Arnaldo Carvalho de Melo <acme@redhat.com>:
On Thu, 22 Jan 2026 13:35:04 -0800 you wrote:
> 3 initial memory leak fix patches for perf annotate.
>
> Move the disasm.c #included arch files into a new util/annotate-arch
> directory. Make the code compile standalone. Try to better encapsulate
> architecture specific code within the files and with a
> arch__new_<arch> function that allows additional data to be associated
> with the struct arch using the standard container_of trick.
>
> [...]
Here is the summary with links:
- [v3,01/12] perf header: Fix memory leaks in process_cpu_domain_info
https://git.kernel.org/riscv/c/d84f24c89886
- [v3,02/12] perf annotate: Fix args leak of map_symbol
https://git.kernel.org/riscv/c/00419892bac2
- [v3,03/12] perf maps: Fix reference count leak in maps__find_ams
https://git.kernel.org/riscv/c/6fdd2676db55
- [v3,04/12] perf disasm: Constify use of struct arch
https://git.kernel.org/riscv/c/57d26593a92f
- [v3,05/12] perf disasm: Constify use of struct ins_op
https://git.kernel.org/riscv/c/1e3b91d6c53e
- [v3,06/12] perf disasm: Constify use of struct ins
https://git.kernel.org/riscv/c/2a1ca20d0b58
- [v3,07/12] perf disasm: Rework the string arch__is to use the ELF machine
https://git.kernel.org/riscv/c/927308527310
- [v3,08/12] perf disasm: Don't include C files from the arch directory
https://git.kernel.org/riscv/c/07b972ff09f4
- [v3,09/12] perf disasm: Refactor ins__is_call/jump to avoid exposing arch ins_ops
https://git.kernel.org/riscv/c/5301cc698821
- [v3,10/12] perf map_symbol: Switch from holding maps to holding thread
https://git.kernel.org/riscv/c/c4e3a00356ff
- [v3,11/12] perf disasm: Refactor arch__find and initialization of arch structs
(no matching commit)
- [v3,12/12] perf disasm: Minor layout tweaks for struct arch
https://git.kernel.org/riscv/c/dc329efc162a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v2 7/9] drm/bridge: analogix_dp: Rename and simplify is_rockchip()
From: Damon Ding @ 2026-03-24 6:12 UTC (permalink / raw)
To: Luca Ceresoli, hjc, heiko, andy.yan, maarten.lankhorst, mripard,
tzimmermann, airlied, simona, robh, krzk+dt, conor+dt,
andrzej.hajda, neil.armstrong, rfoss
Cc: Laurent.pinchart, jonas, jernej.skrabec, nicolas.frattaroli,
alchark, cristian.ciocaltea, sebastian.reichel, kever.yang,
heiko.stuebner, tomeu, amadeus, michael.riesch, didi.debian,
dmitry.baryshkov, dianders, m.szyprowski, dri-devel, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <DHAANFJ6QZKU.5NN7RD47T8TI@bootlin.com>
Hi Luca,
On 3/24/2026 12:14 AM, Luca Ceresoli wrote:
> On Thu Mar 19, 2026 at 11:40 AM CET, Damon Ding wrote:
>> Rename is_rockchip() to analogix_dp_is_rockchip() for naming consistency
>> and readability, and simplify the code with switch.
>>
>> Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
>> Suggested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
>
> The patch content is OK:
> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
>
> However this won't apply without [0], correct?
>
> So, worth mentioning in the cover letter that this series depends on the
> [0] series.
>
> [0] https://lore.kernel.org/all/20260319071452.1961274-8-damon.ding@rock-chips.com/
>
Yes, I will add it in v3.
Best regards,
Damon
^ permalink raw reply
* [PATCH 0/2] arm64: dts: Add NXP i.MX95 audio board support
From: Shengjiu Wang @ 2026-03-24 6:15 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, Frank.Li, dario.binacchi,
alexander.stein, maudspierings, josua, Markus.Niebel,
matthias.schiffer, primoz.fiser, francesco.dolcini, devicetree,
linux-kernel, s.hauer, kernel, festevam, imx, linux-arm-kernel
Add NXP i.MX95 15x15 audio board (version 2) compatible string and device
tree file.
Shengjiu Wang (2):
dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 audio board
(version 2)
arm64: dts: add support for NXP i.MX95 15x15 audio board (version 2)
.../devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx95-15x15-ab2.dts | 669 ++++++++++++++++++
3 files changed, 671 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
--
2.34.1
^ permalink raw reply
* [PATCH 1/2] dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 audio board (version 2)
From: Shengjiu Wang @ 2026-03-24 6:15 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, Frank.Li, dario.binacchi,
alexander.stein, maudspierings, josua, Markus.Niebel,
matthias.schiffer, primoz.fiser, francesco.dolcini, devicetree,
linux-kernel, s.hauer, kernel, festevam, imx, linux-arm-kernel
In-Reply-To: <20260324061556.980621-1-shengjiu.wang@nxp.com>
Introduce a new DT compatible string for the NXP i.MX95 15x15 audio board
(version 2).
i.MX Audio Board is a configurable and functional audio processing
platform. Integrating a variety of audio input and output interfaces into
the system, the i.MX Audio Board supports HDMI input, HDMI eARC,
S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these
features, rich audio application cases can be realized.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index da2be7114f64..04cd1c000ce1 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1482,6 +1482,7 @@ properties:
- description: i.MX95 based Boards
items:
- enum:
+ - fsl,imx95-15x15-ab2 # i.MX95 15x15 Audio Board V2
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
- fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
--
2.34.1
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: add support for NXP i.MX95 15x15 audio board (version 2)
From: Shengjiu Wang @ 2026-03-24 6:15 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, Frank.Li, dario.binacchi,
alexander.stein, maudspierings, josua, Markus.Niebel,
matthias.schiffer, primoz.fiser, francesco.dolcini, devicetree,
linux-kernel, s.hauer, kernel, festevam, imx, linux-arm-kernel
In-Reply-To: <20260324061556.980621-1-shengjiu.wang@nxp.com>
i.MX Audio Board is a configurable and functional audio processing
platform. Integrating a variety of audio input and output interfaces into
the system, the i.MX Audio Board supports HDMI input, HDMI eARC,
S/PDIF I/O, 2-ch ADC line-in, 24-ch DAC line-out and more. Based on these
features, rich audio application cases can be realized.
This is a basic device tree supporting with i.MX95 15x15 SoC and Audio
board (version 2).
- Six Cortex-A55
- NXP PCAL6416 GPIO expanders
- RGB LEDs via GPIO expander
- LPI2C1, LPI2C2, LPI2C3 controllers
- LPUART1 (console)
- USDHC1 (eMMC), USDHC2 (SD)
- Three DAC (AK4458)
- One ADC (AK5552)
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx95-15x15-ab2.dts | 669 ++++++++++++++++++
2 files changed, 670 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index bae24b53bce6..5b0fa6c24877 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -458,6 +458,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-ab2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
new file mode 100644
index 000000000000..f6829145f396
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-ab2.dts
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx95.dtsi"
+
+#define BRD_SM_CTRL_SD3_WAKE 0x8000
+#define BRD_SM_CTRL_PCIE1_WAKE 0x8001
+#define BRD_SM_CTRL_BT_WAKE 0x8002
+#define BRD_SM_CTRL_PCIE2_WAKE 0x8003
+#define BRD_SM_CTRL_BUTTON 0x8004
+
+/ {
+ compatible = "fsl,imx95-15x15-ab2", "fsl,imx95";
+ model = "NXP i.MX95 CPU on AB2";
+
+ aliases {
+ ethernet0 = &enetc_port0;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ stdout-path = &lpuart1;
+ };
+
+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ab2_ana_pwr";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ab2_vdd_pwr_5v0";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SD2_3V3";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
+ reusable;
+ size = <0 0x3c000000>;
+ linux,cma-default;
+ };
+
+ vpu_boot: vpu-boot@a0000000 {
+ reg = <0 0xa0000000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ sound-ak4458 {
+ compatible = "fsl,imx-audio-card";
+ model = "ak4458-audio";
+
+ pri-dai-link {
+ format = "i2s";
+ link-name = "akcodec";
+ fsl,mclk-equal-bclk;
+
+ codec {
+ sound-dai = <&ak4458_1>, <&ak4458_2>;
+ };
+
+ cpu {
+ sound-dai = <&sai2>;
+ };
+ };
+ };
+
+ sound-ak5552 {
+ compatible = "fsl,imx-audio-card";
+ model = "ak5552-audio";
+
+ pri-dai-link {
+ format = "i2s";
+ link-name = "akcodec";
+ fsl,mclk-equal-bclk;
+
+ codec {
+ sound-dai = <&ak5552>;
+ };
+
+ cpu {
+ sound-dai = <&sai3>;
+ };
+ };
+ };
+
+ sound-micfil {
+ compatible = "fsl,imx-audio-card";
+ model = "micfil-audio";
+
+ pri-dai-link {
+ format = "i2s";
+ link-name = "micfil hifi";
+
+ cpu {
+ sound-dai = <&micfil>;
+ };
+ };
+ };
+
+ sound-xcvr {
+ compatible = "fsl,imx-audio-card";
+ model = "imx-audio-xcvr";
+
+ pri-dai-link {
+ link-name = "XCVR PCM";
+
+ cpu {
+ sound-dai = <&xcvr>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x0 0x80000000 0 0x80000000>;
+ device_type = "memory";
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ status = "disabled";
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio5>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ak4458_1: audio-codec@10 {
+ compatible = "asahi-kasei,ak4458";
+ reg = <0x10>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_ab2_ana_pwr>;
+ DVDD-supply = <®_ab2_ana_pwr>;
+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
+ sound-name-prefix = "0";
+ };
+
+ ak4458_3: audio-codec@11 {
+ compatible = "asahi-kasei,ak4458";
+ reg = <0x11>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_ab2_ana_pwr>;
+ DVDD-supply = <®_ab2_ana_pwr>;
+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+ };
+
+ ak4458_2: audio-codec@12 {
+ compatible = "asahi-kasei,ak4458";
+ reg = <0x12>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_ab2_ana_pwr>;
+ DVDD-supply = <®_ab2_ana_pwr>;
+ reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>;
+ sound-name-prefix = "1";
+ };
+
+ ak5552: audio-codec@13 {
+ compatible = "asahi-kasei,ak5552";
+ reg = <0x13>;
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_ab2_ana_pwr>;
+ DVDD-supply = <®_ab2_ana_pwr>;
+ reset-gpios = <&pca6416 3 GPIO_ACTIVE_LOW>;
+ };
+
+ pca6416: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&lpi2c4 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpuart1 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&micfil {
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_PDM>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <49152000>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_pdm>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-0 = <&pinctrl_emdio>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+};
+
+&netcmix_blk_ctrl {
+ status = "okay";
+};
+
+&sai2 {
+ clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>,
+ <&scmi_clk IMX95_CLK_SAI2>, <&dummy>,
+ <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI2>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai2>;
+ pinctrl-names = "default";
+ fsl,sai-asynchronous;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&sai3 {
+ clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>,
+ <&scmi_clk IMX95_CLK_SAI3>, <&dummy>,
+ <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI3>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai3>;
+ pinctrl-names = "default";
+ fsl,sai-asynchronous;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&sai5 {
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI5>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai5>;
+ pinctrl-names = "default";
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <
+ IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
+ IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
+ >;
+ };
+
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <
+ IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
+ IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
+ IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
+ IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
+ IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
+ IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
+ IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
+ IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
+ IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
+ IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
+ IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
+ IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e
+ IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
+ IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
+ >;
+ };
+
+ pinctrl_pdm: pdmgrp {
+ fsl,pins = <
+ IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
+ IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e
+ IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x31e
+ IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x31e
+ IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e
+ IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e
+ IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e
+ IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e
+ IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e
+ IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x31e
+ IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x31e
+ IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e
+ IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e
+ IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e
+ IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e
+ IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e
+ IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e
+ IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x31e
+ IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x31e
+ IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x31e
+ IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x31e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e
+ IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e
+ IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <
+ IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e
+ IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x31e
+ IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x31e
+ IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x31e
+
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO22__SPDIF_IN 0x31e
+ IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
+ IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
+
+&scmi_misc {
+ nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1>,
+ <BRD_SM_CTRL_PCIE1_WAKE 1>,
+ <BRD_SM_CTRL_BT_WAKE 1>,
+ <BRD_SM_CTRL_PCIE2_WAKE 1>,
+ <BRD_SM_CTRL_BUTTON 1>;
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ adp-disable;
+ dr_mode = "host";
+ hnp-disable;
+ srp-disable;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ fsl,tuning-step = <1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&xcvr {
+ clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
+ <&scmi_clk IMX95_CLK_SPDIF>,
+ <&dummy>,
+ <&scmi_clk IMX95_CLK_AUDIOXCVR>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k";
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SPDIF>,
+ <&scmi_clk IMX95_CLK_AUDIOXCVR>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <3932160000>, <3612672000>,
+ <393216000>, <361267200>,
+ <12288000>, <0>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_spdif>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.34.1
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