* Re: [PATCH 2/2] ARM: dts: st: spear: fix dtbs warning on spear thermal sensor
From: Daniel Baluta @ 2026-03-24 10:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Gopi Krishna Menon
Cc: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
vireshk, conor+dt, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, soc, simona.toaca, d-gole, m-chawdhry
In-Reply-To: <20260324-smoky-radical-hyrax-1274a9@quoll>
On 3/24/26 11:26, Krzysztof Kozlowski wrote:
> On Mon, Mar 23, 2026 at 07:08:09PM +0530, Gopi Krishna Menon wrote:
>> Running DTBS checks on st/spear1340-evb.dtb results in the following
>> warning:
>>
>> thermal@e07008c4 (st,thermal-spear1340): Unevaluated properties are not allowed ('thermal_flags' was unexpected)
>> from schema $id: http://devicetree.org/schemas/thermal/st,thermal-spear1340.yaml
> How is it possible if there is no such file?
>
> Did you just add new warning in patch #1 and then claim in patch #2 that
> you fix it?
>
> You completely miss the point why this change is needed: how could the
> DTS work before? It could not. And that should be your justification for
> the patch, with explanation why it could not work.
Correct me if I'm wrong but I think there was a hidden bug here
drivers/thermal/spear_thermal.c:spear_thermal_probe:
if (!np || !of_property_read_u32(np, "st,thermal-flags", &val)) {
» » dev_err(&pdev->dev, "Failed: DT Pdata not passed\n");
» » return -EINVAL;
» }
So, the driver was checking for the correct property as pointed by
bindings/thermal/spear-thermal.txt but the dts was using the wrong
property name: arch/arm/boot/dts/st/spear13xx.dtsi » » » thermal@e07008c4 { » » » » compatible = "st,thermal-spear1340"; » » » » reg = <0xe07008c4 0x4>; » » » » thermal_flags = <0x7000>; » » » }; And because this check is wrong:
if (!np || !of_property_read_u32(np, "st,thermal-flags", &val)) {
people really didn't notice it.
The check should be:
if (!np || of_property_read_u32(np, "st,thermal-flags", &val)) {
» » dev_err(&pdev->dev, "Failed: DT Pdata not passed\n");
» » return -EINVAL;
» }
So, this actual patch has uncovered a bug!
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: spi: Fix clock-names definition
From: Krzysztof Kozlowski @ 2026-03-24 9:56 UTC (permalink / raw)
To: Meiker Gao, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Bayi Cheng, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, linux-spi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <fb3c4fc0-eb8f-431e-8c20-f90428d4c26e@kernel.org>
On 24/03/2026 10:55, Krzysztof Kozlowski wrote:
> On 24/03/2026 07:28, Meiker Gao wrote:
>> Update the device tree binding for the Mediatek
>> MT8196 NOR controller to require that the 'clock-names'
>> property contains exactly six entries, in the strict order:
>> "spi", "sf", "axi", "axi_s", "bclk", "27m".
>>
>> Signed-off-by: Meiker Gao <ot_meiker.gao@mediatek.com>
>> Change-Id: I0542d6d726f1af34ef76c1a58ba4e4b02ec45fe6
>
> You just sent multiple same patches with same errors.
>
> Same feedback.
Heh, I already asked you that last time, two weeks ago... so you keep
repeating same mistakes.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4 1/3] dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-03-24 9:54 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260324095455.1437-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG decoder block found in the
MediaTek MT8189 SoC.
Compared to previous generation ICs, the MT8189 JPEG decoder requires
34-bit IOVA address space support and only needs a single clock
("jpgdec") instead of two. Therefore, it is added as a standalone
compatible string without falling back to older SoCs.
Update the binding schema to include the new compatible string and add
an `allOf` block with conditional checks. This enforces the single clock
requirement for MT8189 while preserving the two-clock requirement
("jpgdec-smi", "jpgdec") for older SoCs.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-decoder.yaml | 39 ++++++++++++++++---
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
index a4aacd3eb189..91c9b2a4687b 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
@@ -17,13 +17,14 @@ properties:
oneOf:
- items:
- enum:
- - mediatek,mt8173-jpgdec
- mediatek,mt2701-jpgdec
+ - mediatek,mt8173-jpgdec
- items:
- enum:
- mediatek,mt7623-jpgdec
- mediatek,mt8188-jpgdec
- const: mediatek,mt2701-jpgdec
+ - const: mediatek,mt8189-jpgdec
reg:
maxItems: 1
@@ -32,13 +33,22 @@ properties:
maxItems: 1
clocks:
+ minItems: 1
maxItems: 2
- minItems: 2
clock-names:
- items:
- - const: jpgdec-smi
- - const: jpgdec
+ minItems: 1
+ maxItems: 2
+ oneOf:
+ - items:
+ - const: jpgdec
+ - items:
+ - const: jpgdec-smi
+ - const: jpgdec
+
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
power-domains:
maxItems: 1
@@ -60,6 +70,25 @@ required:
- power-domains
- iommus
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8189-jpgdec
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ minItems: 2
+
additionalProperties: false
examples:
--
2.46.0
^ permalink raw reply related
* [PATCH v4 0/3] Mediatek MT8189 JPEG support
From: Jianhua Lin @ 2026-03-24 9:54 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
This series is based on tag: next-20260320, linux-next/master
Changes compared with v3:
- The v4 is resending the cover-letter, because the v3 cover-letter was
not sent successfully.
Changes compared with v2:
- Dropped the dts patch (arm64: dts: mt8188: update JPEG encoder/decoder
compatible) as it belongs to a different tree/series.
- Patches 1/3 (dt-bindings: decoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum`.
- Added an `allOf` block with conditional checks to enforce the single
clock ("jpgdec") requirement for MT8189, while preserving the
two-clock requirement for older SoCs.
- Updated commit message to reflect the schema structure changes and
hardware differences.
- Patches 2/3 (dt-bindings: encoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum` inside the `items` list, as it does not fallback to
"mediatek,mtk-jpgenc" due to 34-bit IOVA requirements.
- Updated commit message to explain the standalone compatible design.
- Patches 3/3 (media: mediatek: jpeg):
- Refined commit message for better clarity regarding 34-bit IOVA and
single clock configuration.
Changes compared with v1:
- Patches 1/4:
- Updating commit message
- Patches 2/4, 3/4:
- Updating commit message
- Adjusted property descriptions acorrding to hardware requirements
- Improved formatting for better readability and consistency
- Patches 4/4:
- Updating commit message
Jianhua Lin (3):
dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible
string
dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible
string
media: mediatek: jpeg: add compatible for MT8189 SoC
.../bindings/media/mediatek-jpeg-decoder.yaml | 39 +++++++++++++---
.../bindings/media/mediatek-jpeg-encoder.yaml | 20 ++++++---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++
3 files changed, 91 insertions(+), 12 deletions(-)
--
2.46.0
^ permalink raw reply
* Re: [GIT PULL] Reset controller fixes for v7.0, part 2
From: Philipp Zabel @ 2026-03-24 9:55 UTC (permalink / raw)
To: soc; +Cc: linux-arm-kernel, kernel
In-Reply-To: <20260324094255.3538772-1-p.zabel@pengutronix.de>
On Di, 2026-03-24 at 10:42 +0100, Philipp Zabel wrote:
> Dear arm-soc maintainers,
>
> The following changes since commit e0cf84109bc6c6768337123f1de24ff56b41c91b:
>
> reset: rzg2l-usbphy-ctrl: Check pwrrdy is valid before using it (2026-02-23 17:03:28 +0100)
>
> are available in the Git repository at:
>
> https://git.pengutronix.de/git/pza/linux.git tags/reset-fixes-for-v7.0-2
>
> for you to fetch changes up to a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b:
>
> reset: spacemit: k3: Decouple composite reset lines (2026-03-23 12:25:47 +0100)
>
> ----------------------------------------------------------------
> Reset controller fixes for v7.0, part 2
>
> * Decouple spacemit K3 reset lines that were incorrectly coupled
> together as one, but are in fact separate resets in hardware.
It is important that this makes v7.0, as it fixes an incorrect binding
that has not been part of a release and which has no users yet.
> * Fix a double free in the reset_add_gpio_aux_device() error path.
> This has already been fixed on reset/next by commit a9b95ce36de4
> ("reset: gpio: add a devlink between reset-gpio and its consumer").
Because of this, commit fbffb8c7c7bb ("reset: gpio: fix double free in
reset_add_gpio_aux_device() error path") introduces a merge conflict
with reset/next:
https://lore.kernel.org/all/acFRVzvV9Dww47v_@sirena.org.uk/
Should I resolve this myself by merging this tag in to reset/next as
well, before submitting reset updates for v7.1?
regards
Philipp
^ permalink raw reply
* [PATCH v4 2/3] dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-03-24 9:54 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260324095455.1437-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG encoder block found in the
MediaTek MT8189 SoC.
Unlike some previous SoCs, the MT8189 JPEG encoder requires 34-bit IOVA
address space support. Therefore, it is added as a standalone compatible
string without falling back to the generic "mediatek,mtk-jpgenc" to
ensure the driver applies the correct hardware-specific configurations.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-encoder.yaml | 20 ++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 5b15f8977f67..476b7122d3fc 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -14,13 +14,15 @@ description: |-
properties:
compatible:
- items:
- - enum:
- - mediatek,mt2701-jpgenc
- - mediatek,mt8183-jpgenc
- - mediatek,mt8186-jpgenc
- - mediatek,mt8188-jpgenc
- - const: mediatek,mtk-jpgenc
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-jpgenc
+ - mediatek,mt8183-jpgenc
+ - mediatek,mt8186-jpgenc
+ - mediatek,mt8188-jpgenc
+ - const: mediatek,mtk-jpgenc
+ - const: mediatek,mt8189-jpgenc
reg:
maxItems: 1
@@ -34,6 +36,10 @@ properties:
items:
- const: jpgenc
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
+
power-domains:
maxItems: 1
--
2.46.0
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: spi: Fix clock-names definition
From: Krzysztof Kozlowski @ 2026-03-24 9:55 UTC (permalink / raw)
To: Meiker Gao, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: Bayi Cheng, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, linux-spi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260324062835.1747943-2-ot_meiker.gao@mediatek.com>
On 24/03/2026 07:28, Meiker Gao wrote:
> Update the device tree binding for the Mediatek
> MT8196 NOR controller to require that the 'clock-names'
> property contains exactly six entries, in the strict order:
> "spi", "sf", "axi", "axi_s", "bclk", "27m".
>
> Signed-off-by: Meiker Gao <ot_meiker.gao@mediatek.com>
> Change-Id: I0542d6d726f1af34ef76c1a58ba4e4b02ec45fe6
You just sent multiple same patches with same errors.
Same feedback.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4 3/3] media: mediatek: jpeg: add compatible for MT8189 SoC
From: Jianhua Lin @ 2026-03-24 9:54 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260324095455.1437-1-jianhua.lin@mediatek.com>
Compared to the previous generation ICs, the MT8189 uses a 34-bit IOVA
address space (16GB) and requires a single clock configuration.
Therefore, add new compatible strings ("mediatek,mt8189-jpgenc" and
"mediatek,mt8189-jpgdec") along with their specific driver data to
support the JPEG encoder and decoder of the MT8189 SoC.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index c01124a349f6..c6fc5d228e20 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1866,6 +1866,10 @@ static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = {
{ .id = "jpgdec" },
};
+static struct clk_bulk_data mtk_jpeg_dec_clocks[] = {
+ { .id = "jpgdec" },
+};
+
static const struct mtk_jpeg_variant mt8173_jpeg_drvdata = {
.clks = mt8173_jpeg_dec_clocks,
.num_clks = ARRAY_SIZE(mt8173_jpeg_dec_clocks),
@@ -1897,6 +1901,38 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata = {
.multi_core = false,
};
+static const struct mtk_jpeg_variant mtk8189_jpegenc_drvdata = {
+ .clks = mtk_jpeg_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_clocks),
+ .formats = mtk_jpeg_enc_formats,
+ .num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+ .qops = &mtk_jpeg_enc_qops,
+ .irq_handler = mtk_jpeg_enc_irq,
+ .hw_reset = mtk_jpeg_enc_reset,
+ .m2m_ops = &mtk_jpeg_enc_m2m_ops,
+ .dev_name = "mtk-jpeg-enc",
+ .ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .support_34bit = true,
+};
+
+static const struct mtk_jpeg_variant mtk8189_jpegdec_drvdata = {
+ .clks = mtk_jpeg_dec_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_dec_clocks),
+ .formats = mtk_jpeg_dec_formats,
+ .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+ .qops = &mtk_jpeg_dec_qops,
+ .irq_handler = mtk_jpeg_dec_irq,
+ .hw_reset = mtk_jpeg_dec_reset,
+ .m2m_ops = &mtk_jpeg_dec_m2m_ops,
+ .dev_name = "mtk-jpeg-dec",
+ .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+ .support_34bit = true,
+};
+
static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
.formats = mtk_jpeg_enc_formats,
.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
@@ -1936,6 +1972,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
.compatible = "mediatek,mtk-jpgenc",
.data = &mtk_jpeg_drvdata,
},
+ {
+ .compatible = "mediatek,mt8189-jpgenc",
+ .data = &mtk8189_jpegenc_drvdata,
+ },
+ {
+ .compatible = "mediatek,mt8189-jpgdec",
+ .data = &mtk8189_jpegdec_drvdata,
+ },
{
.compatible = "mediatek,mt8195-jpgenc",
.data = &mtk8195_jpegenc_drvdata,
--
2.46.0
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: spi: Fix clock-names definition
From: Krzysztof Kozlowski @ 2026-03-24 9:54 UTC (permalink / raw)
To: Meiker Gao
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Bayi Cheng,
Project_Global_Chrome_Upstream_Group, sirius.wang, vince-wl.liu,
jh.hsu, linux-spi, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20260324032624.1708029-2-ot_meiker.gao@mediatek.com>
On Tue, Mar 24, 2026 at 11:26:17AM +0800, Meiker Gao wrote:
> Update the device tree binding for the Mediatek
> MT8196 NOR controller to require that the 'clock-names'
> property contains exactly six entries, in the strict order:
> "spi", "sf", "axi", "axi_s", "bclk", "27m".
>
> Signed-off-by: Meiker Gao <ot_meiker.gao@mediatek.com>
> Change-Id: I0542d6d726f1af34ef76c1a58ba4e4b02ec45fe6
Please do not send patches which were never checked with tools. Run
checkpatch.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH net-next 5/5] net: stmmac: dwmac-sofcpga: Drop the struct device reference
From: Russell King (Oracle) @ 2026-03-24 9:53 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Jakub Kicinski, davem, Eric Dumazet, Paolo Abeni,
Simon Horman, Maxime Coquelin, Alexandre Torgue, thomas.petazzoni,
Alexis Lothoré, Rohan G Thomas, Mun Yew Tham, netdev,
linux-kernel, linux-arm-kernel, linux-stm32
In-Reply-To: <20260324092102.687082-6-maxime.chevallier@bootlin.com>
On Tue, Mar 24, 2026 at 10:21:00AM +0100, Maxime Chevallier wrote:
> We keep a reference to our the struct device in the socfpga_dwmac priv
> structure, but now it's only ever used to produce logs in the
> .set_phy_mode() ops, that are specific to this driver.
>
> When we call that ops, we always have a ref to the struct device around,
> so let's pass it to .set_phy_mode(). We can now discard that reference
> from struct socfpga_dwmac.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index ae40de2ed8eb..1d7f0a57d288 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> @@ -53,14 +53,14 @@
>
> struct socfpga_dwmac;
> struct socfpga_dwmac_ops {
> - int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
> + int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv,
> + struct device *dev);
As you're changing the signature of this method, would it be more
sensible to put "struct device *dev" as the first arg, rather than
swapping the order below:
> @@ -552,7 +553,7 @@ static int socfpga_dwmac_init(struct device *dev, void *bsp_priv)
> {
> struct socfpga_dwmac *dwmac = bsp_priv;
>
> - return dwmac->ops->set_phy_mode(dwmac);
> + return dwmac->ops->set_phy_mode(dwmac, dev);
?
In either case:
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH net-next 4/5] net: stmmac: dwmac-socfpga: get the phy_mode with the dedicated helper
From: Russell King (Oracle) @ 2026-03-24 9:51 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Jakub Kicinski, davem, Eric Dumazet, Paolo Abeni,
Simon Horman, Maxime Coquelin, Alexandre Torgue, thomas.petazzoni,
Alexis Lothoré, Rohan G Thomas, Mun Yew Tham, netdev,
linux-kernel, linux-arm-kernel, linux-stm32
In-Reply-To: <20260324092102.687082-5-maxime.chevallier@bootlin.com>
On Tue, Mar 24, 2026 at 10:20:59AM +0100, Maxime Chevallier wrote:
> We enable/disable the sgmii_adapter in the .fix_mac_speed() ops based on
> the phy_mode used in the plat_data. We currently get it with :
>
> socfpga_dwmac
> ->dev
> ->drv_data
> ->netdev
> ->priv
> ->stmmac_priv
> ->plat
> ->phy_interface
>
> where we can get it with :
>
> socfpga_dwmac
> ->plat_data
> ->phy_interface (done by socfpga_get_plat_phymode)
>
> Use that helper here.
>
> Note that we are also being passed a phy_interface_t from the
> .fix_mac_speed() callback, provided by phylink.
>
> We can handle that in the future when dynamic interface selection is
> supported. We'd need to guarantee that we have a Lynx PCS to handle it.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Nice cleanup!
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH net-next 3/5] net: stmmac: dwmac-socfpga: Use the correct type for interface modes
From: Russell King (Oracle) @ 2026-03-24 9:49 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Jakub Kicinski, davem, Eric Dumazet, Paolo Abeni,
Simon Horman, Maxime Coquelin, Alexandre Torgue, thomas.petazzoni,
Alexis Lothoré, Rohan G Thomas, Mun Yew Tham, netdev,
linux-kernel, linux-arm-kernel, linux-stm32
In-Reply-To: <20260324092102.687082-4-maxime.chevallier@bootlin.com>
On Tue, Mar 24, 2026 at 10:20:58AM +0100, Maxime Chevallier wrote:
> The internal helper socfpga_get_plat_phymode() returns an int where we
> actually return a PHY_INTERFACE_MODE_xxx, use the correct type for this.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: mmc: hisilicon,hi3660-dw-mshc: Convert to DT schema
From: Krzysztof Kozlowski @ 2026-03-24 9:49 UTC (permalink / raw)
To: Bhargav Joshi
Cc: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, zhangfei.gao, linux-mmc, daniel.baluta, simona.toaca,
d-gole, m-chawdhry
In-Reply-To: <20260323194400.22886-2-rougueprince47@gmail.com>
On Tue, Mar 24, 2026 at 01:13:59AM +0530, Bhargav Joshi wrote:
> Convert the Hisilicon DesignWare Mobile Storage Host Controller
> (dw-mshc) bindings from text format to DT schema.
>
> As part of this conversion, the binding file is renamed from
> k3-dw-mshc.txt to hisilicon,hi3660-dw-mshc.yaml to align with compatible
> string naming conventions.
Old Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt binding
was saying clocks are biu+ciu, you have here reversed, so this needs
explanation in commit msg why (to match existing in-kernel DTS).
>
> Examples have been updated to pass schema validation.
>
> Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
> ---
> .../mmc/hisilicon,hi3660-dw-mshc.yaml | 111 ++++++++++++++++++
> .../devicetree/bindings/mmc/k3-dw-mshc.txt | 73 ------------
> 2 files changed, 111 insertions(+), 73 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
> delete mode 100644 Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
> new file mode 100644
> index 000000000000..6ba1a42a27ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/hisilicon,hi3660-dw-mshc.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/hisilicon,hi3660-dw-mshc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon specific extensions to the Synopsys Designware Mobile Storage Host Controller
> +
> +maintainers:
> + - Zhangfei Gao <zhangfei.gao@linaro.org>
> +
> +description:
> + The Synopsys designware mobile storage host controller is used to interface
> + a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
> + differences between the core Synopsys dw mshc controller properties described
> + by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
> + extensions to the Synopsys Designware Mobile Storage Host Controller.
> +
> +allOf:
> + - $ref: /schemas/mmc/synopsys-dw-mshc-common.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: hisilicon,hi3660-dw-mshc
This and last two entries should be one enum here.
> + - items:
> + - const: hisilicon,hi3670-dw-mshc
> + - const: hisilicon,hi3660-dw-mshc
> + - const: hisilicon,hi4511-dw-mshc
> + - const: hisilicon,hi6220-dw-mshc
Blank line
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: card interface unit clock
> + - description: bus interface unit clock
> +
> + clock-names:
> + items:
> + - const: ciu
> + - const: biu
> +
> + hisilicon,peripheral-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle of syscon used to control peripheral.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/hi3620-clock.h>
> +
> + mmc@fcd03000 {
> + compatible = "hisilicon,hi4511-dw-mshc";
> + reg = <0xfcd03000 0x1000>;
> + interrupts = <0 16 4>;
Use proper flags (GIC, trigger level).
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
> + clock-names = "ciu", "biu";
> + vmmc-supply = <&ldo12>;
> + fifo-depth = <0x100>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
> + bus-width = <4>;
> + disable-wp;
> + cd-gpios = <&gpio10 3 0>;
Same here
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + };
> +
> + - |
> + #include <dt-bindings/clock/hi6220-clock.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mmc@f723e000 {
> + compatible = "hisilicon,hi6220-dw-mshc";
"reg" goes here
> + bus-width = <0x4>;
That's not hex
> + disable-wp;
> + cap-sd-highspeed;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + card-detect-delay = <200>;
> + hisilicon,peripheral-syscon = <&ao_ctrl>;
> + reg = <0x0 0xf723e000 0x0 0x1000>;
> + interrupts = <0x0 0x49 0x4>;
These are not supposed to be hex...
> + clocks = <&clock_sys HI6220_MMC1_CIUCLK>,
> + <&clock_sys HI6220_MMC1_CLK>;
> + clock-names = "ciu", "biu";
> + cd-gpios = <&gpio1 0 1>;
> + pinctrl-names = "default", "idle";
> + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
> + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
> + vqmmc-supply = <&ldo7>;
> + vmmc-supply = <&ldo10>;
> + };
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH net-next 2/5] net: stmmac: dwmac-socfpga: Use the socfpga_sgmii_config() helper
From: Russell King (Oracle) @ 2026-03-24 9:48 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Jakub Kicinski, davem, Eric Dumazet, Paolo Abeni,
Simon Horman, Maxime Coquelin, Alexandre Torgue, thomas.petazzoni,
Alexis Lothoré, Rohan G Thomas, Mun Yew Tham, netdev,
linux-kernel, linux-arm-kernel, linux-stm32
In-Reply-To: <20260324092102.687082-3-maxime.chevallier@bootlin.com>
On Tue, Mar 24, 2026 at 10:20:57AM +0100, Maxime Chevallier wrote:
> Use the existing socfpga_sgmii_config() helper in
> socfpga_dwmac_fix_mac_speed(), instead of re-coding the register access.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH net-next 1/5] net: stmmac: dwmac-socfpga: Move internal helpers
From: Russell King (Oracle) @ 2026-03-24 9:48 UTC (permalink / raw)
To: Maxime Chevallier
Cc: Andrew Lunn, Jakub Kicinski, davem, Eric Dumazet, Paolo Abeni,
Simon Horman, Maxime Coquelin, Alexandre Torgue, thomas.petazzoni,
Alexis Lothoré, Rohan G Thomas, Mun Yew Tham, netdev,
linux-kernel, linux-arm-kernel, linux-stm32
In-Reply-To: <20260324092102.687082-2-maxime.chevallier@bootlin.com>
On Tue, Mar 24, 2026 at 10:20:56AM +0100, Maxime Chevallier wrote:
> This is preparatory work to allow reusing the SGMII configuration helper
> and the wrapper to get the interface in the fix_mac_speed() callback.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Thanks!
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH 0/6] media: synopsys: Add imx93 support
From: Michael Riesch @ 2026-03-24 9:46 UTC (permalink / raw)
To: Sakari Ailus, Frank Li
Cc: Mauro Carvalho Chehab, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, linux-media, linux-kernel,
devicetree, linux-arm-kernel, linux-rockchip, Guoniu Zhou, imx
In-Reply-To: <acJI3wYnl8_g4WpO@valkosipuli.retiisi.eu>
Hi all,
On 3/24/26 09:18, Sakari Ailus wrote:
> On Mon, Mar 23, 2026 at 03:10:44PM -0400, Frank Li wrote:
>> On Tue, Feb 10, 2026 at 12:11:07PM -0500, Frank Li wrote:
>>> This 3rd time try to support DW CSI2RX support for imx93.
>>>
>>
>> Laurent Pinchart and Sakari Ailus:
>>
>> I am not who will take care this patch?
>> original drivers/media/platform/synopsys/dw-mipi-csi2rx.c picked
>> by Sakari Ailus
>
> Michael seems to have questions on the last patch, too.
I.. don't.. think so. After digging a bit in my memory and lore, I found
a v3 of that series with my Reviewed-by [0]
[0]
https://lore.kernel.org/all/20260216-imx93-dw-csi2-v3-0-aabafee10923@nxp.com/
Best regards,
Michael
^ permalink raw reply
* [GIT PULL] Reset controller fixes for v7.0, part 2
From: Philipp Zabel @ 2026-03-24 9:42 UTC (permalink / raw)
To: soc; +Cc: linux-arm-kernel, kernel, Philipp Zabel
Dear arm-soc maintainers,
The following changes since commit e0cf84109bc6c6768337123f1de24ff56b41c91b:
reset: rzg2l-usbphy-ctrl: Check pwrrdy is valid before using it (2026-02-23 17:03:28 +0100)
are available in the Git repository at:
https://git.pengutronix.de/git/pza/linux.git tags/reset-fixes-for-v7.0-2
for you to fetch changes up to a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b:
reset: spacemit: k3: Decouple composite reset lines (2026-03-23 12:25:47 +0100)
----------------------------------------------------------------
Reset controller fixes for v7.0, part 2
* Decouple spacemit K3 reset lines that were incorrectly coupled
together as one, but are in fact separate resets in hardware.
* Fix a double free in the reset_add_gpio_aux_device() error path.
This has already been fixed on reset/next by commit a9b95ce36de4
("reset: gpio: add a devlink between reset-gpio and its consumer").
* Fix the MODULE_AUTHOR string in the rzg2l-usbphy-ctrl driver.
----------------------------------------------------------------
Biju Das (1):
reset: rzg2l-usbphy-ctrl: Fix malformed MODULE_AUTHOR string
Guangshuo Li (1):
reset: gpio: fix double free in reset_add_gpio_aux_device() error path
Yixun Lan (1):
reset: spacemit: k3: Decouple composite reset lines
drivers/reset/core.c | 1 -
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +-
drivers/reset/spacemit/reset-spacemit-k3.c | 60 +++++++++++++++-----------
include/dt-bindings/reset/spacemit,k3-resets.h | 48 +++++++++++++++------
4 files changed, 73 insertions(+), 38 deletions(-)
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: hisilicon: Rename dwmmc nodes to mmc
From: Krzysztof Kozlowski @ 2026-03-24 9:42 UTC (permalink / raw)
To: Bhargav Joshi
Cc: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, zhangfei.gao, linux-mmc, daniel.baluta, simona.toaca,
d-gole, m-chawdhry
In-Reply-To: <20260323194400.22886-3-rougueprince47@gmail.com>
On Tue, Mar 24, 2026 at 01:14:00AM +0530, Bhargav Joshi wrote:
> The core mmc devicetree schema expects mmc controller nodes to be named
> using '^mmc(@.*)?$' pattern.
>
> The legacy Hisilicon SoC files (hi3660, hi3670, and hi6220) previously
> used the 'dwmmc' prefix for their nodes. This caused warnings during
> dtbs_check.
>
> Rename the 'dwmmc' nodes to 'mmc' to comply with the standard schema and
> dtbs_check warnings. The legacy phandle labels are kept intact.
>
> Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
> ---
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++--
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 ++--
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 +++---
> 3 files changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: dts: ti: Enable overlays for am335x BeagleBoard devicetrees
From: Kory Maincent @ 2026-03-24 9:39 UTC (permalink / raw)
To: Kevin Hilman
Cc: Aaro Koskinen, Andreas Kemnade, Roger Quadros, Tony Lindgren,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Russell King,
Thomas Petazzoni, linux-omap, devicetree, linux-kernel,
linux-arm-kernel, dri-devel, Luca Ceresoli, Bajjuri Praneeth,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Louis Chauvet
In-Reply-To: <177275924369.1445909.1029086854461649971.b4-ty@baylibre.com>
Hello Kevin,
On Thu, 05 Mar 2026 17:07:23 -0800
Kevin Hilman <khilman@baylibre.com> wrote:
> On Mon, 16 Feb 2026 17:55:52 +0100, Kory Maincent (TI) wrote:
> > Allow overlays to be applied to am335x BeagleBoard boards. This adds
> > around ~40% to the total size of the DTB files on average.
> >
> >
>
> Applied, thanks!
>
> [1/3] ARM: dts: ti: Enable overlays for am335x BeagleBoard devicetrees
> commit: 18161bb01ede109fed41c66efa2624a4c27377f7
>
> Best regards,
Thanks for merging it.
I see that you have merged patch 1 and 2 in your for-next branch.
Is there a reason to not merge the patch 3? Are you waiting for a dts
maintainer ack?
Maybe I can resend only the 3rd patch to ping the dts maintainers.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mp-debix-model-a: Correct PAD settings for pmicirqgrp
From: Laurent Pinchart @ 2026-03-24 9:38 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Marco Felsch, Daniel Scally, devicetree, imx, linux-arm-kernel,
linux-kernel, Peng Fan, Kieran Bingham, Stefan Klug
In-Reply-To: <20260324-imx8mp-dts-fix-v1-1-df0eb2f62543@nxp.com>
Hi Peng,
Thank you for the patch.
On Tue, Mar 24, 2026 at 11:16:13AM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
> there is interrupt storm for i.MX8MP DEBIX Model A. Per schematic, there
> is no on board PULL-UP resistors for GPIO1_IO03, so need to set PAD
> PUE and PU together to make pull up work properly.
>
> Fixes: c86d350aae68e ("arm64: dts: Add device tree for the Debix Model A Board")
> Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Closes: https://lore.kernel.org/all/20260323105858.GA2185714@killaraus.ideasonboard.com/
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Frank, would you be able to handle this as a v7.0 regression fix ?
I think the same is needed for imx8mp-debix-som-a.dtsi, but I can't
confirm it as I don't have the schematics for the SoM, neither do I have
access to the board.
Dan, Kieran, Stefan, could one of you check if you get an interrupt
storm from the PMIC on v7.0 ?
> ---
> arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> index 9422beee30b29c5a551b08476c80fbff96af3439..df7489587e48ed0c678f11291f6f2b77082ade95 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> @@ -440,7 +440,7 @@ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>
> pinctrl_pmic: pmicirqgrp {
> fsl,pins = <
> - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
> + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
> >;
> };
>
>
> ---
> base-commit: 09c0f7f1bcdbc3c37a5a760cbec76bf18f278406
> change-id: 20260324-imx8mp-dts-fix-512530fe4dcd
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH 0/2] mmc: hisilicon: Convert dw-mshc bindings and fix dtbs
From: Zhangfei Gao @ 2026-03-24 9:38 UTC (permalink / raw)
To: Bhargav Joshi
Cc: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, linux-mmc, daniel.baluta, simona.toaca, d-gole,
m-chawdhry
In-Reply-To: <20260323194400.22886-1-rougueprince47@gmail.com>
On Tue, 24 Mar 2026 at 03:44, Bhargav Joshi <rougueprince47@gmail.com> wrote:
>
> This series converts the Hisilicon dw-mshc text bindings to DT schema
> format and cleans up legacy node names in Hisilicon board files.
>
> While testing the new YAML schema, dtbs_check flagged the hi3660,
> hi3670, and hi6220 SoC files for using the non-standard 'dwmmc' node
> name prefix. resulting in warnings.
>
> Patch 1 Convert to DT schema
> Patch 2 updates the Hisilicon dtsi files to use standard 'mmc'
> node name.
>
> Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
Thanks Bhargav
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
^ permalink raw reply
* [PATCH v1 7/7] arm64: dts: ti: k3-am62p-verdin: Add Zinnia
From: Francesco Dolcini @ 2026-03-24 9:37 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Francesco Dolcini, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260324093705.26730-1-francesco@dolcini.it>
From: Francesco Dolcini <francesco.dolcini@toradex.com>
Add Zinnia Carrier Board mated with Verdin AM62P.
It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O,
2 x 1GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector
for a modem, USB and SD card interfaces.
Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
.../boot/dts/ti/k3-am62p-verdin-zinnia.dtsi | 469 ++++++++++++++++++
.../ti/k3-am62p5-verdin-nonwifi-zinnia.dts | 22 +
.../dts/ti/k3-am62p5-verdin-wifi-zinnia.dts | 22 +
3 files changed, 513 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi
new file mode 100644
index 000000000000..84ae99dcdda3
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi
@@ -0,0 +1,469 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin AM62P SoM on Zinnia carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_zinnia_leds>;
+
+ /* LED1 Red - SODIMM 48 - LED1_R */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED1 Blue - SODIMM 46 - LED1_B */
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Red - SODIMM 44 - LED3_R */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Green - SODIMM 54 - LED3_G */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Blue - SODIMM 36 - LED3_B */
+ led-4 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Red - SODIMM 34 - LED4_R */
+ led-5 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Green - SODIMM 32 - LED4_G */
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Blue - SODIMM 30 - LED4_B */
+ led-7 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ zinnia-1v8-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_4 */
+ io-channels = <&som_adc 4>;
+ full-ohms = <39000>; /* 12K + 27K */
+ output-ohms = <27000>;
+ };
+
+ zinnia-3v3-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_3 */
+ io-channels = <&som_adc 5>;
+ full-ohms = <54000>; /* 27K + 27K */
+ output-ohms = <27000>;
+ };
+
+ zinnia-5v-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_2 */
+ io-channels = <&som_adc 6>;
+ full-ohms = <39000>; /* 27K + 12K */
+ output-ohms = <12000>;
+ };
+
+ /* Zinnia Power Supply Input Voltage */
+ zinnia-input-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_1 */
+ io-channels = <&som_adc 7>;
+ full-ohms = <204700>; /* 200K + 4.7K */
+ output-ohms = <4700>;
+ };
+};
+
+&main_pmx0 {
+ pinctrl_zinnia_leds: zinnia-leds-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x019c, PIN_INPUT, 7) /* (E24) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */
+ AM62PX_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */
+ AM62PX_IOPAD(0x01a4, PIN_INPUT, 7) /* (F24) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */
+ AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */
+ AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */
+ AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */
+ AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */
+ AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ pinctrl_zinnia_spi1_cs0_gpio: mcu-gpio0-11-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 7) /* (C7) WKUP_UART0_CTSn.GPIO0_11 */ /* SODIMM 143 */
+ >;
+ };
+};
+
+/* Verdin ETHs */
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
+
+ status = "okay";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+ status = "okay";
+
+ carrier_eth_phy: ethernet-phy@2 {
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&cpsw_port1 {
+ status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+ phy-handle = <&carrier_eth_phy>;
+ phy-mode = "rgmii-id";
+
+ status = "okay";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_1_reset>,
+ <&pinctrl_gpio_5>,
+ <&pinctrl_gpio_6>,
+ <&pinctrl_gpio_7>,
+ <&pinctrl_gpio_8>,
+ <&pinctrl_qspi1_io0_gpio>;
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "DI3_RB", /* SODIMM 56 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 40 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "DI2_RB", /* SODIMM 216 */
+ "DI2_EN", /* SODIMM 218 */ /* 50 */
+ "DO3_EN", /* SODIMM 220 */
+ "DI3_EN", /* SODIMM 222 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 60 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 90 */
+ "";
+};
+
+&main_gpio1 {
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 40 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 50 */
+ "";
+};
+
+/* Verdin I2C_1 */
+&main_i2c0 {
+ status = "okay";
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+ status = "okay";
+};
+
+/* Verdin SPI_1 */
+&main_spi1 {
+ pinctrl-0 = <&pinctrl_main_spi1>,
+ <&pinctrl_zinnia_spi1_cs0_gpio>,
+ <&pinctrl_spi1_cs_gpio>;
+ cs-gpios = <&mcu_gpio0 11 GPIO_ACTIVE_LOW>,
+ <&main_gpio0 7 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* Verdin UART_3, used as the Linux console */
+&main_uart0 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+ status = "okay";
+};
+
+&mcu_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_4>,
+ <&pinctrl_gpio_3>;
+ gpio-line-names =
+ "",
+ "DO1_EN", /* SODIMM 206 */
+ "DI1_EN", /* SODIMM 208 */
+ "DI1_RB", /* SODIMM 210 */
+ "DO2_EN", /* SODIMM 212 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb1 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1_RESET# */
+&verdin_pcie_1_reset_hog {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wkup_uart0>,
+ <&pinctrl_wkup_uart0_rts>;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts
new file mode 100644
index 000000000000..8abf4fe60e99
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5.dtsi"
+#include "k3-am62p-verdin.dtsi"
+#include "k3-am62p-verdin-nonwifi.dtsi"
+#include "k3-am62p-verdin-zinnia.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62P on Zinnia Board";
+ compatible = "toradex,verdin-am62p-nonwifi-zinnia",
+ "toradex,verdin-am62p-nonwifi",
+ "toradex,verdin-am62p",
+ "ti,am62p5";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts
new file mode 100644
index 000000000000..e1df7cffdf63
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5.dtsi"
+#include "k3-am62p-verdin.dtsi"
+#include "k3-am62p-verdin-wifi.dtsi"
+#include "k3-am62p-verdin-zinnia.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62P WB on Zinnia Board";
+ compatible = "toradex,verdin-am62p-wifi-zinnia",
+ "toradex,verdin-am62p-wifi",
+ "toradex,verdin-am62p",
+ "ti,am62p5";
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v1 0/7] arm64: dts: ti: verdin-am62[p]: Add Zinnia
From: Francesco Dolcini @ 2026-03-24 9:36 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Francesco Dolcini, linux-arm-kernel, devicetree, linux-kernel
From: Francesco Dolcini <francesco.dolcini@toradex.com>
Add Zinnia Carrier Board mated with Verdin AM62 and Verdin AM62P.
It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O,
2 x 1GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector
for a modem, USB and SD card interfaces.
Some small fixes and cleanup are done on the SOM dtsi file, in preparation
for the Zinnia addition.
Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board
Francesco Dolcini (7):
dt-bindings: arm: ti: Add verdin am62/am62p zinnia board
arm64: dts: ti: k3-am62-verdin: Fix SPI_1 GPIO CS pinctrl label
arm64: dts: ti: k3-am62-verdin: Split UART_2 pinctrl group
arm64: dts: ti: k3-am62-verdin: Add Zinnia
arm64: dts: ti: k3-am62p-verdin: Split UART_2 pinctrl group
arm64: dts: ti: k3-am62p-verdin: Add SPI_1_CS as GPIO
arm64: dts: ti: k3-am62p-verdin: Add Zinnia
.../devicetree/bindings/arm/ti/k3.yaml | 4 +
arch/arm64/boot/dts/ti/Makefile | 2 +
.../boot/dts/ti/k3-am62-verdin-zinnia.dtsi | 493 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 22 +-
.../dts/ti/k3-am625-verdin-nonwifi-zinnia.dts | 22 +
.../dts/ti/k3-am625-verdin-wifi-zinnia.dts | 22 +
.../boot/dts/ti/k3-am62p-verdin-zinnia.dtsi | 469 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 29 +-
.../ti/k3-am62p5-verdin-nonwifi-zinnia.dts | 22 +
.../dts/ti/k3-am62p5-verdin-wifi-zinnia.dts | 22 +
10 files changed, 1098 insertions(+), 9 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts
--
2.47.3
^ permalink raw reply
* [PATCH v1 4/7] arm64: dts: ti: k3-am62-verdin: Add Zinnia
From: Francesco Dolcini @ 2026-03-24 9:36 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Francesco Dolcini, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260324093705.26730-1-francesco@dolcini.it>
From: Francesco Dolcini <francesco.dolcini@toradex.com>
Add Zinnia Carrier Board mated with Verdin AM62.
It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O,
2 x 1GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector
for a modem, USB and SD card interfaces.
Link: https://www.toradex.com/products/carrier-board/zinnia-carrier-board
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../boot/dts/ti/k3-am62-verdin-zinnia.dtsi | 493 ++++++++++++++++++
.../dts/ti/k3-am625-verdin-nonwifi-zinnia.dts | 22 +
.../dts/ti/k3-am625-verdin-wifi-zinnia.dts | 22 +
4 files changed, 539 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 260e211ca277..08f325451038 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -19,11 +19,13 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-zinnia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi
new file mode 100644
index 000000000000..0ce8357797ed
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM on Zinnia carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_zinnia_leds>;
+
+ /* LED1 Red - SODIMM 48 - LED1_R */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED1 Blue - SODIMM 46 - LED1_B */
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Red - SODIMM 44 - LED3_R */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Green - SODIMM 54 - LED3_G */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED3 Blue - SODIMM 36 - LED3_B */
+ led-4 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Red - SODIMM 34 - LED4_R */
+ led-5 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Green - SODIMM 32 - LED4_G */
+ led-6 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* LED4 Blue - SODIMM 30 - LED4_B */
+ led-7 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <4>;
+ gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ zinnia-1v8-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_4 */
+ io-channels = <&verdin_som_adc 4>;
+ full-ohms = <39000>; /* 12K + 27K */
+ output-ohms = <27000>;
+ };
+
+ zinnia-3v3-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_3 */
+ io-channels = <&verdin_som_adc 5>;
+ full-ohms = <54000>; /* 27K + 27K */
+ output-ohms = <27000>;
+ };
+
+ zinnia-5v-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_2 */
+ io-channels = <&verdin_som_adc 6>;
+ full-ohms = <39000>; /* 27K + 12K */
+ output-ohms = <12000>;
+ };
+
+ /* Zinnia Power Supply Input Voltage */
+ zinnia-input-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_1 */
+ io-channels = <&verdin_som_adc 7>;
+ full-ohms = <204700>; /* 200K + 4.7K */
+ output-ohms = <4700>;
+ };
+};
+
+&main_pmx0 {
+ pinctrl_zinnia_leds: zinnia-leds-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */
+ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (B20) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */
+ AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (A19) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */
+ AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (A20) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */
+ AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L17) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */
+ AM62X_IOPAD(0x0098, PIN_INPUT, 7) /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */
+ AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */
+ AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ pinctrl_zinnia_spi1_cs0_gpio: mcu-gpio0-11-default-pins {
+ pinctrl-single,pins = <
+ AM62X_MCU_IOPAD(0x002c, PIN_INPUT, 7) /* (C6) WKUP_UART0_CTSn.GPIO0_11 */ /* SODIMM 143 */
+ >;
+ };
+};
+
+/* Verdin ETH */
+&cpsw3g {
+ status = "okay";
+};
+
+/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
+&cpsw3g_mdio {
+ status = "okay";
+
+ cpsw3g_phy1: ethernet-phy@2 {
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+/* Verdin ETH_1 */
+&cpsw_port1 {
+ status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&cpsw_port2 {
+ phy-handle = <&cpsw3g_phy1>;
+ phy-mode = "rgmii-id";
+
+ status = "okay";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
+ <&pinctrl_gpio_5>,
+ <&pinctrl_gpio_6>,
+ <&pinctrl_gpio_7>,
+ <&pinctrl_gpio_8>,
+ <&pinctrl_qspi1_io0_gpio>;
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "DI3_RB", /* SODIMM 56 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "DI2_EN", /* SODIMM 218 */
+ "",
+ "",
+ "",
+ "DI2_RB", /* SODIMM 216 */ /* 40 */
+ "DO3_EN", /* SODIMM 220 */
+ "DI3_EN", /* SODIMM 222 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 50 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 60 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+&main_gpio1 {
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 40 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 50 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 60 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+ status = "okay";
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+ status = "okay";
+};
+
+/* Verdin SPI_1 */
+&main_spi1 {
+ pinctrl-0 = <&pinctrl_spi1>,
+ <&pinctrl_zinnia_spi1_cs0_gpio>,
+ <&pinctrl_spi1_cs_gpio>;
+ cs-gpios = <&mcu_gpio0 11 GPIO_ACTIVE_LOW>,
+ <&main_gpio0 7 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* Verdin UART_3 */
+&main_uart0 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+ status = "okay";
+};
+
+&mcu_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_3>,
+ <&pinctrl_gpio_4>,
+ <&pinctrl_pcie_1_reset>;
+ gpio-line-names =
+ "",
+ "DO1_EN", /* SODIMM 206 */
+ "DI1_EN", /* SODIMM 208 */
+ "DI1_RB", /* SODIMM 210 */
+ "DO2_EN", /* SODIMM 212 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb1 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1_RESET# */
+&verdin_pcie_1_reset_hog {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wkup_uart0>, <&pinctrl_wkup_uart0_rts>;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts
new file mode 100644
index 000000000000..eba8d7a5b1bf
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-nonwifi.dtsi"
+#include "k3-am62-verdin-zinnia.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62 on Zinnia Board";
+ compatible = "toradex,verdin-am62-nonwifi-zinnia",
+ "toradex,verdin-am62-nonwifi",
+ "toradex,verdin-am62",
+ "ti,am625";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts
new file mode 100644
index 000000000000..6f3f8eb42ed6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/zinnia-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-wifi.dtsi"
+#include "k3-am62-verdin-zinnia.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62 WB on Zinnia Board";
+ compatible = "toradex,verdin-am62-wifi-zinnia",
+ "toradex,verdin-am62-wifi",
+ "toradex,verdin-am62",
+ "ti,am625";
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v1 6/7] arm64: dts: ti: k3-am62p-verdin: Add SPI_1_CS as GPIO
From: Francesco Dolcini @ 2026-03-24 9:37 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Francesco Dolcini, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260324093705.26730-1-francesco@dolcini.it>
From: Francesco Dolcini <francesco.dolcini@toradex.com>
Add a pinctrl to use SPI_1 CS as GPIO.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
---
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
index 1c4c951e5e94..7ee894d59113 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
@@ -247,6 +247,13 @@ AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */
>;
};
+ /* Verdin SPI_1_CS as GPIO */
+ pinctrl_spi1_cs_gpio: main-gpio0-7-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x001c, PIN_OUTPUT, 7) /* (N21) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */
+ >;
+ };
+
/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins {
pinctrl-single,pins = <
--
2.47.3
^ permalink raw reply related
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