* Re: [PATCH] arm64: dts: amlogic: t7: khadas-vim4: fix board model name
From: Neil Armstrong @ 2026-03-26 9:06 UTC (permalink / raw)
To: khilman, martin.blumenstingl, jbrunet, Nick Xie
Cc: krzk+dt, robh, conor+dt, linux-amlogic, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260306030756.2421841-1-nick@khadas.com>
Hi,
On Fri, 06 Mar 2026 11:07:56 +0800, Nick Xie wrote:
> Update the model property to "Khadas VIM4" to match the official
> product branding and maintain consistency with other Khadas boards
> (e.g., VIM1, VIM2, VIM3) in the kernel tree.
>
>
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/1] arm64: dts: amlogic: t7: khadas-vim4: fix board model name
https://git.kernel.org/amlogic/c/771d092af02a11ec565494052d18ddfb5e2f1428
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply
* Re: [PATCH] arm64: dts: amlogic: meson-gxl-s905d-phicomm-n1: add bluetooth node
From: Neil Armstrong @ 2026-03-26 9:06 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-amlogic, Jun Yan
Cc: martin.blumenstingl, jbrunet, khilman, conor+dt, krzk+dt, robh,
yangxuan8282
In-Reply-To: <20260213073810.552341-1-jerrysteve1101@gmail.com>
Hi,
On Fri, 13 Feb 2026 15:38:10 +0800, Jun Yan wrote:
> The Phicomm N1 uses a CY43455 (BCM43438) module with its Bluetooth
> interface connected to uart_A.
>
> Add the required device tree node to enable proper functionality.
>
>
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/1] arm64: dts: amlogic: meson-gxl-s905d-phicomm-n1: add bluetooth node
https://git.kernel.org/amlogic/c/d6df314c0165cb809d6c647a593664a4f5028230
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply
* Re: [PATCH] arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7
From: Neil Armstrong @ 2026-03-26 9:06 UTC (permalink / raw)
To: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Ronald Claveau
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20260305-fix-amlt7-gic-dts-v1-1-5944415c74bf@aliel.fr>
Hi,
On Thu, 05 Mar 2026 23:11:25 +0100, Ronald Claveau wrote:
> This patch aims to fix the GIC register ranges for Amlogic T7 SoC family.
>
> - Context
> Kernel log shows a warning about GIC
> [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
>
> Using cat /proc/interrupts command shows GIC as GIC-0
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/1] arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7
https://git.kernel.org/amlogic/c/dbb92c6f1ecd0dcd76a3d1002141f340737f55f2
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply
* Re: [PATCH v2 0/4] arm64: dts: amlogic: meson-s4-khadas-vim1s: enable LEDs, Keys and Bluetooth
From: Neil Armstrong @ 2026-03-26 9:06 UTC (permalink / raw)
To: khilman, martin.blumenstingl, jbrunet, krzk+dt, Nick Xie
Cc: robh, conor+dt, linux-amlogic, linux-arm-kernel, devicetree,
linux-kernel
In-Reply-To: <20260228063750.701887-1-nick@khadas.com>
Hi,
On Sat, 28 Feb 2026 14:37:46 +0800, Nick Xie wrote:
> This series enables various user interfaces and the Bluetooth module
> for the Khadas VIM1S board (Amlogic S905Y4).
>
> This builds upon the existing board support to fully enable the
> user-facing peripherals.
>
> Changes in v2:
> - Dropped the SARADC and Function Key patches from this series. As
> suggested by Martin Blumenstingl, a dedicated compatible string and
> driver update for the S4 SARADC will be submitted in a separate series
> to ensure forward compatibility.
> - Patch 1: Split the UART_A pinctrl definitions in meson-s4.dtsi into
> separate rx/tx and rts/cts groups to keep the SoC dtsi generic
> (Martin Blumenstingl).
> - Patch 2: Assigned the UART_A pinctrl groups directly in the board dts.
> - Added Martin's 'Reviewed-by' tags to Patches 2, 3, and 4.
> - Link to v1: https://lore.kernel.org/linux-amlogic/20260123022258.136448-1-nick@khadas.com/
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/4] arm64: dts: amlogic: meson-s4: add UART_A node
https://git.kernel.org/amlogic/c/6710d76d7e51a24f978eb1ae0738d1e3c25e034c
[2/4] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable bluetooth
https://git.kernel.org/amlogic/c/ad44c753b976e469f0f014b6f92e7180b6a7ba59
[3/4] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: add PWM LED support
https://git.kernel.org/amlogic/c/b8a95d4c054d9d2e784ce5eeb6a08be0ce9031d0
[4/4] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: add POWER key support
https://git.kernel.org/amlogic/c/31132e11e9dd97c706434e4f9e86b503c67a6bac
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply
* Re: [PATCH] arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0
From: Neil Armstrong @ 2026-03-26 9:06 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, devicetree, linux-arm-kernel,
linux-amlogic, linux-kernel, Anand Moon
In-Reply-To: <20260219103548.18392-1-linux.amoon@gmail.com>
Hi,
On Thu, 19 Feb 2026 16:05:46 +0530, Anand Moon wrote:
> Add missing L1 data and instruction cache parameters to the CPU node 0
> for the Cortex-A53 caches on the Meson AXG SoC.
>
>
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/1] arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0
https://git.kernel.org/amlogic/c/e28f4b18c134f944b0ae93ebf1bacc8e517fdcf5
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
^ permalink raw reply
* [PATCH 0/2] perf: marvell: Add CN20K DDR PMU support
From: Geetha sowjanya @ 2026-03-26 9:06 UTC (permalink / raw)
To: linux-perf-users, linux-kernel, linux-arm-kernel, devicetree
Cc: mark.rutland, will, krzk+dt
This series adds support for the Marvell CN20K DRAM Subsystem (DSS)
performance monitor in the existing marvell_cn10k_ddr_pmu driver, and
documents the device tree binding for the new compatible string.
The CN20K PMU provides eight programmable counters and two fixed
counters (DDR reads and writes). Patch 1 adds the devicetree schema for
"marvell,cn20k-ddr-pmu". Patch 2 wires OF and ACPI (MRVL000B) match
entries, adds CN20K register offsets and event maps, and refactors
platform data to use silicon variant flags.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Geetha sowjanya (2):
dt-bindings: perf: marvell: Document CN20K DDR PMU
perf: marvell: Add CN20K DDR PMU support
.../bindings/perf/marvell-cn20k-ddr.yaml | 37 ++++
drivers/perf/marvell_cn10k_ddr_pmu.c | 186 ++++++++++++++++--
2 files changed, 207 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
--
2.25.1
^ permalink raw reply
* [PATCH 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU
From: Geetha sowjanya @ 2026-03-26 9:06 UTC (permalink / raw)
To: linux-perf-users, linux-kernel, linux-arm-kernel, devicetree
Cc: mark.rutland, will, krzk+dt
In-Reply-To: <20260326090645.22590-1-gakula@marvell.com>
Add a devicetree binding for the Marvell CN20K DDR performance
monitor block, including the marvell,cn20k-ddr-pmu compatible
string and the required MMIO reg region.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
.../bindings/perf/marvell-cn20k-ddr.yaml | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
diff --git a/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
new file mode 100644
index 000000000000..6677d9eb4ba3
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/marvell-cn20k-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell CN20K DDR performance monitor
+
+maintainers:
+ - Geetha sowjanya <gakula@marvell.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - marvell,cn20k-ddr-pmu
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ddrcpmu {
+ compatible = "marvell,cn20k-ddr-pmu";
+ reg = <0xc200 0x00000000 0x0 0x100000>;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH 2/2] perf: marvell: Add CN20K DDR PMU support
From: Geetha sowjanya @ 2026-03-26 9:06 UTC (permalink / raw)
To: linux-perf-users, linux-kernel, linux-arm-kernel, devicetree
Cc: mark.rutland, will, krzk+dt
In-Reply-To: <20260326090645.22590-1-gakula@marvell.com>
The CN20K DRAM Subsystem exposes eight programmable
performance counters and two fixed counters for DDR
read and write traffic. Software selects events for
the programmable counters from traffic at the DDR PHY
interface, the CHI interconnect, or inside the DDR controller.
Add CN20K register offsets, event maps, and sysfs attributes;
match the device via OF (marvell,cn20k-ddr-pmu) and ACPI (MRVL000B).
Represent the SoC variant in platform data with bit flags so
CN20K can reuse the Odyssey PMU code path where appropriate.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
drivers/perf/marvell_cn10k_ddr_pmu.c | 187 ++++++++++++++++++++++++---
1 file changed, 171 insertions(+), 16 deletions(-)
diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index 72ac17efd846..7e2e1823b009 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -13,31 +13,43 @@
#include <linux/hrtimer.h>
#include <linux/acpi.h>
#include <linux/platform_device.h>
+#include <linux/bits.h>
+
+/* SoC variant flags for struct ddr_pmu_platform_data (mutually exclusive in pdata) */
+#define IS_CN10K BIT(0)
+#define IS_ODY BIT(1)
+#define IS_CN20K BIT(2)
/* Performance Counters Operating Mode Control Registers */
#define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
#define ODY_DDRC_PERF_CNT_OP_MODE_CTRL 0x20020
+#define CN20K_DDRC_PERF_CNT_OP_MODE_CTRL 0x20000
#define OP_MODE_CTRL_VAL_MANUAL 0x1
/* Performance Counters Start Operation Control Registers */
#define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028
#define ODY_DDRC_PERF_CNT_START_OP_CTRL 0x200A0
+#define CN20K_DDRC_PERF_CNT_START_OP_CTRL 0x20080
#define START_OP_CTRL_VAL_START 0x1ULL
#define START_OP_CTRL_VAL_ACTIVE 0x2
/* Performance Counters End Operation Control Registers */
#define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030
#define ODY_DDRC_PERF_CNT_END_OP_CTRL 0x200E0
+#define CN20K_DDRC_PERF_CNT_END_OP_CTRL 0x200C0
#define END_OP_CTRL_VAL_END 0x1ULL
/* Performance Counters End Status Registers */
#define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038
#define ODY_DDRC_PERF_CNT_END_STATUS 0x20120
+#define CN20K_DDRC_PERF_CNT_END_STATUS 0x20100
#define END_STATUS_VAL_END_TIMER_MODE_END 0x1
/* Performance Counters Configuration Registers */
#define CN10K_DDRC_PERF_CFG_BASE 0x8040
#define ODY_DDRC_PERF_CFG_BASE 0x20160
+#define CN20K_DDRC_PERF_CFG_BASE 0x20140
+#define CN20K_DDRC_PERF_CFG1_BASE 0x20180
/* 8 Generic event counter + 2 fixed event counters */
#define DDRC_PERF_NUM_GEN_COUNTERS 8
@@ -61,6 +73,23 @@
* DO NOT change these event-id numbers, they are used to
* program event bitmap in h/w.
*/
+
+/* CN20K specific events */
+#define EVENT_PERF_OP_IS_RD16 61
+#define EVENT_PERF_OP_IS_RD32 60
+#define EVENT_PERF_OP_IS_WR16 59
+#define EVENT_PERF_OP_IS_WR32 58
+#define EVENT_OP_IS_ENTER_DSM 44
+#define EVENT_OP_IS_RFM 43
+
+#define EVENT_CN20K_OP_IS_TCR_MRR 50
+#define EVENT_CN20K_OP_IS_DQSOSC_MRR 49
+#define EVENT_CN20K_OP_IS_DQSOSC_MPC 48
+#define EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_WR 47
+#define EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_RD 46
+#define EVENT_CN20K_OP_IS_ZQLATCH 21
+#define EVENT_CN20K_OP_IS_ZQSTART 22
+
#define EVENT_DFI_CMD_IS_RETRY 61
#define EVENT_RD_UC_ECC_ERROR 60
#define EVENT_RD_CRC_ERROR 59
@@ -87,6 +116,9 @@
#define EVENT_OP_IS_SPEC_REF 41
#define EVENT_OP_IS_CRIT_REF 40
#define EVENT_OP_IS_REFRESH 39
+#define EVENT_OP_IS_CAS_WCK_SUS 38
+#define EVENT_OP_IS_CAS_WS_OFF 37
+#define EVENT_OP_IS_CAS_WS 36
#define EVENT_OP_IS_ENTER_MPSM 35
#define EVENT_OP_IS_ENTER_POWERDOWN 31
#define EVENT_OP_IS_ENTER_SELFREF 27
@@ -183,8 +215,8 @@ struct ddr_pmu_platform_data {
u64 cnt_freerun_clr;
u64 cnt_value_wr_op;
u64 cnt_value_rd_op;
- bool is_cn10k;
- bool is_ody;
+ u64 cfg1_base;
+ unsigned int silicon_flags; /* IS_CN10K, IS_ODY, or IS_CN20K */
};
static ssize_t cn10k_ddr_pmu_event_show(struct device *dev,
@@ -336,6 +368,80 @@ static struct attribute *odyssey_ddr_perf_events_attrs[] = {
NULL
};
+static struct attribute *cn20k_ddr_perf_events_attrs[] = {
+ /* Programmable */
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_wr_data_access,
+ EVENT_DFI_WR_DATA_CYCLES),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_rd_data_access,
+ EVENT_DFI_RD_DATA_CYCLES),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access,
+ EVENT_HPR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access,
+ EVENT_LPR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access,
+ EVENT_WR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access,
+ EVENT_OP_IS_RD_OR_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access,
+ EVENT_OP_IS_RD_ACTIVATE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr,
+ EVENT_PRECHARGE_FOR_RDWR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other,
+ EVENT_PRECHARGE_FOR_OTHER),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown,
+ EVENT_OP_IS_ENTER_POWERDOWN),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_ws, EVENT_OP_IS_CAS_WS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_ws_off, EVENT_OP_IS_CAS_WS_OFF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cas_wck_sus, EVENT_OP_IS_CAS_WCK_SUS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rfm, EVENT_OP_IS_RFM),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_dsm, EVENT_OP_IS_ENTER_DSM),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cycles, EVENT_DFI_CYCLES),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,
+ EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr,
+ EVENT_CN20K_VISIBLE_WIN_LIMIT_REACHED_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_CN20K_OP_IS_DQSOSC_MPC),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_CN20K_OP_IS_DQSOSC_MRR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_CN20K_OP_IS_TCR_MRR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_CN20K_OP_IS_ZQSTART),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_CN20K_OP_IS_ZQLATCH),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_read16, EVENT_PERF_OP_IS_RD16),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_read32, EVENT_PERF_OP_IS_RD32),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_write16, EVENT_PERF_OP_IS_WR16),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_write32, EVENT_PERF_OP_IS_WR32),
+ /* Free run event counters */
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES),
+ NULL
+};
+
+static struct attribute_group cn20k_ddr_perf_events_attr_group = {
+ .name = "events",
+ .attrs = cn20k_ddr_perf_events_attrs,
+};
+
static struct attribute_group odyssey_ddr_perf_events_attr_group = {
.name = "events",
.attrs = odyssey_ddr_perf_events_attrs,
@@ -393,6 +499,13 @@ static const struct attribute_group *odyssey_attr_groups[] = {
NULL
};
+static const struct attribute_group *cn20k_attr_groups[] = {
+ &cn20k_ddr_perf_events_attr_group,
+ &cn10k_ddr_perf_format_attr_group,
+ &cn10k_ddr_perf_cpumask_attr_group,
+ NULL
+};
+
/* Default poll timeout is 100 sec, which is very sufficient for
* 48 bit counter incremented max at 5.6 GT/s, which may take many
* hours to overflow.
@@ -412,7 +525,7 @@ static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,
switch (eventid) {
case EVENT_DFI_PARITY_POISON ...EVENT_DFI_CMD_IS_RETRY:
- if (!ddr_pmu->p_data->is_ody) {
+ if (!(ddr_pmu->p_data->silicon_flags & IS_ODY)) {
err = -EINVAL;
break;
}
@@ -524,9 +637,9 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
int counter, bool enable)
{
const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ unsigned int silicon_flags = pmu->p_data->silicon_flags;
u64 ctrl_reg = pmu->p_data->cnt_op_mode_ctrl;
const struct ddr_pmu_ops *ops = pmu->ops;
- bool is_ody = pmu->p_data->is_ody;
u32 reg;
u64 val;
@@ -546,7 +659,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
writeq_relaxed(val, pmu->base + reg);
- if (is_ody) {
+ if (silicon_flags & IS_ODY) {
if (enable) {
/*
* Setup the PMU counter to work in
@@ -621,6 +734,7 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
{
struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ unsigned int silicon_flags = pmu->p_data->silicon_flags;
const struct ddr_pmu_ops *ops = pmu->ops;
struct hw_perf_event *hwc = &event->hw;
u8 config = event->attr.config;
@@ -642,10 +756,17 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
/* Generic counters, configure event id */
reg_offset = DDRC_PERF_CFG(p_data->cfg_base, counter);
- ret = ddr_perf_get_event_bitmap(config, &val, pmu);
- if (ret)
- return ret;
+ if (silicon_flags & IS_CN20K) {
+ val = (1ULL << (config - 1));
+ if (config == EVENT_CN20K_OP_IS_ZQSTART ||
+ config == EVENT_CN20K_OP_IS_ZQLATCH)
+ reg_offset = DDRC_PERF_CFG(p_data->cfg1_base, counter);
+ } else {
+ ret = ddr_perf_get_event_bitmap(config, &val, pmu);
+ if (ret)
+ return ret;
+ }
writeq_relaxed(val, pmu->base + reg_offset);
} else {
/* fixed event counter, clear counter value */
@@ -952,7 +1073,25 @@ static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata = {
.cnt_freerun_clr = 0,
.cnt_value_wr_op = CN10K_DDRC_PERF_CNT_VALUE_WR_OP,
.cnt_value_rd_op = CN10K_DDRC_PERF_CNT_VALUE_RD_OP,
- .is_cn10k = TRUE,
+ .silicon_flags = IS_CN10K,
+};
+
+static const struct ddr_pmu_platform_data cn20k_ddr_pmu_pdata = {
+ .counter_overflow_val = 0,
+ .counter_max_val = GENMASK_ULL(63, 0),
+ .cnt_base = ODY_DDRC_PERF_CNT_VALUE_BASE,
+ .cfg_base = CN20K_DDRC_PERF_CFG_BASE,
+ .cfg1_base = CN20K_DDRC_PERF_CFG1_BASE,
+ .cnt_op_mode_ctrl = CN20K_DDRC_PERF_CNT_OP_MODE_CTRL,
+ .cnt_start_op_ctrl = CN20K_DDRC_PERF_CNT_START_OP_CTRL,
+ .cnt_end_op_ctrl = CN20K_DDRC_PERF_CNT_END_OP_CTRL,
+ .cnt_end_status = CN20K_DDRC_PERF_CNT_END_STATUS,
+ .cnt_freerun_en = 0,
+ .cnt_freerun_ctrl = ODY_DDRC_PERF_CNT_FREERUN_CTRL,
+ .cnt_freerun_clr = ODY_DDRC_PERF_CNT_FREERUN_CLR,
+ .cnt_value_wr_op = ODY_DDRC_PERF_CNT_VALUE_WR_OP,
+ .cnt_value_rd_op = ODY_DDRC_PERF_CNT_VALUE_RD_OP,
+ .silicon_flags = IS_CN20K,
};
#endif
@@ -979,7 +1118,7 @@ static const struct ddr_pmu_platform_data odyssey_ddr_pmu_pdata = {
.cnt_freerun_clr = ODY_DDRC_PERF_CNT_FREERUN_CLR,
.cnt_value_wr_op = ODY_DDRC_PERF_CNT_VALUE_WR_OP,
.cnt_value_rd_op = ODY_DDRC_PERF_CNT_VALUE_RD_OP,
- .is_ody = TRUE,
+ .silicon_flags = IS_ODY,
};
#endif
@@ -989,8 +1128,7 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
struct cn10k_ddr_pmu *ddr_pmu;
struct resource *res;
void __iomem *base;
- bool is_cn10k;
- bool is_ody;
+ unsigned int silicon_flags;
char *name;
int ret;
@@ -1014,10 +1152,9 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
ddr_pmu->base = base;
ddr_pmu->p_data = dev_data;
- is_cn10k = ddr_pmu->p_data->is_cn10k;
- is_ody = ddr_pmu->p_data->is_ody;
+ silicon_flags = ddr_pmu->p_data->silicon_flags;
- if (is_cn10k) {
+ if (silicon_flags & IS_CN10K) {
ddr_pmu->ops = &ddr_pmu_ops;
/* Setup the PMU counter to work in manual mode */
writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base +
@@ -1039,7 +1176,7 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
};
}
- if (is_ody) {
+ if (silicon_flags & IS_ODY) {
ddr_pmu->ops = &ddr_pmu_ody_ops;
ddr_pmu->pmu = (struct pmu) {
@@ -1056,6 +1193,22 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
};
}
+ if (silicon_flags & IS_CN20K) {
+ ddr_pmu->ops = &ddr_pmu_ody_ops;
+
+ ddr_pmu->pmu = (struct pmu) {
+ .module = THIS_MODULE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = cn20k_attr_groups,
+ .event_init = cn10k_ddr_perf_event_init,
+ .add = cn10k_ddr_perf_event_add,
+ .del = cn10k_ddr_perf_event_del,
+ .start = cn10k_ddr_perf_event_start,
+ .stop = cn10k_ddr_perf_event_stop,
+ .read = cn10k_ddr_perf_event_update,
+ };
+ }
/* Choose this cpu to collect perf data */
ddr_pmu->cpu = raw_smp_processor_id();
@@ -1098,6 +1251,7 @@ static void cn10k_ddr_perf_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id cn10k_ddr_pmu_of_match[] = {
{ .compatible = "marvell,cn10k-ddr-pmu", .data = &cn10k_ddr_pmu_pdata },
+ { .compatible = "marvell,cn20k-ddr-pmu", .data = &cn20k_ddr_pmu_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
@@ -1107,6 +1261,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = {
{"MRVL000A", (kernel_ulong_t)&cn10k_ddr_pmu_pdata },
{"MRVL000C", (kernel_ulong_t)&odyssey_ddr_pmu_pdata},
+ {"MRVL000B", (kernel_ulong_t)&cn20k_ddr_pmu_pdata},
{},
};
MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match);
--
2.25.1
^ permalink raw reply related
* [PATCH] perf/arm-cmn: Fix incorrect error check for devm_ioremap()
From: Chen Ni @ 2026-03-26 9:08 UTC (permalink / raw)
To: will
Cc: robin.murphy, mark.rutland, ilkka, linux-arm-kernel,
linux-perf-users, Chen Ni
Check devm_ioremap() return value for NULL instead of ERR_PTR and return
-ENOMEM on failure. devm_ioremap() never returns ERR_PTR, using IS_ERR()
skips the error path and may cause a NULL pointer dereference.
Fixes: 5394396ff548 ("perf/arm-cmn: Stop claiming entire iomem region")
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
---
drivers/perf/arm-cmn.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c
index 1ac91cda6780..9fe00d0f4deb 100644
--- a/drivers/perf/arm-cmn.c
+++ b/drivers/perf/arm-cmn.c
@@ -2573,8 +2573,8 @@ static int arm_cmn_probe(struct platform_device *pdev)
/* Map the whole region now, claim the DTCs once we've found them */
cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
- if (IS_ERR(cmn->base))
- return PTR_ERR(cmn->base);
+ if (!cmn->base)
+ return -ENOMEM;
rootnode = arm_cmn_get_root(cmn, cfg);
if (rootnode < 0)
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: mmc: hisilicon,hi3660-dw-mshc: Convert to DT schema
From: Krzysztof Kozlowski @ 2026-03-26 9:17 UTC (permalink / raw)
To: Bhargav Joshi
Cc: devicetree, linux-arm-kernel, xuwei5, robh, krzk+dt, conor+dt,
ulf.hansson, zhangfei.gao, linux-mmc, daniel.baluta, simona.toaca,
d-gole, m-chawdhry, linux-kernel
In-Reply-To: <20260325225439.68161-2-rougueprince47@gmail.com>
On Thu, Mar 26, 2026 at 04:24:38AM +0530, Bhargav Joshi wrote:
> Convert the Hisilicon DesignWare Mobile Storage Host Controller
> (dw-mshc) bindings from text format to DT schema.
>
> As part of this conversion, the binding file is renamed from
> k3-dw-mshc.txt to hisilicon,hi3660-dw-mshc.yaml to align with compatible
> string naming conventions. Examples have been updated to pass schema
> validation.
>
> Note: synopsys-dw-mshc binding specifies clock names as "biu" followed
> by "ciu". However, this Hisilicon binding reverses the order to 'ciu'
> then 'biu' to match both the legacy text binding and in-kernel Hisilicon
> DTS board files.
>
> Signed-off-by: Bhargav Joshi <rougueprince47@gmail.com>
> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/9] arm64: dts: amlogic: t7: Add eMMC, SD card and SDIO pinctrl nodes
From: Ronald Claveau @ 2026-03-26 9:21 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
linux-mmc, linux-wireless, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ulf Hansson, Johannes Berg, van Spriel
In-Reply-To: <5298e691-99ba-48fc-874b-c9af308664ee@linaro.org>
On 3/26/26 9:52 AM, Neil Armstrong wrote:
> On 3/25/26 10:15, Ronald Claveau wrote:
>> These pinctrl nodes are required by the eMMC, SD card and SDIO drivers
>> to configure pin muxing at runtime.
>>
>> - eMMC: control, 4-bit/8-bit data, data strobe and clock gate pins
>> - SD card: data, clock, command and clock gate pins
>> - SDIO: data, clock, command and clock gate pins
>>
>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 98 +++++++++++++++++++
>> ++++++++++
>> 1 file changed, 98 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/
>> boot/dts/amlogic/amlogic-t7.dtsi
>> index 6510068bcff92..016b5429c8d1b 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -250,6 +250,104 @@ gpio: bank@4000 {
>> #gpio-cells = <2>;
>> gpio-ranges = <&periphs_pinctrl 0 0 157>;
>> };
>> +
>> + emmc_ctrl_pins: emmc-ctrl {
>> + mux-0 {
>> + groups = "emmc_cmd";
>> + function = "emmc";
>> + bias-pull-up;
>> + };
>> +
>> + mux-1 {
>> + groups = "emmc_clk";
>> + function = "emmc";
>> + bias-disable;
>> + };
>> + };
>> +
>> + emmc_data_4b_pins: emmc-data-4b {
>> + mux-0 {
>
> No need for "-0"
>
Thanks I will change that for the three nodes.
>> + groups = "emmc_nand_d0",
>> + "emmc_nand_d1",
>> + "emmc_nand_d2",
>> + "emmc_nand_d3";
>> + function = "emmc";
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + emmc_data_8b_pins: emmc-data-8b {
>> + mux-0 {
>
> No need for "-0"
>
>> + groups = "emmc_nand_d0",
>> + "emmc_nand_d1",
>> + "emmc_nand_d2",
>> + "emmc_nand_d3",
>> + "emmc_nand_d4",
>> + "emmc_nand_d5",
>> + "emmc_nand_d6",
>> + "emmc_nand_d7";
>> + function = "emmc";
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + emmc_ds_pins: emmc-ds {
>> + mux {
>> + groups = "emmc_nand_ds";
>> + function = "emmc";
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + emmc_clk_gate_pins: emmc-clk-gate {
>> + mux {
>> + groups = "GPIOB_8";
>> + function = "gpio_periphs";
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + sdcard_pins: sdcard {
>> + mux {
>> + groups = "sdcard_d0",
>> + "sdcard_d1",
>> + "sdcard_d2",
>> + "sdcard_d3",
>> + "sdcard_clk",
>> + "sdcard_cmd";
>> + function = "sdcard";
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + sdcard_clk_gate_pins: sdcard-clk-gate {
>> + mux {
>> + groups = "GPIOC_4";
>> + function = "gpio_periphs";
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + sdio_pins: sdio {
>> + mux-0 {
>
> No need for "-0"
>
>> + groups = "sdio_d0",
>> + "sdio_d1",
>> + "sdio_d2",
>> + "sdio_d3",
>> + "sdio_clk",
>> + "sdio_cmd";
>> + function = "sdio";
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + sdio_clk_gate_pins: sdio-clk-gate {
>> + mux {
>> + groups = "GPIOX_4";
>> + function = "gpio_periphs";
>> + bias-pull-up;
>> + };
>> + };
>> };
>> gpio_intc: interrupt-controller@4080 {
>>
>
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH v4 3/9] arm64: dts: amlogic: t7: Add MMC controller nodes
From: Ronald Claveau @ 2026-03-26 9:22 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
linux-mmc, linux-wireless, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ulf Hansson, Johannes Berg, van Spriel
In-Reply-To: <4b2ba22d-7d0b-4c71-ad83-46d198718fec@linaro.org>
On 3/26/26 9:52 AM, Neil Armstrong wrote:
> On 3/25/26 10:15, Ronald Claveau wrote:
>> Add device tree nodes for the three MMC controllers available
>> on the Amlogic T7 SoC, using amlogic,meson-axg-mmc as fallback
>> compatible.
>> All nodes are disabled by default and should be
>> enabled in the board-specific DTS file.
>>
>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 39 +++++++++++++++++++
>> ++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/
>> boot/dts/amlogic/amlogic-t7.dtsi
>> index 016b5429c8d1b..62c87d0ef7065 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -374,6 +374,45 @@ sec_ao: ao-secure@10220 {
>> reg = <0x0 0x10220 0x0 0x140>;
>> amlogic,has-chip-id;
>> };
>> +
>> + sd_emmc_a: mmc@88000 {
>> + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
>> + reg = <0x0 0x88000 0x0 0x800>;
>> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>
> move disabled at the end of the properties
>
Thanks I will do.
>> + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
>> + <&clkc_periphs CLKID_SD_EMMC_A>,
>> + <&scmi_clk CLKID_FCLK_DIV2>;
>> + clock-names = "core", "clkin0", "clkin1";
>> + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
>> + assigned-clock-parents = <&xtal>;
>> + };
>> +
>> + sd_emmc_b: mmc@8a000 {
>> + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
>> + reg = <0x0 0x8a000 0x0 0x800>;
>> + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
>> + status = "disabled";
> Ditto
>
>> + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
>> + <&clkc_periphs CLKID_SD_EMMC_B>,
>> + <&scmi_clk CLKID_FCLK_DIV2>;
>> + clock-names = "core", "clkin0", "clkin1";
>> + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
>> + assigned-clock-parents = <&xtal>;
>> + };
>> +
>> + sd_emmc_c: mmc@8c000 {
>> + compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
>> + reg = <0x0 0x8c000 0x0 0x800>;
>> + interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
>> + status = "disabled";
> Ditto
>> + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
>> + <&clkc_periphs CLKID_SD_EMMC_C>,
>> + <&scmi_clk CLKID_FCLK_DIV2>;
>> + clock-names = "core", "clkin0", "clkin1";
>> + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
>> + assigned-clock-parents = <&xtal>;
>> + };
>> };
>> };
>>
>
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH v4 8/9] dt-bindings: net: wireless: brcm: Add compatible for bcm43752
From: Ronald Claveau @ 2026-03-26 9:23 UTC (permalink / raw)
To: Rob Herring
Cc: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Johannes Berg,
van Spriel, linux-arm-kernel, linux-amlogic, devicetree,
linux-kernel, linux-mmc, linux-wireless
In-Reply-To: <20260325170922.GA3822305-robh@kernel.org>
On 3/25/26 6:09 PM, Rob Herring wrote:
> On Wed, Mar 25, 2026 at 10:15:26AM +0100, Ronald Claveau wrote:
>> Add bcm43752 compatible with its bcm4329 compatible fallback.
>>
>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>
> Missing Conor's ack.
>
Thanks for pointing that out, I will add it.
>> ---
>> Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
>> index 3be7576787644..81fd3e37452a6 100644
>> --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
>> +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml
>> @@ -42,6 +42,7 @@ properties:
>> - brcm,bcm4356-fmac
>> - brcm,bcm4359-fmac
>> - brcm,bcm4366-fmac
>> + - brcm,bcm43752-fmac
>> - cypress,cyw4373-fmac
>> - cypress,cyw43012-fmac
>> - infineon,cyw43439-fmac
>>
>> --
>> 2.49.0
>>
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH v11 0/9] Add support MT6316/6363/MT6373 PMICs regulators and MFD
From: Lee Jones @ 2026-03-26 9:25 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: AngeloGioacchino Del Regno, linux-mediatek, robh, krzk+dt,
conor+dt, matthias.bgg, lgirdwood, broonie, devicetree,
linux-kernel, linux-arm-kernel, kernel, igor.belwon
In-Reply-To: <20260326053449.GA910813@google.com>
On Thu, 26 Mar 2026, Chen-Yu Tsai wrote:
> On Fri, Nov 07, 2025 at 10:01:56AM +0100, AngeloGioacchino Del Regno wrote:
> > Il 06/11/25 17:11, Lee Jones ha scritto:
> > > On Mon, 27 Oct 2025, AngeloGioacchino Del Regno wrote:
> > >
> > > > Changes in v11:
> > > > - Removed unnecessary #address-cells in all mt6316 bindings
> > > >
> > > > Changes in v10:
> > > > - Added "struct" prefix to structs kerneldoc
> > > > - Renamed struct mtk_spmi_pmic_pdata to mtk_spmi_pmic_variant
> > > > - Added "REG_" to MT6363/73 mfd register definitions to disambiguate
> > > > - Expanded MTK_SPMI_PMIC_IRQ_GROUP macro parameter names as suggested
> > > > - Some rewording of comments as suggested, addition of more comments
> > > > - Refactored IRQ domain handling due to deprecation of function
> > > > irq_domain_add_tree() to use the new irq_domain_create_tree()
> > > > - Fixed to use generic_handle_domain_irq_safe() to avoid races
> > > > - Added support for two interrupt cells in translation
> > > > - Removed .irq_lock() and .irq_unlock() in favor of lockdep classes
> > > > - Added support for handling PMICs without IRQ Group register for
> > > > upcoming MT6685 implementation
> > >
> > > The MFD part looks okay.
> > >
> > > Let me know when you have all the Acks and the set is ready to be merged.
> > >
> >
> >
> > Lee, the regulators part was picked by Mark, so I guess you can take the MFD part
> > through your tree.
> >
> > I'm not sure if you can also take patch [7/9] (auxadc binding), but it would be
> > great if you could, because there is an auxadc example in the mfd binding that
> > needs that commit in order to succeed the binding check.
>
> Friendly ping. You might want to resend the remaining patches. Looks
> like they are all ready to be merged?
This is an _old_ set.
Please rebase it onto today's -next branch and provide a [RESEND].
--
Lee Jones [李琼斯]
^ permalink raw reply
* [PATCH v3 0/3] Add the missing mpll3 clock and clock controller nodes
From: Jian Hu @ 2026-03-26 9:26 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel, Ronald Claveau, Ferass El Hafidi
This series adds the missing mpll3 parent clock and completes the
Amlogic T7 SoC clock controller DT support.
- Fix redundant hyphen in for gp1 pll
- Add the missing mpll3 parent clock definition to t7-peripherals-clkc.yaml
- Add Amlogic T7 SoC clock controller nodes
Changes in v3 since v2 at [2]:
- Move Ronald's SoB tag to the top (as original author of the base patches)
- Add Krzysztof's Reviewed-by for Patch 2
- Update cover letter structure for clarity
Changes in v2 since v1 at [1]:
- Add Ronald Claveau's Signed-off-by to the first and third patches
- Fix compilation error for amlogic-peripherals-clkc.yaml
- Update commit message for amlogic-peripherals-clkc.yaml
- Add Fixes tag
- Remove the blank line in the watchdog node of meson-t7.dtsi
- Add 'reg' property to sram node
- Add a space after the clock controller label
### Background
This series is based on Ronald's initial T7 clock series [3], which aimed
to enable T7 EMMC DT but lacked a complete clock controller implementation.
The T7 clock tree in Ronald's series (fixed PLL, fixed fdivX and sys clocks)
is handled by the SCP firmware via SCMI [4]. Therefore, his clock drivers
do not need to be added. I have discussed with Ronald and agreed that I
will submit the T7 clock DT first, then he can proceed with his EMMC work.
### Series Overview
1. Patch 1: Fix redundant hyphen in amlogic,t7-pll-clkc DT binding
- Based on Ronald's "[3/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support"
2. Patch 2: Add missing mpll3 parent clock definition to t7-peripherals-clkc.yaml
3. Patch 3: Add complete T7 clock controller nodes
- Based on Ronald's initial PLL and peripheral clock nodes
- Remove unused fixed PLL node
- Add PCIe and HDMI PLL nodes
- Add SCMI clock nodes for clocks handled by SCP firmware
- Update fixed clock index in peripheral clock nodes
- Add gp1 and mpll1 clock index in peripheral clock nodes
### Dependencies
- Patch 3 depends on Patch 2
### ABI Risk
The amlogic,t7-peripherals-clkc DT binding was merged in v7.0-rc1 [5],
but the corresponding Amlogic T7 SoC DT has not been submitted upstream
yet. Thus, no real users or systems are affected by the DT binding ABI
breakage in this series.
### Credit
- Patch 1 is based on Ronald's "[PATCH 3/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support"
- Patch 3 is based on Ronald's "[6/7] arm64: dts: amlogic: Add clock and EMMC for T7"
- Patch 1 and Patch 3 retain Ronald's Signed-off-by
- Thanks to Ronald for pointing out the gp1 pll typo and initial clock work
[1]: https://lore.kernel.org/all/20260305074328.639993-1-jian.hu@amlogic.com
[2]: https://lore.kernel.org/all/20260313070022.700437-1-jian.hu@amlogic.com/
[3]: https://lore.kernel.org/all/20260218101709.35450-1-linux-kernel-dev@aliel.fr/
[4]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/amlogic,t7-scmi.h
[5]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml?h=v7.0-rc1
Jian Hu (3):
dt-bindings: clock: amlogic: Fix redundant hyphen in
"amlogic,t7-gp1--pll" string.
dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
arm64: dts: amlogic: t7: Add clock controller nodes
.../clock/amlogic,t7-peripherals-clkc.yaml | 12 +-
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 2 +-
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++
3 files changed, 134 insertions(+), 5 deletions(-)
--
2.47.1
^ permalink raw reply
* [PATCH v3 1/3] dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string.
From: Jian Hu @ 2026-03-26 9:26 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jian Hu, Ronald Claveau, devicetree, linux-clk, linux-amlogic,
linux-kernel, linux-arm-kernel, Ferass El Hafidi
In-Reply-To: <20260326092645.1053261-1-jian.hu@amlogic.com>
Fix redundant hyphen in "amlogic,t7-gp1--pll" string.
Fixes: 5437753728ac ("dt-bindings: clock: add Amlogic T7 PLL clock controller")
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
.../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
index 49c61f65deff..b488d92b7984 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -72,7 +72,7 @@ allOf:
contains:
enum:
- amlogic,t7-gp0-pll
- - amlogic,t7-gp1--pll
+ - amlogic,t7-gp1-pll
- amlogic,t7-hifi-pll
- amlogic,t7-pcie-pll
- amlogic,t7-mpll
--
2.47.1
^ permalink raw reply related
* [PATCH v3 3/3] arm64: dts: amlogic: t7: Add clock controller nodes
From: Jian Hu @ 2026-03-26 9:26 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jian Hu, Ronald Claveau, devicetree, linux-clk, linux-amlogic,
linux-kernel, linux-arm-kernel, Ferass El Hafidi
In-Reply-To: <20260326092645.1053261-1-jian.hu@amlogic.com>
Add the required clock controller nodes for Amlogic T7 SoC family:
- SCMI clock controller
- PLL clock controller
- Peripheral clock controller
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index 6510068bcff9..a610f642953d 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -6,6 +6,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/amlogic,t7-pwrc.h>
#include "amlogic-t7-reset.h"
+#include <dt-bindings/clock/amlogic,t7-scmi.h>
+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
/ {
interrupt-parent = <&gic>;
@@ -201,6 +204,34 @@ pwrc: power-controller {
};
};
+ sram@f7042000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0xf7042000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf7042000 0x100>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x820000c1>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -224,6 +255,42 @@ apb4: bus@fe000000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ clkc_periphs: clock-controller@0 {
+ compatible = "amlogic,t7-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x1c8>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&hifi CLKID_HIFI_PLL>,
+ <&gp0 CLKID_GP0_PLL>,
+ <&gp1 CLKID_GP1_PLL>,
+ <&mpll CLKID_MPLL1>,
+ <&mpll CLKID_MPLL2>,
+ <&mpll CLKID_MPLL3>;
+ clock-names = "xtal",
+ "sys",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "hifi",
+ "gp0",
+ "gp1",
+ "mpll1",
+ "mpll2",
+ "mpll3";
+ };
+
reset: reset-controller@2000 {
compatible = "amlogic,t7-reset";
reg = <0x0 0x2000 0x0 0x98>;
@@ -269,6 +336,64 @@ uart_a: serial@78000 {
status = "disabled";
};
+ gp0: clock-controller@8080 {
+ compatible = "amlogic,t7-gp0-pll";
+ reg = <0x0 0x8080 0x0 0x20>;
+ clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ gp1: clock-controller@80c0 {
+ compatible = "amlogic,t7-gp1-pll";
+ reg = <0x0 0x80c0 0x0 0x14>;
+ clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ hifi: clock-controller@8100 {
+ compatible = "amlogic,t7-hifi-pll";
+ reg = <0x0 0x8100 0x0 0x20>;
+ clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ pcie: clock-controller@8140 {
+ compatible = "amlogic,t7-pcie-pll";
+ reg = <0x0 0x8140 0x0 0x1c>;
+ clocks = <&scmi_clk CLKID_PCIE_OSC>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ mpll: clock-controller@8180 {
+ compatible = "amlogic,t7-mpll";
+ reg = <0x0 0x8180 0x0 0x28>;
+ clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ hdmi: clock-controller@81c0 {
+ compatible = "amlogic,t7-hdmi-pll";
+ reg = <0x0 0x81c0 0x0 0x20>;
+ clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
+ clock-names = "in0";
+ #clock-cells = <1>;
+ };
+
+ mclk: clock-controller@8300 {
+ compatible = "amlogic,t7-mclk-pll";
+ reg = <0x0 0x8300 0x0 0x18>;
+ clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
+ <&xtal>,
+ <&scmi_clk CLKID_FCLK_50M>;
+ clock-names = "in0", "in1", "in2";
+ #clock-cells = <1>;
+ };
+
sec_ao: ao-secure@10220 {
compatible = "amlogic,t7-ao-secure",
"amlogic,meson-gx-ao-secure",
--
2.47.1
^ permalink raw reply related
* [PATCH v3 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
From: Jian Hu @ 2026-03-26 9:26 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Stephen Boyd, Michael Turquette, robh+dt, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jian Hu, Krzysztof Kozlowski, devicetree, linux-clk,
linux-amlogic, linux-kernel, linux-arm-kernel, Ronald Claveau,
Ferass El Hafidi
In-Reply-To: <20260326092645.1053261-1-jian.hu@amlogic.com>
The mpll3 clock is one parent clock of the sd_emmc and mipi_isp clocks
on the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml
bindings. Add the mpll3 clock source to the T7 peripherals clock
controller input clock list, so that sd_emmc and mipi_isp can use it.
For logical consistency, place the required mpll3 entry before the
optional entry.
This change breaks the ABI, but while the amlogic,t7-peripherals-clkc
bindings have been merged upstream, the corresponding DT has not been
merged yet. Thus, no real users or systems are affected.
Fixes: b4156204e0f5 ("dt-bindings: clock: add Amlogic T7 peripherals clock controller")
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/clock/amlogic,t7-peripherals-clkc.yaml | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
index 55bb73707d58..a4b214a941ea 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
@@ -24,7 +24,7 @@ properties:
const: 1
clocks:
- minItems: 14
+ minItems: 15
items:
- description: input oscillator
- description: input sys clk
@@ -40,12 +40,13 @@ properties:
- description: input gp1 pll
- description: input mpll1
- description: input mpll2
+ - description: input mpll3
- description: external input rmii oscillator (optional)
- description: input video pll0 (optional)
- description: external pad input for rtc (optional)
clock-names:
- minItems: 14
+ minItems: 15
items:
- const: xtal
- const: sys
@@ -61,6 +62,7 @@ properties:
- const: gp1
- const: mpll1
- const: mpll2
+ - const: mpll3
- const: ext_rmii
- const: vid_pll0
- const: ext_rtc
@@ -97,7 +99,8 @@ examples:
<&gp0 1>,
<&gp1 1>,
<&mpll 4>,
- <&mpll 6>;
+ <&mpll 6>,
+ <&mpll 8>;
clock-names = "xtal",
"sys",
"fix",
@@ -111,6 +114,7 @@ examples:
"gp0",
"gp1",
"mpll1",
- "mpll2";
+ "mpll2",
+ "mpll3";
};
};
--
2.47.1
^ permalink raw reply related
* Re: [PATCH v4 9/9] arm64: dts: amlogic: t7: khadas-vim4: Add MMC nodes
From: Ronald Claveau @ 2026-03-26 9:27 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
linux-mmc, linux-wireless, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ulf Hansson, Johannes Berg, van Spriel
In-Reply-To: <512d95b5-5348-4c7c-961c-b6ca1431cee4@linaro.org>
On 3/26/26 9:54 AM, Neil Armstrong wrote:
> On 3/25/26 10:15, Ronald Claveau wrote:
>> Enable and configure the three MMC controllers for the Khadas VIM4 board:
>> - sd_emmc_a: SDIO interface for the BCM43752 Wi-Fi module
>> - sd_emmc_b: SD card slot
>> - sd_emmc_c: eMMC storage
>>
>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>> ---
>> .../dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 90 ++++++++++++
>> +++++++++-
>> 1 file changed, 89 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-
>> vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> index 770f06b0b16c7..5a73ae081036c 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
>> @@ -14,7 +14,10 @@ / {
>> compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";
>> aliases {
>> - serial0 = &uart_a;
>> + serial0 = &uart_a;
>
> Spurious change
>
Thanks I will keep space instead of tab here.
>> + mmc0 = &sd_emmc_c;
>> + mmc1 = &sd_emmc_b;
>> + mmc2 = &sd_emmc_a;
>> };
>> memory@0 {
>> @@ -159,6 +162,91 @@ &pwm_ab {
>> pinctrl-names = "default";
>> };
>> +/* SDIO */
>> +&sd_emmc_a {
>> + status = "okay";
>> + pinctrl-0 = <&sdio_pins>;
>> + pinctrl-1 = <&sdio_clk_gate_pins>;
>> + pinctrl-names = "default", "clk-gate";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + bus-width = <4>;
>> + cap-sd-highspeed;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> + cap-sdio-irq;
>> + max-frequency = <200000000>;
>> + non-removable;
>> + disable-wp;
>> + no-mmc;
>> + no-sd;
>> +
>> + power-domains = <&pwrc PWRC_T7_SDIO_A_ID>;
>> +
>> + keep-power-in-suspend;
>> +
>> + mmc-pwrseq = <&sdio_pwrseq>;
>> +
>> + vmmc-supply = <&vddao_3v3>;
>> + vqmmc-supply = <&vddao_1v8>;
>> +
>> + brcmf: wifi@1 {
>> + reg = <1>;
>> + compatible = "brcm,bcm43752-fmac", "brcm,bcm4329-fmac";
>> + };
>> +};
>> +
>> +/* SD card */
>> +&sd_emmc_b {
>> + status = "okay";
>> + pinctrl-0 = <&sdcard_pins>;
>> + pinctrl-1 = <&sdcard_clk_gate_pins>;
>> + pinctrl-names = "default", "clk-gate";
>> +
>> + bus-width = <4>;
>> + cap-sd-highspeed;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> + max-frequency = <200000000>;
>> + disable-wp;
>> + no-sdio;
>> + no-mmc;
>> +
>> + power-domains = <&pwrc PWRC_T7_SDIO_B_ID>;
>> +
>> + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
>> + vmmc-supply = <&sd_3v3>;
>> + vqmmc-supply = <&vddio_c>;
>> +};
>> +
>> +/* eMMC */
>> +&sd_emmc_c {
>> + status = "okay";
>> + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>,
>> <&emmc_ds_pins>;
>> + pinctrl-1 = <&emmc_clk_gate_pins>;
>> + pinctrl-names = "default", "clk-gate";
>> +
>> + bus-width = <8>;
>> + cap-mmc-highspeed;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + max-frequency = <200000000>;
>> + disable-wp;
>> + non-removable;
>> + no-sdio;
>> + no-sd;
>> +
>> + power-domains = <&pwrc PWRC_T7_EMMC_ID>;
>> +
>> + vmmc-supply = <&vddio_3v3>;
>> + vqmmc-supply = <&vddio_1v8>;
>> +};
>> +
>> &uart_a {
>> status = "okay";
>> clocks = <&xtal>, <&xtal>, <&xtal>;
>>
>
> With that:
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> Thanks,
> Neil
--
Best regards,
Ronald
^ permalink raw reply
* [PATCH] drm/exynos/dma: Drop iommu_dma_init_domain() stub
From: Chen-Yu Tsai @ 2026-03-26 9:30 UTC (permalink / raw)
To: Inki Dae, Seung-Woo Kim, Kyungmin Park, Krzysztof Kozlowski,
Alim Akhtar
Cc: Chen-Yu Tsai, David Airlie, Simona Vetter, dri-devel,
linux-samsung-soc, linux-arm-kernel, linux-kernel
Commit 1feda5eb77fc ("drm/exynos: Use selected dma_dev default iommu
domain instead of a fake one") removed the code around creating a
custom IOMMU domain, but forgot to remove the stub.
Remove the iommu_dma_init_domain() stub as the function is no longer
referenced, and was also made private to the IOMMU DMA code.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/gpu/drm/exynos/exynos_drm_dma.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dma.c b/drivers/gpu/drm/exynos/exynos_drm_dma.c
index 6a6761935224..ccc6b852ee7d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dma.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dma.c
@@ -23,10 +23,6 @@
#define to_dma_iommu_mapping(dev) NULL
#endif
-#if !defined(CONFIG_IOMMU_DMA)
-#define iommu_dma_init_domain(...) ({ -EINVAL; })
-#endif
-
#define EXYNOS_DEV_ADDR_START 0x20000000
#define EXYNOS_DEV_ADDR_SIZE 0x40000000
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply related
* Re: [PATCH] arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel nt37801
From: Ayushi Makhija @ 2026-03-26 9:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt,
dmitry.baryshkov, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, quic_rajeevny, quic_vproddut
In-Reply-To: <acHwvzjcvqNxUjm3@baldur>
[-- Attachment #1: Type: text/plain, Size: 1565 bytes --]
On 3/24/2026 7:34 AM, Bjorn Andersson wrote:
> On Mon, Mar 23, 2026 at 03:52:29PM +0530, Ayushi Makhija wrote:
>> The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
>> VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801.
>>
>
> Please add Fixes: tag.
Hi Bjorn,
Sure, will add in new patchset.
>
>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>
> Please start using your oss.qualcomm.com address.
>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> index 3837f6785320..6ba4e69bf377 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> @@ -462,7 +462,7 @@ vreg_l11b_1p0: ldo11 {
>>
>> vreg_l12b_1p8: ldo12 {
>> regulator-name = "vreg_l12b_1p8";
>> - regulator-min-microvolt = <1200000>;
>> + regulator-min-microvolt = <1650000>;
>
> Are you sure it's not supposed to be 1.8V, given the name of the rail?
>
> Regards,
> Bjorn
>
There was already discussion regarding the minimum voltage for this regulator for sm8550 target
on other upstream patch. Attaching the link of the patch.
This values is according to the NT37801 panel sec
"The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
VDDI=1.65V~1.95V."
Thanks,
Ayushi
>> regulator-max-microvolt = <1800000>;
>> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> regulator-allow-set-load;
>> --
>> 2.34.1
>>
[-- Attachment #2: https://lore.kernel.org/all/aQQdQoCLeKhYtY7W@yuanjiey.ap.qualcomm.com/ --]
[-- Type: text/html, Size: 4445 bytes --]
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel nt37801
From: Ayushi Makhija @ 2026-03-26 9:36 UTC (permalink / raw)
To: Bjorn Andersson
Cc: konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt,
dmitry.baryshkov, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, quic_rajeevny, quic_vproddut
In-Reply-To: <acHwvzjcvqNxUjm3@baldur>
On 3/24/2026 7:34 AM, Bjorn Andersson wrote:
> On Mon, Mar 23, 2026 at 03:52:29PM +0530, Ayushi Makhija wrote:
>> The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
>> VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801.
>>
>
> Please add Fixes: tag.
>
Hi Bjorn,
Sure, will add in new patchset.
>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>
> Please start using your oss.qualcomm.com address.
>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> index 3837f6785320..6ba4e69bf377 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> @@ -462,7 +462,7 @@ vreg_l11b_1p0: ldo11 {
>>
>> vreg_l12b_1p8: ldo12 {
>> regulator-name = "vreg_l12b_1p8";
>> - regulator-min-microvolt = <1200000>;
>> + regulator-min-microvolt = <1650000>;
>
> Are you sure it's not supposed to be 1.8V, given the name of the rail?
>
> Regards,
> Bjorn
There was already discussion regarding the minimum voltage for this regulator on sm8550 target
on other upstream patch.
Link: https://lore.kernel.org/all/aQQdQoCLeKhYtY7W@yuanjiey.ap.qualcomm.com/
This values is according to the NT37801 panel sec
"The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
VDDI=1.65V~1.95V."
Thanks,
Ayushi
>> regulator-max-microvolt = <1800000>;
>> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> regulator-allow-set-load;
>> --
>> 2.34.1
>>
^ permalink raw reply
* [PATCH 1/4] drm/exynos: Internalize exynos_drm_gem_free_object()
From: Chen-Yu Tsai @ 2026-03-26 9:43 UTC (permalink / raw)
To: Inki Dae, Seung-Woo Kim, Kyungmin Park, Krzysztof Kozlowski,
Alim Akhtar
Cc: Chen-Yu Tsai, David Airlie, Simona Vetter, dri-devel,
linux-samsung-soc, linux-arm-kernel, linux-kernel
In-Reply-To: <20260326094308.1161335-1-wenst@chromium.org>
exynos_drm_gem_free_object() is only provided as a callback for GEM
objects. It does not need to be exposed to the rest of the driver.
Move it above where it is used and internalize it to just the GEM
functions.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 10 +++++-----
drivers/gpu/drm/exynos/exynos_drm_gem.h | 3 ---
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 69ef6cda1ce9..59fd736a1fb9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -133,6 +133,11 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem *exynos_gem)
kfree(exynos_gem);
}
+static void exynos_drm_gem_free_object(struct drm_gem_object *obj)
+{
+ exynos_drm_gem_destroy(to_exynos_gem(obj));
+}
+
static const struct vm_operations_struct exynos_drm_gem_vm_ops = {
.open = drm_gem_vm_open,
.close = drm_gem_vm_close,
@@ -318,11 +323,6 @@ int exynos_drm_gem_get_ioctl(struct drm_device *dev, void *data,
return 0;
}
-void exynos_drm_gem_free_object(struct drm_gem_object *obj)
-{
- exynos_drm_gem_destroy(to_exynos_gem(obj));
-}
-
int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index 79d7e1a87419..8b5bd20ae8c1 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -88,9 +88,6 @@ static inline void exynos_drm_gem_put(struct exynos_drm_gem *exynos_gem)
int exynos_drm_gem_get_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-/* free gem object. */
-void exynos_drm_gem_free_object(struct drm_gem_object *obj);
-
/* create memory region for drm framebuffer. */
int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
struct drm_device *dev,
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply related
* [PATCH 2/4] drm/exynos: Use DRM core dedicated DMA device tracking facility
From: Chen-Yu Tsai @ 2026-03-26 9:43 UTC (permalink / raw)
To: Inki Dae, Seung-Woo Kim, Kyungmin Park, Krzysztof Kozlowski,
Alim Akhtar
Cc: Chen-Yu Tsai, David Airlie, Simona Vetter, dri-devel,
linux-samsung-soc, linux-arm-kernel, linux-kernel
In-Reply-To: <20260326094308.1161335-1-wenst@chromium.org>
The exynos driver tracks a dedicated DMA device in its private data.
The DRM core already has facilities to do this, and it is integrated
into DRM PRIME imports and GEM DMA helpers.
Convert the exynos driver to use the core's dedicated DMA device
tracking facility. Also get rid of exynos_drm_gem_prime_import() as
it is identical to drm_gem_prime_import() after the conversion.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/gpu/drm/exynos/exynos_drm_dma.c | 11 +++++-----
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.h | 8 --------
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 11 +++++-----
drivers/gpu/drm/exynos/exynos_drm_gem.c | 27 ++++++++++---------------
drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 --
6 files changed, 23 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dma.c b/drivers/gpu/drm/exynos/exynos_drm_dma.c
index ccc6b852ee7d..734741c80cbe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dma.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dma.c
@@ -8,6 +8,7 @@
#include <linux/iommu.h>
#include <linux/platform_device.h>
+#include <drm/drm_device.h>
#include <drm/drm_print.h>
#include <drm/exynos_drm.h>
@@ -41,7 +42,7 @@ static int drm_iommu_attach_device(struct drm_device *drm_dev,
struct exynos_drm_private *priv = drm_dev->dev_private;
int ret = 0;
- if (get_dma_ops(priv->dma_dev) != get_dma_ops(subdrv_dev)) {
+ if (get_dma_ops(drm_dev_dma_dev(drm_dev)) != get_dma_ops(subdrv_dev)) {
DRM_DEV_ERROR(subdrv_dev, "Device %s lacks support for IOMMU\n",
dev_name(subdrv_dev));
return -EINVAL;
@@ -93,8 +94,8 @@ int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
{
struct exynos_drm_private *priv = drm->dev_private;
- if (!priv->dma_dev) {
- priv->dma_dev = dev;
+ if (drm_dev_dma_dev(drm) == drm->dev) {
+ drm_dev_set_dma_dev(drm, dev);
DRM_INFO("Exynos DRM: using %s device for DMA mapping operations\n",
dev_name(dev));
}
@@ -109,7 +110,7 @@ int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
mapping = arm_iommu_create_mapping(dev,
EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE);
else if (IS_ENABLED(CONFIG_IOMMU_DMA))
- mapping = iommu_get_domain_for_dev(priv->dma_dev);
+ mapping = iommu_get_domain_for_dev(dev);
if (!mapping)
return -ENODEV;
@@ -135,5 +136,5 @@ void exynos_drm_cleanup_dma(struct drm_device *drm)
arm_iommu_release_mapping(priv->mapping);
priv->mapping = NULL;
- priv->dma_dev = NULL;
+ drm_dev_set_dma_dev(drm, NULL);
}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 2101a74dc1ed..9ee30086879f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -109,7 +109,6 @@ static const struct drm_driver exynos_drm_driver = {
.open = exynos_drm_open,
.postclose = exynos_drm_postclose,
.dumb_create = exynos_drm_gem_dumb_create,
- .gem_prime_import = exynos_drm_gem_prime_import,
.gem_prime_import_sg_table = exynos_drm_gem_prime_import_sg_table,
EXYNOS_DRM_FBDEV_DRIVER_OPS,
.ioctls = exynos_ioctls,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 06c29ff2aac0..1ab7195d09ae 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -198,7 +198,6 @@ struct drm_exynos_file_private {
*/
struct exynos_drm_private {
struct device *g2d_dev;
- struct device *dma_dev;
struct device *vidi_dev;
void *mapping;
@@ -208,13 +207,6 @@ struct exynos_drm_private {
wait_queue_head_t wait;
};
-static inline struct device *to_dma_dev(struct drm_device *dev)
-{
- struct exynos_drm_private *priv = dev->dev_private;
-
- return priv->dma_dev;
-}
-
static inline bool is_drm_iommu_supported(struct drm_device *drm_dev)
{
struct exynos_drm_private *priv = drm_dev->dev_private;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 348603262af0..85a3a247dfca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -20,6 +20,7 @@
#include <linux/uaccess.h>
#include <linux/workqueue.h>
+#include <drm/drm_device.h>
#include <drm/drm_file.h>
#include <drm/drm_print.h>
#include <drm/exynos_drm.h>
@@ -278,7 +279,7 @@ static int g2d_init_cmdlist(struct g2d_data *g2d)
g2d->cmdlist_dma_attrs = DMA_ATTR_WRITE_COMBINE;
- g2d->cmdlist_pool_virt = dma_alloc_attrs(to_dma_dev(g2d->drm_dev),
+ g2d->cmdlist_pool_virt = dma_alloc_attrs(drm_dev_dma_dev(g2d->drm_dev),
G2D_CMDLIST_POOL_SIZE,
&g2d->cmdlist_pool, GFP_KERNEL,
g2d->cmdlist_dma_attrs);
@@ -311,7 +312,7 @@ static int g2d_init_cmdlist(struct g2d_data *g2d)
return 0;
err:
- dma_free_attrs(to_dma_dev(g2d->drm_dev), G2D_CMDLIST_POOL_SIZE,
+ dma_free_attrs(drm_dev_dma_dev(g2d->drm_dev), G2D_CMDLIST_POOL_SIZE,
g2d->cmdlist_pool_virt,
g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
return ret;
@@ -322,7 +323,7 @@ static void g2d_fini_cmdlist(struct g2d_data *g2d)
kfree(g2d->cmdlist_node);
if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) {
- dma_free_attrs(to_dma_dev(g2d->drm_dev),
+ dma_free_attrs(drm_dev_dma_dev(g2d->drm_dev),
G2D_CMDLIST_POOL_SIZE,
g2d->cmdlist_pool_virt,
g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
@@ -397,7 +398,7 @@ static void g2d_userptr_put_dma_addr(struct g2d_data *g2d,
return;
out:
- dma_unmap_sgtable(to_dma_dev(g2d->drm_dev), g2d_userptr->sgt,
+ dma_unmap_sgtable(drm_dev_dma_dev(g2d->drm_dev), g2d_userptr->sgt,
DMA_BIDIRECTIONAL, 0);
unpin_user_pages_dirty_lock(g2d_userptr->pages, g2d_userptr->npages,
@@ -506,7 +507,7 @@ static dma_addr_t *g2d_userptr_get_dma_addr(struct g2d_data *g2d,
g2d_userptr->sgt = sgt;
- ret = dma_map_sgtable(to_dma_dev(g2d->drm_dev), sgt,
+ ret = dma_map_sgtable(drm_dev_dma_dev(g2d->drm_dev), sgt,
DMA_BIDIRECTIONAL, 0);
if (ret) {
DRM_DEV_ERROR(g2d->dev, "failed to map sgt with dma region.\n");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 59fd736a1fb9..9ec76163609f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -10,6 +10,7 @@
#include <linux/shmem_fs.h>
#include <linux/module.h>
+#include <drm/drm_device.h>
#include <drm/drm_dumb_buffers.h>
#include <drm/drm_prime.h>
#include <drm/drm_print.h>
@@ -29,7 +30,7 @@ static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem, bool kvmap)
unsigned long attr = 0;
if (exynos_gem->dma_addr) {
- DRM_DEV_DEBUG_KMS(to_dma_dev(dev), "already allocated.\n");
+ DRM_DEV_DEBUG_KMS(drm_dev_dma_dev(dev), "already allocated.\n");
return 0;
}
@@ -54,18 +55,18 @@ static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem, bool kvmap)
attr |= DMA_ATTR_NO_KERNEL_MAPPING;
exynos_gem->dma_attrs = attr;
- exynos_gem->cookie = dma_alloc_attrs(to_dma_dev(dev), exynos_gem->size,
+ exynos_gem->cookie = dma_alloc_attrs(drm_dev_dma_dev(dev), exynos_gem->size,
&exynos_gem->dma_addr, GFP_KERNEL,
exynos_gem->dma_attrs);
if (!exynos_gem->cookie) {
- DRM_DEV_ERROR(to_dma_dev(dev), "failed to allocate buffer.\n");
+ DRM_DEV_ERROR(drm_dev_dma_dev(dev), "failed to allocate buffer.\n");
return -ENOMEM;
}
if (kvmap)
exynos_gem->kvaddr = exynos_gem->cookie;
- DRM_DEV_DEBUG_KMS(to_dma_dev(dev), "dma_addr(0x%lx), size(0x%lx)\n",
+ DRM_DEV_DEBUG_KMS(drm_dev_dma_dev(dev), "dma_addr(0x%lx), size(0x%lx)\n",
(unsigned long)exynos_gem->dma_addr, exynos_gem->size);
return 0;
}
@@ -82,7 +83,7 @@ static void exynos_drm_free_buf(struct exynos_drm_gem *exynos_gem)
DRM_DEV_DEBUG_KMS(dev->dev, "dma_addr(0x%lx), size(0x%lx)\n",
(unsigned long)exynos_gem->dma_addr, exynos_gem->size);
- dma_free_attrs(to_dma_dev(dev), exynos_gem->size, exynos_gem->cookie,
+ dma_free_attrs(drm_dev_dma_dev(dev), exynos_gem->size, exynos_gem->cookie,
(dma_addr_t)exynos_gem->dma_addr,
exynos_gem->dma_attrs);
}
@@ -101,7 +102,7 @@ static int exynos_drm_gem_handle_create(struct drm_gem_object *obj,
if (ret)
return ret;
- DRM_DEV_DEBUG_KMS(to_dma_dev(obj->dev), "gem handle = 0x%x\n", *handle);
+ DRM_DEV_DEBUG_KMS(drm_dev_dma_dev(obj->dev), "gem handle = 0x%x\n", *handle);
/* drop reference from allocate - handle holds it now. */
drm_gem_object_put(obj);
@@ -113,7 +114,7 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem *exynos_gem)
{
struct drm_gem_object *obj = &exynos_gem->base;
- DRM_DEV_DEBUG_KMS(to_dma_dev(obj->dev), "handle count = %d\n",
+ DRM_DEV_DEBUG_KMS(drm_dev_dma_dev(obj->dev), "handle count = %d\n",
obj->handle_count);
/*
@@ -289,7 +290,7 @@ static int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem *exynos_gem,
if (vm_size > exynos_gem->size)
return -EINVAL;
- ret = dma_mmap_attrs(to_dma_dev(drm_dev), vma, exynos_gem->cookie,
+ ret = dma_mmap_attrs(drm_dev_dma_dev(drm_dev), vma, exynos_gem->cookie,
exynos_gem->dma_addr, exynos_gem->size,
exynos_gem->dma_attrs);
if (ret < 0) {
@@ -372,7 +373,7 @@ static int exynos_drm_gem_mmap(struct drm_gem_object *obj, struct vm_area_struct
vm_flags_set(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP);
- DRM_DEV_DEBUG_KMS(to_dma_dev(obj->dev), "flags = 0x%x\n",
+ DRM_DEV_DEBUG_KMS(drm_dev_dma_dev(obj->dev), "flags = 0x%x\n",
exynos_gem->flags);
/* non-cachable as default. */
@@ -398,12 +399,6 @@ static int exynos_drm_gem_mmap(struct drm_gem_object *obj, struct vm_area_struct
}
/* low-level interface prime helpers */
-struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev,
- struct dma_buf *dma_buf)
-{
- return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev));
-}
-
struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
{
struct exynos_drm_gem *exynos_gem = to_exynos_gem(obj);
@@ -415,7 +410,7 @@ struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
if (!sgt)
return ERR_PTR(-ENOMEM);
- ret = dma_get_sgtable_attrs(to_dma_dev(drm_dev), sgt, exynos_gem->cookie,
+ ret = dma_get_sgtable_attrs(drm_dev_dma_dev(drm_dev), sgt, exynos_gem->cookie,
exynos_gem->dma_addr, exynos_gem->size,
exynos_gem->dma_attrs);
if (ret) {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h
index 8b5bd20ae8c1..b6785f1136ab 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h
@@ -94,8 +94,6 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
struct drm_mode_create_dumb *args);
/* low-level interface prime helpers */
-struct drm_gem_object *exynos_drm_gem_prime_import(struct drm_device *dev,
- struct dma_buf *dma_buf);
struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);
struct drm_gem_object *
exynos_drm_gem_prime_import_sg_table(struct drm_device *dev,
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply related
* [PATCH 0/4] drm/exynos: Random cleanups
From: Chen-Yu Tsai @ 2026-03-26 9:43 UTC (permalink / raw)
To: Inki Dae, Seung-Woo Kim, Kyungmin Park, Krzysztof Kozlowski,
Alim Akhtar
Cc: Chen-Yu Tsai, David Airlie, Simona Vetter, dri-devel,
linux-samsung-soc, linux-arm-kernel, linux-kernel
Hi,
Here are some cleanups for the exynos drm driver. This was done as part
of the conversion of the driver to GEM DMA helpers. These patches have
no dependency, unlike the actual conversion, so I am sending them
separately for inclusion now.
Please take a look.
Thanks
ChenYu
Chen-Yu Tsai (4):
drm/exynos: Internalize exynos_drm_gem_free_object()
drm/exynos: Use DRM core dedicated DMA device tracking facility
drm/exynos: Drop exynos_drm_gem.size field
drm/exynos: Drop MAX_FB_BUFFER in favor of DRM_FORMAT_MAX_PLANES
drivers/gpu/drm/exynos/exynos_drm_dma.c | 11 +++---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 1 -
drivers/gpu/drm/exynos/exynos_drm_drv.h | 9 -----
drivers/gpu/drm/exynos/exynos_drm_fb.c | 6 +--
drivers/gpu/drm/exynos/exynos_drm_g2d.c | 13 ++++---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 50 +++++++++++--------------
drivers/gpu/drm/exynos/exynos_drm_gem.h | 8 ----
drivers/gpu/drm/exynos/exynos_drm_ipp.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_ipp.h | 4 +-
9 files changed, 41 insertions(+), 63 deletions(-)
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply
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