* [PATCH v1 2/7] drivers/clocksource/rockchip: Use the TIMER_PDEV_DECLARE() macro
From: Daniel Lezcano @ 2026-03-27 17:55 UTC (permalink / raw)
To: daniel.lezcano, tglx, zhipeng.wang_1
Cc: shawnguo, jstultz, linux-kernel, Heiko Stuebner,
moderated list:ARM/Rockchip SoC support,
open list:ARM/Rockchip SoC support
In-Reply-To: <20260327175533.3044-1-daniel.lezcano@kernel.org>
The previous change introduce the TIMER_PDEV_DECLARE() marco which
allows to use the platform driver to initialize a timer driver with
the benefit of having the devres to rollback automatically in case of
error.
Use this macro and change the function to rely on the devm_ variants,
allowing to cleanup the code.
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
---
drivers/clocksource/timer-rockchip.c | 99 ++++++++++------------------
1 file changed, 34 insertions(+), 65 deletions(-)
diff --git a/drivers/clocksource/timer-rockchip.c b/drivers/clocksource/timer-rockchip.c
index 540a16667145..486bbffba464 100644
--- a/drivers/clocksource/timer-rockchip.c
+++ b/drivers/clocksource/timer-rockchip.c
@@ -124,18 +124,18 @@ static u64 notrace rk_timer_sched_read(void)
return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
}
-static int __init
-rk_timer_probe(struct rk_timer *timer, struct device_node *np)
+static int rk_timer_init(struct rk_timer *timer, struct device *dev)
{
+ struct device_node *np = dev->of_node;
struct clk *timer_clk;
struct clk *pclk;
- int ret = -EINVAL, irq;
+ int irq;
u32 ctrl_reg = TIMER_CONTROL_REG3288;
- timer->base = of_iomap(np, 0);
- if (!timer->base) {
+ timer->base = devm_of_iomap(dev, np, 0, NULL);
+ if (IS_ERR(timer->base)) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
- return -ENXIO;
+ return PTR_ERR(timer->base);
}
if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
@@ -143,31 +143,17 @@ rk_timer_probe(struct rk_timer *timer, struct device_node *np)
timer->ctrl = timer->base + ctrl_reg;
- pclk = of_clk_get_by_name(np, "pclk");
+ pclk = devm_clk_get_enabled(dev, "pclk");
if (IS_ERR(pclk)) {
- ret = PTR_ERR(pclk);
pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
- goto out_unmap;
- }
-
- ret = clk_prepare_enable(pclk);
- if (ret) {
- pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
- goto out_unmap;
+ return PTR_ERR(pclk);
}
timer->pclk = pclk;
- timer_clk = of_clk_get_by_name(np, "timer");
+ timer_clk = devm_clk_get_enabled(dev, "timer");
if (IS_ERR(timer_clk)) {
- ret = PTR_ERR(timer_clk);
pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
- goto out_timer_clk;
- }
-
- ret = clk_prepare_enable(timer_clk);
- if (ret) {
- pr_err("Failed to enable timer clock\n");
- goto out_timer_clk;
+ return PTR_ERR(timer_clk);
}
timer->clk = timer_clk;
@@ -175,47 +161,32 @@ rk_timer_probe(struct rk_timer *timer, struct device_node *np)
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
- ret = -EINVAL;
pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
- goto out_irq;
+ return -EINVAL;
}
timer->irq = irq;
rk_timer_interrupt_clear(timer);
rk_timer_disable(timer);
- return 0;
-
-out_irq:
- clk_disable_unprepare(timer_clk);
-out_timer_clk:
- clk_disable_unprepare(pclk);
-out_unmap:
- iounmap(timer->base);
-
- return ret;
-}
-static void __init rk_timer_cleanup(struct rk_timer *timer)
-{
- clk_disable_unprepare(timer->clk);
- clk_disable_unprepare(timer->pclk);
- iounmap(timer->base);
+ return 0;
}
-static int __init rk_clkevt_init(struct device_node *np)
+static int rk_clkevt_init(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct clock_event_device *ce;
int ret = -EINVAL;
- rk_clkevt = kzalloc_obj(struct rk_clkevt);
+ rk_clkevt = devm_kzalloc(dev, sizeof(*rk_clkevt), GFP_KERNEL);
if (!rk_clkevt) {
ret = -ENOMEM;
goto out;
}
- ret = rk_timer_probe(&rk_clkevt->timer, np);
+ ret = rk_timer_init(&rk_clkevt->timer, dev);
if (ret)
- goto out_probe;
+ goto out;
ce = &rk_clkevt->ce;
ce->name = TIMER_NAME;
@@ -233,36 +204,33 @@ static int __init rk_clkevt_init(struct device_node *np)
if (ret) {
pr_err("Failed to initialize '%s': %d\n",
TIMER_NAME, ret);
- goto out_irq;
+ goto out;
}
clockevents_config_and_register(&rk_clkevt->ce,
rk_clkevt->timer.freq, 1, UINT_MAX);
return 0;
-out_irq:
- rk_timer_cleanup(&rk_clkevt->timer);
-out_probe:
- kfree(rk_clkevt);
out:
/* Leave rk_clkevt not NULL to prevent future init */
rk_clkevt = ERR_PTR(ret);
return ret;
}
-static int __init rk_clksrc_init(struct device_node *np)
+static int rk_clksrc_init(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
int ret = -EINVAL;
- rk_clksrc = kzalloc_obj(struct rk_timer);
+ rk_clksrc = devm_kzalloc(dev, sizeof(*rk_clksrc), GFP_KERNEL);
if (!rk_clksrc) {
ret = -ENOMEM;
goto out;
}
- ret = rk_timer_probe(rk_clksrc, np);
+ ret = rk_timer_init(rk_clksrc, dev);
if (ret)
- goto out_probe;
+ goto out;
rk_timer_update_counter(UINT_MAX, rk_clksrc);
rk_timer_enable(rk_clksrc, 0);
@@ -272,33 +240,34 @@ static int __init rk_clksrc_init(struct device_node *np)
clocksource_mmio_readl_down);
if (ret) {
pr_err("Failed to register clocksource\n");
- goto out_clocksource;
+ goto out;
}
sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
return 0;
-out_clocksource:
- rk_timer_cleanup(rk_clksrc);
-out_probe:
- kfree(rk_clksrc);
out:
/* Leave rk_clksrc not NULL to prevent future init */
rk_clksrc = ERR_PTR(ret);
return ret;
}
-static int __init rk_timer_init(struct device_node *np)
+static int rk_timer_probe(struct platform_device *pdev)
{
if (!rk_clkevt)
- return rk_clkevt_init(np);
+ return rk_clkevt_init(pdev);
if (!rk_clksrc)
- return rk_clksrc_init(np);
+ return rk_clksrc_init(pdev);
pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
return -EINVAL;
}
-TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
-TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
+static const struct of_device_id rk_timer_match_table[] = {
+ { .compatible = "rockchip,rk3288-timer" },
+ { .compatible = "rockchip,rk3399-timer" },
+ { /* sentinel */ }
+};
+
+TIMER_PDEV_DECLARE(rk_timer, rk_timer_probe, NULL, rk_timer_match_table);
--
2.43.0
^ permalink raw reply related
* [PATCH v1 0/7] Timer driver module support
From: Daniel Lezcano @ 2026-03-27 17:55 UTC (permalink / raw)
To: daniel.lezcano, tglx, zhipeng.wang_1
Cc: shawnguo, jstultz, linux-kernel, Matthias Brugger,
AngeloGioacchino Del Regno,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
Converting the timer driver modules requires a particular care
because, depending on the platform, that may be not supported.
A previous study showed we are safe regarding how the module refcount
is held and if THIS_MODULE is set for the clockevent and the
clocksource when they are registered.
It won't be possible to unload a module if a clockevent is registered.
It will be possible to unload a module if only a clocksource is
registered and it is not the current one.
However platforms without architected timers may need the timer driver
to be initialized very early and others can be initialized later. The
former can not be a module and the init function receives a
device_node pointer, there is no device associated and devres is not
used. That results in a lot of rollbacking code where usually it is
where we find bug and resource leaks. The latter can be converted to a
module and uses a module_platform_driver(), thus the init function is
a probe function receiving a struct platform_device pointer parameter.
We end up with two approaches and duplicate code for the init
functions. This is not optimal.
Finally, we have the driver having to be initialized very early on
some platforms and be built as a module on other platforms, resulting
on having two init functions co-existing in the same driver.
This series provides what is needed to move to the same probe function
for early init, builtin and module timers.
A new macro is introduced: TIMER_PDEV_DECLARE() and a new Kconfig
option is added CONFIG_EARLY_TIMER. TIMER_PDEV_DECLARE() will have
different behavior depending on the context:
- The driver is a module and CONFIG_EARLY_TIMER=no
--> the driver is a module
- The driver is builtin and CONFIG_EARLY_TIMER=no
--> the driver is loaded later
- The driver is builtin or a module but CONFIG_EARLY_TIMER=yes
--> the driver is initialized through the timer-probe function
The different timer driver framework functions have their __init
sections removed and the symbols exported in order to be compatible
with the drivers converted into modules.
The series provides a couple of drivers changed. The Mediatek as a
recent requested target which is only compiled-tested. The Rockchip
timer which was tested on a rk3588 in the three different
configurations.
Daniel Lezcano (7):
clocksource/drivers/timer-probe: Create a platform_device before the
framework is initialized
drivers/clocksource/rockchip: Use the TIMER_PDEV_DECLARE() macro
clocksource/drivers/mmio: Make the code compatible with modules
clocksource/drivers/timer-of: Make the code compatible with modules
clocksource/drivers/timer-probe: Add the module support for the
TIMER_PDEV_DECLARE() macro
clocksource/drivers/rockchip: Add rockchip timer module support
clocksource/drivers/mediatek: Convert to module support
drivers/clocksource/Kconfig | 7 +-
drivers/clocksource/mmio.c | 11 ++-
drivers/clocksource/timer-mediatek.c | 29 ++++++--
drivers/clocksource/timer-of.c | 24 ++++---
drivers/clocksource/timer-of.h | 5 +-
drivers/clocksource/timer-probe.c | 69 ++++++++++++++++--
drivers/clocksource/timer-rockchip.c | 101 ++++++++++-----------------
include/asm-generic/vmlinux.lds.h | 10 +++
include/linux/clocksource.h | 31 ++++++++
9 files changed, 194 insertions(+), 93 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH v3 0/3] arm64: Add HPE GSC platform support
From: nick.hawkins @ 2026-03-27 17:44 UTC (permalink / raw)
To: catalin.marinas, will, robh, krzk+dt, conor+dt
Cc: nick.hawkins, linux-arm-kernel, devicetree, linux-kernel
From: Nick Hawkins <nick.hawkins@hpe.com>
Add initial platform support for the HPE GSC ARM64 BMC SoC.
Changes since v2:
- Patch 1: Removed separate ARM64/HPE GSC MAINTAINERS entry; instead
renamed existing ARM/HPE GXP to ARM/HPE GXP/GSC and added arm64 DTS
path there (Conor Dooley)
- Patch 2: Replaced menuconfig ARCH_HPE + nested ARCH_HPE_GSC with a
single config ARCH_HPE; removed extra blank line (Krzysztof Kozlowski)
- Patch 3: Dropped clocks wrapper node, renamed fixed clock to
clock-33333333; renamed ahb bus node to soc; reordered UART nodes by
address for DTS coding style; replaced raw interrupt triplets with
GIC_SPI/IRQ_TYPE_LEVEL_HIGH defines (Krzysztof Kozlowski)
Nick Hawkins (3):
dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
arm64: Kconfig: Add ARCH_HPE platform
arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
.../devicetree/bindings/arm/hpe,gxp.yaml | 7 +-
MAINTAINERS | 3 +-
arch/arm64/Kconfig.platforms | 11 ++
arch/arm64/boot/dts/hpe/Makefile | 2 +
arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 +++
arch/arm64/boot/dts/hpe/gsc.dtsi | 104 ++++++++++++++++++
6 files changed, 143 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/hpe/Makefile
create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
--
2.34.1
^ permalink raw reply
* [PATCH v3 3/3] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
From: nick.hawkins @ 2026-03-27 17:44 UTC (permalink / raw)
To: catalin.marinas, will, robh, krzk+dt, conor+dt
Cc: nick.hawkins, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU
cluster, GIC v3 interrupt controller, ARM64 generic timer, and console
UART.
Add the board-level DTS for the HPE DL340 Gen12, which includes
gsc.dtsi and adds memory and chosen nodes.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
arch/arm64/boot/dts/hpe/Makefile | 2 +
arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++
arch/arm64/boot/dts/hpe/gsc.dtsi | 104 +++++++++++++++++++++
3 files changed, 124 insertions(+)
create mode 100644 arch/arm64/boot/dts/hpe/Makefile
create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Makefile
new file mode 100644
index 000000000000..6b547b8a8154
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+dtb-$(CONFIG_ARCH_HPE) += gsc-dl340gen12.dtb
diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
new file mode 100644
index 000000000000..42cfeac99029
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "gsc.dtsi"
+
+/ {
+ compatible = "hpe,gsc-dl340gen12", "hpe,gsc";
+ model = "HPE ProLiant DL340 Gen12";
+
+ chosen {
+ stdout-path = &uartc;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc.dtsi
new file mode 100644
index 000000000000..087688b089e9
--- /dev/null
+++ b/arch/arm64/boot/dts/hpe/gsc.dtsi
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GSC
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0xa0008048>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0xa0008048>;
+ };
+ };
+
+ osc: clock-33333333 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "osc";
+ clock-frequency = <33333333>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gic>;
+ };
+
+ soc: soc@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x80000000>;
+ ranges;
+
+ gic: gic@ce000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x20000>;
+ #redistributor-regions = <1>;
+ reg = <0xce000000 0x10000>,
+ <0xce060000 0x40000>,
+ <0xce200000 0x40000>;
+ };
+
+ uarta: serial@c00000e0 {
+ compatible = "ns16550a";
+ reg = <0xc00000e0 0x8>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartb: serial@c00000e8 {
+ compatible = "ns16550a";
+ reg = <0xc00000e8 0x8>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uartc: serial@c00000f0 {
+ compatible = "ns16550a";
+ reg = <0xc00000f0 0x8>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+
+ uarte: serial@c00003e0 {
+ compatible = "ns16550a";
+ reg = <0xc00003e0 0x8>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clock-frequency = <1846153>;
+ reg-shift = <0>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
From: nick.hawkins @ 2026-03-27 17:44 UTC (permalink / raw)
To: catalin.marinas, will, robh, krzk+dt, conor+dt
Cc: nick.hawkins, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add the HPE GSC ARM64 BMC SoC compatibles to the existing
hpe,gxp.yaml binding.
The initial board compatible is hpe,gsc-dl340gen12 for the DL340 Gen12
server platform.
Add the arm64 DTS path to the existing ARM/HPE GXP MAINTAINERS entry,
renamed to ARM/HPE GXP/GSC ARCHITECTURE.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
Documentation/devicetree/bindings/arm/hpe,gxp.yaml | 7 ++++++-
MAINTAINERS | 3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
index 224bbcb93f95..6f057cd58571 100644
--- a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
+++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: HPE BMC GXP platforms
+title: HPE BMC GXP and GSC platforms
maintainers:
- Nick Hawkins <nick.hawkins@hpe.com>
@@ -18,6 +18,11 @@ properties:
- enum:
- hpe,gxp-dl360gen10
- const: hpe,gxp
+ - description: GSC Based Boards
+ items:
+ - enum:
+ - hpe,gsc-dl340gen12
+ - const: hpe,gsc
required:
- compatible
diff --git a/MAINTAINERS b/MAINTAINERS
index 2265e2c9bfbe..80c66de5e342 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2859,7 +2859,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kristoffer/linux-hpc.git
F: arch/arm/mach-sa1100/include/mach/jornada720.h
F: arch/arm/mach-sa1100/jornada720.c
-ARM/HPE GXP ARCHITECTURE
+ARM/HPE GXP/GSC ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
M: Nick Hawkins <nick.hawkins@hpe.com>
S: Maintained
@@ -2870,6 +2870,7 @@ F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml
F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml
F: Documentation/hwmon/gxp-fan-ctrl.rst
F: arch/arm/boot/dts/hpe/
+F: arch/arm64/boot/dts/hpe/
F: drivers/clocksource/timer-gxp.c
F: drivers/hwmon/gxp-fan-ctrl.c
F: drivers/i2c/busses/i2c-gxp.c
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/3] arm64: Kconfig: Add ARCH_HPE platform
From: nick.hawkins @ 2026-03-27 17:44 UTC (permalink / raw)
To: catalin.marinas, will, robh, krzk+dt, conor+dt
Cc: nick.hawkins, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-1-nick.hawkins@hpe.com>
From: Nick Hawkins <nick.hawkins@hpe.com>
Add the ARCH_HPE config for HPE ARM64 BMC SoCs to Kconfig.platforms.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
---
arch/arm64/Kconfig.platforms | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 54eb1d7fd419..b4217809c774 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -168,6 +168,17 @@ config ARCH_HISI
help
This enables support for Hisilicon ARMv8 SoC family
+config ARCH_HPE
+ bool "HPE SoC Support"
+ select PINCTRL
+ select GENERIC_IRQ_CHIP
+ select CLKSRC_MMIO
+ help
+ This enables support for HPE ARM-based SoC chips used
+ on HPE servers. HPE SoCs serve as the Baseboard
+ Management Controller (BMC) providing out-of-band server
+ management.
+
config ARCH_KEEMBAY
bool "Keem Bay SoC"
help
--
2.34.1
^ permalink raw reply related
* Re: [RFT PATCH v3] ARM: omap1: enable real software node lookup of GPIOs on Nokia 770
From: Bartosz Golaszewski @ 2026-03-27 17:27 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Janusz Krzysztofik, Arnd Bergmann, Bartosz Golaszewski,
Tony Lindgren, Russell King, Dmitry Torokhov, Hans de Goede,
Linux-OMAP, linux-arm-kernel, linux-kernel, Kevin Hilman,
Aaro Koskinen, Andy Shevchenko
In-Reply-To: <CAMRc=McVPskF4pMQSz=hR8CkyZhoPmCU_yJFT66vgTCPJd3-Vw@mail.gmail.com>
On Fri, 27 Mar 2026 18:23:29 +0100, Bartosz Golaszewski <brgl@kernel.org> said:
> On Fri, Mar 27, 2026 at 5:59 PM Aaro Koskinen <aaro.koskinen@iki.fi> wrote:
>>
>> Hi,
>>
>> On Fri, Mar 27, 2026 at 03:22:12PM +0100, Bartosz Golaszewski wrote:
>> > Hmm, I'm wondering if there's a race with consumers already requesting
>> > the GPIOs after the controller device is registered but before the
>> > software node is added. I'll send a version with software nodes being
>> > registered first, then passes as firmware nodes to the platform device
>> > API before the device is registered.
>>
>> It crashes early, I was able to get an UART log from OSK (another
>> 16xx board):
>>
>> [ 1.001525] Register r12 information: 2-page vmalloc region starting at 0xc2808000 allocated at kernel_clone+0xa4/0x20c
>> [ 1.013092] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
>> [ 1.019500] Stack: (0xc2809ed0 to 0xc280a000)
>> [ 1.024230] 9ec0: c072d000 c0529474 c06b3aa0 c050a3cc
>> [ 1.032958] 9ee0: c072d000 c085c000 00000002 c052582c c050a324 c072d000 00000000 c0503160
>> [ 1.041687] 9f00: 00002710 00000000 c04da8f8 c0060900 c2809f64 ffffffff 00010000 946f70b5
>> [ 1.050384] 9f20: 00000062 c0816120 00000002 c052582c c0525848 c072d000 c04da8f8 c0060a18
>> [ 1.059112] 9f40: c2809f64 c2809f64 00000000 946f70b5 00000062 c0816120 00000002 c052582c
>> [ 1.067810] 9f60: c052584c c072d000 c04da8f8 c050352c 00000002 00000002 00000000 c0502400
>> [ 1.076507] 9f80: c2809f7c 00000000 c03f86f4 00000000 00000000 00000000 00000000 00000000
>> [ 1.085205] 9fa0: 00000000 c03f8704 00000000 c000850c 00000000 00000000 00000000 00000000
>> [ 1.093902] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>> [ 1.102600] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
>> [ 1.111206] Call trace:
>> [ 1.111328] software_node_to_swnode from device_add_software_node+0x20/0x80
>> [ 1.121704] device_add_software_node from omap16xx_gpio_init+0xa8/0xe4
>> [ 1.128997] omap16xx_gpio_init from do_one_initcall+0x68/0x1f4
>> [ 1.135620] do_one_initcall from kernel_init_freeable+0x1ec/0x240
>> [ 1.142517] kernel_init_freeable from kernel_init+0x10/0x108
>> [ 1.148864] kernel_init from ret_from_fork+0x14/0x28
>> [ 1.154357] Exception stack(0xc2809fb0 to 0xc2809ff8)
>> [ 1.159820] 9fa0: 00000000 00000000 00000000 00000000
>> [ 1.168518] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>> [ 1.177185] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000
>> [ 1.184295] Code: e3500000 012fff1e e59f3034 e5932000 (e5923000)
>> [ 1.191040] ---[ end trace 0000000000000000 ]---
>> [ 1.196350] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
>> [ 1.204559] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---
>>
>
> Thanks. This makes sense. Both omap16xx_gpio_init() and
> software_node_init() run as postcore_initcall() so if the order is not
> right, it will fail.
>
> Cc'ing Andy who's a reviewer for software nodes. Andy: is there any
> reason to run software_node_init() as a postcore initcall? It only
> allocates the kset, can we move it to core_initcall() by any chance?
>
> Bart
>
In any case, Aaro: the following should theoretically fix it:
diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c
index 51320837f3a9..5ba904f8a08a 100644
--- a/drivers/base/swnode.c
+++ b/drivers/base/swnode.c
@@ -1134,7 +1134,7 @@ static int __init software_node_init(void)
return -ENOMEM;
return 0;
}
-postcore_initcall(software_node_init);
+core_initcall(software_node_init);
static void __exit software_node_exit(void)
{
If you could give it a spin and let me know if it does, it would be awesome.
Bart
^ permalink raw reply related
* Re: [RFT PATCH v3] ARM: omap1: enable real software node lookup of GPIOs on Nokia 770
From: Bartosz Golaszewski @ 2026-03-27 17:23 UTC (permalink / raw)
To: Aaro Koskinen, Andy Shevchenko
Cc: Janusz Krzysztofik, Arnd Bergmann, Bartosz Golaszewski,
Tony Lindgren, Russell King, Dmitry Torokhov, Hans de Goede,
Linux-OMAP, linux-arm-kernel, linux-kernel, Kevin Hilman
In-Reply-To: <aca3ajb_G3gD24S7@darkstar.musicnaut.iki.fi>
On Fri, Mar 27, 2026 at 5:59 PM Aaro Koskinen <aaro.koskinen@iki.fi> wrote:
>
> Hi,
>
> On Fri, Mar 27, 2026 at 03:22:12PM +0100, Bartosz Golaszewski wrote:
> > Hmm, I'm wondering if there's a race with consumers already requesting
> > the GPIOs after the controller device is registered but before the
> > software node is added. I'll send a version with software nodes being
> > registered first, then passes as firmware nodes to the platform device
> > API before the device is registered.
>
> It crashes early, I was able to get an UART log from OSK (another
> 16xx board):
>
> [ 1.001525] Register r12 information: 2-page vmalloc region starting at 0xc2808000 allocated at kernel_clone+0xa4/0x20c
> [ 1.013092] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
> [ 1.019500] Stack: (0xc2809ed0 to 0xc280a000)
> [ 1.024230] 9ec0: c072d000 c0529474 c06b3aa0 c050a3cc
> [ 1.032958] 9ee0: c072d000 c085c000 00000002 c052582c c050a324 c072d000 00000000 c0503160
> [ 1.041687] 9f00: 00002710 00000000 c04da8f8 c0060900 c2809f64 ffffffff 00010000 946f70b5
> [ 1.050384] 9f20: 00000062 c0816120 00000002 c052582c c0525848 c072d000 c04da8f8 c0060a18
> [ 1.059112] 9f40: c2809f64 c2809f64 00000000 946f70b5 00000062 c0816120 00000002 c052582c
> [ 1.067810] 9f60: c052584c c072d000 c04da8f8 c050352c 00000002 00000002 00000000 c0502400
> [ 1.076507] 9f80: c2809f7c 00000000 c03f86f4 00000000 00000000 00000000 00000000 00000000
> [ 1.085205] 9fa0: 00000000 c03f8704 00000000 c000850c 00000000 00000000 00000000 00000000
> [ 1.093902] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 1.102600] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
> [ 1.111206] Call trace:
> [ 1.111328] software_node_to_swnode from device_add_software_node+0x20/0x80
> [ 1.121704] device_add_software_node from omap16xx_gpio_init+0xa8/0xe4
> [ 1.128997] omap16xx_gpio_init from do_one_initcall+0x68/0x1f4
> [ 1.135620] do_one_initcall from kernel_init_freeable+0x1ec/0x240
> [ 1.142517] kernel_init_freeable from kernel_init+0x10/0x108
> [ 1.148864] kernel_init from ret_from_fork+0x14/0x28
> [ 1.154357] Exception stack(0xc2809fb0 to 0xc2809ff8)
> [ 1.159820] 9fa0: 00000000 00000000 00000000 00000000
> [ 1.168518] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 1.177185] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000
> [ 1.184295] Code: e3500000 012fff1e e59f3034 e5932000 (e5923000)
> [ 1.191040] ---[ end trace 0000000000000000 ]---
> [ 1.196350] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
> [ 1.204559] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---
>
Thanks. This makes sense. Both omap16xx_gpio_init() and
software_node_init() run as postcore_initcall() so if the order is not
right, it will fail.
Cc'ing Andy who's a reviewer for software nodes. Andy: is there any
reason to run software_node_init() as a postcore initcall? It only
allocates the kset, can we move it to core_initcall() by any chance?
Bart
^ permalink raw reply
* Re: (subset) [PATCH v17 0/8] support FEAT_LSUI
From: Catalin Marinas @ 2026-03-27 17:18 UTC (permalink / raw)
To: Yeoreum Yun
Cc: linux-arm-kernel, linux-kernel, kvmarm, kvm, linux-kselftest,
will, maz, oupton, miko.lenczewski, kevin.brodsky, broonie, ardb,
suzuki.poulose, lpieralisi, joey.gouly, yuzenghui
In-Reply-To: <acaMex3Pq13njdRt@e129823.arm.com>
On Fri, Mar 27, 2026 at 01:56:11PM +0000, Yeoreum Yun wrote:
> > I decided to drop patch [6/8] (arm64: armv8_deprecated: disable swp
> > emulation when FEAT_LSUI present). The way FEAT_LSUI support looks now,
> > we still have uaccess_enable_privileged() working properly and we could
> > even support SWP emulation using exclusives. While it's highly unlikely
> > to see both 32-bit EL0 and FEAT_LSUI in practice,
>
> This is one of decisive reason to drop the swp emulation with LSUI
> (https://lore.kernel.org/all/aXDbBKhE1SdCW6q4@willie-the-truck/)
Ah, I forgot about this discussion. It's a valid point, I just thought
it's unnecessary given that __uaccess_disable_hw_pan() still works.
If we want strict no PAN, I can add it back (really small patch). I
wonder whether we should also add a
WARN_ON_ONCE(cpus_have_final_cap(ARM64_HAS_LSUI)) to the pan disabling
function. Not urgent though.
--
Catalin
^ permalink raw reply
* Re: [PATCH v1 1/1] arm64: dts: imx91-var-dart-sonata: add RGB select supply for PCA6408
From: Stefano Radaelli @ 2026-03-27 17:16 UTC (permalink / raw)
To: Frank Li
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
In-Reply-To: <aca1jdx0DjmmHqFk@lizhi-Precision-Tower-5810>
Hi Frank,
On Fri, Mar 27, 2026 at 12:51:25PM -0400, Frank Li wrote:
> On Fri, Mar 27, 2026 at 05:32:43PM +0100, Stefano Radaelli wrote:
> > From: Stefano Radaelli <stefano.r@variscite.com>
> >
> > RGB_SEL controls the routing of some carrier board lines on the Sonata
> > board. The two PCA6408 GPIO expanders depend on that path being enabled,
> > so describe the selector as a fixed regulator and use it as their
> > vcc-supply.
>
> Does below resolve your problem?
> https://lore.kernel.org/imx/20260325-pinctrl-mux-v4-0-043c2c82e623@nxp.com/
>
> So needn't hack select as regualtor
>
Thanks for pointing me your patch, interesting improvement!
Actually, in this case RGB_SEL is not meant to model a selectable mux
on the Sonata carrier.
On this board it must stay asserted permanently, otherwise the
downstream path to the two PCA6408 expanders is not accessible.
Modeling it as a mux might be confusing for users of the DART-MX91, as
as it would suggest that the routing is configurable, while on this
board it is actually fixed.
Best Regards,
Stefano
^ permalink raw reply
* [PATCH] ARM: OMAP1: Fix DEBUG_LL and earlyprintk on OMAP16XX
From: Aaro Koskinen @ 2026-03-27 17:15 UTC (permalink / raw)
To: Janusz Krzysztofik, Tony Lindgren, Kevin Hilman, linux-omap
Cc: linux-arm-kernel, linux-kernel
On OMAP16XX, the UART enable bit shifts are written instead of the actual
bits. This breaks the boot when DEBUG_LL and earlyprintk is enabled;
the UART gets disabled and some random bits get enabled. Fix that.
Fixes: 34c86239b184 ("ARM: OMAP1: clock: Fix early UART rate issues")
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
---
arch/arm/mach-omap1/clock_data.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c58d200e4816..5203b047deac 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -700,8 +700,8 @@ int __init omap1_clk_init(void)
/* Make sure UART clocks are enabled early */
if (cpu_is_omap16xx())
omap_writel(omap_readl(MOD_CONF_CTRL_0) |
- CONF_MOD_UART1_CLK_MODE_R |
- CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
+ (1 << CONF_MOD_UART1_CLK_MODE_R) |
+ (1 << CONF_MOD_UART3_CLK_MODE_R), MOD_CONF_CTRL_0);
#endif
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
--
2.39.2
^ permalink raw reply related
* Re: [PATCH v4 3/7] pinctrl: extract pinctrl_generic_to_map() from pinctrl_generic_pins_function_dt_node_to_map()
From: Conor Dooley @ 2026-03-27 17:14 UTC (permalink / raw)
To: Frank Li
Cc: Peter Rosin, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rafał Miłecki, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-kernel, linux-gpio,
devicetree, imx, linux-arm-kernel, Haibo Chen
In-Reply-To: <aca2UquiW9lFikhR@lizhi-Precision-Tower-5810>
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On Fri, Mar 27, 2026 at 12:54:42PM -0400, Frank Li wrote:
> On Fri, Mar 27, 2026 at 12:09:32AM +0000, Conor Dooley wrote:
> > On Wed, Mar 25, 2026 at 07:04:12PM -0400, Frank Li wrote:
> > > Refactor pinctrl_generic_pins_function_dt_subnode_to_map() by separating DT
> > > parsing logic from map creation. Introduce a new helper
> > > pinctrl_generic_to_map() to handle mapping to kernel data structures, while
> > > keeping DT property parsing in the subnode function.
> > >
> > > Improve code structure and enables easier reuse for platforms using
> > > different DT properties (e.g. pinmux) without modifying the
> > > dt_node_to_map-style callback API. Avoid unnecessary coupling to
> > > pinctrl_generic_pins_function_dt_node_to_map(), which provides
> > > functionality not needed when the phandle target is unambiguous.
> > >
> > > Maximize code reuse and provide a cleaner extension point for future
> > > pinctrl drivers.
> > >
> > > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > > ---
> > > change in v4
> > > - new patch
> > > ---
> > > drivers/pinctrl/pinconf.h | 18 ++++++++
> > > drivers/pinctrl/pinctrl-generic.c | 91 ++++++++++++++++++++++++---------------
> > > 2 files changed, 74 insertions(+), 35 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
> > > index 2880adef476e68950ffdd540ea42cdee6a16ec27..ffdabddb9660324ed8886a2e8dcacff7e1c6c529 100644
> > > --- a/drivers/pinctrl/pinconf.h
> > > +++ b/drivers/pinctrl/pinconf.h
> > > @@ -166,6 +166,13 @@ int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > > struct device_node *np,
> > > struct pinctrl_map **maps,
> > > unsigned int *num_maps);
> > > +
> > > +int
> > > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > > + struct device_node *np, struct pinctrl_map **maps,
> > > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > > + const char **group_name, unsigned int ngroups,
> > > + const char **functions, unsigned int *pins);
> > > #else
> > > static inline int
> > > pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > > @@ -175,4 +182,15 @@ pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > > {
> > > return -ENOTSUPP;
> > > }
> > > +
> > > +static inline int
> > > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > > + struct device_node *np, struct pinctrl_map **maps,
> > > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > > + const char **group_name, unsigned int ngroups,
> > > + const char **functions, unsigned int *pins,
> > > + void *function_data)
> > > +{
> > > + return -ENOTSUPP;
> > > +}
> > > #endif
> > > diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
> > > index efb39c6a670331775855efdc8566102b5c6202ef..20a216ae63e91b69985ea4cfcd0b57103c6ca950 100644
> > > --- a/drivers/pinctrl/pinctrl-generic.c
> > > +++ b/drivers/pinctrl/pinctrl-generic.c
> > > @@ -17,29 +17,18 @@
> > > #include "pinctrl-utils.h"
> > > #include "pinmux.h"
> > >
> > > -static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> > > - struct device_node *parent,
> > > - struct device_node *np,
> > > - struct pinctrl_map **maps,
> > > - unsigned int *num_maps,
> > > - unsigned int *num_reserved_maps,
> > > - const char **group_names,
> > > - unsigned int ngroups)
> > > +int
> > > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > > + struct device_node *np, struct pinctrl_map **maps,
> > > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > > + const char **group_names, unsigned int ngroups,
> > > + const char **functions, unsigned int *pins)
> >
> > npins needs to be an argument to this function also, otherwise
> > pinctrl_generic_add_group() uses it uninitialised...
>
> Is this one the root cause of then broken?
No, this is not the cause of the breakage. I can't believe I still have
to say that. Go read the code and you'll see why that allocation thing
is problematic.
> I am not sure why compiler have not report waring for it.
It did, that's how I found it. Used uninitialised warnings are normally
from clang, so your toolchain might not have seen it. clangd integration
with my editor is how I saw it.
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^ permalink raw reply
* Re: Warning from free_reserved_area() in next-20260325+
From: Mike Rapoport @ 2026-03-27 17:12 UTC (permalink / raw)
To: Bert Karwatzki
Cc: linux-kernel, Liam.Howlett, akpm, andreas, ardb, bp, brauner,
catalin.marinas, chleroy, dave.hansen, davem, david, devicetree,
dvyukov, elver, glider, hannes, hpa, ilias.apalodimas, iommu,
jack, jackmanb, kasan-dev, linux-arm-kernel, linux-efi,
linux-fsdevel, linux-mm, linux-trace-kernel, linuxppc-dev,
lorenzo.stoakes, m.szyprowski, maddy, mhiramat, mhocko, mingo,
mpe, npiggin, robh, robin.murphy, saravanak, sparclinux, surenb,
tglx, vbabka, viro, will, x86, ziy
In-Reply-To: <20260327140109.7561-1-spasswolf@web.de>
Hi Bert,
On Fri, Mar 27, 2026 at 03:01:08PM +0100, Bert Karwatzki wrote:
> Starting with linux next-20260325 I see the following warning early in the
> boot process of a machine running debian stable (trixie) (except for the kernel):
Thanks for the report!
> [ 0.027118] [ T0] ------------[ cut here ]------------
> [ 0.027118] [ T0] Cannot free reserved memory because of deferred initialization of the memory map
> [ 0.027119] [ T0] WARNING: mm/memblock.c:904 at __free_reserved_area+0xa9/0xc0, CPU#0: swapper/0/0
> [ 0.027122] [ T0] Modules linked in:
> [ 0.027123] [ T0] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.0.0-rc5-next-20260326-master #385 PREEMPT_RT
> [ 0.027125] [ T0] Hardware name: ASUS System Product Name/ROG STRIX B850-F GAMING WIFI, BIOS 1627 02/05/2026
> [ 0.027125] [ T0] RIP: 0010:__free_reserved_area+0xa9/0xc0
> [ 0.027126] [ T0] Code: 48 89 df 48 89 ee e8 06 fe ff ff 48 89 c3 48 39 e8 72 a0 5b 4c 89 e8 5d 41 5c 41 5d 41 5e c3 cc cc cc cc 48 8d 3d 97 c2 c6 00 <67> 48 0f b9 3a 45 31 ed eb df 66 66 2e 0f 1f 84 00 00 00 00 00 66
> [ 0.027127] [ T0] RSP: 0000:ffffffff9b203e98 EFLAGS: 00010202
> [ 0.027128] [ T0] RAX: 0000000e91c00001 RBX: ffffffff9b100c0f RCX: 0000000080000001
> [ 0.027128] [ T0] RDX: 00000000000000cc RSI: 0000000e2d42d000 RDI: ffffffff9b32ef60
> [ 0.027128] [ T0] RBP: ffff9eeafdd6fbc0 R08: 0000000000000000 R09: 0000000000000001
> [ 0.027129] [ T0] R10: 0000000000001000 R11: 8000000000000163 R12: 000000000000006f
> [ 0.027129] [ T0] R13: 0000000000000000 R14: 0000000000000045 R15: 000000005c8a1000
> [ 0.027129] [ T0] FS: 0000000000000000(0000) GS:ffff9eeb21c05000(0000) knlGS:0000000000000000
> [ 0.027130] [ T0] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 0.027130] [ T0] CR2: ffff9ee8ad801000 CR3: 0000000e2ce1e000 CR4: 0000000000f50ef0
> [ 0.027131] [ T0] PKRU: 55555554
> [ 0.027131] [ T0] Call Trace:
> [ 0.027132] [ T0] <TASK>
> [ 0.027132] [ T0] free_reserved_area+0x89/0xd0
> [ 0.027133] [ T0] alternative_instructions+0xee/0x110
> [ 0.027136] [ T0] arch_cpu_finalize_init+0x10f/0x160
> [ 0.027138] [ T0] start_kernel+0x686/0x710
> [ 0.027140] [ T0] x86_64_start_reservations+0x24/0x30
> [ 0.027141] [ T0] x86_64_start_kernel+0xd4/0xe0
> [ 0.027142] [ T0] common_startup_64+0x13e/0x141
> [ 0.027143] [ T0] </TASK>
> [ 0.027144] [ T0] ---[ end trace 0000000000000000 ]---
Does this patch fix it for you?
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index e87da25d1236..62936a3bde19 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -2448,19 +2448,31 @@ void __init alternative_instructions(void)
__smp_locks, __smp_locks_end,
_text, _etext);
}
+#endif
+ restart_nmi();
+ alternatives_patched = 1;
+
+ alt_reloc_selftest();
+}
+
+#ifdef CONFIG_SMP
+/*
+ * With CONFIG_DEFERRED_STRUCT_PAGE_INIT enabled we can free_init_pages() only
+ * after the deferred initialization of the memory map is complete.
+ */
+static int __init free_smp_locks(void)
+{
if (!uniproc_patched || num_possible_cpus() == 1) {
free_init_pages("SMP alternatives",
(unsigned long)__smp_locks,
(unsigned long)__smp_locks_end);
}
-#endif
- restart_nmi();
- alternatives_patched = 1;
-
- alt_reloc_selftest();
+ return 0;
}
+arch_initcall(free_smp_locks);
+#endif
/**
* text_poke_early - Update instructions on a live kernel at boot time
> Bert Karwatzki
--
Sincerely yours,
Mike.
^ permalink raw reply related
* Re: [PATCH v4] crypto: testmgr - Add test vectors for authenc(hmac(md5),cbc(aes))
From: Aleksander Jan Bajkowski @ 2026-03-27 17:03 UTC (permalink / raw)
To: Herbert Xu
Cc: davem, mcoquelin.stm32, alexandre.torgue, linux-crypto,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <abToanZh-mkEjmJ-@gondor.apana.org.au>
Hi Herbert,
On 14/03/2026 05:47, Herbert Xu wrote:
> On Tue, Mar 03, 2026 at 07:48:44PM +0100, Aleksander Jan Bajkowski wrote:
>> Test vectors were generated starting from existing CBC(AES) test vectors
>> (RFC3602, NIST SP800-38A) and adding HMAC(MD5) computed with Python
>> script. Then, the results were double-checked on Mediatek MT7981 (safexcel)
>> and NXP P2020 (talitos). Both platforms pass self-tests.
>>
>> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
>> ---
>> v4:
>> - rename aes-generic -> aes-lib
>> v3:
>> - correct sha384 -> md5 in description
>> v2:
>> - rebase and resolve conflicts
>> ---
>> crypto/testmgr.c | 7 ++
>> crypto/testmgr.h | 255 +++++++++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 262 insertions(+)
> The previous patch has already been applied. Please redo this
> as an incremental patch.
Checked the crypto tree, and this patch still isn't applied. I've sent
multiple test vectors, and you're probably referring to a another patch.
Should I send it again, or will you accept it as is?
By the way, that's the last one. As of now, all my routers have the
missing vectors added :)
Regards, Aleksander
^ permalink raw reply
* [PATCH RFC net-next] net: stmmac: qcom-ethqos: set clk_csr
From: Russell King (Oracle) @ 2026-03-27 17:02 UTC (permalink / raw)
To: Mohd Ayaan Anwar
Cc: Alexandre Torgue, Andrew Lunn, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-stm32, netdev, Paolo Abeni
The clocks for qcom-ethqos return a rate of zero as firmware manages
their rate. According to hardware documentation, the clock which is
fed to the slave AHB interface can crange between 50 and 100MHz.
Currently, stmmac uses an undefined divisor value. Instead, use
STMMAC_CSR_60_100M which will mean we meet IEEE 802.3 specification
since this will generate between a 1.19MHz and 2.38MHz MDC clock for
this range. Add a comment describing this.
Link: https://lore.kernel.org/r/acGhQ0oui+dVRdLY@oss.qualcomm.com
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
This likely needs the qcom-ethqos 15 patch cleanup series.
I think this is what's needed to fix the MDC clocking issue. Please
review and test. Thanks.
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index ad3a983d2a08..ac7d6d3e205a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -764,6 +764,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
qcom_ethqos_set_sgmii_loopback(ethqos, true);
ethqos_set_func_clk_en(ethqos);
+ /* The clocks are controlled by firmware, so we don't know for certain
+ * what clock rate is being used. Hardware documentation mentions that
+ * the AHB slave clock will be in the range of 50 to 100MHz, which
+ * equates to a MDC between 1.19 and 2.38MHz.
+ */
+ plat_dat->clk_csr = STMMAC_CSR_60_100M;
plat_dat->bsp_priv = ethqos;
plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
plat_dat->dump_debug_regs = rgmii_dump;
--
2.47.3
^ permalink raw reply related
* Re: [RFT PATCH v3] ARM: omap1: enable real software node lookup of GPIOs on Nokia 770
From: Aaro Koskinen @ 2026-03-27 16:59 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Janusz Krzysztofik, Arnd Bergmann, Bartosz Golaszewski,
Tony Lindgren, Russell King, Dmitry Torokhov, Hans de Goede,
Linux-OMAP, linux-arm-kernel, linux-kernel, Kevin Hilman
In-Reply-To: <CAMRc=McDdK8Y7wtG8WObjD6WF-2ftKBDwKbvj=xL-NMfeV=bPQ@mail.gmail.com>
Hi,
On Fri, Mar 27, 2026 at 03:22:12PM +0100, Bartosz Golaszewski wrote:
> Hmm, I'm wondering if there's a race with consumers already requesting
> the GPIOs after the controller device is registered but before the
> software node is added. I'll send a version with software nodes being
> registered first, then passes as firmware nodes to the platform device
> API before the device is registered.
It crashes early, I was able to get an UART log from OSK (another
16xx board):
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 7.0.0-rc5-osk-00010-g9a0a87d27dc0 (aakoskin@lonestar) (arm-linux-gnueabi-gcc (GCC) 13.4.0, GNU ld (GNU Binutils) 2.45) #1 2026-03-26
[ 0.000000] CPU: ARM926EJ-S [41069263] revision 3 (ARMv5TEJ), cr=0005317f
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: TI-OSK
[ 0.000000] Ignoring tag cmdline (using the default kernel command line)
[ 0.000000] printk: legacy bootconsole [earlycon0] enabled
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] OMAP1611b revision 2 handled as 16xx id: 8d058f7948920905
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000010000000-0x0000000011ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000010000000-0x0000000011ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000010000000-0x0000000011ffffff]
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Kernel command line: mem=32M console=ttyS0,115200 earlyprintk initcall_debug loglevel=9
[ 0.000000] printk: log buffer data + meta data: 131072 + 409600 = 540672 bytes
[ 0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes, linear)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 8192
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000000] Total of 128 interrupts in 4 interrupt banks
[ 0.000000] Clocks: ARM_SYSST: 0x1000 DPLL_CTL: 0x2833 ARM_CKCTL: 0x2000
[ 0.000000] Clocking rate (xtal/DPLL1/MPU): 12.0/96.0/96.0 MHz
[ 0.000000] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[ 0.000030] sched_clock: 32 bits at 33kHz, resolution 30517ns, wraps every 65535999984741ns
[ 0.008880] OMAP clocksource: 32k_counter at 32768 Hz
[ 0.015106] Calibrating delay loop... 47.51 BogoMIPS (lpj=237568)
[ 0.130798] CPU: Testing write buffer coherency: ok
[ 0.137451] pid_max: default: 32768 minimum: 301
[ 0.144683] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.152648] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.166381] VFS: Finished mounting rootfs on nullfs
[ 0.197753] entering initcall level: early
[ 0.202270] calling allocate_overflow_stacks+0x0/0x50 @ 1
[ 0.209045] initcall allocate_overflow_stacks+0x0/0x50 returned 0 after 0 usecs
[ 0.217315] calling init_static_idmap+0x0/0x118 @ 1
[ 0.223144] Setting up static identity map for 0x10008400 - 0x1000843c
[ 0.230438] initcall init_static_idmap+0x0/0x118 returned 0 after 10000 usecs
[ 0.238555] calling spawn_ksoftirqd+0x0/0x70 @ 1
[ 0.246643] initcall spawn_ksoftirqd+0x0/0x70 returned 0 after 10000 usecs
[ 0.254516] calling init_signal_sysctls+0x0/0x4c @ 1
[ 0.260589] initcall init_signal_sysctls+0x0/0x4c returned 0 after 0 usecs
[ 0.268432] calling init_umh_sysctls+0x0/0x2c @ 1
[ 0.274139] initcall init_umh_sysctls+0x0/0x2c returned 0 after 10000 usecs
[ 0.281799] calling kthreads_init+0x0/0x34 @ 1
[ 0.287139] initcall kthreads_init+0x0/0x34 returned 0 after 0 usecs
[ 0.294372] calling migration_init+0x0/0x2c @ 1
[ 0.299560] initcall migration_init+0x0/0x2c returned 0 after 0 usecs
[ 0.306823] calling printk_set_kthreads_ready+0x0/0x34 @ 1
[ 0.312957] initcall printk_set_kthreads_ready+0x0/0x34 returned 0 after 0 usecs
[ 0.321105] calling irq_work_init_threads+0x0/0x8 @ 1
[ 0.326995] initcall irq_work_init_threads+0x0/0x8 returned 0 after 0 usecs
[ 0.334777] calling init_zero_pfn+0x0/0x2c @ 1
[ 0.339813] initcall init_zero_pfn+0x0/0x2c returned 0 after 0 usecs
[ 0.346954] calling init_fs_inode_sysctls+0x0/0x2c @ 1
[ 0.352874] initcall init_fs_inode_sysctls+0x0/0x2c returned 0 after 0 usecs
[ 0.360809] calling init_fs_locks_sysctls+0x0/0x2c @ 1
[ 0.366943] initcall init_fs_locks_sysctls+0x0/0x2c returned 0 after 0 usecs
[ 0.374938] calling init_fs_sysctls+0x0/0x2c @ 1
[ 0.380310] initcall init_fs_sysctls+0x0/0x2c returned 0 after 0 usecs
[ 0.389282] Memory: 24296K/32768K available (4054K kernel code, 525K rwdata, 888K rodata, 1688K init, 197K bss, 7868K reserved, 0K cma-reserved)
[ 0.408447] devtmpfs: initialized
[ 0.428741] entering initcall level: pure
[ 0.433135] calling ipc_ns_init+0x0/0x40 @ 1
[ 0.438537] initcall ipc_ns_init+0x0/0x40 returned 0 after 0 usecs
[ 0.445617] calling mmap_min_addr_init+0x0/0x44 @ 1
[ 0.451202] initcall mmap_min_addr_init+0x0/0x44 returned 0 after 0 usecs
[ 0.458801] calling pci_realloc_setup_params+0x0/0x48 @ 1
[ 0.465057] initcall pci_realloc_setup_params+0x0/0x48 returned 0 after 0 usecs
[ 0.472991] calling inet_frag_wq_init+0x0/0x4c @ 1
[ 0.480957] initcall inet_frag_wq_init+0x0/0x4c returned 0 after 0 usecs
[ 0.489318] entering initcall level: core
[ 0.493927] calling ptrace_break_init+0x0/0x2c @ 1
[ 0.499328] initcall ptrace_break_init+0x0/0x2c returned 0 after 0 usecs
[ 0.506805] calling omap1_pm_runtime_init+0x0/0x20 @ 1
[ 0.513122] initcall omap1_pm_runtime_init+0x0/0x20 returned 0 after 0 usecs
[ 0.521118] calling wq_sysfs_init+0x0/0x14 @ 1
[ 0.527404] initcall wq_sysfs_init+0x0/0x14 returned 0 after 0 usecs
[ 0.534698] calling ksysfs_init+0x0/0x9c @ 1
[ 0.540008] initcall ksysfs_init+0x0/0x9c returned 0 after 0 usecs
[ 0.547088] calling init_jiffies_clocksource+0x0/0x14 @ 1
[ 0.553131] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.564086] initcall init_jiffies_clocksource+0x0/0x14 returned 0 after 20000 usecs
[ 0.572387] calling posixtimer_init+0x0/0xd4 @ 1
[ 0.578155] posixtimers hash table entries: 512 (order: 0, 2048 bytes, linear)
[ 0.586212] initcall posixtimer_init+0x0/0xd4 returned 0 after 10000 usecs
[ 0.593994] calling futex_init+0x0/0xa0 @ 1
[ 0.598876] futex hash table entries: 256 (4096 bytes on 1 NUMA nodes, total 4 KiB, linear).
[ 0.608123] initcall futex_init+0x0/0xa0 returned 0 after 10000 usecs
[ 0.615386] calling cgroup_wq_init+0x0/0x78 @ 1
[ 0.620819] initcall cgroup_wq_init+0x0/0x78 returned 0 after 0 usecs
[ 0.628112] calling cgroup1_wq_init+0x0/0x38 @ 1
[ 0.633758] initcall cgroup1_wq_init+0x0/0x38 returned 0 after 0 usecs
[ 0.640899] calling fsnotify_init+0x0/0x30 @ 1
[ 0.646606] initcall fsnotify_init+0x0/0x30 returned 0 after 0 usecs
[ 0.653961] calling filelock_init+0x0/0xf8 @ 1
[ 0.659484] initcall filelock_init+0x0/0xf8 returned 0 after 0 usecs
[ 0.666839] calling init_script_binfmt+0x0/0x1c @ 1
[ 0.672393] initcall init_script_binfmt+0x0/0x1c returned 0 after 0 usecs
[ 0.680114] calling init_elf_binfmt+0x0/0x1c @ 1
[ 0.685699] initcall init_elf_binfmt+0x0/0x1c returned 0 after 0 usecs
[ 0.692901] calling gpiolib_dev_init+0x0/0x110 @ 1
[ 0.699584] initcall gpiolib_dev_init+0x0/0x110 returned 0 after 0 usecs
[ 0.707244] calling sock_init+0x0/0x108 @ 1
[ 0.714630] initcall sock_init+0x0/0x108 returned 0 after 10000 usecs
[ 0.721862] calling sock_struct_check+0x0/0x8 @ 1
[ 0.727539] initcall sock_struct_check+0x0/0x8 returned 0 after 0 usecs
[ 0.735107] calling net_inuse_init+0x0/0x24 @ 1
[ 0.740417] initcall net_inuse_init+0x0/0x24 returned 0 after 0 usecs
[ 0.747802] calling init_default_flow_dissectors+0x0/0x4c @ 1
[ 0.754577] initcall init_default_flow_dissectors+0x0/0x4c returned 0 after 0 usecs
[ 0.763244] calling netlink_proto_init+0x0/0xf8 @ 1
[ 0.774932] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.781799] initcall netlink_proto_init+0x0/0xf8 returned 0 after 10000 usecs
[ 0.789947] calling genl_init+0x0/0x38 @ 1
[ 0.795166] initcall genl_init+0x0/0x38 returned 0 after 0 usecs
[ 0.802490] entering initcall level: postcore
[ 0.807495] calling atomic_pool_init+0x0/0x134 @ 1
[ 0.816711] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.824401] initcall atomic_pool_init+0x0/0x134 returned 0 after 10000 usecs
[ 0.832092] calling omap16xx_gpio_init+0x0/0xe4 @ 1
[ 0.838867] 8<--- cut here ---
[ 0.842224] Unable to handle kernel NULL pointer dereference at virtual address 00000000 when read
[ 0.851989] [00000000] *pgd=00000000
[ 0.856262] Internal error: Oops: 5 [#1] ARM
[ 0.860931] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 7.0.0-rc5-osk-00010-g9a0a87d27dc0 #1 VOLUNTARY
[ 0.871368] Hardware name: TI-OSK
[ 0.874938] PC is at software_node_to_swnode+0x10/0x48
[ 0.880554] LR is at device_add_software_node+0x20/0x80
[ 0.886230] pc : [<c0273f10>] lr : [<c0274f20>] psr: a0000053
[ 0.892883] sp : c2809ed0 ip : c2809d94 fp : c052e6ec
[ 0.898437] r10: 00000000 r9 : 00000014 r8 : c052bae8
[ 0.903991] r7 : 00000005 r6 : c03fe9d4 r5 : c06b3ab0 r4 : c072d000
[ 0.910919] r3 : c0759b10 r2 : 00000000 r1 : c03fe9d4 r0 : c03fe9d4
[ 0.917846] Flags: NzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
[ 0.925506] Control: 0005317f Table: 10004000 DAC: 00000053
[ 0.931579] Register r0 information: non-slab/vmalloc memory
[ 0.937713] Register r1 information: non-slab/vmalloc memory
[ 0.943786] Register r2 information: NULL pointer
[ 0.948883] Register r3 information: non-slab/vmalloc memory
[ 0.954956] Register r4 information: non-slab/vmalloc memory
[ 0.961029] Register r5 information: non-slab/vmalloc memory
[ 0.967132] Register r6 information: non-slab/vmalloc memory
[ 0.973205] Register r7 information: non-paged memory
[ 0.978637] Register r8 information: non-slab/vmalloc memory
[ 0.984710] Register r9 information: non-paged memory
[ 0.990173] Register r10 information: NULL pointer
[ 0.995330] Register r11 information: non-slab/vmalloc memory
[ 1.001525] Register r12 information: 2-page vmalloc region starting at 0xc2808000 allocated at kernel_clone+0xa4/0x20c
[ 1.013092] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
[ 1.019500] Stack: (0xc2809ed0 to 0xc280a000)
[ 1.024230] 9ec0: c072d000 c0529474 c06b3aa0 c050a3cc
[ 1.032958] 9ee0: c072d000 c085c000 00000002 c052582c c050a324 c072d000 00000000 c0503160
[ 1.041687] 9f00: 00002710 00000000 c04da8f8 c0060900 c2809f64 ffffffff 00010000 946f70b5
[ 1.050384] 9f20: 00000062 c0816120 00000002 c052582c c0525848 c072d000 c04da8f8 c0060a18
[ 1.059112] 9f40: c2809f64 c2809f64 00000000 946f70b5 00000062 c0816120 00000002 c052582c
[ 1.067810] 9f60: c052584c c072d000 c04da8f8 c050352c 00000002 00000002 00000000 c0502400
[ 1.076507] 9f80: c2809f7c 00000000 c03f86f4 00000000 00000000 00000000 00000000 00000000
[ 1.085205] 9fa0: 00000000 c03f8704 00000000 c000850c 00000000 00000000 00000000 00000000
[ 1.093902] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.102600] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 1.111206] Call trace:
[ 1.111328] software_node_to_swnode from device_add_software_node+0x20/0x80
[ 1.121704] device_add_software_node from omap16xx_gpio_init+0xa8/0xe4
[ 1.128997] omap16xx_gpio_init from do_one_initcall+0x68/0x1f4
[ 1.135620] do_one_initcall from kernel_init_freeable+0x1ec/0x240
[ 1.142517] kernel_init_freeable from kernel_init+0x10/0x108
[ 1.148864] kernel_init from ret_from_fork+0x14/0x28
[ 1.154357] Exception stack(0xc2809fb0 to 0xc2809ff8)
[ 1.159820] 9fa0: 00000000 00000000 00000000 00000000
[ 1.168518] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.177185] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 1.184295] Code: e3500000 012fff1e e59f3034 e5932000 (e5923000)
[ 1.191040] ---[ end trace 0000000000000000 ]---
[ 1.196350] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 1.204559] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---
A.
^ permalink raw reply
* Re: [PATCH v4 3/7] pinctrl: extract pinctrl_generic_to_map() from pinctrl_generic_pins_function_dt_node_to_map()
From: Frank Li @ 2026-03-27 16:54 UTC (permalink / raw)
To: Conor Dooley
Cc: Peter Rosin, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rafał Miłecki, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-kernel, linux-gpio,
devicetree, imx, linux-arm-kernel, Haibo Chen
In-Reply-To: <20260327-overdrawn-stretch-2311ec39aa58@spud>
On Fri, Mar 27, 2026 at 12:09:32AM +0000, Conor Dooley wrote:
> On Wed, Mar 25, 2026 at 07:04:12PM -0400, Frank Li wrote:
> > Refactor pinctrl_generic_pins_function_dt_subnode_to_map() by separating DT
> > parsing logic from map creation. Introduce a new helper
> > pinctrl_generic_to_map() to handle mapping to kernel data structures, while
> > keeping DT property parsing in the subnode function.
> >
> > Improve code structure and enables easier reuse for platforms using
> > different DT properties (e.g. pinmux) without modifying the
> > dt_node_to_map-style callback API. Avoid unnecessary coupling to
> > pinctrl_generic_pins_function_dt_node_to_map(), which provides
> > functionality not needed when the phandle target is unambiguous.
> >
> > Maximize code reuse and provide a cleaner extension point for future
> > pinctrl drivers.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change in v4
> > - new patch
> > ---
> > drivers/pinctrl/pinconf.h | 18 ++++++++
> > drivers/pinctrl/pinctrl-generic.c | 91 ++++++++++++++++++++++++---------------
> > 2 files changed, 74 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
> > index 2880adef476e68950ffdd540ea42cdee6a16ec27..ffdabddb9660324ed8886a2e8dcacff7e1c6c529 100644
> > --- a/drivers/pinctrl/pinconf.h
> > +++ b/drivers/pinctrl/pinconf.h
> > @@ -166,6 +166,13 @@ int pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > struct device_node *np,
> > struct pinctrl_map **maps,
> > unsigned int *num_maps);
> > +
> > +int
> > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > + struct device_node *np, struct pinctrl_map **maps,
> > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > + const char **group_name, unsigned int ngroups,
> > + const char **functions, unsigned int *pins);
> > #else
> > static inline int
> > pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > @@ -175,4 +182,15 @@ pinctrl_generic_pins_function_dt_node_to_map(struct pinctrl_dev *pctldev,
> > {
> > return -ENOTSUPP;
> > }
> > +
> > +static inline int
> > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > + struct device_node *np, struct pinctrl_map **maps,
> > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > + const char **group_name, unsigned int ngroups,
> > + const char **functions, unsigned int *pins,
> > + void *function_data)
> > +{
> > + return -ENOTSUPP;
> > +}
> > #endif
> > diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
> > index efb39c6a670331775855efdc8566102b5c6202ef..20a216ae63e91b69985ea4cfcd0b57103c6ca950 100644
> > --- a/drivers/pinctrl/pinctrl-generic.c
> > +++ b/drivers/pinctrl/pinctrl-generic.c
> > @@ -17,29 +17,18 @@
> > #include "pinctrl-utils.h"
> > #include "pinmux.h"
> >
> > -static int pinctrl_generic_pins_function_dt_subnode_to_map(struct pinctrl_dev *pctldev,
> > - struct device_node *parent,
> > - struct device_node *np,
> > - struct pinctrl_map **maps,
> > - unsigned int *num_maps,
> > - unsigned int *num_reserved_maps,
> > - const char **group_names,
> > - unsigned int ngroups)
> > +int
> > +pinctrl_generic_to_map(struct pinctrl_dev *pctldev, struct device_node *parent,
> > + struct device_node *np, struct pinctrl_map **maps,
> > + unsigned int *num_maps, unsigned int *num_reserved_maps,
> > + const char **group_names, unsigned int ngroups,
> > + const char **functions, unsigned int *pins)
>
> npins needs to be an argument to this function also, otherwise
> pinctrl_generic_add_group() uses it uninitialised...
Is this one the root cause of then broken? I am not sure why compiler have
not report waring for it.
Frank
> >
^ permalink raw reply
* Re: [PATCH v2 3/4] elf: align ET_DYN base to max folio size for PTE coalescing
From: Usama Arif @ 2026-03-27 16:53 UTC (permalink / raw)
To: WANG Rui
Cc: Liam.Howlett, ajd, akpm, apopple, baohua, baolin.wang, brauner,
catalin.marinas, david, dev.jain, jack, kees, kevin.brodsky,
lance.yang, linux-arm-kernel, linux-fsdevel, linux-fsdevel,
linux-kernel, linux-mm, lorenzo.stoakes, mhocko, npache,
pasha.tatashin, rmclure, rppt, ryan.roberts, surenb, vbabka, viro,
willy
In-Reply-To: <20260320160519.80962-1-r@hev.cc>
On 20/03/2026 19:05, WANG Rui wrote:
> Hi Usama,
>
> On Fri, Mar 20, 2026 at 10:04 PM Usama Arif <usama.arif@linux.dev> wrote:
>> diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
>> index 8e89cc5b28200..042af81766fcd 100644
>> --- a/fs/binfmt_elf.c
>> +++ b/fs/binfmt_elf.c
>> @@ -49,6 +49,7 @@
>> #include <uapi/linux/rseq.h>
>> #include <asm/param.h>
>> #include <asm/page.h>
>> +#include <linux/pagemap.h>
>>
>> #ifndef ELF_COMPAT
>> #define ELF_COMPAT 0
>> @@ -488,19 +489,51 @@ static int elf_read(struct file *file, void *buf, size_t len, loff_t pos)
>> return 0;
>> }
>>
>> -static unsigned long maximum_alignment(struct elf_phdr *cmds, int nr)
>> +static unsigned long maximum_alignment(struct elf_phdr *cmds, int nr,
>> + struct file *filp)
>> {
>> unsigned long alignment = 0;
>> + unsigned long max_folio_size = PAGE_SIZE;
>> int i;
>>
>> + if (filp && filp->f_mapping)
>> + max_folio_size = mapping_max_folio_size(filp->f_mapping);
>
> From experiments (with 16K base pages), mapping_max_folio_size() appears to
> depend on the filesystem. It returns 8M on ext4, while on btrfs it always
> falls back to PAGE_SIZE (it seems CONFIG_BTRFS_EXPERIMENTAL=y may change this).
> This looks overly conservative and ends up missing practical optimization
> opportunities.
mapping_max_folio_size() reflects what the page cache will actually
allocate for a given filesystem, since readahead caps folio allocation
at mapping_max_folio_order() (in page_cache_ra_order()). If btrfs
reports PAGE_SIZE, readahead won't allocate large folios for it, so
there are no large folios to coalesce PTEs for, aligning the binary
beyond that would only reduce ASLR entropy for no benefit.
I don't think we should over-align binaries on filesystems that can't
take advantage of it.
>
>> +
>> for (i = 0; i < nr; i++) {
>> if (cmds[i].p_type == PT_LOAD) {
>> unsigned long p_align = cmds[i].p_align;
>> + unsigned long size;
>>
>> /* skip non-power of two alignments as invalid */
>> if (!is_power_of_2(p_align))
>> continue;
>> alignment = max(alignment, p_align);
>> +
>> + /*
>> + * Try to align the binary to the largest folio
>> + * size that the page cache supports, so the
>> + * hardware can coalesce PTEs (e.g. arm64
>> + * contpte) or use PMD mappings for large folios.
>> + *
>> + * Use the largest power-of-2 that fits within
>> + * the segment size, capped by what the page
>> + * cache will allocate. Only align when the
>> + * segment's virtual address and file offset are
>> + * already aligned to the folio size, as
>> + * misalignment would prevent coalescing anyway.
>> + *
>> + * The segment size check avoids reducing ASLR
>> + * entropy for small binaries that cannot
>> + * benefit.
>> + */
>> + if (!cmds[i].p_filesz)
>> + continue;
>> + size = rounddown_pow_of_two(cmds[i].p_filesz);
>> + size = min(size, max_folio_size);
>> + if (size > PAGE_SIZE &&
>> + IS_ALIGNED(cmds[i].p_vaddr, size) &&
>> + IS_ALIGNED(cmds[i].p_offset, size))
>> + alignment = max(alignment, size);
>
> In my patch [1], by aligning eligible segments to PMD_SIZE, THP can quickly
> collapse them into large mappings with minimal warmup. That doesn’t happen
> with the current behavior. I think allowing a reasonably sized PMD (say <= 32M)
> is worth considering. All we really need here is to ensure virtual address
> alignment. The rest can be left to THP under always, which can decide whether
> to collapse or not based on memory pressure and other factors.
>
> [1] https://lore.kernel.org/linux-fsdevel/20260313005211.882831-1-r@hev.cc
>
>> }
>> }
>>
>> @@ -1104,7 +1137,8 @@ static int load_elf_binary(struct linux_binprm *bprm)
>> }
>>
>> /* Calculate any requested alignment. */
>> - alignment = maximum_alignment(elf_phdata, elf_ex->e_phnum);
>> + alignment = maximum_alignment(elf_phdata, elf_ex->e_phnum,
>> + bprm->file);
>>
>> /**
>> * DOC: PIE handling
>> --
>> 2.52.0
>>
>
> Thanks,
> Rui
^ permalink raw reply
* Re: [PATCH v2 3/4] elf: align ET_DYN base to max folio size for PTE coalescing
From: Usama Arif @ 2026-03-27 16:51 UTC (permalink / raw)
To: Matthew Wilcox
Cc: Andrew Morton, david, ryan.roberts, linux-mm, r, jack, ajd,
apopple, baohua, baolin.wang, brauner, catalin.marinas, dev.jain,
kees, kevin.brodsky, lance.yang, Liam.Howlett, linux-arm-kernel,
linux-fsdevel, linux-kernel, lorenzo.stoakes, mhocko, npache,
pasha.tatashin, rmclure, rppt, surenb, vbabka, Al Viro,
wilts.infradead.org, ziy, hannes, kas, shakeel.butt, kernel-team
In-Reply-To: <ab1uqdcMBP1cBr7Q@casper.infradead.org>
On 20/03/2026 18:58, Matthew Wilcox wrote:
> On Fri, Mar 20, 2026 at 06:58:53AM -0700, Usama Arif wrote:
>> -static unsigned long maximum_alignment(struct elf_phdr *cmds, int nr)
>> +static unsigned long maximum_alignment(struct elf_phdr *cmds, int nr,
>> + struct file *filp)
>> {
>> unsigned long alignment = 0;
>> + unsigned long max_folio_size = PAGE_SIZE;
>> int i;
>>
>> + if (filp && filp->f_mapping)
>> + max_folio_size = mapping_max_folio_size(filp->f_mapping);
>
> Under what circumstances can bprm->file be NULL?
Yeah its unnecessary here. Its used in other places and this is never
checked, so we can remove it.
>
> Also we tend to prefer the name "file" rather than "filp" for new code
> (yes, there's a lot of old code out there).
>
ack. will change in next revision.
>> +
>> + /*
>> + * Try to align the binary to the largest folio
>> + * size that the page cache supports, so the
>> + * hardware can coalesce PTEs (e.g. arm64
>> + * contpte) or use PMD mappings for large folios.
>> + *
>> + * Use the largest power-of-2 that fits within
>> + * the segment size, capped by what the page
>> + * cache will allocate. Only align when the
>> + * segment's virtual address and file offset are
>> + * already aligned to the folio size, as
>> + * misalignment would prevent coalescing anyway.
>> + *
>> + * The segment size check avoids reducing ASLR
>> + * entropy for small binaries that cannot
>> + * benefit.
>> + */
>> + if (!cmds[i].p_filesz)
>> + continue;
>> + size = rounddown_pow_of_two(cmds[i].p_filesz);
>> + size = min(size, max_folio_size);
>> + if (size > PAGE_SIZE &&
>> + IS_ALIGNED(cmds[i].p_vaddr, size) &&
>> + IS_ALIGNED(cmds[i].p_offset, size))
>> + alignment = max(alignment, size);
>
> Can this not all be factored out into a different function? Also, I
> think it was done a bit better here:
> https://lore.kernel.org/linux-fsdevel/20260313005211.882831-1-r@hev.cc/
>
> + if (!IS_ALIGNED(cmd->p_vaddr | cmd->p_offset, PMD_SIZE))
> + return false;
>
ack, will try and address this accordingly.
Thanks for the reviews!!
^ permalink raw reply
* Re: [PATCH v1 1/1] arm64: dts: imx91-var-dart-sonata: add RGB select supply for PCA6408
From: Frank Li @ 2026-03-27 16:51 UTC (permalink / raw)
To: Stefano Radaelli
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
In-Reply-To: <20260327163243.17334-1-stefano.r@variscite.com>
On Fri, Mar 27, 2026 at 05:32:43PM +0100, Stefano Radaelli wrote:
> From: Stefano Radaelli <stefano.r@variscite.com>
>
> RGB_SEL controls the routing of some carrier board lines on the Sonata
> board. The two PCA6408 GPIO expanders depend on that path being enabled,
> so describe the selector as a fixed regulator and use it as their
> vcc-supply.
Does below resolve your problem?
https://lore.kernel.org/imx/20260325-pinctrl-mux-v4-0-043c2c82e623@nxp.com/
So needn't hack select as regualtor
Frank
>
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> ---
> arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
> index afa39dab240a..3b5816884f24 100644
> --- a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
> +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
> @@ -90,6 +90,13 @@ reg_vref_1v8: regulator-adc-vref {
> regulator-max-microvolt = <1800000>;
> };
>
> + reg_rgb_sel: regulator-rgb-sel {
> + compatible = "regulator-fixed";
> + regulator-name = "rgb-select";
> + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
> compatible = "regulator-fixed";
> pinctrl-names = "default";
> @@ -195,6 +202,7 @@ pca6408_1: gpio@20 {
> #gpio-cells = <2>;
> interrupt-parent = <&gpio1>;
> interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> + vcc-supply = <®_rgb_sel>;
> };
>
> pca6408_2: gpio@21 {
> @@ -204,6 +212,7 @@ pca6408_2: gpio@21 {
> #gpio-cells = <2>;
> interrupt-parent = <&gpio1>;
> interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> + vcc-supply = <®_rgb_sel>;
> };
>
> pca9534: gpio@22 {
> --
> 2.47.3
>
^ permalink raw reply
* [PATCH v4 5/5] dt-bindings: usb: atmel,at91sam9rl-udc: convert to DT schema
From: Charan Pedumuru @ 2026-03-27 16:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Claudiu Beznea, Herve Codina, Nicolas Ferre,
Alexandre Belloni
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel,
Charan Pedumuru
In-Reply-To: <20260327-atmel-usb-v4-0-eb8b6e49b29d@gmail.com>
Convert Atmel High-Speed USB Device Controller (USBA) binding to DT schema.
Changes during conversion:
- Make the "clock-names" property flexible enough to accept the items
in any order as the existing in tree DTS nodes doesn't follow an order.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../bindings/usb/atmel,at91sam9rl-udc.yaml | 74 ++++++++++++++++++++++
.../devicetree/bindings/usb/atmel-usb.txt | 46 --------------
2 files changed, 74 insertions(+), 46 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/atmel,at91sam9rl-udc.yaml b/Documentation/devicetree/bindings/usb/atmel,at91sam9rl-udc.yaml
new file mode 100644
index 000000000000..cdbbd17f8036
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/atmel,at91sam9rl-udc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/atmel,at91sam9rl-udc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel High-Speed USB Device Controller (USBA)
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+description:
+ The Atmel High-Speed USB Device Controller (USBA) provides USB 2.0
+ high-speed gadget functionality on several Atmel and Microchip SoCs.
+ The controller requires a peripheral clock and a host clock for operation
+ and may optionally use a GPIO to detect VBUS presence.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - atmel,at91sam9rl-udc
+ - atmel,at91sam9g45-udc
+ - atmel,sama5d3-udc
+ - items:
+ - const: microchip,lan9662-udc
+ - const: atmel,sama5d3-udc
+ - const: microchip,sam9x60-udc
+
+ reg:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ enum: [pclk, hclk]
+
+ atmel,vbus-gpio:
+ description: GPIO used to detect the presence of VBUS, indicating that
+ the USB cable is connected.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/gpio/gpio.h>
+ gadget@fff78000 {
+ compatible = "atmel,at91sam9g45-udc";
+ reg = <0x00600000 0x80000
+ 0xfff78000 0x400>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clock-names = "pclk", "hclk";
+ atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
deleted file mode 100644
index ab353576d1de..000000000000
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Atmel SOC USB controllers
-
-Atmel High-Speed USB device controller
-
-Required properties:
- - compatible: Should be one of the following
- "atmel,at91sam9rl-udc"
- "atmel,at91sam9g45-udc"
- "atmel,sama5d3-udc"
- "microchip,sam9x60-udc"
- "microchip,lan9662-udc"
- For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc"
- is required.
- - reg: Address and length of the register set for the device
- - interrupts: Should contain usba interrupt
- - clocks: Should reference the peripheral and host clocks
- - clock-names: Should contain two strings
- "pclk" for the peripheral clock
- "hclk" for the host clock
-
-Deprecated property:
- - ep childnode: To specify the number of endpoints and their properties.
-
-Optional properties:
- - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
- vbus is present (USB is connected).
-
-Deprecated child node properties:
- - name: Name of the endpoint.
- - reg: Num of the endpoint.
- - atmel,fifo-size: Size of the fifo.
- - atmel,nb-banks: Number of banks.
- - atmel,can-dma: Boolean to specify if the endpoint support DMA.
- - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
-
-usb2: gadget@fff78000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "atmel,at91sam9rl-udc";
- reg = <0x00600000 0x80000
- 0xfff78000 0x400>;
- interrupts = <27 4 0>;
- clocks = <&utmi>, <&udphs_clk>;
- clock-names = "hclk", "pclk";
- atmel,vbus-gpio = <&pioB 19 0>;
-};
--
2.53.0
^ permalink raw reply related
* [PATCH v4 4/5] dt-bindings: usb: atmel,at91rm9200-udc: convert to DT schema
From: Charan Pedumuru @ 2026-03-27 16:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Claudiu Beznea, Herve Codina, Nicolas Ferre,
Alexandre Belloni
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel,
Charan Pedumuru
In-Reply-To: <20260327-atmel-usb-v4-0-eb8b6e49b29d@gmail.com>
Convert Atmel AT91 USB Device Controller (UDC) binding to DT schema.
Changes during conversion:
- Include "atmel,pullup-gpio" and "atmel,matrix" in the properties since
they are required by existing in-tree DTS definitions.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../bindings/usb/atmel,at91rm9200-udc.yaml | 76 ++++++++++++++++++++++
.../devicetree/bindings/usb/atmel-usb.txt | 28 --------
2 files changed, 76 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/atmel,at91rm9200-udc.yaml b/Documentation/devicetree/bindings/usb/atmel,at91rm9200-udc.yaml
new file mode 100644
index 000000000000..a4eabb935e6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/atmel,at91rm9200-udc.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/atmel,at91rm9200-udc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel AT91 USB Device Controller (UDC)
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+description:
+ The Atmel AT91 USB Device Controller provides USB gadget (device-mode)
+ functionality on AT91 SoCs. It requires a peripheral clock and an AHB
+ clock for operation and may optionally control VBUS power through a GPIO.
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91rm9200-udc
+ - atmel,at91sam9260-udc
+ - atmel,at91sam9261-udc
+ - atmel,at91sam9263-udc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: hclk
+
+ atmel,vbus-gpio:
+ description: GPIO used to enable or control VBUS power for the USB bus.
+ maxItems: 1
+
+ atmel,matrix:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the Atmel bus matrix controller.
+
+ atmel,pullup-gpio:
+ description:
+ GPIO controlling the USB D+ pull-up resistor used to signal device
+ connection to the host.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/gpio/gpio.h>
+ gadget@fffa4000 {
+ compatible = "atmel,at91rm9200-udc";
+ reg = <0xfffa4000 0x4000>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&udc_clk>, <&udpck>;
+ clock-names = "pclk", "hclk";
+ atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index bf2149e5f0b3..ab353576d1de 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -1,33 +1,5 @@
Atmel SOC USB controllers
-AT91 USB device controller
-
-Required properties:
- - compatible: Should be one of the following
- "atmel,at91rm9200-udc"
- "atmel,at91sam9260-udc"
- "atmel,at91sam9261-udc"
- "atmel,at91sam9263-udc"
- - reg: Address and length of the register set for the device
- - interrupts: Should contain macb interrupt
- - clocks: Should reference the peripheral and the AHB clocks
- - clock-names: Should contain two strings
- "pclk" for the peripheral clock
- "hclk" for the AHB clock
-
-Optional properties:
- - atmel,vbus-gpio: If present, specifies a gpio that needs to be
- activated for the bus to be powered.
-
-usb1: gadget@fffa4000 {
- compatible = "atmel,at91rm9200-udc";
- reg = <0xfffa4000 0x4000>;
- interrupts = <10 4>;
- clocks = <&udc_clk>, <&udpck>;
- clock-names = "pclk", "hclk";
- atmel,vbus-gpio = <&pioC 5 0>;
-};
-
Atmel High-Speed USB device controller
Required properties:
--
2.53.0
^ permalink raw reply related
* [PATCH v4 3/5] dt-bindings: usb: generic-ehci: fix schema structure and add at91sam9g45 constraints
From: Charan Pedumuru @ 2026-03-27 16:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Claudiu Beznea, Herve Codina, Nicolas Ferre,
Alexandre Belloni
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel,
Charan Pedumuru
In-Reply-To: <20260327-atmel-usb-v4-0-eb8b6e49b29d@gmail.com>
Add clock and phy constraints for atmel,at91sam9g45-ehci and reorganize
the allOf section to fix dtbs_check warnings.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../devicetree/bindings/usb/atmel-usb.txt | 24 -----------
.../devicetree/bindings/usb/generic-ehci.yaml | 46 ++++++++++++++++------
2 files changed, 33 insertions(+), 37 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index c09685283109..bf2149e5f0b3 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -1,29 +1,5 @@
Atmel SOC USB controllers
-EHCI
-
-Required properties:
- - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
- used in host mode.
- - reg: Address and length of the register set for the device
- - interrupts: Should contain ehci interrupt
- - clocks: Should reference the peripheral and the UTMI clocks
- - clock-names: Should contain two strings
- "ehci_clk" for the peripheral clock
- "usb_clk" for the UTMI clock
-
-Optional properties:
- - phy_type : For multi port host USB controllers, should be one of
- "utmi", or "hsic".
-
-usb1: ehci@800000 {
- compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
- reg = <0x00800000 0x100000>;
- interrupts = <22 4>;
- clocks = <&utmi>, <&uhphs_clk>;
- clock-names = "usb_clk", "ehci_clk";
-};
-
AT91 USB device controller
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 601f097c09a6..55a5aa7d7a54 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -9,19 +9,6 @@ title: USB EHCI Controller
maintainers:
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-allOf:
- - $ref: usb-hcd.yaml
- - if:
- properties:
- compatible:
- not:
- contains:
- const: ibm,usb-ehci-440epx
- then:
- properties:
- reg:
- maxItems: 1
-
properties:
compatible:
oneOf:
@@ -167,6 +154,39 @@ required:
- reg
- interrupts
+allOf:
+ - $ref: usb-hcd.yaml
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: ibm,usb-ehci-440epx
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,at91sam9g45-ehci
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: usb_clk
+ - const: ehci_clk
+
+ phy_type:
+ enum:
+ - utmi
+ - hsic
+
+ required:
+ - clocks
+ - clock-names
+
unevaluatedProperties: false
examples:
--
2.53.0
^ permalink raw reply related
* [PATCH v4 2/5] dt-bindings: usb: generic-ohci: add AT91RM9200 OHCI binding support
From: Charan Pedumuru @ 2026-03-27 16:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Claudiu Beznea, Herve Codina, Nicolas Ferre,
Alexandre Belloni
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel,
Charan Pedumuru
In-Reply-To: <20260327-atmel-usb-v4-0-eb8b6e49b29d@gmail.com>
Convert the Atmel AT91RM9200 OHCI USB host controller binding to DT schema
by defining it in the existing generic OHCI schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../devicetree/bindings/usb/atmel-usb.txt | 27 --------------
.../devicetree/bindings/usb/generic-ohci.yaml | 41 ++++++++++++++++++++++
2 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 12183ef47ee4..c09685283109 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -1,32 +1,5 @@
Atmel SOC USB controllers
-OHCI
-
-Required properties:
- - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
- used in host mode.
- - reg: Address and length of the register set for the device
- - interrupts: Should contain ohci interrupt
- - clocks: Should reference the peripheral, host and system clocks
- - clock-names: Should contain three strings
- "ohci_clk" for the peripheral clock
- "hclk" for the host clock
- "uhpck" for the system clock
- - num-ports: Number of ports.
- - atmel,vbus-gpio: If present, specifies a gpio that needs to be
- activated for the bus to be powered.
- - atmel,oc-gpio: If present, specifies a gpio that needs to be
- activated for the overcurrent detection.
-
-usb0: ohci@500000 {
- compatible = "atmel,at91rm9200-ohci", "usb-ohci";
- reg = <0x00500000 0x100000>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
- clock-names = "ohci_clk", "hclk", "uhpck";
- interrupts = <20 4>;
- num-ports = <2>;
-};
-
EHCI
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 961cbf85eeb5..d42f448fa204 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -55,6 +55,7 @@ properties:
- ti,ohci-omap3
- items:
- enum:
+ - atmel,at91rm9200-ohci
- cavium,octeon-6335-ohci
- nintendo,hollywood-usb-ohci
- nxp,ohci-nxp
@@ -137,6 +138,24 @@ properties:
The associated ISP1301 device. Necessary for the UDC controller for
connecting to the USB physical layer.
+ atmel,vbus-gpio:
+ description:
+ GPIO used to control or sense the USB VBUS power. Each entry
+ represents a VBUS-related GPIO; count and order may vary by hardware.
+ Entries follow standard GPIO specifier format. A value of 0 indicates
+ an unused or unavailable VBUS signal.
+ minItems: 1
+ maxItems: 3
+
+ atmel,oc-gpio:
+ description:
+ GPIO used to signal USB overcurrent condition. Each entry represents
+ an OC detection GPIO; count and order may vary by hardware. Entries
+ follow standard GPIO specifier format. A value of 0 indicates an
+ unused or unavailable OC signal.
+ minItems: 1
+ maxItems: 3
+
required:
- compatible
- reg
@@ -144,6 +163,28 @@ required:
allOf:
- $ref: usb-hcd.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,at91rm9200-ohci
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: ohci_clk
+ - const: hclk
+ - const: uhpck
+
+ required:
+ - clocks
+ - clock-names
+
+ else:
+ properties:
+ atmel,vbus-gpio: false
+ atmel,oc-gpio: false
+
- if:
not:
properties:
--
2.53.0
^ permalink raw reply related
* [PATCH v4 1/5] arm: dts: at91: remove unused #address-cells/#size-cells from sam9x60 udc node
From: Charan Pedumuru @ 2026-03-27 16:47 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Claudiu Beznea, Herve Codina, Nicolas Ferre,
Alexandre Belloni
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel,
Charan Pedumuru
In-Reply-To: <20260327-atmel-usb-v4-0-eb8b6e49b29d@gmail.com>
The UDC node does not define any child nodes, so the "#address-cells" and
"#size-cells" properties are unnecessary. Remove these unused properties
to simplify the devicetree node and keep it consistent with DT conventions.
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
arch/arm/boot/dts/microchip/sam9x60.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index b075865e6a76..e708b3df4ccd 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -75,8 +75,6 @@ ahb {
ranges;
usb0: gadget@500000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "microchip,sam9x60-udc";
reg = <0x00500000 0x100000
0xf803c000 0x400>;
--
2.53.0
^ permalink raw reply related
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