* Re: [PATCH v4 0/3] KVM: arm64: Fix SPE and TRBE nVHE world switch
From: Marc Zyngier @ 2026-03-28 17:13 UTC (permalink / raw)
To: kvmarm, Will Deacon
Cc: mark.rutland, linux-arm-kernel, Oliver Upton, James Clark,
Leo Yan, Suzuki K Poulose, Fuad Tabba, Alexandru Elisei,
Yabin Cui
In-Reply-To: <20260327130047.21065-1-will@kernel.org>
On Fri, 27 Mar 2026 13:00:43 +0000, Will Deacon wrote:
> I got the Sashiko treatment on v3, so here's a quick respin to address
> the BRBE thinko it found in the last patch.
>
> Previous versions of the series are available at:
>
> v1: https://lore.kernel.org/r/20260216130959.19317-1-will@kernel.org
> v2: https://lore.kernel.org/r/20260227212136.7660-1-will@kernel.org
> v3: https://lore.kernel.org/r/20260326141214.18990-1-will@kernel.org
>
> [...]
Applied to next, thanks!
[1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
commit: d133aa75e39dd72e0b8577ab1f5fc17c72246536
[2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
commit: 07695f7dc1e141601254057a00bf4e23301eb0b2
[3/3] KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines
commit: 7aba10efef1d972fc82b00b84911f07f6afbdb78
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* [PATCH 2/2] spi: stm32-ospi: Fix DMA channel leak on stm32_ospi_dma_setup() failure
From: Felix Gu @ 2026-03-28 16:07 UTC (permalink / raw)
To: Mark Brown, Maxime Coquelin, Alexandre Torgue, Philipp Zabel,
Patrice Chotard
Cc: linux-spi, linux-stm32, linux-arm-kernel, linux-kernel, Felix Gu
In-Reply-To: <20260329-stm32-ospi-v1-0-142122466412@gmail.com>
When stm32_ospi_dma_setup() fails, the DMA channels allocated by
stm32_ospi_get_resources() were never released. Add proper cleanup
in the error path.
Fixes: e35a7607e05d ("spi: stm32-ospi: Set DMA maxburst dynamically")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
drivers/spi/spi-stm32-ospi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c
index 52997c3f7174..34498939bcdf 100644
--- a/drivers/spi/spi-stm32-ospi.c
+++ b/drivers/spi/spi-stm32-ospi.c
@@ -923,7 +923,7 @@ static int stm32_ospi_probe(struct platform_device *pdev)
dma_cfg.dst_addr = ospi->regs_phys_base + OSPI_DR;
ret = stm32_ospi_dma_setup(ospi, &dma_cfg);
if (ret)
- return ret;
+ goto err_dma_free;
mutex_init(&ospi->lock);
@@ -975,6 +975,7 @@ static int stm32_ospi_probe(struct platform_device *pdev)
err_pm_enable:
pm_runtime_force_suspend(ospi->dev);
mutex_destroy(&ospi->lock);
+err_dma_free:
if (ospi->dma_chtx)
dma_release_channel(ospi->dma_chtx);
if (ospi->dma_chrx)
--
2.43.0
^ permalink raw reply related
* [PATCH 1/2] spi: stm32-ospi: Fix reset control leak on probe error
From: Felix Gu @ 2026-03-28 16:07 UTC (permalink / raw)
To: Mark Brown, Maxime Coquelin, Alexandre Torgue, Philipp Zabel,
Patrice Chotard
Cc: linux-spi, linux-stm32, linux-arm-kernel, linux-kernel, Felix Gu
In-Reply-To: <20260329-stm32-ospi-v1-0-142122466412@gmail.com>
When spi_register_controller() fails after reset_control_acquire()
succeeds, the reset control is never released. This causes a resource
leak in the error path.
Add the missing reset_control_release() call in the error path.
Fixes: cf2c3eceb757 ("spi: stm32-ospi: Make usage of reset_control_acquire/release() API")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
drivers/spi/spi-stm32-ospi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c
index acf2d182e8b1..52997c3f7174 100644
--- a/drivers/spi/spi-stm32-ospi.c
+++ b/drivers/spi/spi-stm32-ospi.c
@@ -960,13 +960,15 @@ static int stm32_ospi_probe(struct platform_device *pdev)
if (ret) {
/* Disable ospi */
writel_relaxed(0, ospi->regs_base + OSPI_CR);
- goto err_pm_resume;
+ goto err_reset_control;
}
pm_runtime_put_autosuspend(ospi->dev);
return 0;
+err_reset_control:
+ reset_control_release(ospi->rstc);
err_pm_resume:
pm_runtime_put_sync_suspend(ospi->dev);
--
2.43.0
^ permalink raw reply related
* [PATCH 0/2] spi: stm32-ospi: two fixes
From: Felix Gu @ 2026-03-28 16:07 UTC (permalink / raw)
To: Mark Brown, Maxime Coquelin, Alexandre Torgue, Philipp Zabel,
Patrice Chotard
Cc: linux-spi, linux-stm32, linux-arm-kernel, linux-kernel, Felix Gu
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
Felix Gu (2):
spi: stm32-ospi: Fix reset control leak on probe error
spi: stm32-ospi: Fix DMA channel leak on stm32_ospi_dma_setup() failure
drivers/spi/spi-stm32-ospi.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
---
base-commit: 3b058d1aeeeff27a7289529c4944291613b364e9
change-id: 20260328-stm32-ospi-6d2ca0833eb6
Best regards,
--
Felix Gu <ustc.gu@gmail.com>
^ permalink raw reply
* Re: [PATCH v3 2/3] drm/gem-dma: Use the dma_*_attr API variant
From: kernel test robot @ 2026-03-28 15:54 UTC (permalink / raw)
To: Chen-Yu Tsai, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter
Cc: oe-kbuild-all, Rob Herring, dri-devel, linux-kernel,
linux-arm-kernel, Chen-Yu Tsai
In-Reply-To: <20260326100248.1171828-3-wenst@chromium.org>
Hi Chen-Yu,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on next-20260327]
[cannot apply to sunxi/sunxi/for-next linus/master v7.0-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/drm-Introduce-DRM_MODE_DUMB_KERNEL_MAP-flag/20260328-141115
base: https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-next
patch link: https://lore.kernel.org/r/20260326100248.1171828-3-wenst%40chromium.org
patch subject: [PATCH v3 2/3] drm/gem-dma: Use the dma_*_attr API variant
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20260328/202603282331.VKpi5ANh-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260328/202603282331.VKpi5ANh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603282331.VKpi5ANh-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c: In function 'rcar_du_vsp_map_fb':
>> drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c:296:82: error: expected ')' before 'gem'
296 | gem->dma_addr, gem->base.size
| ^
| )
297 | gem->dma_attrs);
| ~~~
drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c:295:52: note: to match this '('
295 | ret = dma_get_sgtable_attrs(rcdu->dev, sgt, gem->vaddr,
| ^
>> drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c:295:31: error: too few arguments to function 'dma_get_sgtable_attrs'; expected 6, have 5
295 | ret = dma_get_sgtable_attrs(rcdu->dev, sgt, gem->vaddr,
| ^~~~~~~~~~~~~~~~~~~~~
In file included from include/linux/dma-buf.h:21,
from include/drm/drm_gem.h:38,
from include/drm/drm_gem_dma_helper.h:7,
from drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c:18:
include/linux/dma-mapping.h:172:5: note: declared here
172 | int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
| ^~~~~~~~~~~~~~~~~~~~~
vim +296 drivers/gpu/drm/renesas/rcar-du/rcar_du_vsp.c
258
259 int rcar_du_vsp_map_fb(struct rcar_du_vsp *vsp, struct drm_framebuffer *fb,
260 struct sg_table sg_tables[3])
261 {
262 struct rcar_du_device *rcdu = vsp->dev;
263 unsigned int i, j;
264 int ret;
265
266 for (i = 0; i < fb->format->num_planes; ++i) {
267 struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i);
268 struct sg_table *sgt = &sg_tables[i];
269
270 if (gem->sgt) {
271 struct scatterlist *src;
272 struct scatterlist *dst;
273
274 /*
275 * If the GEM buffer has a scatter gather table, it has
276 * been imported from a dma-buf and has no physical
277 * address as it might not be physically contiguous.
278 * Copy the original scatter gather table to map it to
279 * the VSP.
280 */
281 ret = sg_alloc_table(sgt, gem->sgt->orig_nents,
282 GFP_KERNEL);
283 if (ret)
284 goto fail;
285
286 src = gem->sgt->sgl;
287 dst = sgt->sgl;
288 for (j = 0; j < gem->sgt->orig_nents; ++j) {
289 sg_set_page(dst, sg_page(src), src->length,
290 src->offset);
291 src = sg_next(src);
292 dst = sg_next(dst);
293 }
294 } else {
> 295 ret = dma_get_sgtable_attrs(rcdu->dev, sgt, gem->vaddr,
> 296 gem->dma_addr, gem->base.size
297 gem->dma_attrs);
298 if (ret)
299 goto fail;
300 }
301
302 ret = vsp1_du_map_sg(vsp->vsp, sgt);
303 if (ret) {
304 sg_free_table(sgt);
305 goto fail;
306 }
307 }
308
309 return 0;
310
311 fail:
312 while (i--) {
313 struct sg_table *sgt = &sg_tables[i];
314
315 vsp1_du_unmap_sg(vsp->vsp, sgt);
316 sg_free_table(sgt);
317 }
318
319 return ret;
320 }
321
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH 1/7] dt-bindings: rtc: sun6i: Add Allwinner A733 support
From: Chen-Yu Tsai @ 2026-03-28 12:37 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland,
Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-rtc, devicetree
In-Reply-To: <20260121-a733-rtc-v1-1-d359437f23a7@pigmoral.tech>
On Wed, Jan 21, 2026 at 7:03 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> The RTC module in the Allwinner A733 SoC is functionally compatible with
> the sun6i RTC, but its internal Clock Control Unit (CCU) has significant
> changes.
>
> The A733 supports selecting the oscillator between three frequencies:
> 19.2MHz, 24MHz, and 26MHz. The RTC CCU relies on hardware to detect
> which frequency is actually used on the board. By defining all three
> frequencies as fixed-clocks in the device tree, the driver can identify
> the hardware-detected frequency and expose it to the rest of the system.
No. The board device tree shall have the exact and correct frequency
defined in the external crystal device node. The operating system can
use the hardware-detected frequency to "fix" the in-system representation
if it is off.
> Additionally, the A733 RTC CCU provides several new DCXO gate clocks for
> specific modules, including SerDes, HDMI, and UFS.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 38 ++++++++++++++++++++--
> include/dt-bindings/clock/sun60i-a733-rtc.h | 16 +++++++++
> 2 files changed, 52 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> index 9df5cdb6f63f..b18431955783 100644
> --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
> @@ -26,6 +26,7 @@ properties:
> - allwinner,sun50i-h6-rtc
> - allwinner,sun50i-h616-rtc
> - allwinner,sun50i-r329-rtc
> + - allwinner,sun60i-a733-rtc
> - items:
> - const: allwinner,sun50i-a64-rtc
> - const: allwinner,sun8i-h3-rtc
> @@ -46,11 +47,11 @@ properties:
>
> clocks:
> minItems: 1
> - maxItems: 4
> + maxItems: 6
>
> clock-names:
> minItems: 1
> - maxItems: 4
> + maxItems: 6
>
> clock-output-names:
> minItems: 1
> @@ -156,6 +157,38 @@ allOf:
> - clocks
> - clock-names
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: allwinner,sun60i-a733-rtc
> +
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + items:
> + - description: Bus clock for register access
> + - description: 19.2 MHz oscillator
> + - description: 24 MHz oscillator
> + - description: 26 MHz oscillator
No. There is only one input. As in there is only one set of pins for the
DCXO. The inputs are the same as on R329 / A523. Just use that list.
> + - description: AHB parent for internal SPI clock
> + - description: External 32768 Hz oscillator
> +
> + clock-names:
> + minItems: 5
> + items:
> + - const: bus
> + - const: osc19M
> + - const: osc24M
> + - const: osc26M
> + - const: ahb
> + - const: ext-osc32k
> +
> + required:
> + - clocks
> + - clock-names
> +
> - if:
> properties:
> compatible:
> @@ -164,6 +197,7 @@ allOf:
> - allwinner,sun8i-r40-rtc
> - allwinner,sun50i-h616-rtc
> - allwinner,sun50i-r329-rtc
> + - allwinner,sun60i-a733-rtc
>
> then:
> properties:
> diff --git a/include/dt-bindings/clock/sun60i-a733-rtc.h b/include/dt-bindings/clock/sun60i-a733-rtc.h
> new file mode 100644
> index 000000000000..8a2b5facad73
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun60i-a733-rtc.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> +
> +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_
> +#define _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_
> +
> +#define CLK_IOSC 0
> +#define CLK_OSC32K 1
> +#define CLK_HOSC 2
The DCXO enable control has been present since at least the H6. We just
never added it, as we would never disable it anyway.
If you compare the RTC clock trees of the A733 and A523, the only addition
besides the new gates seems to be the LOSC auto selection. But even that
is just an illusion, as the A523 has the same registers for that.
One could say the A733 RTC is almost backward compatible to the A523, if
not for the two fastboot registers the A523 has at 0x120 and 0x124.
So I ask that you try to integrate the differences into the existing
driver and bindings. You can tweak and export internal clks if you
need.
> +#define CLK_RTC_32K 3
AFAICT besides being an internal clock, this is also fed to GPIO for
debounce? We probably need to expose this on the A523 as well.
Thanks
ChenYu
> +#define CLK_OSC32K_FANOUT 4
> +#define CLK_HOSC_SERDES1 5
> +#define CLK_HOSC_SERDES0 6
> +#define CLK_HOSC_HDMI 7
> +#define CLK_HOSC_UFS 8
> +
> +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_ */
>
> --
> 2.52.0
>
>
^ permalink raw reply
* Re: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support
From: Chen-Yu Tsai @ 2026-03-28 14:41 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland,
Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-rtc, devicetree, André Przywara
In-Reply-To: <20260121-a733-rtc-v1-7-d359437f23a7@pigmoral.tech>
On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> Add support for the internal CCU found in the RTC module of the Allwinner
> A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible
> with older SoCs like the sun6i, the A733 introduces several new features.
>
> The A733 RTC CCU supports choosing one of three external crystal
> frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection
> logic to automatically identify the frequency used on the board and
> exports this DCXO signal as the "hosc" clock.
>
> Furthermore, the driver implements logic to derive a 32kHz reference
> from the HOSC. This is achieved through a muxed clock path using fixed
> pre-dividers to normalize the different crystal frequencies to ~32kHz.
Have you tested whether the actually normalizes the frequency, i.e.
selects a different divider based on the DCXO frequency? Otherwise
we're just lying about the frequency.
> This path reuses the same hardware mux registers as the HOSC clock.
>
> Additionally, this CCU provides several gate clocks for specific
> peripherals, including SerDes, HDMI, and UFS. The driver is implemented
> as an auxiliary driver to be bound to the sun6i-rtc driver.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> drivers/clk/sunxi-ng/Kconfig | 5 +
> drivers/clk/sunxi-ng/Makefile | 2 +
> drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++++++++++
> drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 +++
> drivers/clk/sunxi-ng/ccu_rtc.h | 7 +
> 5 files changed, 236 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 6af2d020e03e..16afbf249f26 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU
> default ARCH_SUNXI
> depends on ARM64 || COMPILE_TEST
>
> +config SUN60I_A733_RTC_CCU
> + tristate "Support for the Allwinner A733 RTC CCU"
> + default ARCH_SUNXI
> + depends on ARM64 || COMPILE_TEST
> +
> config SUN4I_A10_CCU
> tristate "Support for the Allwinner A10/A20 CCU"
> default ARCH_SUNXI
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index c3f810a025a8..b0d823440c33 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
> obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o
> obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o
> obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o
> +obj-$(CONFIG_SUN60I_A733_RTC_CCU) += sun60i-a733-rtc-ccu.o
> obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
> obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
> obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
> @@ -67,6 +68,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o
> sun55i-a523-ccu-y += ccu-sun55i-a523.o
> sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o
> sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o
> +sun60i-a733-rtc-ccu-y += ccu-sun60i-a733-rtc.o
> sun4i-a10-ccu-y += ccu-sun4i-a10.o
> sun5i-ccu-y += ccu-sun5i.o
> sun6i-a31-ccu-y += ccu-sun6i-a31.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c
> new file mode 100644
> index 000000000000..d17aceffa16e
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c
> @@ -0,0 +1,204 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/auxiliary_bus.h>
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +
> +#include "ccu_common.h"
> +
> +#include "ccu_gate.h"
> +#include "ccu_mux.h"
> +#include "ccu_rtc.h"
> +
> +#include "ccu-sun60i-a733-rtc.h"
> +
> +static struct ccu_common iosc_clk = {
> + .reg = DCXO_CTRL_REG,
> + .features = CCU_FEATURE_IOSC_CALIBRATION,
> + .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops,
> + CLK_GET_RATE_NOCACHE),
> +};
> +
> +static struct ccu_common iosc_32k_clk = {
> + .features = CCU_FEATURE_IOSC_CALIBRATION,
> + .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
> + &ccu_iosc_32k_ops,
> + CLK_GET_RATE_NOCACHE),
> +};
> +
> +static SUNXI_CCU_GATE_FW(ext_osc32k_gate_clk, "ext-osc32k-gate",
> + "ext-osc32k", 0x0, BIT(4), 0);
> +
> +static const struct clk_hw *osc32k_parents[] = {
> + &iosc_32k_clk.hw,
> + &ext_osc32k_gate_clk.common.hw,
> +};
> +
> +static struct ccu_mux osc32k_clk = {
> + .mux = _SUNXI_CCU_MUX(0, 1),
> + .common = {
> + .reg = LOSC_CTRL_REG,
> + .features = CCU_FEATURE_KEY_FIELD,
> + .hw.init = CLK_HW_INIT_PARENTS_HW("osc32k",
> + osc32k_parents,
> + &ccu_mux_ops,
> + 0),
> + },
> +};
> +
> +static const struct clk_parent_data hosc_parents[] = {
> + { .fw_name = "osc24M" },
> + { .fw_name = "osc19M" },
> + { .fw_name = "osc26M" },
> + { .fw_name = "osc24M" },
> +};
As mentioned in my reply to the binding, this is wrong. There is only
one input.
The most you can do is check the rate of the parent clock against the
detected one, and _scream_ that the DT is wrong. And maybe override
the reported frequency.
If you want to do the latter, you could add a new fixed rate gated
clock type to our library. You would fill in the rate before the
clocks get registered. I probably wouldn't go that far. We want people
to have correct hardware descriptions.
Funnily enough Allwinner's BSP actually implements a fixed rate gate
for the next 24M-to-32k divider clock.
> +
> +struct ccu_mux hosc_clk = {
> + .enable = DCXO_CTRL_DCXO_EN,
> + .mux = _SUNXI_CCU_MUX(14, 2),
> + .common = {
> + .reg = DCXO_CTRL_REG,
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc",
> + hosc_parents,
> + &ccu_mux_ro_ops,
> + 0),
> + },
> +};
So this is wrong.
> +
> +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] = {
> + { .index = 0, .div = 732 },
Why is it 732 instead of 750?
> + { .index = 1, .div = 586 },
> + { .index = 2, .div = 793 },
> + { .index = 3, .div = 732 },
> +};
> +
> +static struct ccu_mux hosc_32k_mux_clk = {
> + .enable = DCXO_CTRL_DCXO_EN,
No. The parent "hosc" clock owns this. The enable bit for this clock
is actually bit 16 of LOSC_OUT_GATING_REG, which you model below as
a separate gate.
> + .mux = {
> + .shift = 14,
> + .width = 2,
> + .fixed_predivs = hosc_32k_predivs,
> + .n_predivs = ARRAY_SIZE(hosc_32k_predivs),
> + },
> + .common = {
> + .reg = DCXO_CTRL_REG,
> + .features = CCU_FEATURE_FIXED_PREDIV,
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("hosc-32k-mux",
> + hosc_parents,
> + &ccu_mux_ro_ops,
Again, this is just not the way to do it.
> + 0),
> + },
> +};
I would test that it actually does switch dividers, Or at the very least,
it has a larger divider for 26M.
Maybe Andre can help? At least on this SoC the fanout pins are much more
accessible.
> +
> +static SUNXI_CCU_GATE_HW(hosc_32k_clk, "hosc-32k", &hosc_32k_mux_clk.common.hw,
> + LOSC_OUT_GATING_REG, BIT(16), 0);
> +
> +static const struct clk_hw *rtc_32k_parents[] = {
> + &osc32k_clk.common.hw,
> + &hosc_32k_clk.common.hw,
> +};
> +
> +static struct ccu_mux rtc_32k_clk = {
> + .mux = _SUNXI_CCU_MUX(1, 1),
> + .common = {
> + .reg = LOSC_CTRL_REG,
> + .features = CCU_FEATURE_KEY_FIELD,
> + .hw.init = CLK_HW_INIT_PARENTS_HW("rtc-32k",
> + rtc_32k_parents,
> + &ccu_mux_ops,
> + 0),
> + },
> +};
> +
> +static const struct clk_parent_data osc32k_fanout_parents[] = {
> + { .hw = &osc32k_clk.common.hw },
> + { .hw = &ext_osc32k_gate_clk.common.hw },
> + { .hw = &hosc_32k_clk.common.hw },
> +};
> +
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", osc32k_fanout_parents,
> + LOSC_OUT_GATING_REG,
> + 1, 2, /* mux */
> + BIT(0), /* gate */
> + 0);
> +
> +static SUNXI_CCU_GATE_HW(hosc_serdes1_clk, "hosc-serdes1", &hosc_clk.common.hw,
> + DCXO_GATING_REG, DCXO_SERDES1_GATING, 0);
^
Just use the BIT() expression here. Adding these macros doesn't really help.
> +static SUNXI_CCU_GATE_HW(hosc_serdes0_clk, "hosc-serdes0", &hosc_clk.common.hw,
> + DCXO_GATING_REG, DCXO_SERDES0_GATING, 0);
> +static SUNXI_CCU_GATE_HW(hosc_hdmi_clk, "hosc-hdmi", &hosc_clk.common.hw,
> + DCXO_GATING_REG, DCXO_HDMI_GATING, 0);
> +static SUNXI_CCU_GATE_HW(hosc_ufs_clk, "hosc-ufs", &hosc_clk.common.hw,
> + DCXO_GATING_REG, DCXO_UFS_GATING, 0);
> +
> +static struct ccu_common *sun60i_rtc_ccu_clks[] = {
> + &iosc_clk,
> + &iosc_32k_clk,
> + &ext_osc32k_gate_clk.common,
> + &osc32k_clk.common,
> + &hosc_clk.common,
> + &hosc_32k_mux_clk.common,
> + &hosc_32k_clk.common,
> + &rtc_32k_clk.common,
> + &osc32k_fanout_clk.common,
> + &hosc_serdes1_clk.common,
> + &hosc_serdes0_clk.common,
> + &hosc_hdmi_clk.common,
> + &hosc_ufs_clk.common,
> +};
> +
> +static struct clk_hw_onecell_data sun60i_rtc_ccu_hw_clks = {
> + .num = CLK_NUMBER,
> + .hws = {
> + [CLK_IOSC] = &iosc_clk.hw,
> + [CLK_OSC32K] = &osc32k_clk.common.hw,
> + [CLK_HOSC] = &hosc_clk.common.hw,
> + [CLK_RTC_32K] = &rtc_32k_clk.common.hw,
> + [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw,
> + [CLK_HOSC_SERDES1] = &hosc_serdes1_clk.common.hw,
> + [CLK_HOSC_SERDES0] = &hosc_serdes0_clk.common.hw,
> + [CLK_HOSC_HDMI] = &hosc_hdmi_clk.common.hw,
> + [CLK_HOSC_UFS] = &hosc_ufs_clk.common.hw,
> + [CLK_IOSC_32K] = &iosc_32k_clk.hw,
> + [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw,
> + [CLK_HOSC_32K_MUX] = &hosc_32k_mux_clk.common.hw,
> + [CLK_HOSC_32K] = &hosc_32k_clk.common.hw,
> + },
> +};
> +
> +static const struct sunxi_ccu_desc sun60i_rtc_ccu_desc = {
> + .ccu_clks = sun60i_rtc_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sun60i_rtc_ccu_clks),
> +
> + .hw_clks = &sun60i_rtc_ccu_hw_clks,
> +};
> +
> +static int sun60i_rtc_ccu_probe(struct auxiliary_device *adev,
> + const struct auxiliary_device_id *id)
> +{
> + struct device *dev = &adev->dev;
> + void __iomem *reg = dev->platform_data;
> +
> + return devm_sunxi_ccu_probe(dev, reg, &sun60i_rtc_ccu_desc);
> +}
> +
> +static const struct auxiliary_device_id sun60i_ccu_rtc_ids[] = {
> + { .name = SUN6I_RTC_AUX_ID(sun60i) },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(auxiliary, sun60i_ccu_rtc_ids);
> +
> +static struct auxiliary_driver sun60i_ccu_rtc_driver = {
> + .probe = sun60i_rtc_ccu_probe,
> + .id_table = sun60i_ccu_rtc_ids,
> +};
> +module_auxiliary_driver(sun60i_ccu_rtc_driver);
> +
> +MODULE_IMPORT_NS("SUNXI_CCU");
> +MODULE_DESCRIPTION("Support for the Allwinner A733 RTC CCU");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h
> new file mode 100644
> index 000000000000..41ec6195b5e7
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#ifndef _CCU_SUN60I_A733_RTC_H_
> +#define _CCU_SUN60I_A733_RTC_H_
> +
> +#include <dt-bindings/clock/sun60i-a733-rtc.h>
> +
> +#define CLK_IOSC_32K 9
> +#define CLK_EXT_OSC32K_GATE 10
> +#define CLK_HOSC_32K_MUX 11
> +#define CLK_HOSC_32K 12
> +
> +#define CLK_NUMBER (CLK_HOSC_32K + 1)
> +
> +#endif /* _CCU_SUN60I_A733_RTC_H_ */
> diff --git a/drivers/clk/sunxi-ng/ccu_rtc.h b/drivers/clk/sunxi-ng/ccu_rtc.h
> index 1c44c2206a25..665162723796 100644
> --- a/drivers/clk/sunxi-ng/ccu_rtc.h
> +++ b/drivers/clk/sunxi-ng/ccu_rtc.h
> @@ -27,8 +27,15 @@
> #define LOSC_OUT_GATING_REG 0x60
>
> #define DCXO_CTRL_REG 0x160
> +#define DCXO_CTRL_DCXO_EN BIT(1)
> #define DCXO_CTRL_CLK16M_RC_EN BIT(0)
>
> +#define DCXO_GATING_REG 0x16c
> +#define DCXO_SERDES1_GATING BIT(5)
> +#define DCXO_SERDES0_GATING BIT(4)
> +#define DCXO_HDMI_GATING BIT(1)
> +#define DCXO_UFS_GATING BIT(0)
Adding them to the header is probably even less useful, as the output
could change in future chips.
ChenYu
^ permalink raw reply
* Re: [PATCH 6/7] rtc: sun6i: Add support for A733 RTC
From: Chen-Yu Tsai @ 2026-03-28 12:40 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Jernej Skrabec, Samuel Holland,
Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, linux-clk, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-rtc, devicetree
In-Reply-To: <20260121-a733-rtc-v1-6-d359437f23a7@pigmoral.tech>
On Wed, Jan 21, 2026 at 7:04 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> The RTC in the Allwinner A733 SoC is compatible with the H616 in terms
> of its time storage and alarm functionality. However, its internal CCU
> is different, with additional DCXO handling logic.
>
> Add new match data to register a new auxiliary device for its CCU part.
This is probably incorrect, since you aren't actually adding auxiliary
devices. It should just say "add a new compatible and matching data for
the new SoC".
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> drivers/rtc/rtc-sun6i.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
> index b4489e0a09ce..a58d9c6b917c 100644
> --- a/drivers/rtc/rtc-sun6i.c
> +++ b/drivers/rtc/rtc-sun6i.c
> @@ -865,6 +865,11 @@ static const struct sun6i_rtc_match_data sun6i_rtc_match_data = {
> .flags = RTC_LINEAR_DAY,
> };
>
> +static const struct sun6i_rtc_match_data sun60i_rtc_match_data = {
> + .adev_name = "sun60i",
> + .flags = RTC_LINEAR_DAY,
> +};
> +
> /*
> * As far as RTC functionality goes, all models are the same. The
> * datasheets claim that different models have different number of
> @@ -883,6 +888,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = {
> .data = &sun6i_rtc_match_data },
> { .compatible = "allwinner,sun50i-r329-rtc",
> .data = &sun6i_rtc_match_data },
> + { .compatible = "allwinner,sun60i-a733-rtc",
> + .data = &sun60i_rtc_match_data },
> { /* sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
>
> --
> 2.52.0
>
>
^ permalink raw reply
* Re: [PATCH RFC 3/8] clk: sunxi-ng: a733: Add PRCM CCU
From: Chen-Yu Tsai @ 2026-03-28 15:04 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jernej Skrabec, Samuel Holland, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Richard Cochran, linux-clk, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv, netdev
In-Reply-To: <20260310-a733-clk-v1-3-36b4e9b24457@pigmoral.tech>
On Tue, Mar 10, 2026 at 4:42 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> Add support for the Power Reset Clock Management (PRCM) module found in
> the Allwinner A733 SoC. This clock controller manages the clock control
> and reset functions for device modules within the CPUS domain.
>
> The PRCM module includes the management of three primary buses: r-ahb,
> r-apb0, and r-apb1. It also provides clocking for several key
> peripherals, such as R-UART, R-I2C, R-SPI, and the R-RISCV subsystem.
> Additionally, the reset lines for these modules are integrated.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> drivers/clk/sunxi-ng/Kconfig | 5 +
> drivers/clk/sunxi-ng/Makefile | 2 +
> drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 276 +++++++++++++++++++++++++++++++
> 3 files changed, 283 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 6af2d020e03e..202e793dc754 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU
> default ARCH_SUNXI
> depends on ARM64 || COMPILE_TEST
>
> +config SUN60I_A733_R_CCU
> + tristate "Support for the Allwinner A733 PRCM CCU"
> + default ARCH_SUNXI
> + depends on ARM64 || COMPILE_TEST
> +
> config SUN4I_A10_CCU
> tristate "Support for the Allwinner A10/A20 CCU"
> default ARCH_SUNXI
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index a1c4087d7241..d3702bdb7a23 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
> obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o
> obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o
> obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o
> +obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o
> obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
> obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
> obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
> @@ -64,6 +65,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o
> sun55i-a523-ccu-y += ccu-sun55i-a523.o
> sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o
> sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o
> +sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o
> sun4i-a10-ccu-y += ccu-sun4i-a10.o
> sun5i-ccu-y += ccu-sun5i.o
> sun6i-a31-ccu-y += ccu-sun6i-a31.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c
> new file mode 100644
> index 000000000000..06679be1eaae
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c
> @@ -0,0 +1,276 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023 rengaomin@allwinnertech.com
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + * Based on the A523 CCU driver:
> + * Copyright (C) 2024 Arm Ltd.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/sun60i-a733-r-ccu.h>
> +#include <dt-bindings/reset/sun60i-a733-r-ccu.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +
> +static const struct clk_parent_data r_ahb_parents[] = {
> + { .fw_name = "hosc" },
> + { .fw_name = "losc" },
> + { .fw_name = "iosc" },
> + { .fw_name = "pll-periph0-200m" },
> + { .fw_name = "pll-periph0-300m" },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb", r_ahb_parents, 0x000,
> + 0, 5, /* M */
> + 24, 3, /* mux */
> + 0);
> +
> +static const struct clk_parent_data r_apb_parents[] = {
> + { .fw_name = "hosc" },
> + { .fw_name = "losc" },
> + { .fw_name = "iosc" },
> + { .fw_name = "pll-periph0-200m" },
> + { .fw_name = "sys-24m" },
> +};
> +
> +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0", r_apb_parents, 0x00c,
> + 0, 5, /* M */
> + 24, 3, /* mux */
> + 0);
> +
> +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", r_apb_parents, 0x010,
> + 0, 5, /* M */
> + 24, 3, /* mux */
> + 0);
> +
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100,
> + 0, 0, /* no M */
> + 1, 3, /* P */
> + 4, 3, /* mux */
> + BIT(0), /* gate */
> + 0);
Use SUNXI_CCU_P_DATA_WITH_MUX_GATE(). Same for the other ones.
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104,
> + 0, 0, /* no M */
> + 1, 3, /* P */
> + 4, 3, /* mux */
> + BIT(0), /* gate */
> + 0);
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_parents, 0x108,
> + 0, 0, /* no M */
> + 1, 3, /* P */
> + 4, 3, /* mux */
> + BIT(0), /* gate */
> + 0);
> +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0x10c,
> + 0, 0, /* no M */
> + 1, 3, /* P */
> + 4, 3, /* mux */
> + BIT(0), /* gate */
> + 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw, 0x11c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_twd_clk, "bus-r-twd", &r_apb0_clk.common.hw, 0x12c, BIT(0), 0);
> +
> +static const struct clk_parent_data r_pwmctrl_parents[] = {
> + { .fw_name = "hosc" },
> + { .fw_name = "losc" },
> + { .fw_name = "iosc" },
> + { .fw_name = "sys-24m" },
> +};
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", r_pwmctrl_parents, 0x130,
r_pwm_clk, "r-pwm", ...
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
bus_r_pwm_clk, "bus-r-pwm".
> + &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
> +
> +static const struct clk_parent_data r_spi_parents[] = {
> + { .fw_name = "hosc" },
> + { .fw_name = "pll-periph0-200m" },
> + { .fw_name = "pll-periph0-300m" },
> + { .fw_name = "pll-periph1-300m" },
> + { .fw_name = "sys-24m" },
> +};
> +static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
> + 0, 5, /* M */
> + 8, 5, /* N */
> + 24, 3, /* mux */
> + BIT(31), /* gate */
> + 0);
> +static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi", &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0", &r_apb1_clk.common.hw, 0x18c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1", &r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0", &r_apb1_clk.common.hw, 0x19c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1", &r_apb1_clk.common.hw, 0x19c, BIT(1), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2", &r_apb1_clk.common.hw, 0x19c, BIT(2), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_tzma_clk, "bus-r-tzma", &r_apb0_clk.common.hw, 0x1b0, BIT(0), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist", &r_apb0_clk.common.hw,
> + 0x1bc, BIT(0), 0);
> +
> +static const struct clk_parent_data r_ir_rx_parents[] = {
> + { .fw_name = "losc" },
> + { .fw_name = "hosc" },
> + { .fw_name = "sys-24m" },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx", r_ir_rx_parents, 0x1c0,
> + 0, 5, /* M */
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_clk.common.hw, 0x20c, BIT(0), 0);
> +
> +static const struct clk_parent_data r_riscv_parents[] = {
> + { .fw_name = "hosc" },
> + { .fw_name = "losc" },
> + { .fw_name = "iosc" },
> +};
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, "r-riscv", r_riscv_parents, 0x210,
> + 24, 2, /* mux */
> + BIT(31), /* gate */
> + 0);
> +static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw,
> + 0x21c, BIT(0), 0);
> +static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, "bus-r-riscv-cfg", &r_apb0_clk.common.hw,
> + 0x21c, BIT(1), 0);
> +
> +static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_clk.common.hw,
> + 0x22c, BIT(0), CLK_IS_CRITICAL);
> +
> +static struct ccu_common *sun60i_a733_r_ccu_clks[] = {
> + &r_ahb_clk.common,
> + &r_apb0_clk.common,
> + &r_apb1_clk.common,
> + &r_cpu_timer0.common,
> + &r_cpu_timer1.common,
> + &r_cpu_timer2.common,
> + &r_cpu_timer3.common,
> + &bus_r_timer_clk.common,
> + &bus_r_twd_clk.common,
> + &r_pwmctrl_clk.common,
> + &bus_r_pwmctrl_clk.common,
> + &r_spi_clk.common,
> + &bus_r_spi_clk.common,
> + &bus_r_msgbox_clk.common,
> + &bus_r_uart0_clk.common,
> + &bus_r_uart1_clk.common,
> + &bus_r_i2c0_clk.common,
> + &bus_r_i2c1_clk.common,
> + &bus_r_i2c2_clk.common,
> + &bus_r_ppu_clk.common,
> + &bus_r_tzma_clk.common,
> + &bus_r_cpu_bist_clk.common,
> + &r_ir_rx_clk.common,
> + &bus_r_ir_rx_clk.common,
> + &bus_r_rtc_clk.common,
> + &r_riscv_clk.common,
> + &bus_r_riscv_clk.common,
> + &bus_r_riscv_cfg_clk.common,
> + &bus_r_cpucfg_clk.common,
> +};
> +
> +static struct clk_hw_onecell_data sun60i_a733_r_hw_clks = {
> + .hws = {
> + [CLK_R_AHB] = &r_ahb_clk.common.hw,
> + [CLK_R_APB0] = &r_apb0_clk.common.hw,
> + [CLK_R_APB1] = &r_apb1_clk.common.hw,
> + [CLK_R_TIMER0] = &r_cpu_timer0.common.hw,
> + [CLK_R_TIMER1] = &r_cpu_timer1.common.hw,
> + [CLK_R_TIMER2] = &r_cpu_timer2.common.hw,
> + [CLK_R_TIMER3] = &r_cpu_timer3.common.hw,
> + [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
> + [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
> + [CLK_R_PWMCTRL] = &r_pwmctrl_clk.common.hw,
> + [CLK_BUS_R_PWMCTRL] = &bus_r_pwmctrl_clk.common.hw,
> + [CLK_R_SPI] = &r_spi_clk.common.hw,
> + [CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
> + [CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
> + [CLK_BUS_R_UART0] = &bus_r_uart0_clk.common.hw,
> + [CLK_BUS_R_UART1] = &bus_r_uart1_clk.common.hw,
> + [CLK_BUS_R_I2C0] = &bus_r_i2c0_clk.common.hw,
> + [CLK_BUS_R_I2C1] = &bus_r_i2c1_clk.common.hw,
> + [CLK_BUS_R_I2C2] = &bus_r_i2c2_clk.common.hw,
> + [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
> + [CLK_BUS_R_TZMA] = &bus_r_tzma_clk.common.hw,
> + [CLK_BUS_R_CPU_BIST] = &bus_r_cpu_bist_clk.common.hw,
> + [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
> + [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
> + [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
> + [CLK_R_RISCV] = &r_riscv_clk.common.hw,
> + [CLK_BUS_R_RISCV] = &bus_r_riscv_clk.common.hw,
> + [CLK_BUS_R_RISCV_CFG] = &bus_r_riscv_cfg_clk.common.hw,
> + [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
> + },
> + .num = CLK_BUS_R_CPUCFG + 1,
> +};
> +
> +static struct ccu_reset_map sun60i_a733_r_ccu_resets[] = {
> + [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
> + [RST_BUS_R_PWM] = { 0x13c, BIT(16) },
> + [RST_BUS_R_SPI] = { 0x15c, BIT(16) },
> + [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
> + [RST_BUS_R_UART0] = { 0x18c, BIT(16) },
> + [RST_BUS_R_UART1] = { 0x18c, BIT(17) },
> + [RST_BUS_R_I2C0] = { 0x19c, BIT(16) },
> + [RST_BUS_R_I2C1] = { 0x19c, BIT(17) },
> + [RST_BUS_R_I2C2] = { 0x19c, BIT(18) },
> + [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
> + [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
> + [RST_BUS_R_RISCV_CFG] = { 0x21c, BIT(16) },
> + [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
> +};
> +
> +static const struct sunxi_ccu_desc sun60i_a733_r_ccu_desc = {
> + .ccu_clks = sun60i_a733_r_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sun60i_a733_r_ccu_clks),
> +
> + .hw_clks = &sun60i_a733_r_hw_clks,
> +
> + .resets = sun60i_a733_r_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun60i_a733_r_ccu_resets),
> +};
> +
> +static int sun60i_a733_r_ccu_probe(struct platform_device *pdev)
> +{
> + void __iomem *reg;
> +
> + reg = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(reg))
> + return PTR_ERR(reg);
> +
> + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_r_ccu_desc);
> +}
> +
> +static const struct of_device_id sun60i_a733_r_ccu_ids[] = {
> + { .compatible = "allwinner,sun60i-a733-r-ccu" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sun60i_a733_r_ccu_ids);
> +
> +static struct platform_driver sun60i_a733_r_ccu_driver = {
> + .probe = sun60i_a733_r_ccu_probe,
> + .driver = {
> + .name = "sun60i-a733-r-ccu",
> + .suppress_bind_attrs = true,
> + .of_match_table = sun60i_a733_r_ccu_ids,
> + },
> +};
> +module_platform_driver(sun60i_a733_r_ccu_driver);
> +
> +MODULE_IMPORT_NS("SUNXI_CCU");
> +MODULE_DESCRIPTION("Support for the Allwinner A733 PRCM CCU");
> +MODULE_LICENSE("GPL");
The rest look OK.
ChenYu
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: Add RK3562 serial aliases
From: Krzysztof Kozlowski @ 2026-03-28 15:08 UTC (permalink / raw)
To: 谢致邦 (XIE Zhibang), linux-rockchip
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Kever Yang, Finley Xiao, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <tencent_4BED6C3FFB8102B4BB3D08D6F47F2CCFC908@qq.com>
On 28/03/2026 14:05, 谢致邦 (XIE Zhibang) wrote:
> This fixes the stdout-path in rk3562-evb2-v10.dts.
>
> Fixes: ceb6ef1ea900 ("arm64: dts: rockchip: Add RK3562 evb2 devicetree")
> Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3562.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> index e4816aa3dae0..14e74e8ac7df 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
> @@ -26,6 +26,16 @@ aliases {
> gpio2 = &gpio2;
> gpio3 = &gpio3;
> gpio4 = &gpio4;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + serial6 = &uart6;
> + serial7 = &uart7;
> + serial8 = &uart8;
> + serial9 = &uart9;
UART aliases are properties of the boards, not SoC.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 2/2] KVM: arm64: Refactor stage2 mmu tear down functions
From: Wei-Lin Chang @ 2026-03-28 14:54 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, linux-kernel
Cc: Marc Zyngier, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Wei-Lin Chang
In-Reply-To: <20260328145439.2501562-1-weilin.chang@arm.com>
With NV, "stage2 mmu" becomes ambiguous, it could refer to the canonical
one or one of the nested ones. Modify kvm_uninit_stage2_mmu() so that it
can uninitialize both the canonical s2 mmu and nested s2 mmus.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
---
arch/arm64/include/asm/kvm_mmu.h | 2 +-
arch/arm64/kvm/mmu.c | 8 +++++---
arch/arm64/kvm/nested.c | 4 ++--
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 960b6aed4ffa..4b49aabecbf3 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -176,7 +176,7 @@ void kvm_stage2_wp_range(struct kvm_s2_mmu *mmu, phys_addr_t addr, phys_addr_t e
void stage2_unmap_vm(struct kvm *kvm);
int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long type);
-void kvm_uninit_stage2_mmu(struct kvm *kvm);
+void kvm_uninit_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu);
void kvm_free_stage2(struct kvm_s2_mmu *mmu);
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
phys_addr_t pa, unsigned long size, bool writable);
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index b19b9a9b3c27..a2affd70eca6 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1018,10 +1018,12 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long t
return err;
}
-void kvm_uninit_stage2_mmu(struct kvm *kvm)
+void kvm_uninit_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu)
{
- kvm_free_stage2(&kvm->arch.mmu);
- kvm_mmu_free_memory_cache(&kvm->arch.mmu.split_page_cache);
+ kvm_free_stage2(mmu);
+
+ if (!kvm_is_nested_s2_mmu(kvm, mmu))
+ kvm_mmu_free_memory_cache(&mmu->split_page_cache);
}
static void stage2_unmap_memslot(struct kvm *kvm,
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 772d922cf0ee..5eba94d6cc67 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1194,12 +1194,12 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i];
if (!WARN_ON(atomic_read(&mmu->refcnt)))
- kvm_free_stage2(mmu);
+ kvm_uninit_stage2_mmu(kvm, mmu);
}
kvfree(kvm->arch.nested_mmus);
kvm->arch.nested_mmus = NULL;
kvm->arch.nested_mmus_size = 0;
- kvm_uninit_stage2_mmu(kvm);
+ kvm_uninit_stage2_mmu(kvm, &kvm->arch.mmu);
}
/*
--
2.43.0
^ permalink raw reply related
* [PATCH 1/2] KVM: arm64: Rename kvm_free_stage2_pgd()
From: Wei-Lin Chang @ 2026-03-28 14:54 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, linux-kernel
Cc: Marc Zyngier, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Wei-Lin Chang
In-Reply-To: <20260328145439.2501562-1-weilin.chang@arm.com>
kvm_free_stage2_pgd() reads like it is only freeing the top level page
tables (pgd), but it frees every level in kvm_stage2_destroy().
Rename it to kvm_free_stage2() instead.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
---
arch/arm64/include/asm/kvm_mmu.h | 2 +-
arch/arm64/kvm/mmu.c | 4 ++--
arch/arm64/kvm/nested.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 01e9c72d6aa7..960b6aed4ffa 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -177,7 +177,7 @@ void kvm_stage2_wp_range(struct kvm_s2_mmu *mmu, phys_addr_t addr, phys_addr_t e
void stage2_unmap_vm(struct kvm *kvm);
int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long type);
void kvm_uninit_stage2_mmu(struct kvm *kvm);
-void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
+void kvm_free_stage2(struct kvm_s2_mmu *mmu);
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
phys_addr_t pa, unsigned long size, bool writable);
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 17d64a1e11e5..b19b9a9b3c27 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1020,7 +1020,7 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu, unsigned long t
void kvm_uninit_stage2_mmu(struct kvm *kvm)
{
- kvm_free_stage2_pgd(&kvm->arch.mmu);
+ kvm_free_stage2(&kvm->arch.mmu);
kvm_mmu_free_memory_cache(&kvm->arch.mmu.split_page_cache);
}
@@ -1094,7 +1094,7 @@ void stage2_unmap_vm(struct kvm *kvm)
srcu_read_unlock(&kvm->srcu, idx);
}
-void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu)
+void kvm_free_stage2(struct kvm_s2_mmu *mmu)
{
struct kvm *kvm = kvm_s2_mmu_to_kvm(mmu);
struct kvm_pgtable *pgt = NULL;
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 883b6c1008fb..772d922cf0ee 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -110,7 +110,7 @@ int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu)
if (ret) {
for (int i = kvm->arch.nested_mmus_size; i < num_mmus; i++)
- kvm_free_stage2_pgd(&kvm->arch.nested_mmus[i]);
+ kvm_free_stage2(&kvm->arch.nested_mmus[i]);
free_page((unsigned long)vcpu->arch.ctxt.vncr_array);
vcpu->arch.ctxt.vncr_array = NULL;
@@ -1194,7 +1194,7 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i];
if (!WARN_ON(atomic_read(&mmu->refcnt)))
- kvm_free_stage2_pgd(mmu);
+ kvm_free_stage2(mmu);
}
kvfree(kvm->arch.nested_mmus);
kvm->arch.nested_mmus = NULL;
--
2.43.0
^ permalink raw reply related
* [PATCH 0/2] KVM: arm64: Small cleanups for stage-2 mmu teardown
From: Wei-Lin Chang @ 2026-03-28 14:54 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm, linux-kernel
Cc: Marc Zyngier, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Wei-Lin Chang
Hi,
While reading the code I found the uninitialization paths of the s2 mmus
a bit confusing, so I did a small cleanup. It includes renaming a
function and a small refactor. Please see the commit messages for the
details.
Thanks!
Wei-Lin Chang (2):
KVM: arm64: Rename kvm_free_stage2_pgd()
KVM: arm64: Refactor stage2 mmu tear down functions
arch/arm64/include/asm/kvm_mmu.h | 4 ++--
arch/arm64/kvm/mmu.c | 10 ++++++----
arch/arm64/kvm/nested.c | 6 +++---
3 files changed, 11 insertions(+), 9 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH v3 3/3] drm/gem-dma: Support DRM_MODE_DUMB_KERNEL_MAP flag
From: kernel test robot @ 2026-03-28 14:52 UTC (permalink / raw)
To: Chen-Yu Tsai, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter
Cc: oe-kbuild-all, Rob Herring, dri-devel, linux-kernel,
linux-arm-kernel, Chen-Yu Tsai, Sasha Finkelstein, Janne Grunau,
Liviu Dudau, Paul Kocialkowski, Neil Armstrong, Laurent Pinchart,
Tomi Valkeinen, Kieran Bingham, Biju Das, Yannick Fertre,
Raphael Gallais-Pou, Philippe Cornu, Jernej Skrabec,
Dave Stevenson, Maíra Canal, Raspberry Pi Kernel Maintenance,
Icenowy Zheng
In-Reply-To: <20260326100248.1171828-4-wenst@chromium.org>
Hi Chen-Yu,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on next-20260327]
[cannot apply to sunxi/sunxi/for-next linus/master v7.0-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/drm-Introduce-DRM_MODE_DUMB_KERNEL_MAP-flag/20260328-141115
base: https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-next
patch link: https://lore.kernel.org/r/20260326100248.1171828-4-wenst%40chromium.org
patch subject: [PATCH v3 3/3] drm/gem-dma: Support DRM_MODE_DUMB_KERNEL_MAP flag
config: arm-randconfig-001-20260328 (https://download.01.org/0day-ci/archive/20260328/202603282230.Yz4kBrTt-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260328/202603282230.Yz4kBrTt-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603282230.Yz4kBrTt-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/gpu/drm/stm/drv.c: In function 'stm_gem_dma_dumb_create':
>> drivers/gpu/drm/stm/drv.c:55:23: error: 'DRM_MODE_DUMB_KERNEL_MAP' undeclared (first use in this function)
55 | args->flags = DRM_MODE_DUMB_KERNEL_MAP;
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/stm/drv.c:55:23: note: each undeclared identifier is reported only once for each function it appears in
--
drivers/gpu/drm/arm/malidp_drv.c: In function 'malidp_dumb_create':
>> drivers/gpu/drm/arm/malidp_drv.c:467:23: error: 'DRM_MODE_DUMB_KERNEL_MAP' undeclared (first use in this function)
467 | args->flags = DRM_MODE_DUMB_KERNEL_MAP;
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/arm/malidp_drv.c:467:23: note: each undeclared identifier is reported only once for each function it appears in
--
drivers/gpu/drm/arm/display/komeda/komeda_kms.c: In function 'komeda_gem_dma_dumb_create':
>> drivers/gpu/drm/arm/display/komeda/komeda_kms.c:32:23: error: 'DRM_MODE_DUMB_KERNEL_MAP' undeclared (first use in this function)
32 | args->flags = DRM_MODE_DUMB_KERNEL_MAP;
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/arm/display/komeda/komeda_kms.c:32:23: note: each undeclared identifier is reported only once for each function it appears in
vim +/DRM_MODE_DUMB_KERNEL_MAP +55 drivers/gpu/drm/stm/drv.c
43
44 static int stm_gem_dma_dumb_create(struct drm_file *file,
45 struct drm_device *dev,
46 struct drm_mode_create_dumb *args)
47 {
48 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
49
50 /*
51 * in order to optimize data transfer, pitch is aligned on
52 * 128 bytes, height is aligned on 4 bytes
53 */
54 args->height = roundup(args->height, 4);
> 55 args->flags = DRM_MODE_DUMB_KERNEL_MAP;
56 args->pitch = roundup(min_pitch, 128);
57
58 return drm_gem_dma_dumb_create_internal(file, dev, args);
59 }
60
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v3 3/3] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
From: Krzysztof Kozlowski @ 2026-03-28 14:03 UTC (permalink / raw)
To: nick.hawkins
Cc: catalin.marinas, will, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-4-nick.hawkins@hpe.com>
On Fri, Mar 27, 2026 at 12:44:45PM -0500, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> Add SoC-level DTSI for the HPE GSC ARM64 BMC SoC, covering the CPU
> cluster, GIC v3 interrupt controller, ARM64 generic timer, and console
> UART.
>
> Add the board-level DTS for the HPE DL340 Gen12, which includes
> gsc.dtsi and adds memory and chosen nodes.
>
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
You miss fourth commit adding it to defconfig.
> arch/arm64/boot/dts/hpe/Makefile | 2 +
> arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts | 18 ++++
> arch/arm64/boot/dts/hpe/gsc.dtsi | 104 +++++++++++++++++++++
> 3 files changed, 124 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hpe/Makefile
> create mode 100644 arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
> create mode 100644 arch/arm64/boot/dts/hpe/gsc.dtsi
>
> diff --git a/arch/arm64/boot/dts/hpe/Makefile b/arch/arm64/boot/dts/hpe/Makefile
> new file mode 100644
> index 000000000000..6b547b8a8154
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hpe/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +dtb-$(CONFIG_ARCH_HPE) += gsc-dl340gen12.dtb
> diff --git a/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
> new file mode 100644
> index 000000000000..42cfeac99029
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hpe/gsc-dl340gen12.dts
> @@ -0,0 +1,18 @@
> +// SPDX-License-Identifier: GPL-2.0-only
Keep consistent SPDX, so I guess "GPL-2.0" here.
> +/dts-v1/;
> +
> +#include "gsc.dtsi"
> +
> +/ {
> + compatible = "hpe,gsc-dl340gen12", "hpe,gsc";
> + model = "HPE ProLiant DL340 Gen12";
> +
> + chosen {
> + stdout-path = &uartc;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/hpe/gsc.dtsi b/arch/arm64/boot/dts/hpe/gsc.dtsi
> new file mode 100644
> index 000000000000..087688b089e9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hpe/gsc.dtsi
> @@ -0,0 +1,104 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for HPE GSC
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0xa0008048>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <1>;
> + enable-method = "spin-table";
> + cpu-release-addr = <0 0xa0008048>;
> + };
> + };
> +
> + osc: clock-33333333 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-output-names = "osc";
> + clock-frequency = <33333333>;
> + };
> +
> + timer {
Same comment as last time. I see you ignored few more comments and never
responded to them, so I finish the review here.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 2/3] arm64: Kconfig: Add ARCH_HPE platform
From: Krzysztof Kozlowski @ 2026-03-28 14:00 UTC (permalink / raw)
To: nick.hawkins
Cc: catalin.marinas, will, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-3-nick.hawkins@hpe.com>
On Fri, Mar 27, 2026 at 12:44:44PM -0500, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> Add the ARCH_HPE config for HPE ARM64 BMC SoCs to Kconfig.platforms.
>
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
> arch/arm64/Kconfig.platforms | 11 +++++++++++
> 1 file changed, 11 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 1/3] dt-bindings: arm: hpe,gxp: Add HPE GSC platform compatible
From: Krzysztof Kozlowski @ 2026-03-28 14:00 UTC (permalink / raw)
To: nick.hawkins
Cc: catalin.marinas, will, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260327174445.3275835-2-nick.hawkins@hpe.com>
On Fri, Mar 27, 2026 at 12:44:43PM -0500, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> Add the HPE GSC ARM64 BMC SoC compatibles to the existing
> hpe,gxp.yaml binding.
>
> The initial board compatible is hpe,gsc-dl340gen12 for the DL340 Gen12
> server platform.
>
> Add the arm64 DTS path to the existing ARM/HPE GXP MAINTAINERS entry,
> renamed to ARM/HPE GXP/GSC ARCHITECTURE.
>
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
> Documentation/devicetree/bindings/arm/hpe,gxp.yaml | 7 ++++++-
> MAINTAINERS | 3 ++-
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
> index 224bbcb93f95..6f057cd58571 100644
> --- a/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
> +++ b/Documentation/devicetree/bindings/arm/hpe,gxp.yaml
> @@ -4,7 +4,7 @@
> $id: http://devicetree.org/schemas/arm/hpe,gxp.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: HPE BMC GXP platforms
> +title: HPE BMC GXP and GSC platforms
>
> maintainers:
> - Nick Hawkins <nick.hawkins@hpe.com>
> @@ -18,6 +18,11 @@ properties:
> - enum:
> - hpe,gxp-dl360gen10
> - const: hpe,gxp
> + - description: GSC Based Boards
> + items:
> + - enum:
> + - hpe,gsc-dl340gen12
> + - const: hpe,gsc
What sort of ordering are you going to use in this file? Usual choice is
the fallback compatible, but I see you have chosen something else. That
is fine, just keep that else sorting in the future instead of adding to
the end.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 2/2] phy: rockchip: samsung-hdptx: Add support for FRL TxFFE level control
From: Cristian Ciocaltea @ 2026-03-28 13:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com>
During HDMI 2.1 FRL link training, the source may need to incrementally
raise the TxFFE level in response to persistent link failures reported
by the sink during LTS3. The phy_configure_opts_hdmi struct now carries
ffe_level and set_ffe_level fields to convey such an update
independently of a full rate reconfiguration.
Wire up the optional TxFFE control in the Samsung HDPTX PHY driver.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 74 +++++++++++++++++++++--
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 3bde7fbb34b1..c4669853ad0e 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -333,6 +333,7 @@
#define FRL_3G3L_RATE 900000000
#define FRL_6G3L_RATE 1800000000
#define FRL_8G4L_RATE 3200000000
+#define FRL_FFE_MAX_LEVEL 3
enum dp_link_rate {
DP_BW_RBR,
@@ -466,6 +467,16 @@ static const struct ropll_config rk_hdptx_tmds_ropll_cfg[] = {
{ 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, 1, 1, },
};
+static const struct ffe_config {
+ u8 pre_shoot;
+ u8 de_emphasis;
+} rk_hdptx_frl_ffe_cfg[FRL_FFE_MAX_LEVEL + 1] = {
+ { 0x3, 0x4 },
+ { 0x3, 0x6 },
+ { 0x3, 0x8 },
+ { 0x3, 0x9 },
+};
+
static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] = {
REG_SEQ0(CMN_REG(0009), 0x0c),
REG_SEQ0(CMN_REG(000a), 0x83),
@@ -1321,6 +1332,45 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_hdptx_phy *hdptx)
return rk_hdptx_post_enable_lane(hdptx);
}
+static int rk_hdptx_frl_ffe_config(struct rk_hdptx_phy *hdptx, u8 ffe_level)
+{
+ u8 val;
+
+ if (ffe_level > FRL_FFE_MAX_LEVEL)
+ return -EINVAL;
+
+ val = rk_hdptx_frl_ffe_cfg[ffe_level].pre_shoot;
+
+ regmap_update_bits(hdptx->regmap, LANE_REG(0305),
+ LN_TX_DRV_PRE_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0405),
+ LN_TX_DRV_PRE_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0505),
+ LN_TX_DRV_PRE_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0605),
+ LN_TX_DRV_PRE_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val));
+
+ val = rk_hdptx_frl_ffe_cfg[ffe_level].de_emphasis;
+
+ regmap_update_bits(hdptx->regmap, LANE_REG(0304),
+ LN_TX_DRV_POST_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0404),
+ LN_TX_DRV_POST_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0504),
+ LN_TX_DRV_POST_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val));
+ regmap_update_bits(hdptx->regmap, LANE_REG(0604),
+ LN_TX_DRV_POST_LVL_CTRL_MASK,
+ FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val));
+ return 0;
+}
+
static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
{
reset_control_assert(hdptx->rsts[RST_LANE].rstc);
@@ -1730,6 +1780,13 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
unsigned long long frl_rate = 100000000ULL * hdmi_in->frl.lanes *
hdmi_in->frl.rate_per_lane;
+ if (hdmi_in->frl.set_ffe_level) {
+ if (hdmi_in->frl.ffe_level > FRL_FFE_MAX_LEVEL)
+ return -EINVAL;
+
+ return 0;
+ }
+
switch (hdmi_in->frl.rate_per_lane) {
case 3:
case 6:
@@ -2076,11 +2133,18 @@ static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opt
if (ret) {
dev_err(hdptx->dev, "invalid hdmi params for phy configure\n");
} else {
- hdptx->pll_config_dirty = true;
-
- dev_dbg(hdptx->dev, "%s %s rate=%llu bpc=%u\n", __func__,
- hdptx->hdmi_cfg.mode ? "FRL" : "TMDS",
- hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
+ if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL &&
+ opts->hdmi.frl.set_ffe_level) {
+ dev_dbg(hdptx->dev, "%s ffe_level=%u\n", __func__,
+ opts->hdmi.frl.ffe_level);
+ ret = rk_hdptx_frl_ffe_config(hdptx, opts->hdmi.frl.ffe_level);
+ } else {
+ hdptx->pll_config_dirty = true;
+
+ dev_dbg(hdptx->dev, "%s %s rate=%llu bpc=%u\n", __func__,
+ hdptx->hdmi_cfg.mode ? "FRL" : "TMDS",
+ hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc);
+ }
}
return ret;
--
2.52.0
^ permalink raw reply related
* [PATCH 0/2] phy: hdmi: Add FRL TxFFE level control
From: Cristian Ciocaltea @ 2026-03-28 13:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
During HDMI 2.1 Fixed Rate Link training, the source and sink may
negotiate a Transmitter Feed Forward Equalizer (TxFFE) level to
compensate for signal quality degradation on the physical channel. The
source starts at level 0 and may increment it up to a maximum agreed
upon during LTS3 in response to persistent link failures reported by the
sink. TxFFE adjustment is optional and entirely independent of the FRL
rate and lane count selection.
Patch 1 extends the HDMI PHY configuration API with two new fields in
the frl sub-struct: ffe_level to carry the requested level, and a
set_ffe_level flag that switches the semantics of a phy_configure() call
to a pure equalizer update, leaving all other fields ignored.
Patch 2 implements the new interface in the Rockchip Samsung HDPTX PHY
driver.
The series depends on the "[PATCH 0/6] phy: rockchip: samsung-hdptx:
Clock fixes and API transition cleanups" patchset:
https://lore.kernel.org/all/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com/
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Cristian Ciocaltea (2):
phy: hdmi: Add optional FRL TxFFE config options
phy: rockchip: samsung-hdptx: Add support for FRL TxFFE level control
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 74 +++++++++++++++++++++--
include/linux/phy/phy-hdmi.h | 6 ++
2 files changed, 75 insertions(+), 5 deletions(-)
---
base-commit: f7b64ed948718290209074a50bb0df17e5944873
change-id: 20260328-hdptx-ffe-a89c51e66904
prerequisite-change-id: 20260227-hdptx-clk-fixes-47426632f862:v1
prerequisite-patch-id: 5c1d442fae39103bb758f54738aff33d2491401d
prerequisite-patch-id: b86f30292308345387d2a6b50949ad040b931592
prerequisite-patch-id: b1335105db9177cb10c64ed1bf0867832e6aac2f
prerequisite-patch-id: 83db6603d13e19f239e89fde2b26366eb0106b7e
prerequisite-patch-id: b534395ad315811861f11859a3946f65c90c631a
prerequisite-patch-id: f9637e57c902f35218cda658397416f84f7285cb
^ permalink raw reply
* [PATCH 1/2] phy: hdmi: Add optional FRL TxFFE config options
From: Cristian Ciocaltea @ 2026-03-28 13:54 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: kernel, linux-phy, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com>
During HDMI 2.1 FRL link training, the source and sink can negotiate a
Transmitter Feed Forward Equalizer (TxFFE) level to compensate for
signal quality degradation. Starting from zero, the source may
increment the TxFFE level up to a maximum agreed during the LTS3 stage
if the sink keeps reporting FLT failures.
It's worth noting TxFFE adjustment is optional and only attempted when
both the source and the connected sink support it.
Since the existing HDMI PHY configuration API covers the FRL rate/lane
selection only, provide the following fields to the frl sub-struct of
phy_configure_opts_hdmi:
* ffe_level: the TxFFE level to apply, only meaningful when
set_ffe_level is set.
* set_ffe_level: a 1-bit flag that changes the semantics of the
phy_configure() call, i.e. when set, the PHY driver must apply the new
ffe_level and ignore the other frl related fields.
The flag-based approach reflects an important invariant in the link
training process: whenever the FRL rate or lane count changes, the TxFFE
level must be reset to zero. A separate phy_configure() call with
set_ffe_level can only follow after the rate has been established,
making the two operations deliberately distinct.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
include/linux/phy/phy-hdmi.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
index d4cf4430ee8f..1d4b62475079 100644
--- a/include/linux/phy/phy-hdmi.h
+++ b/include/linux/phy/phy-hdmi.h
@@ -19,6 +19,10 @@ enum phy_hdmi_mode {
* @tmds_char_rate: HDMI TMDS Character Rate in Hertz.
* @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps.
* @frl.lanes: HDMI FRL lanes count.
+ * @frl.ffe_level: Transmitter Feed Forward Equalizer Level.
+ * Optional, only meaningful when set_ffe_level flag is on.
+ * @frl.set_ffe_level: Flag indicating whether or not to reconfigure ffe_level.
+ * All the other struct fields must be ignored when this is used.
*
* This structure is used to represent the configuration state of a HDMI phy.
*/
@@ -29,6 +33,8 @@ struct phy_configure_opts_hdmi {
struct {
u8 rate_per_lane;
u8 lanes;
+ u8 ffe_level;
+ u8 set_ffe_level : 1;
} frl;
};
};
--
2.52.0
^ permalink raw reply related
* [PATCH] net: stmmac: dwmac-rk: Fix typo in comment
From: 谢致邦 (XIE Zhibang) @ 2026-03-28 13:43 UTC (permalink / raw)
To: linux-rockchip
Cc: 谢致邦 (XIE Zhibang), Heiko Stuebner,
Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Russell King (Oracle), linux-arm-kernel, netdev, linux-stm32,
linux-kernel
Correct the typo "rk3520" to "rk3528" in comment.
Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index b0441a368cb1..8d7042e68926 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -214,7 +214,7 @@ static int rk_configure_io_clksel(struct rk_priv_data *bsp_priv)
cru = !io;
/* The io_clksel configuration can be either:
- * 0=CRU, 1=IO (rk3506, rk3520, rk3576) or
+ * 0=CRU, 1=IO (rk3506, rk3528, rk3576) or
* 0=IO, 1=CRU (rk3588)
* where CRU means the transmit clock comes from the CRU and IO
* means the transmit clock comes from IO.
--
2.43.0
^ permalink raw reply related
* [PATCH] arm64: dts: rockchip: Add RK3562 serial aliases
From: 谢致邦 (XIE Zhibang) @ 2026-03-28 13:05 UTC (permalink / raw)
To: linux-rockchip
Cc: 谢致邦 (XIE Zhibang), Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Kever Yang,
Finley Xiao, devicetree, linux-arm-kernel, linux-kernel
This fixes the stdout-path in rk3562-evb2-v10.dts.
Fixes: ceb6ef1ea900 ("arm64: dts: rockchip: Add RK3562 evb2 devicetree")
Signed-off-by: 谢致邦 (XIE Zhibang) <Yeking@Red54.com>
---
arch/arm64/boot/dts/rockchip/rk3562.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
index e4816aa3dae0..14e74e8ac7df 100644
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -26,6 +26,16 @@ aliases {
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
};
xin32k: clock-xin32k {
--
2.43.0
^ permalink raw reply related
* Re: [PATCH] soc: fsl: qe_ports_ic: Add missing cleanup on device removal
From: Christophe Leroy (CS GROUP) @ 2026-03-28 12:44 UTC (permalink / raw)
To: Felix Gu, Qiang Zhao; +Cc: linuxppc-dev, linux-arm-kernel, linux-kernel
In-Reply-To: <20260310-qe_ports_ic-v1-1-608293026561@gmail.com>
Le 09/03/2026 à 17:25, Felix Gu a écrit :
> [Vous ne recevez pas souvent de courriers de ustc.gu@gmail.com. Découvrez pourquoi ceci est important à https://aka.ms/LearnAboutSenderIdentification ]
>
> Add a devm action handler to properly clean up the irq_domain and
> chained handler when the device is removed.
>
> Fixes: f0bcd784e1b7 ("soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports")
> Signed-off-by: Felix Gu <ustc.gu@gmail.com>
> ---
> drivers/soc/fsl/qe/qe_ports_ic.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c
> index 8e2107e2cde5..5e3fae19f314 100644
> --- a/drivers/soc/fsl/qe/qe_ports_ic.c
> +++ b/drivers/soc/fsl/qe/qe_ports_ic.c
> @@ -17,6 +17,7 @@
> struct qepic_data {
> void __iomem *reg;
> struct irq_domain *host;
> + int irq;
> };
>
> static void qepic_mask(struct irq_data *d)
> @@ -92,11 +93,18 @@ static const struct irq_domain_ops qepic_host_ops = {
> .map = qepic_host_map,
> };
>
> +static void qepic_remove(void *res)
> +{
> + struct qepic_data *data = res;
> +
> + irq_set_chained_handler_and_data(data->irq, NULL, NULL);
> + irq_domain_remove(data->host);
> +}
> +
> static int qepic_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct qepic_data *data;
> - int irq;
>
> data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> if (!data)
> @@ -106,17 +114,18 @@ static int qepic_probe(struct platform_device *pdev)
> if (IS_ERR(data->reg))
> return PTR_ERR(data->reg);
>
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0)
> - return irq;
> + data->irq = platform_get_irq(pdev, 0);
> + if (data->irq < 0)
> + return data->irq;
>
> data->host = irq_domain_add_linear(dev->of_node, 32, &qepic_host_ops, data);
> if (!data->host)
> return -ENODEV;
>
> - irq_set_chained_handler_and_data(irq, qepic_cascade, data);
> + irq_set_chained_handler_and_data(data->irq, qepic_cascade, data);
> +
> + return devm_add_action_or_reset(dev, qepic_remove, data);
>
> - return 0;
> }
>
> static const struct of_device_id qepic_match[] = {
>
> ---
> base-commit: a0ae2a256046c0c5d3778d1a194ff2e171f16e5f
> change-id: 20260310-qe_ports_ic-ca4c98bd1c4f
>
> Best regards,
> --
> Felix Gu <ustc.gu@gmail.com>
>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH RFC 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
From: Chen-Yu Tsai @ 2026-03-28 12:07 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jernej Skrabec, Samuel Holland, Philipp Zabel,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Richard Cochran, linux-clk, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv, netdev
In-Reply-To: <20260310-a733-clk-v1-1-36b4e9b24457@pigmoral.tech>
On Tue, Mar 10, 2026 at 4:42 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> The CCU and R-CCU (PRCM) modules provide clocks and reset functions for
> the Allwinner A733 SoC. The clock architecture of the A733 is evolved
> from the A523, though the root clocking strategy transitions from a
> static oscillator frequency in the Devicetree to the "hosc" clock, which
> is determined by choosing from three possible frequencies (19.2MHz,
> 24MHz, or 26MHz) by the RTC hardware, and finally feeds the CCU and
> R-CCU.
>
> Additionally, the MCU_CCU module found in previous designs is removed
> from the A733, and the clock tree is expanded with more clock outputs
> to support new functional modules.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
> .../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 ++++++++
> include/dt-bindings/clock/sun60i-a733-ccu.h | 289 +++++++++++++++++++++
> include/dt-bindings/clock/sun60i-a733-r-ccu.h | 39 +++
> include/dt-bindings/reset/sun60i-a733-ccu.h | 131 ++++++++++
> include/dt-bindings/reset/sun60i-a733-r-ccu.h | 23 ++
> 5 files changed, 589 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml
> new file mode 100644
> index 000000000000..aff3ff731285
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner A733 Clock Control Unit
> +
> +maintainers:
> + - Junhui Liu <junhui.liu@pigmoral.tech>
> +
> +properties:
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + compatible:
> + enum:
> + - allwinner,sun60i-a733-ccu
> + - allwinner,sun60i-a733-r-ccu
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 4
> + maxItems: 7
> +
> + clock-names:
> + minItems: 4
> + maxItems: 7
> +
> +required:
> + - "#clock-cells"
> + - "#reset-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + enum:
> + - allwinner,sun60i-a733-ccu
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)
> + - description: Low Frequency Oscillator (usually at 32kHz)
> + - description: Internal Oscillator
> + - description: Low Frequency Oscillator fanout
> +
> + clock-names:
> + items:
> + - const: hosc
> + - const: losc
> + - const: iosc
> + - const: losc-fanout
> +
> + - if:
> + properties:
> + compatible:
> + enum:
> + - allwinner,sun60i-a733-r-ccu
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)
> + - description: Low Frequency Oscillator (usually at 32kHz)
> + - description: Internal Oscillator
> + - description: System 24MHz Clock
> + - description: Peripherals PLL 0 (200 MHz output)
> + - description: Peripherals PLL 0 (300 MHz output)
> + - description: Peripherals PLL 1 (300 MHz output)
> +
> + clock-names:
> + items:
> + - const: hosc
> + - const: losc
> + - const: iosc
> + - const: sys-24m
> + - const: pll-periph0-200m
> + - const: pll-periph0-300m
> + - const: pll-periph1-300m
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@2002000 {
> + compatible = "allwinner,sun60i-a733-ccu";
> + reg = <0x02002000 0x2000>;
> + clocks = <&rtc 2>, <&rtc 1>, <&rtc 0>, <&rtc 4>;
> + clock-names = "hosc", "losc", "iosc", "losc-fanout";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> +...
This part looks correct.
> diff --git a/include/dt-bindings/clock/sun60i-a733-ccu.h b/include/dt-bindings/clock/sun60i-a733-ccu.h
> new file mode 100644
> index 000000000000..1a98bea8ca9a
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun60i-a733-ccu.h
> @@ -0,0 +1,289 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_
> +#define _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_
> +
> +#define CLK_PLL_REF 0
> +#define CLK_SYS_24M 1
> +#define CLK_PLL_DDR 2
> +#define CLK_PLL_PERIPH0_4X 3
> +#define CLK_PLL_PERIPH0_2X 4
> +#define CLK_PLL_PERIPH0_800M 5
> +#define CLK_PLL_PERIPH0_480M 6
> +#define CLK_PLL_PERIPH0_600M 7
> +#define CLK_PLL_PERIPH0_400M 8
> +#define CLK_PLL_PERIPH0_300M 9
> +#define CLK_PLL_PERIPH0_200M 10
> +#define CLK_PLL_PERIPH0_160M 11
> +#define CLK_PLL_PERIPH0_150M 12
> +#define CLK_PLL_PERIPH1_4X 13
> +#define CLK_PLL_PERIPH1_2X 14
> +#define CLK_PLL_PERIPH1_800M 15
> +#define CLK_PLL_PERIPH1_480M 16
> +#define CLK_PLL_PERIPH1_600M 17
> +#define CLK_PLL_PERIPH1_400M 18
> +#define CLK_PLL_PERIPH1_300M 19
> +#define CLK_PLL_PERIPH1_200M 20
> +#define CLK_PLL_PERIPH1_160M 21
> +#define CLK_PLL_PERIPH1_150M 22
> +#define CLK_PLL_GPU 23
Please keep the unit number even if there is only one instance.
This is PLL_GPU0.
> +#define CLK_PLL_VIDEO0_8X 24
If this is the common parent for the 4X and 3X dividers, shouldn't it
be 12X?
> +#define CLK_PLL_VIDEO0_4X 25
> +#define CLK_PLL_VIDEO0_3X 26
> +#define CLK_PLL_VIDEO1_8X 27
Same here.
> +#define CLK_PLL_VIDEO1_4X 28
> +#define CLK_PLL_VIDEO1_3X 29
> +#define CLK_PLL_VIDEO2_8X 30
And here.
> +#define CLK_PLL_VIDEO2_4X 31
> +#define CLK_PLL_VIDEO2_3X 32
> +#define CLK_PLL_VE0 33
> +#define CLK_PLL_VE1 34
> +#define CLK_PLL_AUDIO0_4X 35
> +#define CLK_PLL_AUDIO1 36
> +#define CLK_PLL_AUDIO1_DIV2 37
> +#define CLK_PLL_AUDIO1_DIV5 38
> +#define CLK_PLL_NPU 39
> +#define CLK_PLL_DE 40
Should be DE_12X?
> +#define CLK_PLL_DE_4X 41
> +#define CLK_PLL_DE_3X 42
> +#define CLK_AHB 43
> +#define CLK_APB0 44
> +#define CLK_APB1 45
> +#define CLK_APB_UART 46
> +#define CLK_TRACE 47
> +#define CLK_GIC 48
> +#define CLK_CPU_PERI 49
> +#define CLK_BUS_ITS_PCIE 50
Please preserve the _ACLK suffix.
Please keep the unit number even if there is only one instance.
Basically, use the naming from the user manual. This is ITS0.
> +#define CLK_NSI 51
> +#define CLK_BUS_NSI 52
CLK_BUS_NSI_CFG
> +#define CLK_MBUS 53
> +#define CLK_MBUS_IOMMU0_SYS 54
> +#define CLK_APB_IOMMU0_SYS 55
> +#define CLK_AHB_IOMMU0_SYS 56
Please add a comment at the top describing the renaming to let the
reader know how to search for the in the user manual.
PCLK -> APB
HCLK -> AHB
MCLK -> MBUS
And that the bus name was moved from the end of the name to the front.
> +#define CLK_BUS_MSI_LITE0 57
> +#define CLK_BUS_MSI_LITE1 58
> +#define CLK_BUS_MSI_LITE2 59
> +#define CLK_MBUS_IOMMU1_SYS 60
> +#define CLK_APB_IOMMU1_SYS 61
> +#define CLK_AHB_IOMMU1_SYS 62
> +#define CLK_AHB_VE_DEC 63
> +#define CLK_AHB_VE_ENC 64
> +#define CLK_AHB_VID_IN 65
> +#define CLK_AHB_VID_COUT0 66
> +#define CLK_AHB_VID_COUT1 67
> +#define CLK_AHB_DE 68
> +#define CLK_AHB_NPU 69
> +#define CLK_AHB_GPU0 70
> +#define CLK_AHB_SERDES 71
> +#define CLK_AHB_USB_SYS 72
> +#define CLK_AHB_MSI_LITE0 73
> +#define CLK_AHB_STORE 74
> +#define CLK_AHB_CPUS 75
> +#define CLK_MBUS_IOMMU0 76
> +#define CLK_MBUS_IOMMU1 77
> +#define CLK_MBUS_DESYS 78
> +#define CLK_MBUS_VE_ENC_GATE 79
Please keep the unit number even if there is only one instance.
This is VE_ENC0.
> +#define CLK_MBUS_VE_DEC_GATE 80
> +#define CLK_MBUS_GPU0 81
> +#define CLK_MBUS_NPU 82
> +#define CLK_MBUS_VID_IN 83
> +#define CLK_MBUS_SERDES 84
> +#define CLK_MBUS_MSI_LITE0 85
> +#define CLK_MBUS_STORE 86
> +#define CLK_MBUS_MSI_LITE2 87
> +#define CLK_MBUS_DMA0 88
> +#define CLK_MBUS_VE_ENC 89
> +#define CLK_MBUS_CE 90
> +#define CLK_MBUS_DMA1 91
> +#define CLK_MBUS_NAND 92
> +#define CLK_MBUS_CSI 93
> +#define CLK_MBUS_ISP 94
> +#define CLK_MBUS_GMAC0 95
> +#define CLK_MBUS_GMAC1 96
There is no GMAC1 in the A733 user manual v0.92. Please add a note about
where this came from.
> +#define CLK_MBUS_VE_DEC 97
> +#define CLK_BUS_DMA0 98
> +#define CLK_BUS_DMA1 99
> +#define CLK_BUS_SPINLOCK 100
> +#define CLK_BUS_MSGBOX 101
Please keep the unit number even if there is only one instance.
This is MSGBOX0.
> +#define CLK_BUS_PWM0 102
> +#define CLK_BUS_PWM1 103
> +#define CLK_BUS_DBG 104
> +#define CLK_BUS_SYSDAP 105
> +#define CLK_TIMER0 106
> +#define CLK_TIMER1 107
> +#define CLK_TIMER2 108
> +#define CLK_TIMER3 109
> +#define CLK_TIMER4 110
> +#define CLK_TIMER5 111
> +#define CLK_TIMER6 112
> +#define CLK_TIMER7 113
> +#define CLK_TIMER8 114
> +#define CLK_TIMER9 115
> +#define CLK_BUS_TIMER 116
> +#define CLK_AVS 117
There is no AVS in the A733 user manual v0.92. Please add a note about
where this came from.
> +#define CLK_DE 118
Please keep the unit number even if there is only one instance.
This is DE0.
> +#define CLK_BUS_DE 119
Same here.
> +#define CLK_DI 120
> +#define CLK_BUS_DI 121
> +#define CLK_G2D 122
> +#define CLK_BUS_G2D 123
> +#define CLK_EINK 124
> +#define CLK_EINK_PANEL 125
> +#define CLK_BUS_EINK 126
> +#define CLK_VE_ENC 127
Please keep the unit number even if there is only one instance.
This is VE_ENC0.
> +#define CLK_VE_DEC 128
> +#define CLK_BUS_VE_ENC 129
Same here.
> +#define CLK_BUS_VE_DEC 130
> +#define CLK_CE 131
> +#define CLK_BUS_CE 132
> +#define CLK_BUS_CE_SYS 133
> +#define CLK_NPU 134
> +#define CLK_BUS_NPU 135
> +#define CLK_GPU 136
> +#define CLK_BUS_GPU 137
Please keep the unit number even if there is only one instance.
This is GPU0.
> +#define CLK_DRAM 138
> +#define CLK_BUS_DRAM 139
This is DRAM0.
> +#define CLK_NAND0 140
CLK_NAND0_CLK0
> +#define CLK_NAND1 141
CLK_NAND0_CLK1
> +#define CLK_BUS_NAND 142
CLK_BUS_NAND0
> +#define CLK_MMC0 143
> +#define CLK_MMC1 144
> +#define CLK_MMC2 145
> +#define CLK_MMC3 146
> +#define CLK_BUS_MMC0 147
> +#define CLK_BUS_MMC1 148
> +#define CLK_BUS_MMC2 149
> +#define CLK_BUS_MMC3 150
The ordering is wrong. The module clocks and bus clocks are interleaved.
MMC0, BUS_MMC0, MMC1, BUS_MMC1, ...
> +#define CLK_UFS_AXI 151
> +#define CLK_UFS_CFG 152
> +#define CLK_BUS_UFS 153
> +#define CLK_BUS_UART0 154
> +#define CLK_BUS_UART1 155
> +#define CLK_BUS_UART2 156
> +#define CLK_BUS_UART3 157
> +#define CLK_BUS_UART4 158
> +#define CLK_BUS_UART5 159
> +#define CLK_BUS_UART6 160
> +#define CLK_BUS_I2C0 161
> +#define CLK_BUS_I2C1 162
> +#define CLK_BUS_I2C2 163
> +#define CLK_BUS_I2C3 164
> +#define CLK_BUS_I2C4 165
> +#define CLK_BUS_I2C5 166
> +#define CLK_BUS_I2C6 167
> +#define CLK_BUS_I2C7 168
> +#define CLK_BUS_I2C8 169
> +#define CLK_BUS_I2C9 170
> +#define CLK_BUS_I2C10 171
> +#define CLK_BUS_I2C11 172
> +#define CLK_BUS_I2C12 173
> +#define CLK_SPI0 174
> +#define CLK_SPI1 175
> +#define CLK_SPI2 176
> +#define CLK_SPI3 177
> +#define CLK_SPI4 178
> +#define CLK_BUS_SPI0 179
> +#define CLK_BUS_SPI1 180
> +#define CLK_BUS_SPI2 181
> +#define CLK_BUS_SPI3 182
> +#define CLK_BUS_SPI4 183
Same as MMC ones, SPI module clocks and bus clocks are interleaved.
The user manual doesn't show SPI4. Please add a note saying where the
information is from.
> +#define CLK_SPIF 184
> +#define CLK_BUS_SPIF 185
SPIF comes before SPI3. Please keep the ordering based on the registers.
> +#define CLK_GPADC 186
CLK_GPADC_24M
> +#define CLK_BUS_GPADC 187
CLK_BUS_GPADC0
> +#define CLK_BUS_THS 188
CLK_BUS_THS0
> +#define CLK_IRRX 189
> +#define CLK_BUS_IRRX 190
> +#define CLK_IRTX 191
> +#define CLK_BUS_IRTX 192
> +#define CLK_BUS_LRADC 193
> +#define CLK_SGPIO 194
> +#define CLK_BUS_SGPIO 195
> +#define CLK_LPC 196
> +#define CLK_BUS_LPC 197
These aren't found in the user manual. Please document where they were found.
> +#define CLK_I2SPCM0 198
> +#define CLK_I2SPCM1 199
> +#define CLK_I2SPCM2 200
> +#define CLK_I2SPCM3 201
> +#define CLK_I2SPCM4 202
> +#define CLK_BUS_I2SPCM0 203
> +#define CLK_BUS_I2SPCM1 204
> +#define CLK_BUS_I2SPCM2 205
> +#define CLK_BUS_I2SPCM3 206
> +#define CLK_BUS_I2SPCM4 207
Module clocks and bus clocks are interleaved.
> +#define CLK_I2SPCM2_ASRC 208
This would come before BUS_I2SPCM2.
> +#define CLK_OWA_TX 209
> +#define CLK_OWA_RX 210
> +#define CLK_BUS_OWA 211
s/OWA/SPDIF/
> +#define CLK_DMIC 212
> +#define CLK_BUS_DMIC 213
> +#define CLK_USB_OHCI0 214
> +#define CLK_BUS_OTG 215
> +#define CLK_BUS_EHCI0 216
> +#define CLK_BUS_OHCI0 217
Order should be OHCI0 -> EHCI0 -> OTG
> +#define CLK_USB_OHCI1 218
> +#define CLK_BUS_EHCI1 219
> +#define CLK_BUS_OHCI1 220
OHCI1, then EHCI1.
> +#define CLK_USB_REF 221
USB01_REF to keep the numbering but keeping it short.
> +#define CLK_USB2_U2_REF 222
> +#define CLK_USB2_SUSPEND 223
> +#define CLK_USB2_MF 224
> +#define CLK_USB2_U3_UTMI 225
> +#define CLK_USB2_U2_PIPE 226
Side-note:
I think the manual got this reversed, since UTMI is used for USB 2.0,
while PIPE is used for USB 3.0. But we will stick to whatever the user
manual says.
> +#define CLK_PCIE_AUX 227
> +#define CLK_PCIE_AXI_SLV 228
> +#define CLK_SERDES_PHY 229
> +#define CLK_GMAC_PTP 230
> +#define CLK_GMAC0_PHY 231
> +#define CLK_GMAC1_PHY 232
> +#define CLK_BUS_GMAC0 233
Based on your driver, BUS_GMAC0 should come before GMAC1_PHY.
> +#define CLK_BUS_GMAC1 234
There is no GMAC1 mentioned in the A733 manual. Please document where
you found this.
> +#define CLK_TCON_LCD0 235
> +#define CLK_TCON_LCD1 236
> +#define CLK_TCON_LCD2 237
> +#define CLK_BUS_TCON_LCD0 238
> +#define CLK_BUS_TCON_LCD1 239
> +#define CLK_BUS_TCON_LCD2 240
Module clocks are interleaved with bus clock gates.
> +#define CLK_DSI0 241
> +#define CLK_DSI1 242
> +#define CLK_BUS_DSI0 243
> +#define CLK_BUS_DSI1 244
Same for DSI.
> +#define CLK_COMBPHY0 245
> +#define CLK_COMBPHY1 246
> +#define CLK_BUS_TCON_TV0 247
> +#define CLK_BUS_TCON_TV1 248
> +#define CLK_EDP_TV 249
> +#define CLK_BUS_EDP_TV 250
> +#define CLK_HDMI_CEC_32K 251
> +#define CLK_HDMI_CEC 252
> +#define CLK_HDMI_TV 253
> +#define CLK_BUS_HDMI_TV 254
> +#define CLK_HDMI_SFR 255
> +#define CLK_HDMI_ESM 256
HDCP_ESM.
> +#define CLK_BUS_DPSS_TOP0 257
> +#define CLK_BUS_DPSS_TOP1 258
> +#define CLK_LEDC 259
> +#define CLK_BUS_LEDC 260
> +#define CLK_BUS_DSC 261
> +#define CLK_CSI_MASTER0 262
> +#define CLK_CSI_MASTER1 263
> +#define CLK_CSI_MASTER2 264
> +#define CLK_CSI 265
> +#define CLK_BUS_CSI 266
> +#define CLK_ISP 267
I guess we don't need to add any of the PLL output gates since they are
auto-gated?
Also, there is a RES_DCAP_24M_GATE at 0x1a00. Any idea about this one?
> +#define CLK_APB2JTAG 268
> +#define CLK_FANOUT_24M 269
> +#define CLK_FANOUT_12M 270
> +#define CLK_FANOUT_16M 271
> +#define CLK_FANOUT_25M 272
> +#define CLK_FANOUT_27M 273
> +#define CLK_FANOUT_PCLK 274
> +#define CLK_FANOUT0 275
> +#define CLK_FANOUT1 276
> +#define CLK_FANOUT2 277
> +#define CLK_FANOUT3 278
The rest are fine.
> +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ */
> diff --git a/include/dt-bindings/clock/sun60i-a733-r-ccu.h b/include/dt-bindings/clock/sun60i-a733-r-ccu.h
> new file mode 100644
> index 000000000000..1c717cc588b8
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun60i-a733-r-ccu.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_
> +#define _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_
> +
> +#define CLK_R_AHB 0
> +#define CLK_R_APB0 1
> +#define CLK_R_APB1 2
> +#define CLK_R_TIMER0 3
> +#define CLK_R_TIMER1 4
> +#define CLK_R_TIMER2 5
> +#define CLK_R_TIMER3 6
> +#define CLK_BUS_R_TIMER 7
> +#define CLK_BUS_R_TWD 8
> +#define CLK_R_PWMCTRL 9
> +#define CLK_BUS_R_PWMCTRL 10
*_R_PWM.
> +#define CLK_R_SPI 11
> +#define CLK_BUS_R_SPI 12
> +#define CLK_BUS_R_MSGBOX 13
> +#define CLK_BUS_R_UART0 14
> +#define CLK_BUS_R_UART1 15
> +#define CLK_BUS_R_I2C0 16
> +#define CLK_BUS_R_I2C1 17
> +#define CLK_BUS_R_I2C2 18
> +#define CLK_BUS_R_PPU 19
> +#define CLK_BUS_R_TZMA 20
> +#define CLK_BUS_R_CPU_BIST 21
> +#define CLK_R_IR_RX 22
> +#define CLK_BUS_R_IR_RX 23
> +#define CLK_BUS_R_RTC 24
> +#define CLK_R_RISCV 25
> +#define CLK_BUS_R_RISCV 26
> +#define CLK_BUS_R_RISCV_CFG 27
> +#define CLK_BUS_R_CPUCFG 28
> +
> +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ */
> diff --git a/include/dt-bindings/reset/sun60i-a733-ccu.h b/include/dt-bindings/reset/sun60i-a733-ccu.h
> new file mode 100644
> index 000000000000..11ce78cf04dd
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun60i-a733-ccu.h
> @@ -0,0 +1,131 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_SUN60I_A733_CCU_H_
> +#define _DT_BINDINGS_RST_SUN60I_A733_CCU_H_
> +
> +#define RST_BUS_ITS_PCIE 0
> +#define RST_BUS_NSI 1
> +#define RST_BUS_NSI_CFG 2
> +#define RST_BUS_IOMMU0_SYS 3
> +#define RST_BUS_MSI_LITE0_AHB 4
> +#define RST_BUS_MSI_LITE0_MBUS 5
> +#define RST_BUS_MSI_LITE1_AHB 6
> +#define RST_BUS_MSI_LITE1_MBUS 7
> +#define RST_BUS_MSI_LITE2_AHB 8
> +#define RST_BUS_MSI_LITE2_MBUS 9
> +#define RST_BUS_IOMMU1_SYS 10
> +#define RST_BUS_DMA0 11
> +#define RST_BUS_DMA1 12
> +#define RST_BUS_SPINLOCK 13
> +#define RST_BUS_MSGBOX 14
> +#define RST_BUS_PWM0 15
> +#define RST_BUS_PWM1 16
> +#define RST_BUS_DBG 17
> +#define RST_BUS_SYSDAP 18
> +#define RST_BUS_TIMER0 19
> +#define RST_BUS_DE 20
Please keep the unit number even if there is only one instance.
This is DE0.
> +#define RST_BUS_DI 21
> +#define RST_BUS_G2D 22
> +#define RST_BUS_EINK 23
> +#define RST_BUS_DE_SYS 24
> +#define RST_BUS_VE_ENC 25
Please keep the unit number even if there is only one instance.
This is VE_ENC0.
> +#define RST_BUS_VE_DEC 26
> +#define RST_BUS_CE 27
> +#define RST_BUS_CE_SYS 28
> +#define RST_BUS_NPU_CORE 29
> +#define RST_BUS_NPU_AXI 30
> +#define RST_BUS_NPU_AHB 31
> +#define RST_BUS_NPU_SRAM 32
> +#define RST_BUS_GPU 33
> +#define RST_BUS_DRAM 34
> +#define RST_BUS_NAND 35
> +#define RST_BUS_MMC0 36
> +#define RST_BUS_MMC1 37
> +#define RST_BUS_MMC2 38
> +#define RST_BUS_MMC3 39
> +#define RST_BUS_UFS_AHB 40
> +#define RST_BUS_UFS_AXI 41
> +#define RST_BUS_UFS_PHY 42
> +#define RST_BUS_UFS_CORE 43
> +#define RST_BUS_UART0 44
> +#define RST_BUS_UART1 45
> +#define RST_BUS_UART2 46
> +#define RST_BUS_UART3 47
> +#define RST_BUS_UART4 48
> +#define RST_BUS_UART5 49
> +#define RST_BUS_UART6 50
> +#define RST_BUS_I2C0 51
> +#define RST_BUS_I2C1 52
> +#define RST_BUS_I2C2 53
> +#define RST_BUS_I2C3 54
> +#define RST_BUS_I2C4 55
> +#define RST_BUS_I2C5 56
> +#define RST_BUS_I2C6 57
> +#define RST_BUS_I2C7 58
> +#define RST_BUS_I2C8 59
> +#define RST_BUS_I2C9 60
> +#define RST_BUS_I2C10 61
> +#define RST_BUS_I2C11 62
> +#define RST_BUS_I2C12 63
> +#define RST_BUS_SPI0 64
> +#define RST_BUS_SPI1 65
> +#define RST_BUS_SPI2 66
> +#define RST_BUS_SPIF 67
Here you have SPIF in the correct position.
> +#define RST_BUS_SPI3 68
> +#define RST_BUS_SPI4 69
Please add a note saying where SPI4 was found.
> +#define RST_BUS_GPADC 70
RST_BUS_GPADC0
> +#define RST_BUS_THS 71
RST_BUS_THS0
> +#define RST_BUS_IRRX 72
> +#define RST_BUS_IRTX 73
> +#define RST_BUS_LRADC 74
> +#define RST_BUS_SGPIO 75
> +#define RST_BUS_LPC 76
> +#define RST_BUS_I2SPCM0 77
> +#define RST_BUS_I2SPCM1 78
> +#define RST_BUS_I2SPCM2 79
> +#define RST_BUS_I2SPCM3 80
> +#define RST_BUS_I2SPCM4 81
> +#define RST_BUS_OWA 82
> +#define RST_BUS_DMIC 83
> +#define RST_USB_PHY0 84
> +#define RST_BUS_OHCI0 85
> +#define RST_BUS_EHCI0 86
> +#define RST_BUS_OTG 87
> +#define RST_USB_PHY1 88
> +#define RST_BUS_OHCI1 89
> +#define RST_BUS_EHCI1 90
> +#define RST_BUS_USB2 91
> +#define RST_BUS_PCIE 92
> +#define RST_BUS_PCIE_PWRUP 93
PCIE_PWRUP comes before PCIE.
> +#define RST_BUS_SERDES 94
> +#define RST_BUS_GMAC0 95
> +#define RST_BUS_GMAC0_AXI 96
> +#define RST_BUS_GMAC1 97
> +#define RST_BUS_GMAC1_AXI 98
> +#define RST_BUS_TCON_LCD0 99
> +#define RST_BUS_TCON_LCD1 100
> +#define RST_BUS_TCON_LCD2 101
> +#define RST_BUS_LVDS0 102
> +#define RST_BUS_LVDS1 103
> +#define RST_BUS_DSI0 104
> +#define RST_BUS_DSI1 105
> +#define RST_BUS_TCON_TV0 106
> +#define RST_BUS_TCON_TV1 107
> +#define RST_BUS_EDP 108
> +#define RST_BUS_HDMI_MAIN 109
> +#define RST_BUS_HDMI_SUB 110
> +#define RST_BUS_HDMI_HDCP 111
> +#define RST_BUS_DPSS_TOP0 112
> +#define RST_BUS_DPSS_TOP1 113
> +#define RST_BUS_VIDEO_OUT0 114
> +#define RST_BUS_VIDEO_OUT1 115
> +#define RST_BUS_LEDC 116
> +#define RST_BUS_DSC 117
> +#define RST_BUS_CSI 118
> +#define RST_BUS_VIDEO_IN 119
> +#define RST_BUS_APB2JTAG 120
> +
The rest look correct.
> +#endif /* _DT_BINDINGS_RST_SUN60I_A733_CCU_H_ */
> diff --git a/include/dt-bindings/reset/sun60i-a733-r-ccu.h b/include/dt-bindings/reset/sun60i-a733-r-ccu.h
> new file mode 100644
> index 000000000000..629e546d1998
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun60i-a733-r-ccu.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#ifndef _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_
> +#define _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_
> +
> +#define RST_BUS_R_TIMER 0
> +#define RST_BUS_R_PWM 1
> +#define RST_BUS_R_SPI 2
> +#define RST_BUS_R_MSGBOX 3
> +#define RST_BUS_R_UART0 4
> +#define RST_BUS_R_UART1 5
> +#define RST_BUS_R_I2C0 6
> +#define RST_BUS_R_I2C1 7
> +#define RST_BUS_R_I2C2 8
> +#define RST_BUS_R_IR_RX 9
> +#define RST_BUS_R_RTC 10
> +#define RST_BUS_R_RISCV_CFG 11
> +#define RST_BUS_R_CPUCFG 12
> +
> +#endif /* _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_ */
This part looks correct.
ChenYu
^ permalink raw reply
* Re: [PATCH v4 11/14] dt-bindings: media: mediatek: vcodec: add decoder dt-bindings for mt8196
From: Krzysztof Kozlowski @ 2026-03-28 12:22 UTC (permalink / raw)
To: Yunfei Dong
Cc: Nícolas F . R . A . Prado, Sebastian Fricke,
Nicolas Dufresne, Hans Verkuil, AngeloGioacchino Del Regno,
Benjamin Gaignard, Nathan Hebert, Daniel Almeida, Hsin-Yi Wang,
Fritz Koenig, Daniel Vetter, Steve Cho, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20260328051630.7937-12-yunfei.dong@mediatek.com>
On Sat, Mar 28, 2026 at 01:16:21PM +0800, Yunfei Dong wrote:
> Add decoder document in dt-bindings yaml file for mt8196 platform.
>
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> ---
> .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 1 +
> 1 file changed, 1 insertion(+)
Still incomplete constraints. If the binding defines flexibly/variable
lists, each device MUST have them constrained.
Or explained WHY NOT in the commit msg. You have entire commit msg to
say something useful explaining unexpected changes, instead of repeating
the subject.
Also, reversed subject prefix:
Please use subject prefixes matching the subsystem. You can get them for
example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
Best regards,
Krzysztof
^ permalink raw reply
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