* [PATCH v2 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU
From: Geetha sowjanya @ 2026-03-29 15:24 UTC (permalink / raw)
To: linux-perf-users, linux-kernel, linux-arm-kernel, devicetree
Cc: mark.rutland, will, krzk+dt
In-Reply-To: <20260329152439.10573-1-gakula@marvell.com>
Add a devicetree binding for the Marvell CN20K DDR performance
monitor block, including the marvell,cn20k-ddr-pmu compatible
string and the required MMIO reg region.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
Changes in v1:
- Added a description field to the binding.
- Simplified the compatible property using 'const' instead of 'items/enum'.
- Updated the example node name to include a unit-address matching the reg base.
.../bindings/perf/marvell-cn20k-ddr.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
diff --git a/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
new file mode 100644
index 000000000000..470eac0a53c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/marvell-cn20k-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell CN20K DDR performance monitor
+
+description:
+ Performance Monitoring Unit (PMU) for the DDR controller
+ in Marvell CN20K SoCs.
+
+maintainers:
+ - Geetha sowjanya <gakula@marvell.com>
+
+properties:
+ compatible:
+ const: marvell,cn20k-ddr-pmu
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ddr-pmu@c200000000 {
+ compatible = "marvell,cn20k-ddr-pmu";
+ reg = <0xc200 0x00000000 0x0 0x100000>;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v2 0/2] perf: marvell: Add CN20K DDR PMU support
From: Geetha sowjanya @ 2026-03-29 15:24 UTC (permalink / raw)
To: linux-perf-users, linux-kernel, linux-arm-kernel, devicetree
Cc: mark.rutland, will, krzk+dt
This series adds support for the Marvell CN20K DRAM Subsystem (DSS)
performance monitor in the existing marvell_cn10k_ddr_pmu driver, and
documents the device tree binding for the new compatible string.
The CN20K PMU provides eight programmable counters and two fixed
counters (DDR reads and writes). Patch 1 adds the devicetree schema for
"marvell,cn20k-ddr-pmu". Patch 2 wires OF and ACPI (MRVL000B) match
entries, adds CN20K register offsets and event maps, and refactors
platform data to use silicon variant flags.
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Changes in v1:
- Added a description field to the binding.
- Simplified the compatible property using 'const' instead of 'items/enum'.
- Updated the example node name to include a unit-address matching the reg base.
Geetha sowjanya (2):
dt-bindings: perf: marvell: Document CN20K DDR PMU
perf: marvell: Add CN20K DDR PMU support
.../bindings/perf/marvell-cn20k-ddr.yaml | 37 ++++
drivers/perf/marvell_cn10k_ddr_pmu.c | 186 ++++++++++++++++--
2 files changed, 207 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml
--
2.25.1
^ permalink raw reply
* [GIT PULL 7/7] arm64: tegra: Default configuration changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-arm64-defconfig
for you to fetch changes up to c655a14958363aea8a1d0bbf3358fcee7f89a210:
arm64: tegra: defconfig: Drop redundant ARCH_TEGRA_foo_SOC (2026-03-25 10:49:46 +0100)
Thanks,
Thierry
----------------------------------------------------------------
arm64: tegra: Default configuration changes for v7.1-rc1
Drop the various ARCH_TEGRA_*_SOC options from the default configurations
since they are now enabled by default for ARCH_TEGRA.
----------------------------------------------------------------
Krzysztof Kozlowski (2):
soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults for NVIDIA Tegra
arm64: tegra: defconfig: Drop redundant ARCH_TEGRA_foo_SOC
Thierry Reding (1):
Merge branch 'for-7.1/soc' into for-7.1/arm64/defconfig
arch/arm64/configs/defconfig | 7 -------
drivers/soc/tegra/Kconfig | 11 +++++++++++
2 files changed, 11 insertions(+), 7 deletions(-)
^ permalink raw reply
* [GIT PULL 5/7] ARM: tegra: Default configuration changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-arm-defconfig
for you to fetch changes up to 21e380f272415387454d81788f2d62642e1fe93a:
ARM: tegra: defconfig: Drop redundant ARCH_TEGRA_foo_SOC (2026-03-25 10:49:00 +0100)
Thanks,
Thierry
----------------------------------------------------------------
ARM: tegra: Default configuration changes for v7.1-rc1
Drop the various ARCH_TEGRA_*_SOC options from the default configurations
since they are now enabled by default for ARCH_TEGRA.
----------------------------------------------------------------
Krzysztof Kozlowski (2):
soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults for NVIDIA Tegra
ARM: tegra: defconfig: Drop redundant ARCH_TEGRA_foo_SOC
Thierry Reding (1):
Merge branch 'for-7.1/soc' into for-7.1/arm/defconfig
arch/arm/configs/multi_v7_defconfig | 4 ----
arch/arm/configs/tegra_defconfig | 4 ----
drivers/soc/tegra/Kconfig | 11 +++++++++++
3 files changed, 11 insertions(+), 8 deletions(-)
^ permalink raw reply
* [GIT PULL 2/7] soc/tegra: Changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-soc
for you to fetch changes up to 4b23febb6b11cd06183bed3d21b87ba7d6a8a1e0:
MAINTAINERS: Change email address for Thierry Reding (2026-03-28 01:41:07 +0100)
Thanks,
Thierry
----------------------------------------------------------------
soc/tegra: Changes for v7.1-rc1
A number of fixes went into this for the PMC and CBB drivers. The PMC
driver also gains support for Tegra264 and a Kconfig symbol for the
upcoming Tegra238 is added. The various per-generation Kconfig symbols
are now also enabled by default for ARCH_TEGRA in order to reduce the
number of configuration options that need to be explicitly enabled.
----------------------------------------------------------------
Jon Hunter (10):
soc/tegra: pmc: Add kerneldoc for reboot notifier
soc/tegra: pmc: Correct function names in kerneldoc
soc/tegra: pmc: Add kerneldoc for wake-up variables
soc/tegra: pmc: Remove unused AOWAKE definitions
soc/tegra: pmc: Add support for SoC specific AOWAKE offsets
soc/tegra: pmc: Add AOWAKE regs for Tegra264
soc/tegra: pmc: Add Tegra264 wake events
soc/tegra: pmc: Refactor IO pad voltage control
soc/tegra: pmc: Rename has_impl_33v_pwr flag
soc/tegra: pmc: Add IO pads for Tegra264
Krzysztof Kozlowski (1):
soc/tegra: Make ARCH_TEGRA_SOC_FOO defaults for NVIDIA Tegra
Sumit Gupta (4):
soc/tegra: cbb: Add support for CBB fabrics in Tegra238
soc/tegra: cbb: Set ERD on resume for err interrupt
soc/tegra: cbb: Fix incorrect ARRAY_SIZE in fabric lookup tables
soc/tegra: cbb: Fix cross-fabric target timeout lookup
Svyatoslav Ryhel (2):
soc/tegra: pmc: Enable core domain support for Tegra114
soc/tegra: common: Add Tegra114 support to devm_tegra_core_dev_init_opp_table
Thierry Reding (2):
soc/tegra: Add Tegra238 Kconfig symbol
MAINTAINERS: Change email address for Thierry Reding
MAINTAINERS | 14 +-
drivers/soc/tegra/Kconfig | 20 ++
drivers/soc/tegra/cbb/tegra234-cbb.c | 169 ++++++++-
drivers/soc/tegra/common.c | 5 +-
drivers/soc/tegra/pmc.c | 662 ++++++++++++++++++++++-------------
5 files changed, 611 insertions(+), 259 deletions(-)
^ permalink raw reply
* [GIT PULL 6/7] arm64: tegra: Device tree changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-arm64-dt
for you to fetch changes up to c70e6bc11d2008fbb19695394b69fd941ab39030:
arm64: tegra: Add Tegra264 GPIO controllers (2026-03-28 01:36:46 +0100)
Thanks,
Thierry
----------------------------------------------------------------
arm64: tegra: Device tree changes for v7.1-rc1
Various fixes and new additions across a number of devices. GPIO and PCI
are enabled on Tegra264 and the Jetson AGX Thor Developer Kit, allowing
it to boot via network and mass storage.
----------------------------------------------------------------
Diogo Ivo (1):
arm64: tegra: smaug: Enable SPI-NOR flash
Jon Hunter (1):
arm64: tegra: Fix RTC aliases
Prathamesh Shete (1):
arm64: tegra: Add Tegra264 GPIO controllers
Thierry Reding (6):
dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
Merge branch for-7.1/dt-bindings into for-7.1/pci
arm64: tegra: Fix snps,blen properties
arm64: tegra: Drop redundant clock and reset names for TSEC
arm64: tegra: Add PCI controllers on Tegra264
arm64: tegra: Add Jetson AGX Thor Developer Kit support
.../bindings/pci/nvidia,tegra264-pcie.yaml | 149 +++++++++
arch/arm64/boot/dts/nvidia/Makefile | 2 +
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 -
arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +-
.../dts/nvidia/tegra264-p4071-0000+p3834-0008.dts | 11 +
.../boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 12 +
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 336 +++++++++++++++++++--
10 files changed, 500 insertions(+), 32 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
create mode 100644 arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
create mode 100644 arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
^ permalink raw reply
* [GIT PULL 4/7] ARM: tegra: Device tree changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-arm-dt
for you to fetch changes up to ce74a6c6d88ba9ee29a6b99ac97ffcded577c85d:
ARM: tegra: paz00: Configure WiFi rfkill switch through device tree (2026-03-28 00:56:36 +0100)
Thanks,
Thierry
----------------------------------------------------------------
ARM: tegra: Device tree changes for v7.1-rc1
Various improvements for Tegra114 boards, as well as some legacy cleanup
for PAZ00 and Transformers devices.
----------------------------------------------------------------
Dmitry Torokhov (1):
ARM: tegra: paz00: Configure WiFi rfkill switch through device tree
Svyatoslav Ryhel (8):
ARM: tegra: Add SOCTHERM support on Tegra114
ARM: tn7: Adjust panel node
ARM: tegra: lg-x3: Add panel and bridge nodes
ARM: tegra: lg-x3: Add USB and power related nodes
ARM: tegra: lg-x3: Add node for capacitive buttons
ARM: tegra: Add ACTMON node to Tegra114 device tree
ARM: tegra: Add External Memory Controller node on Tegra114
ARM: tegra: transformers: Add connector node
arch/arm/boot/dts/nvidia/tegra114-tn7.dts | 13 +-
arch/arm/boot/dts/nvidia/tegra114.dtsi | 221 +++++++++++++++++++++++
arch/arm/boot/dts/nvidia/tegra20-paz00.dts | 8 +
arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts | 21 ++-
arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 23 +++
arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts | 33 ++++
arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi | 174 +++++++++++++++++-
arch/arm/mach-tegra/Makefile | 2 -
arch/arm/mach-tegra/board-paz00.c | 56 ------
arch/arm/mach-tegra/board.h | 2 -
arch/arm/mach-tegra/tegra.c | 4 -
11 files changed, 482 insertions(+), 75 deletions(-)
delete mode 100644 arch/arm/mach-tegra/board-paz00.c
^ permalink raw reply
* [GIT PULL 1/7] dt-bindings: Changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-dt-bindings
for you to fetch changes up to bed2f5b4de6c6fd8f8928f6373ad92e8795c370f:
dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit (2026-03-28 01:05:24 +0100)
Thanks,
Thierry
----------------------------------------------------------------
dt-bindings: Changes for v7.1-rc1
This contains a few conversions to DT schema along with various
additions and fixes to reduce the amount of validation warnings.
Included are also a new binding for the PCIe controller found on
Tegra264 as well as compatible strings for the Jetson AGX Thor
Developer Kit.
----------------------------------------------------------------
Sumit Gupta (1):
dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings
Svyatoslav Ryhel (1):
dt-bindings: display: tegra: Document Tegra20 HDMI port
Thierry Reding (9):
dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
dt-bindings: phy: tegra-xusb: Document Type C support
dt-bindings: clock: tegra124-dfll: Convert to json-schema
dt-bindings: interrupt-controller: tegra: Fix reg entries
dt-bindings: arm: tegra: Add missing compatible strings
dt-bindings: phy: tegra: Document Tegra210 USB PHY
dt-bindings: memory: Add Tegra210 memory controller bindings
dt-bindings: memory: tegra210: Mark EMC as cooling device
dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit
Documentation/devicetree/bindings/arm/tegra.yaml | 56 +++-
.../bindings/arm/tegra/nvidia,tegra234-cbb.yaml | 4 +
.../bindings/clock/nvidia,tegra124-dfll.txt | 155 -----------
.../bindings/clock/nvidia,tegra124-dfll.yaml | 290 +++++++++++++++++++++
.../display/tegra/nvidia,tegra20-hdmi.yaml | 13 +-
.../interrupt-controller/nvidia,tegra20-ictlr.yaml | 23 +-
.../memory-controllers/nvidia,tegra210-emc.yaml | 6 +-
.../memory-controllers/nvidia,tegra210-mc.yaml | 77 ++++++
.../bindings/pci/nvidia,tegra264-pcie.yaml | 149 +++++++++++
.../bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 39 ++-
.../bindings/phy/nvidia,tegra20-usb-phy.yaml | 1 +
11 files changed, 649 insertions(+), 164 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
^ permalink raw reply
* [GIT PULL 3/7] firmware: tegra: Changes for v7.1-rc1
From: Thierry Reding @ 2026-03-29 15:10 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
From: Thierry Reding <thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-firmware
for you to fetch changes up to e68d494b8946e9060e60427f365107194f90ba0d:
soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP (2026-03-27 16:30:54 +0100)
Thanks,
Thierry
----------------------------------------------------------------
firmware: tegra: Changes for v7.1-rc1
This introduces a new API for the BPMP to be pass along a specifier from
DT when getting a reference from a phandle. This is used to reference
specific instances of the PCI controller on Tegra264. The ABI header for
BPMP is updated to the latest version and BPMP APIs now use the more
intuitive ENODEV instead of the non SUSV4 ENOTSUPP error code for stub
implementations.
----------------------------------------------------------------
Thierry Reding (4):
firmware: tegra: bpmp: Rename Tegra239 to Tegra238
soc/tegra: Update BPMP ABI header
firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function
soc/tegra: bpmp: Use ENODEV instead of ENOTSUPP
drivers/firmware/tegra/bpmp.c | 34 +
include/soc/tegra/bpmp-abi.h | 4573 +++++++++++++++++++++++++++++++++--------
include/soc/tegra/bpmp.h | 20 +-
3 files changed, 3725 insertions(+), 902 deletions(-)
^ permalink raw reply
* Re: (subset) [PATCH net-next v4 0/2] Add ICSSG0 dual EMAC support for AM642 EVM
From: Vignesh Raghavendra @ 2026-03-29 14:49 UTC (permalink / raw)
To: Nishanth Menon, Meghana Malladi
Cc: Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel, devicetree, linux-kernel, netdev, srk,
danishanwar
In-Reply-To: <20260323090358.632329-1-m-malladi@ti.com>
Hi Meghana Malladi,
On Mon, 23 Mar 2026 14:33:56 +0530, Meghana Malladi wrote:
> Add ICSSG0 dual EMAC support for AM642 EVM
>
> This series adds device tree overlay support for enabling ICSSG0 dual EMAC
> on the AM642 EVM, along with the necessary PHY driver configuration.
>
> The overlay enables both ICSSG0 Ethernet interfaces (port0 and port1) in
> dual EMAC mode and can be combined with the existing ICSSG1 overlay to
> enable all four ICSSG interfaces if needed.
>
> [...]
I have applied the following to branch ti-k3-config-next on [1].
Thank you!
[2/2] arm64: defconfig: Enable DP83TG720 PHY driver
commit: 192c7f34d2f63552211ef4cb8bbd2933f95106e2
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply
* Re: [PATCH v9 0/5] PCI: of: Remove max-link-speed generation validation
From: Hans Zhang @ 2026-03-29 14:47 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: lpieralisi, jingoohan1, mani, kwilczynski, bhelgaas,
florian.fainelli, jim2101024, robh, ilpo.jarvinen, linux-arm-msm,
linux-arm-kernel, linux-renesas-soc, claudiu.beznea.uj,
linux-mediatek, linux-tegra, linux-omap, bcm-kernel-feedback-list,
linux-pci, linux-kernel, shawn.lin
In-Reply-To: <20260327164250.GA1513325@bhelgaas>
On 3/28/26 00:42, Bjorn Helgaas wrote:
> On Sat, Mar 14, 2026 at 12:55:17AM +0800, Hans Zhang wrote:
>> Hi,
>>
>> This series moves the validation from the common OF function to the
>> individual PCIe controller drivers. To protect against out-of-bounds
>> accesses to the pcie_link_speed[] array, we first introduce a helper
>> function pcie_get_link_speed() that safely returns the speed value
>> (or PCI_SPEED_UNKNOWN) for a given generation number.
>>
>> Then all direct uses of pcie_link_speed[] as an array are converted to
>> use the new helper, ensuring that even if an invalid generation number
>> reaches those code paths, no out-of-bounds access occurs.
>>
>> For several drivers that read the "max-link-speed" property
>> (pci-j721e, brcmstb, mediatek-gen3, rzg3s-host), we add an explicit
>> validation step: if the value is missing, out of range, or unsupported
>> by the hardware, a safe default is used (usually Gen2). Other drivers
>> (mainly DesignWare glue drivers) rely on the helper to safely handle
>> invalid values, but do not yet include fallback logic or warnings.
>>
>> Finally, the range check is removed from of_pci_get_max_link_speed(),
>> so that future PCIe generations can be supported without modifying
>> drivers/pci/of.c.
>
> Thanks for this series.
>
> We still have a couple references to pcie_link_speed[] that bypass
> pcie_get_link_speed(). These are safe because PCI_EXP_LNKSTA_CLS is
> 0xf and pcie_link_speed[] is size 16, but I'm not sure the direct
> reference is necessary.
>
> The array itself is exported, which I suppose we needed for modular
> PCI controller drivers, but we probably don't need it now that
> pcie_get_link_speed() is exported?
>
> $ git grep "\<pcie_link_speed\>"
> drivers/pci/pci-sysfs.c: speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
> drivers/pci/pci.c: return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
> drivers/pci/pci.h:extern const unsigned char pcie_link_speed[];
> drivers/pci/pci.h: bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
> drivers/pci/probe.c:const unsigned char pcie_link_speed[] = {
> drivers/pci/probe.c:EXPORT_SYMBOL_GPL(pcie_link_speed);
> drivers/pci/probe.c: if (speed >= ARRAY_SIZE(pcie_link_speed))
> drivers/pci/probe.c: return pcie_link_speed[speed];
> drivers/pci/probe.c: bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Hi Bjorn,
Yes, I also realized that this array is directly used in other places.
So I submitted this series and I would appreciate it if you could review
it to ensure its correctness.
See also this series:
https://patchwork.kernel.org/project/linux-pci/patch/20260315160057.127639-1-18255117159@163.com/
Best regards,
Hans
^ permalink raw reply
* Re: (subset) [PATCH v3 0/2] Add ICSSG0 dual EMAC support for AM642 EVM
From: Vignesh Raghavendra @ 2026-03-29 14:48 UTC (permalink / raw)
To: Nishanth Menon, Meghana Malladi
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, netdev, srk, danishanwar
In-Reply-To: <20260311053852.1034244-1-m-malladi@ti.com>
Hi Meghana Malladi,
On Wed, 11 Mar 2026 11:08:50 +0530, Meghana Malladi wrote:
> This series adds device tree overlay support for enabling ICSSG0 dual EMAC
> on the AM642 EVM, along with the necessary PHY driver configuration.
>
> The overlay enables both ICSSG0 Ethernet interfaces (port0 and port1) in
> dual EMAC mode and can be combined with the existing ICSSG1 overlay to
> enable all four ICSSG interfaces if needed.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/2] arm64: dts: ti: k3-am642-evm: Add ICSSG0 overlay for dual EMAC support
commit: 8bafdf5dd89b961b698d8bd2cfcebc8e4d3764fd
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply
* Re: [PATCH v1 0/7] arm64: dts: ti: verdin-am62[p]: Add Zinnia
From: Vignesh Raghavendra @ 2026-03-29 14:46 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Francesco Dolcini
Cc: Francesco Dolcini, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260324093705.26730-1-francesco@dolcini.it>
Hi Francesco Dolcini,
On Tue, 24 Mar 2026 10:36:55 +0100, Francesco Dolcini wrote:
> arm64: dts: ti: verdin-am62[p]: Add Zinnia
>
> From: Francesco Dolcini <francesco.dolcini@toradex.com>
>
> Add Zinnia Carrier Board mated with Verdin AM62 and Verdin AM62P.
>
> It features 1 x RS232, 1 x RS485, 1 x CAN, 3 x isolated digital I/O,
> 2 x 1GBit/s Ethernet, a mini PCIe slot with USB / SIM card connector
> for a modem, USB and SD card interfaces.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/7] dt-bindings: arm: ti: Add verdin am62/am62p zinnia board
commit: bae382fc0c9555d21bc125a0310c2b0895489f87
[2/7] arm64: dts: ti: k3-am62-verdin: Fix SPI_1 GPIO CS pinctrl label
commit: 5a8f6fa5131357c7326ca1956644a588d5b492f7
[3/7] arm64: dts: ti: k3-am62-verdin: Split UART_2 pinctrl group
commit: 0e390541a3ae62e713708ddb263982b6ba0a49e7
[4/7] arm64: dts: ti: k3-am62-verdin: Add Zinnia
commit: 72f86c677905c752418861c2ca122d903d457514
[5/7] arm64: dts: ti: k3-am62p-verdin: Split UART_2 pinctrl group
commit: 16dfb22d7f6fee84386f0f298ccb968545b8943b
[6/7] arm64: dts: ti: k3-am62p-verdin: Add SPI_1_CS as GPIO
commit: ad8cdc8b98e2b8de82fa19c7f67a42a59ef8936b
[7/7] arm64: dts: ti: k3-am62p-verdin: Add Zinnia
commit: bbe7a708f753cc7009c1af08dca7357e7a43e157
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply
* Re: [PATCH 0/2] arm64: dts: ti: k3-pinctrl: some minor cleanup
From: Vignesh Raghavendra @ 2026-03-29 14:42 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rasmus Villemoes; +Cc: linux-arm-kernel
In-Reply-To: <20260327141513.1250499-1-linux@rasmusvillemoes.dk>
Hi Rasmus Villemoes,
On Fri, 27 Mar 2026 15:15:11 +0100, Rasmus Villemoes wrote:
> arm64: dts: ti: k3-pinctrl: some minor cleanup
>
> I stumbled on a few things one might want to clean up. No functional change.
>
> Rasmus Villemoes (2):
> arm64: dts: ti: k3-pinctrl: consistently use tabs for alignment
> arm64: dts: ti: k3-pinctrl: sort shift values numerically
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/2] arm64: dts: ti: k3-pinctrl: consistently use tabs for alignment
commit: 8bd215d1e4f27a8feb762b19a8d030178cf0337d
[2/2] arm64: dts: ti: k3-pinctrl: sort shift values numerically
commit: 06498fabf2965233440072d70146798e4372a8fc
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply
* Re: [PATCH net-next 01/10] net: stmmac: fix TSO support when some channels have TBS available
From: Andrew Lunn @ 2026-03-29 14:03 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-stm32, netdev,
Ong Boon Leong, Paolo Abeni
In-Reply-To: <acjzmxY9xmBInSwm@shell.armlinux.org.uk>
> * Packets that won't trigger the COE e.g. most DSA-tagged packets will
> * also have to be checksummed in software.
> */
I doubt DSA will work with TSO, it would have to include the DSA
header into the replicated header when doing segmentation.
I thought we had some code in DSA to turn off features which are
likely to cause issues. But i don't see it.
Hardware checksumming has been an issue in the past with DSA. Some MAC
hardware from switch vendors, Marvell, Broadcom etc, understand the
DSA header and so can do the checksum correctly when the DSA tag is
present. MAC hardware from other vendors often get confused so
software checksumming is needed.
Andrew
^ permalink raw reply
* Re: [PATCH net-next 00/10] net: airoha: Support multiple net_devices connected to the same GDM port
From: Benjamin Larsson @ 2026-03-29 13:40 UTC (permalink / raw)
To: Lorenzo Bianconi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Christian Marangi, linux-arm-kernel, linux-mediatek, netdev,
devicetree, Xuegang Lu
In-Reply-To: <20260329-airoha-eth-multi-serdes-v1-0-00f52dc360ca@kernel.org>
Hi.
On 29/03/2026 15:07, Lorenzo Bianconi wrote:
> EN7581 or AN7583 SoCs support connecting multiple external SerDes (e.g.
> Ethernet or USB SerDes) to GDM3 or GDM4 ports via a hw multiplexer that
> manages the traffic in a TDM manner.
I think the word for this is arbiter. I think the common use of mux is
as a more fixed data path selector.
> As a result multiple net_devices can
> connect to the same GDM{3,4} port and there is a theoretical "1:n"
> relation between GDM ports and net_devices.
>
> ┌─────────────────────────────────┐
> │ │ ┌──────┐
> │ P1 GDM1 ├────►MT7530│
> │ │ └──────┘
> │ │ ETH0 (DSA conduit)
> │ │
> │ PSE/FE │
> │ │
> │ │
> │ │ ┌─────┐
> │ P0 CDM1 ├────►QDMA0│
> │ P4 P9 GDM4 │ └─────┘
> └──┬─────────────────────────┬────┘
> │ │
> ┌──▼──┐ ┌────▼────┐
> │ PPE │ │ MUX │
> └─────┘ └─┬─────┬─┘
> │ │
> ┌──▼──┐┌─▼───┐
> │ ETH ││ USB │
> └─────┘└─────┘
> ETH1 ETH2
A more representative picture is like the following and in the GDM2 path
there is a real mux present(not relevant for this patch series though).
Thus I think it is important to have the distinction between mux and
arbiter. (Feel free to reuse the following illustration freely).
┌─────────────────────────────────┐
│ │ ┌──────┐
┌─────────┐ │ P1 GDM1 ├────►MT7530│
│ MUX ├──│ P2 GDM2 │ └──────┘
└─┬─────┬─┘ │ │ ETH0 (DSA conduit)
│ │ │ │
┌──▼──┐┌─▼───┐│ PSE/FE │
│ PON ││ PON ││ │
└─────┘└─────┘│ │
ETH5 XPON │ │ ┌─────┐
│ P0 CDM1 ├────►QDMA0│
│ P4 P3 GDM3 P9 GDM4 │ └─────┘
└──┬──────────┬──────────────┬────┘
│ │ │
┌──▼──┐ ┌────▼────┐ ┌────▼────┐
│ PPE │ │ ARB │ │ ARB │
└─────┘ └─┬─────┬─┘ └─┬─────┬─┘
│ │ │ │
┌──▼──┐┌─▼───┐ ┌──▼──┐┌─▼───┐
│PCIE0││PCIE1│ │ ETH ││ USB │
└─────┘└─────┘ └─────┘└─────┘
ETH3 ETH4 ETH1 ETH2
MvH
Benjamin Larsson
^ permalink raw reply
* [GIT PULL] Allwinner Device Tree Changes for 7.1 - Part 1
From: Chen-Yu Tsai @ 2026-03-29 13:48 UTC (permalink / raw)
To: soc
Cc: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, linux-sunxi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1968 bytes --]
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git tags/sunxi-dt-for-7.1
for you to fetch changes up to b912e48bee355b6b1faf86efc4a23191324ffecb:
arm64: dts: allwinner: h6: Add TaiqiCat (TQC) A01 support (2026-03-14 15:27:04 +0800)
There are more patches to come, once they have been in -next for a few
days.
----------------------------------------------------------------
Allwinner device tree changes for 7.1 - part 1
Only minor additions this cycle.
Allwinner A523 SoC family had LED controller enabled.
Avaota A1 board had SPI NAND enabled.
New board added:
- TaiqiCat (TQC) A01
----------------------------------------------------------------
Chen-Yu Tsai (5):
dt-bindings: leds: sun50i-a100: Add compatible for Allwinner A523 SoC
arm64: dts: allwinner: sun55i-a523: Add LED controller
arm64: dts: allwinner: sun55i-t527: avaota-a1: Enable LEDs
arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
Jun Yan (3):
dt-bindings: vendor-prefixes: Add Beijing Ultrapower Software Co., Ltd.
dt-bindings: arm: sunxi: Add TaiqiCat (TQC) A01
arm64: dts: allwinner: h6: Add TaiqiCat (TQC) A01 support
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
.../bindings/leds/allwinner,sun50i-a100-ledc.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h6-taiqicat-a01.dts | 361 +++++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 57 ++++
.../boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 56 ++++
7 files changed, 483 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-taiqicat-a01.dts
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [GIT PULL] Allwinner Fixes for 7.0
From: Chen-Yu Tsai @ 2026-03-29 13:46 UTC (permalink / raw)
To: soc
Cc: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, linux-sunxi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 855 bytes --]
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git tags/sunxi-fixes-for-7.0
for you to fetch changes up to 6896ca5a9d05275fbeb38640c9bbdb95698de188:
arm64: dts: allwinner: sun55i: Fix r-spi DMA (2026-03-24 11:08:10 +0800)
----------------------------------------------------------------
Allwinner fixes for 7.0
Just one fix to make the r-spi SPI controller use the mcu-dma DMA
controller for DMA instead of the main DMA controller.
----------------------------------------------------------------
Chen-Yu Tsai (1):
arm64: dts: allwinner: sun55i: Fix r-spi DMA
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v2 21/30] KVM: arm64: Kill topup_memcache from kvm_s2_fault
From: Fuad Tabba @ 2026-03-29 13:41 UTC (permalink / raw)
To: Marc Zyngier
Cc: kvmarm, linux-arm-kernel, kvm, Joey Gouly, Suzuki K Poulose,
Oliver Upton, Zenghui Yu, Will Deacon, Quentin Perret
In-Reply-To: <86ecl549aw.wl-maz@kernel.org>
Hi Marc,
On Fri, 27 Mar 2026 at 14:49, Marc Zyngier <maz@kernel.org> wrote:
>
> On Fri, 27 Mar 2026 11:36:09 +0000,
> Marc Zyngier <maz@kernel.org> wrote:
> >
> > The topup_memcache field can be easily replaced by the equivalent
> > conditions, and the resulting code is not much worse.
This is easier to reason about I think, so (not sure if it applies to
fold-ins, but fwiw):
Reviewed-by: Fuad Tabba <tabba@google.com>
Thanks,
/fuad
> >
> > Tested-by: Fuad Tabba <tabba@google.com>
> > Reviewed-by: Fuad Tabba <tabba@google.com>
> > Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > arch/arm64/kvm/mmu.c | 12 ++++++------
> > 1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
> > index e8bda71e862b2..5b05caecdbd92 100644
> > --- a/arch/arm64/kvm/mmu.c
> > +++ b/arch/arm64/kvm/mmu.c
> > @@ -1712,7 +1712,6 @@ static short kvm_s2_resolve_vma_size(const struct kvm_s2_fault_desc *s2fd,
> >
> > struct kvm_s2_fault {
> > bool writable;
> > - bool topup_memcache;
> > bool mte_allowed;
> > bool is_vma_cacheable;
> > bool s2_force_noncacheable;
> > @@ -1983,9 +1982,8 @@ static int user_mem_abort(const struct kvm_s2_fault_desc *s2fd)
> > .logging_active = logging_active,
> > .force_pte = logging_active,
> > .prot = KVM_PGTABLE_PROT_R,
> > - .topup_memcache = !perm_fault || (logging_active && kvm_is_write_fault(s2fd->vcpu)),
> > };
> > - void *memcache;
> > + void *memcache = NULL;
> > int ret;
> >
> > /*
> > @@ -1994,9 +1992,11 @@ static int user_mem_abort(const struct kvm_s2_fault_desc *s2fd)
> > * only exception to this is when dirty logging is enabled at runtime
> > * and a write fault needs to collapse a block entry into a table.
> > */
> > - ret = prepare_mmu_memcache(s2fd->vcpu, fault.topup_memcache, &memcache);
> > - if (ret)
> > - return ret;
> > + if (!perm_fault || (logging_active && kvm_is_write_fault(s2fd->vcpu))) {
> > + ret = prepare_mmu_memcache(s2fd->vcpu, true, &memcache);
> > + if (ret)
> > + return ret;
> > + }
> >
> > /*
> > * Let's check if we will get back a huge page backed by hugetlbfs, or
>
> Sashiko has spotted [1] an interesting corner case here, which is that the
> original code always initialises memcache to its correct value, while
> we now only do it in a limited number of cases.
>
> I'm proposing to restore the original behaviour by folding the
> following change into this patch, splitting the retrieval of the
> memcache pointer from the top-up and avoiding the ugly pointer
> indirection:
>
> diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
> index 1fe7182be45ac..03e1f389339c7 100644
> --- a/arch/arm64/kvm/mmu.c
> +++ b/arch/arm64/kvm/mmu.c
> @@ -1513,25 +1513,22 @@ static bool kvm_vma_is_cacheable(struct vm_area_struct *vma)
> }
> }
>
> -static int prepare_mmu_memcache(struct kvm_vcpu *vcpu, bool topup_memcache,
> - void **memcache)
> +static void *get_mmu_memcache(struct kvm_vcpu *vcpu)
> {
> - int min_pages;
> -
> if (!is_protected_kvm_enabled())
> - *memcache = &vcpu->arch.mmu_page_cache;
> + return &vcpu->arch.mmu_page_cache;
> else
> - *memcache = &vcpu->arch.pkvm_memcache;
> -
> - if (!topup_memcache)
> - return 0;
> + return &vcpu->arch.pkvm_memcache;
> +}
>
> - min_pages = kvm_mmu_cache_min_pages(vcpu->arch.hw_mmu);
> +static int topup_mmu_memcache(struct kvm_vcpu *vcpu, void *memcache)
> +{
> + int min_pages = kvm_mmu_cache_min_pages(vcpu->arch.hw_mmu);
>
> if (!is_protected_kvm_enabled())
> - return kvm_mmu_topup_memory_cache(*memcache, min_pages);
> + return kvm_mmu_topup_memory_cache(memcache, min_pages);
>
> - return topup_hyp_memcache(*memcache, min_pages);
> + return topup_hyp_memcache(memcache, min_pages);
> }
>
> /*
> @@ -1589,7 +1586,8 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd)
> gfn_t gfn;
> int ret;
>
> - ret = prepare_mmu_memcache(s2fd->vcpu, true, &memcache);
> + memcache = get_mmu_memcache(s2fd->vcpu);
> + ret = topup_mmu_memcache(s2fd->vcpu, memcache);
> if (ret)
> return ret;
>
> @@ -1993,7 +1991,7 @@ static int user_mem_abort(const struct kvm_s2_fault_desc *s2fd)
> bool perm_fault = kvm_vcpu_trap_is_permission_fault(s2fd->vcpu);
> struct kvm_s2_fault_vma_info s2vi = {};
> enum kvm_pgtable_prot prot;
> - void *memcache = NULL;
> + void *memcache;
> int ret;
>
> /*
> @@ -2002,9 +2000,10 @@ static int user_mem_abort(const struct kvm_s2_fault_desc *s2fd)
> * only exception to this is when dirty logging is enabled at runtime
> * and a write fault needs to collapse a block entry into a table.
> */
> + memcache = get_mmu_memcache(s2fd->vcpu);
> if (!perm_fault || (memslot_is_logging(s2fd->memslot) &&
> kvm_is_write_fault(s2fd->vcpu))) {
> - ret = prepare_mmu_memcache(s2fd->vcpu, true, &memcache);
> + ret = topup_mmu_memcache(s2fd->vcpu, memcache);
> if (ret)
> return ret;
> }
>
> The bot has also pointed out a couple of cases where memcache and
> permission faults interact badly. I'll look into them separately, as
> they predate this rework.
>
> Thanks,
>
> M.
>
> [1] https://sashiko.dev/#/patchset/20260327113618.4051534-1-maz%40kernel.org?patch=12134
>
> --
> Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH] arm64: dts: allwinner: enable h616 timer support
From: Chen-Yu Tsai @ 2026-03-29 13:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec,
Samuel Holland, Michal Piekos
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
In-Reply-To: <20260329-h616-timer-v1-1-5966d0420a66@mmpsystems.pl>
On Sun, 29 Mar 2026 13:43:04 +0200, Michal Piekos wrote:
> Add support for timer by reusing existing sun4i timer driver.
>
> H616 timer is compatible with earlier sunxi timer variants and provides
> both clocksource and clockevent functionality. It runs from 24 MHz
> oscillator. It can serve as broadcast clockevent for wake up from idle
> states.
>
> [...]
Applied to sunxi/dt-for-7.1 in local tree, thanks!
[1/1] arm64: dts: allwinner: enable h616 timer support
commit: c755e39836ec492b0bc210fd96c2b720b5b4a690
Best regards,
--
Chen-Yu Tsai <wens@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: allwinner: sun50i-a64: add UART DMA channels
From: Chen-Yu Tsai @ 2026-03-29 13:22 UTC (permalink / raw)
To: Jernej Skrabec, Samuel Holland, Chen-Yu Tsai
Cc: linux-sunxi, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260324161930.1602083-1-wens@kernel.org>
On Wed, 25 Mar 2026 00:19:28 +0800, Chen-Yu Tsai wrote:
> All the UARTs support DMA and are hooked up to the DMA controller.
>
> Add the DMA channels for the UARTs
>
>
Applied to sunxi/dt-for-7.1 in local tree, thanks!
[1/2] arm64: dts: allwinner: sun50i-a64: add UART DMA channels
commit: 1e80a0367bca7ffe3dfff41948474fe3c3ad3587
[2/2] arm64: dts: allwinner: sun50i-h6: add UART DMA channels
commit: 2e4858d2f027080827c5fc557306a06fbfcecd0a
Best regards,
--
Chen-Yu Tsai <wens@kernel.org>
^ permalink raw reply
* [PATCH net-next 10/10] net: airoha: Rename get_src_port_id callback in get_sport
From: Lorenzo Bianconi @ 2026-03-29 13:08 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi
Cc: Christian Marangi, linux-arm-kernel, linux-mediatek, netdev,
devicetree
In-Reply-To: <20260329-airoha-eth-multi-serdes-v1-0-00f52dc360ca@kernel.org>
For code consistency, rename get_src_port_id callback in get_sport.
Please note this patch does not introduce any logical change and it is
just a cosmetic patch.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 10 +++++-----
drivers/net/ethernet/airoha/airoha_eth.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 3926866e711e51bb20665dfda464c5283b7616fa..5f5224838092abb1943e739733791a05b6f46526 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1751,7 +1751,7 @@ static int airhoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX));
airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX));
- src_port = eth->soc->ops.get_src_port_id(port, dev->nbq);
+ src_port = eth->soc->ops.get_sport(port, dev->nbq);
if (src_port < 0)
return src_port;
@@ -3227,7 +3227,7 @@ static const char * const en7581_xsi_rsts_names[] = {
"xfp-mac",
};
-static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq)
+static int airoha_en7581_get_sport(struct airoha_gdm_port *port, int nbq)
{
switch (port->id) {
case AIROHA_GDM3_IDX:
@@ -3291,7 +3291,7 @@ static const char * const an7583_xsi_rsts_names[] = {
"xfp-mac",
};
-static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq)
+static int airoha_an7583_get_sport(struct airoha_gdm_port *port, int nbq)
{
switch (port->id) {
case AIROHA_GDM3_IDX:
@@ -3349,7 +3349,7 @@ static const struct airoha_eth_soc_data en7581_soc_data = {
.num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names),
.num_ppe = 2,
.ops = {
- .get_src_port_id = airoha_en7581_get_src_port_id,
+ .get_sport = airoha_en7581_get_sport,
.get_dev_from_sport = airoha_en7581_get_dev_from_sport,
},
};
@@ -3360,7 +3360,7 @@ static const struct airoha_eth_soc_data an7583_soc_data = {
.num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names),
.num_ppe = 1,
.ops = {
- .get_src_port_id = airoha_an7583_get_src_port_id,
+ .get_sport = airoha_an7583_get_sport,
.get_dev_from_sport = airoha_an7583_get_dev_from_sport,
},
};
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index c076e36b741ce691cf309850435c352fc1fd7986..2a862be0a18d7df9589dd35935e92667c77961c9 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -586,7 +586,7 @@ struct airoha_eth_soc_data {
int num_xsi_rsts;
int num_ppe;
struct {
- int (*get_src_port_id)(struct airoha_gdm_port *port, int nbq);
+ int (*get_sport)(struct airoha_gdm_port *port, int nbq);
int (*get_dev_from_sport)(struct airoha_qdma_desc *desc,
u16 *port, u16 *dev);
} ops;
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 09/10] net: airoha: Do not stop GDM port if it is shared
From: Lorenzo Bianconi @ 2026-03-29 13:07 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi
Cc: Christian Marangi, linux-arm-kernel, linux-mediatek, netdev,
devicetree, Xuegang Lu
In-Reply-To: <20260329-airoha-eth-multi-serdes-v1-0-00f52dc360ca@kernel.org>
Theoretically, in the current codebase, two independent net_devices can
be connected to the same GDM port so we need to check the GDM port is not
used by any other running net_device before setting the forward
configuration to FE_PSE_PORT_DROP.
Tested-by: Xuegang Lu <xuegang.lu@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 9 ++++++---
drivers/net/ethernet/airoha/airoha_eth.h | 2 ++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 11b6dbf3fa80c0c7620fc912b4db904eb5711b2c..3926866e711e51bb20665dfda464c5283b7616fa 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1662,6 +1662,7 @@ static int airoha_dev_open(struct net_device *netdev)
}
airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id),
pse_port);
+ atomic_inc(&port->users);
return 0;
}
@@ -1681,9 +1682,6 @@ static int airoha_dev_stop(struct net_device *netdev)
for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++)
netdev_tx_reset_subqueue(netdev, i);
- airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id),
- FE_PSE_PORT_DROP);
-
if (atomic_dec_and_test(&qdma->users)) {
airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
GLOBAL_CFG_TX_DMA_EN_MASK |
@@ -1697,6 +1695,11 @@ static int airoha_dev_stop(struct net_device *netdev)
}
}
+ if (atomic_dec_and_test(&port->users))
+ airoha_set_gdm_port_fwd_cfg(qdma->eth,
+ REG_GDM_FWD_CFG(port->id),
+ FE_PSE_PORT_DROP);
+
return 0;
}
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 7549960fc37c68a5df73c49eace0aa57fda98030..c076e36b741ce691cf309850435c352fc1fd7986 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -546,6 +546,8 @@ struct airoha_gdm_port {
struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
int id;
+ atomic_t users;
+
struct airoha_hw_stats stats;
DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 08/10] net: airoha: Support multiple net_devices for a single FE GDM port
From: Lorenzo Bianconi @ 2026-03-29 13:07 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi
Cc: Christian Marangi, linux-arm-kernel, linux-mediatek, netdev,
devicetree, Xuegang Lu
In-Reply-To: <20260329-airoha-eth-multi-serdes-v1-0-00f52dc360ca@kernel.org>
EN7581 or AN7583 SoCs support connecting multiple external SerDes (e.g.
Ethernet or USB SerDes) to GDM3 or GDM4 ports via a hw multiplexer that
manages the traffic in a TDM manner. As a result multiple net_devices can
connect to the same GDM{3,4} port and there is a theoretical "1:n"
relation between GDM ports and net_devices.
┌─────────────────────────────────┐
│ │ ┌──────┐
│ P1 GDM1 ├────►MT7530│
│ │ └──────┘
│ │ ETH0 (DSA conduit)
│ │
│ PSE/FE │
│ │
│ │
│ │ ┌─────┐
│ P0 CDM1 ├────►QDMA0│
│ P4 P9 GDM4 │ └─────┘
└──┬─────────────────────────┬────┘
│ │
┌──▼──┐ ┌────▼────┐
│ PPE │ │ MUX │
└─────┘ └─┬─────┬─┘
│ │
┌──▼──┐┌─▼───┐
│ ETH ││ USB │
└─────┘└─────┘
ETH1 ETH2
Introduce support for multiple net_devices connected to the same Frame
Engine (FE) GDM port (GDM3 or GDM4) via an external hw multiplexer.
Please note GDM1 or GDM2 does not support the connection with the external
multiplexer.
Add get_dev_from_sport callback since EN7581 and AN7583 have different
logics for the net_device type connected to GDM3 or GDM4.
Tested-by: Xuegang Lu <xuegang.lu@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 229 ++++++++++++++++++++++++-------
drivers/net/ethernet/airoha/airoha_eth.h | 9 +-
drivers/net/ethernet/airoha/airoha_ppe.c | 10 +-
3 files changed, 196 insertions(+), 52 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 65046010ebabd336109a9f2afd4e6ce1d21e8593..11b6dbf3fa80c0c7620fc912b4db904eb5711b2c 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -580,24 +580,26 @@ static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
return nframes;
}
-static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
- struct airoha_qdma_desc *desc)
+static struct airoha_gdm_dev *
+airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)
{
- u32 port, sport, msg1 = le32_to_cpu(desc->msg1);
+ struct airoha_gdm_port *port;
+ u16 p, d;
- sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1);
- switch (sport) {
- case 0x10 ... 0x14:
- port = 0;
- break;
- case 0x2 ... 0x4:
- port = sport - 1;
- break;
- default:
- return -EINVAL;
- }
+ if (eth->soc->ops.get_dev_from_sport(desc, &p, &d))
+ return ERR_PTR(-ENODEV);
+
+ if (p >= ARRAY_SIZE(eth->ports))
+ return ERR_PTR(-ENODEV);
+
+ port = eth->ports[p];
+ if (!port)
+ return ERR_PTR(-ENODEV);
+
+ if (d >= ARRAY_SIZE(port->devs))
+ return ERR_PTR(-ENODEV);
- return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
+ return port->devs[d] ? port->devs[d] : ERR_PTR(-ENODEV);
}
static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
@@ -614,9 +616,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
struct page *page = virt_to_head_page(e->buf);
u32 desc_ctrl = le32_to_cpu(desc->ctrl);
- struct airoha_gdm_port *port;
- struct net_device *netdev;
- int data_len, len, p;
+ struct airoha_gdm_dev *dev;
+ int data_len, len;
if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
break;
@@ -633,12 +634,10 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
if (!len || data_len < len)
goto free_frag;
- p = airoha_qdma_get_gdm_port(eth, desc);
- if (p < 0 || !eth->ports[p])
+ dev = airoha_qdma_get_gdm_dev(eth, desc);
+ if (IS_ERR(dev))
goto free_frag;
- port = eth->ports[p];
- netdev = port->dev->dev;
if (!q->skb) { /* first buffer */
q->skb = napi_build_skb(e->buf, q->buf_size);
if (!q->skb)
@@ -646,8 +645,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
__skb_put(q->skb, len);
skb_mark_for_recycle(q->skb);
- q->skb->dev = netdev;
- q->skb->protocol = eth_type_trans(q->skb, netdev);
+ q->skb->dev = dev->dev;
+ q->skb->protocol = eth_type_trans(q->skb, dev->dev);
q->skb->ip_summed = CHECKSUM_UNNECESSARY;
skb_record_rx_queue(q->skb, qid);
} else { /* scattered frame */
@@ -665,7 +664,9 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
continue;
- if (netdev_uses_dsa(netdev)) {
+ if (netdev_uses_dsa(dev->dev)) {
+ struct airoha_gdm_port *port = dev->port;
+
/* PPE module requires untagged packets to work
* properly and it provides DSA port index via the
* DMA descriptor. Report DSA tag to the DSA stack
@@ -1717,7 +1718,7 @@ static int airhoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
{
struct airoha_gdm_port *port = dev->port;
struct airoha_eth *eth = dev->eth;
- u32 val, pse_port, chan, nbq;
+ u32 val, pse_port, chan;
int src_port;
/* Forward the traffic to the proper GDM port */
@@ -1747,9 +1748,7 @@ static int airhoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX));
airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX));
- /* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */
- nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0;
- src_port = eth->soc->ops.get_src_port_id(port, nbq);
+ src_port = eth->soc->ops.get_src_port_id(port, dev->nbq);
if (src_port < 0)
return src_port;
@@ -1763,7 +1762,7 @@ static int airhoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
__field_prep(SP_CPORT_MASK(val), FE_PSE_PORT_CDM2));
if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
- u32 mask = FC_ID_OF_SRC_PORT_MASK(nbq);
+ u32 mask = FC_ID_OF_SRC_PORT_MASK(dev->nbq);
airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask,
__field_prep(mask, AIROHA_GDM2_IDX));
@@ -1967,7 +1966,8 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
}
fport = airoha_get_fe_port(dev);
- msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
+ msg1 = FIELD_PREP(QDMA_ETH_TXMSG_NBOQ_MASK, dev->nbq) |
+ FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
q = &qdma->q_tx[qid];
@@ -2881,12 +2881,15 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
+ int j;
if (!port)
continue;
- if (port->dev == dev)
- return true;
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ if (port->devs[j] == dev)
+ return true;
+ }
}
return false;
@@ -2894,10 +2897,11 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
static int airoha_alloc_gdm_device(struct airoha_eth *eth,
struct airoha_gdm_port *port,
- struct device_node *np)
+ int nbq, struct device_node *np)
{
- struct airoha_gdm_dev *dev;
struct net_device *netdev;
+ struct airoha_gdm_dev *dev;
+ u8 index;
int err;
netdev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*dev),
@@ -2935,11 +2939,24 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
netdev->dev_addr);
}
+ /* Allowed nbq for EN7581 on GDM3 port are 4 and 5 for PCIE0
+ * and PCIE1 respectively.
+ */
+ index = nbq;
+ if (airoha_is_7581(eth) && port->id == AIROHA_GDM3_IDX)
+ index -= 4;
+
+ if (index >= ARRAY_SIZE(port->devs) || port->devs[index]) {
+ dev_err(eth->dev, "invalid nbq id: %d\n", nbq);
+ return -EINVAL;
+ }
+
dev = netdev_priv(netdev);
dev->dev = netdev;
dev->port = port;
- port->dev = dev;
dev->eth = eth;
+ dev->nbq = nbq;
+ port->devs[index] = dev;
return 0;
}
@@ -2949,7 +2966,8 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
{
const __be32 *id_ptr = of_get_property(np, "reg", NULL);
struct airoha_gdm_port *port;
- int err, p;
+ struct device_node *node;
+ int err, p, d = 0;
u32 id;
if (!id_ptr) {
@@ -2983,7 +3001,36 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
if (err)
return err;
- return airoha_alloc_gdm_device(eth, port, np);
+ for_each_child_of_node(np, node) {
+ /* Multiple external serdes connected to the FE GDM port via an
+ * external arbiter.
+ */
+ const __be32 *nbq_ptr;
+
+ if (!of_device_is_compatible(node, "airoha,eth-port"))
+ continue;
+
+ d++;
+ if (!of_device_is_available(node))
+ continue;
+
+ nbq_ptr = of_get_property(node, "reg", NULL);
+ if (!nbq_ptr) {
+ dev_err(eth->dev, "missing nbq id\n");
+ err = -EINVAL;
+ of_node_put(node);
+ break;
+ }
+
+ err = airoha_alloc_gdm_device(eth, port, be32_to_cpup(nbq_ptr),
+ node);
+ if (err) {
+ of_node_put(node);
+ return err;
+ }
+ }
+
+ return !d ? airoha_alloc_gdm_device(eth, port, 0, np) : 0;
}
static int airoha_register_gdm_devices(struct airoha_eth *eth)
@@ -2992,14 +3039,22 @@ static int airoha_register_gdm_devices(struct airoha_eth *eth)
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
- int err;
+ int j;
if (!port)
continue;
- err = register_netdev(port->dev->dev);
- if (err)
- return err;
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ struct airoha_gdm_dev *dev = port->devs[j];
+ int err;
+
+ if (!dev)
+ continue;
+
+ err = register_netdev(dev->dev);
+ if (err)
+ return err;
+ }
}
set_bit(DEV_STATE_REGISTERED, ð->state);
@@ -3106,14 +3161,20 @@ static int airoha_probe(struct platform_device *pdev)
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
- struct airoha_gdm_dev *dev;
+ int j;
if (!port)
continue;
- dev = port->dev;
- if (dev && dev->dev->reg_state == NETREG_REGISTERED)
- unregister_netdev(dev->dev);
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ struct airoha_gdm_dev *dev = port->devs[j];
+
+ if (!dev)
+ continue;
+
+ if (dev->dev->reg_state == NETREG_REGISTERED)
+ unregister_netdev(dev->dev);
+ }
airoha_metadata_dst_free(port);
}
airoha_hw_cleanup(eth);
@@ -3134,14 +3195,19 @@ static void airoha_remove(struct platform_device *pdev)
for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
struct airoha_gdm_port *port = eth->ports[i];
- struct airoha_gdm_dev *dev;
+ int j;
if (!port)
continue;
- dev = port->dev;
- if (dev)
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ struct airoha_gdm_dev *dev = port->devs[j];
+
+ if (!dev)
+ continue;
+
unregister_netdev(dev->dev);
+ }
airoha_metadata_dst_free(port);
}
airoha_hw_cleanup(eth);
@@ -3182,6 +3248,39 @@ static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq)
return -EINVAL;
}
+static int airoha_en7581_get_dev_from_sport(struct airoha_qdma_desc *desc,
+ u16 *port, u16 *dev)
+{
+ u32 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK,
+ le32_to_cpu(desc->msg1));
+
+ *dev = 0;
+ switch (sport) {
+ case 0x10 ... 0x14:
+ *port = 0; /* GDM1 */
+ break;
+ case 0x2:
+ *port = 1; /* GDM2 */
+ break;
+ case HSGMII_LAN_7581_PCIE1_SRCPORT:
+ *dev = 1;
+ fallthrough;
+ case HSGMII_LAN_7581_PCIE0_SRCPORT:
+ *port = 2; /* GDM3 */
+ break;
+ case HSGMII_LAN_7581_USB_SRCPORT:
+ *dev = 1;
+ fallthrough;
+ case HSGMII_LAN_7581_ETH_SRCPORT:
+ *port = 3; /* GDM4 */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const char * const an7583_xsi_rsts_names[] = {
"xsi-mac",
"hsi0-mac",
@@ -3211,6 +3310,36 @@ static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq)
return -EINVAL;
}
+static int airoha_an7583_get_dev_from_sport(struct airoha_qdma_desc *desc,
+ u16 *port, u16 *dev)
+{
+ u32 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK,
+ le32_to_cpu(desc->msg1));
+
+ *dev = 0;
+ switch (sport) {
+ case 0x10 ... 0x14:
+ *port = 0; /* GDM1 */
+ break;
+ case 0x2:
+ *port = 1; /* GDM2 */
+ break;
+ case HSGMII_LAN_7583_ETH_SRCPORT:
+ *port = 2; /* GDM3 */
+ break;
+ case HSGMII_LAN_7583_USB_SRCPORT:
+ *dev = 1;
+ fallthrough;
+ case HSGMII_LAN_7583_PCIE_SRCPORT:
+ *port = 3; /* GDM4 */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct airoha_eth_soc_data en7581_soc_data = {
.version = 0x7581,
.xsi_rsts_names = en7581_xsi_rsts_names,
@@ -3218,6 +3347,7 @@ static const struct airoha_eth_soc_data en7581_soc_data = {
.num_ppe = 2,
.ops = {
.get_src_port_id = airoha_en7581_get_src_port_id,
+ .get_dev_from_sport = airoha_en7581_get_dev_from_sport,
},
};
@@ -3228,6 +3358,7 @@ static const struct airoha_eth_soc_data an7583_soc_data = {
.num_ppe = 1,
.ops = {
.get_src_port_id = airoha_an7583_get_src_port_id,
+ .get_dev_from_sport = airoha_an7583_get_dev_from_sport,
},
};
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index e41e99738217b6aa61c5643b4b3894f6ca2aa1c8..7549960fc37c68a5df73c49eace0aa57fda98030 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -17,6 +17,7 @@
#include <net/dsa.h>
#define AIROHA_MAX_NUM_GDM_PORTS 4
+#define AIROHA_MAX_NUM_GDM_DEVS 2
#define AIROHA_MAX_NUM_QDMA 2
#define AIROHA_MAX_NUM_IRQ_BANKS 4
#define AIROHA_MAX_DSA_PORTS 7
@@ -535,12 +536,14 @@ struct airoha_qdma {
struct airoha_gdm_dev {
struct airoha_gdm_port *port;
struct airoha_qdma *qdma;
- struct net_device *dev;
struct airoha_eth *eth;
+ struct net_device *dev;
+
+ int nbq;
};
struct airoha_gdm_port {
- struct airoha_gdm_dev *dev;
+ struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
int id;
struct airoha_hw_stats stats;
@@ -582,6 +585,8 @@ struct airoha_eth_soc_data {
int num_ppe;
struct {
int (*get_src_port_id)(struct airoha_gdm_port *port, int nbq);
+ int (*get_dev_from_sport)(struct airoha_qdma_desc *desc,
+ u16 *port, u16 *dev);
} ops;
};
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index 85ad27c8d71a1af6431195a457f53817b647e644..a1199127b22629ae7fdd9cefb52dc447f121f940 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -163,6 +163,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
for (p = 0; p < ARRAY_SIZE(eth->ports); p++) {
struct airoha_gdm_port *port = eth->ports[p];
+ int j;
airoha_fe_rmw(eth, REG_PPE_MTU(i, p),
FP0_EGRESS_MTU_MASK |
@@ -174,7 +175,14 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
if (!port)
continue;
- airoha_ppe_set_cpu_port(port->dev, i);
+ for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
+ struct airoha_gdm_dev *dev = port->devs[j];
+
+ if (!dev)
+ continue;
+
+ airoha_ppe_set_cpu_port(dev, i);
+ }
}
}
}
--
2.53.0
^ permalink raw reply related
* [PATCH net-next 07/10] net: airoha: Rely on airoha_gdm_dev pointer in airhoa_is_lan_gdm_port()
From: Lorenzo Bianconi @ 2026-03-29 13:07 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lorenzo Bianconi
Cc: Christian Marangi, linux-arm-kernel, linux-mediatek, netdev,
devicetree, Xuegang Lu
In-Reply-To: <20260329-airoha-eth-multi-serdes-v1-0-00f52dc360ca@kernel.org>
Rename airhoa_is_lan_gdm_port in airhoa_is_lan_gdm_dev. Moreover, rely
on airoha_gdm_dev pointer in airhoa_is_lan_gdm_dev() instead of
airoha_gdm_port one.
This is a preliminary patch to support multiple net_devices connected to
the same GDM{3,4} port via an external hw multiplexer.
Tested-by: Xuegang Lu <xuegang.lu@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 6 ++----
drivers/net/ethernet/airoha/airoha_eth.h | 4 +++-
drivers/net/ethernet/airoha/airoha_ppe.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index b56a3a1668cd36deb808e53a5e90204b1e9c1d98..65046010ebabd336109a9f2afd4e6ce1d21e8593 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -73,12 +73,10 @@ static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
static void airoha_set_macaddr(struct airoha_gdm_dev *dev, const u8 *addr)
{
- struct airoha_gdm_port *port = dev->port;
struct airoha_eth *eth = dev->eth;
u32 val, reg;
- reg = airoha_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H
- : REG_FE_WAN_MAC_H;
+ reg = airoha_is_lan_gdm_dev(dev) ? REG_FE_LAN_MAC_H : REG_FE_WAN_MAC_H;
val = (addr[0] << 16) | (addr[1] << 8) | addr[2];
airoha_fe_wr(eth, reg, val);
@@ -1782,7 +1780,7 @@ static int airoha_dev_init(struct net_device *netdev)
int i;
/* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */
- dev->qdma = ð->qdma[!airoha_is_lan_gdm_port(port)];
+ dev->qdma = ð->qdma[!airoha_is_lan_gdm_dev(dev)];
dev->dev->irq = dev->qdma->irq_banks[0].irq;
airoha_set_macaddr(dev, netdev->dev_addr);
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index 222ae993435e8cf080278958e92d98c58d5f5f92..e41e99738217b6aa61c5643b4b3894f6ca2aa1c8 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -633,8 +633,10 @@ u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
#define airoha_qdma_clear(qdma, offset, val) \
airoha_rmw((qdma)->regs, (offset), (val), 0)
-static inline bool airoha_is_lan_gdm_port(struct airoha_gdm_port *port)
+static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev)
{
+ struct airoha_gdm_port *port = dev->port;
+
/* GDM1 port on EN7581 SoC is connected to the lan dsa switch.
* GDM{2,3,4} can be used as wan port connected to an external
* phy module.
diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
index eb8b7ed76fed5f36ad77886f5537a73eba0f0624..85ad27c8d71a1af6431195a457f53817b647e644 100644
--- a/drivers/net/ethernet/airoha/airoha_ppe.c
+++ b/drivers/net/ethernet/airoha/airoha_ppe.c
@@ -347,7 +347,7 @@ static int airoha_ppe_foe_entry_prepare(struct airoha_eth *eth,
/* For downlink traffic consume SRAM memory for hw
* forwarding descriptors queue.
*/
- if (airoha_is_lan_gdm_port(port))
+ if (airoha_is_lan_gdm_dev(dev))
val |= AIROHA_FOE_IB2_FAST_PATH;
if (dsa_port >= 0)
val |= FIELD_PREP(AIROHA_FOE_IB2_NBQ,
--
2.53.0
^ permalink raw reply related
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