* [PATCH net] net: airoha: Fix memory leak in airoha_qdma_rx_process()
From: Lorenzo Bianconi @ 2026-04-02 12:57 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni
Cc: linux-arm-kernel, linux-mediatek, netdev, Lorenzo Bianconi
If an error occurs on the subsequents buffers belonging to the
non-linear part of the skb (e.g. due to an error in the payload length
reported by the NIC or if we consumed all the available fragments for
the skb), the page_pool fragment will not be linked to the skb so it will
not return to the pool in the airoha_qdma_rx_process() error path. Fix the
memory leak partially reverting commit 'd6d2b0e1538d ("net: airoha: Fix
page recycling in airoha_qdma_rx_process()")' and always running
page_pool_put_full_page routine in the airoha_qdma_rx_process() error
path.
Fixes: d6d2b0e1538d ("net: airoha: Fix page recycling in airoha_qdma_rx_process()")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
drivers/net/ethernet/airoha/airoha_eth.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 95ba99b89428e4cafb91ff7813e43ffeb38e6d9b..91cb63a32d9904e0700bcce45b53624677d75c6c 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -697,9 +697,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
if (q->skb) {
dev_kfree_skb(q->skb);
q->skb = NULL;
- } else {
- page_pool_put_full_page(q->page_pool, page, true);
}
+ page_pool_put_full_page(q->page_pool, page, true);
}
airoha_qdma_fill_rx_queue(q);
---
base-commit: a1822cb524e89b4cd2cf0b82e484a2335496a6d9
change-id: 20260402-airoha_qdma_rx_process-mem-leak-fix-27b53dbaaa4f
Best regards,
--
Lorenzo Bianconi <lorenzo@kernel.org>
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: rng: mtk-rng: add SMC-based TRNG variants
From: Daniel Golle @ 2026-04-02 12:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Olivia Mackall, Herbert Xu, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang, linux-crypto, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20260402-towering-transparent-malamute-1e44b8@quoll>
On Thu, Apr 02, 2026 at 09:57:59AM +0200, Krzysztof Kozlowski wrote:
> On Thu, Apr 02, 2026 at 01:37:02AM +0100, Daniel Golle wrote:
> > Add compatible strings for MediaTek SoCs where the hardware random number
> > generator is accessed via a vendor-defined Secure Monitor Call (SMC)
> > rather than direct MMIO register access:
> >
> > - mediatek,mt7981-rng
> > - mediatek,mt7987-rng
> > - mediatek,mt7988-rng
> >
> > These variants require no reg, clocks, or clock-names properties since
> > the RNG hardware is managed by ARM Trusted Firmware-A.
> >
> > Relax the $nodename pattern to also allow 'rng' in addition to the
> > existing 'rng@...' pattern.
> >
> > Add a second example showing the minimal SMC variant binding.
> >
> > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > ---
> > v2: express compatibilities with fallback
> >
> > .../devicetree/bindings/rng/mtk-rng.yaml | 28 ++++++++++++++++---
> > 1 file changed, 24 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
> > index 7e8dc62e5d3a6..34648b53d14c6 100644
> > --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml
> > +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
> > @@ -11,12 +11,13 @@ maintainers:
> >
> > properties:
> > $nodename:
> > - pattern: "^rng@[0-9a-f]+$"
> > + pattern: "^rng(@[0-9a-f]+)?$"
> >
> > compatible:
> > oneOf:
> > - enum:
> > - mediatek,mt7623-rng
> > + - mediatek,mt7981-rng
> > - items:
> > - enum:
> > - mediatek,mt7622-rng
> > @@ -25,6 +26,11 @@ properties:
> > - mediatek,mt8365-rng
> > - mediatek,mt8516-rng
> > - const: mediatek,mt7623-rng
> > + - items:
> > + - enum:
> > + - mediatek,mt7987-rng
> > + - mediatek,mt7988-rng
> > + - const: mediatek,mt7981-rng
> >
> > reg:
> > maxItems: 1
> > @@ -38,9 +44,19 @@ properties:
> >
> > required:
> > - compatible
> > - - reg
> > - - clocks
> > - - clock-names
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + not:
>
> As requested last time - drop
>
> > + contains:
> > + const: mediatek,mt7981-rng
> > + then:
>
> missing constraints for mediatek,mt7981-rng. So does it have IO space
> and clocks or not?
The firmware variant which has the RNG under the control of TF-A and
requires Linux to use SMC to access it implies that Linux should not
touch the clk and cannot access the IO space (which is accessible from
secure-land only in this case).
Do you think something like the hunk below would properly express that?
@@ -38,9 +44,23 @@ properties:
required:
- compatible
- - reg
- - clocks
- - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt7981-rng
+ then:
+ properties:
+ reg: false
+ clocks: false
+ clock-names: false
+ else:
+ required:
+ - reg
+ - clocks
+ - clock-names
additionalProperties: false
>
> > + required:
> > + - reg
> > + - clocks
> > + - clock-names
> >
> > additionalProperties: false
> >
> > @@ -53,3 +69,7 @@ examples:
> > clocks = <&infracfg CLK_INFRA_TRNG>;
> > clock-names = "rng";
> > };
> > + - |
> > + rng {
> > + compatible = "mediatek,mt7981-rng";
>
> No improvements.
>
> Also, make the example complete since binding claims you have clocks and
> reg.
So clocks and reg have to be prohibited, not just allowed to be absent,
right?
>
> I am not sure it should be even same file, but if you are making it same
> file, then make it correct.
It's the same hardware. In case of the MT7986 SoC MediaTek has even switched
from requiring the mediatek,mt7623-rng driver implementation to have the TRNG
controlled by TF-A in newer firmware, see driver implementation
auto-detecting this as a work-around...
^ permalink raw reply
* Re: [PATCH v3 0/5] Support the FEAT_HDBSS introduced in Armv9.5
From: Leonardo Bras @ 2026-04-02 12:42 UTC (permalink / raw)
To: Tian Zheng
Cc: Leonardo Bras, maz, oupton, catalin.marinas, corbet, pbonzini,
will, yuzenghui, wangzhou1, liuyonglong, Jonathan.Cameron,
yezhenyu2, linuxarm, joey.gouly, kvmarm, kvm, linux-arm-kernel,
linux-doc, linux-kernel, skhan, suzuki.poulose
In-Reply-To: <730aaffa-9dfd-40c3-a372-c774d203b6e1@huawei.com>
On Thu, Apr 02, 2026 at 10:40:37AM +0800, Tian Zheng wrote:
>
> On 3/31/2026 10:13 PM, Leonardo Bras wrote:
> > On Wed, Feb 25, 2026 at 12:04:16PM +0800, Tian Zheng wrote:
> > > This series of patches add support to the Hardware Dirty state tracking
> > > Structure(HDBSS) feature, which is introduced by the ARM architecture
> > > in the DDI0601(ID121123) version.
> > >
> > > The HDBSS feature is an extension to the architecture that enhances
> > > tracking translation table descriptors' dirty state, identified as
> > > FEAT_HDBSS. This feature utilizes hardware assistance to achieve dirty
> > > page tracking, aiming to significantly reduce the overhead of scanning
> > > for dirty pages.
> > >
> > > The purpose of this feature is to make the execution overhead of live
> > > migration lower to both the guest and the host, compared to existing
> > > approaches (write-protect or search stage 2 tables).
> > >
> > > After these patches, users(such as qemu) can use the
> > > KVM_CAP_ARM_HW_DIRTY_STATE_TRACK ioctl to enable or disable the HDBSS
> > > feature before and after the live migration.
> > >
> > > v2:
> > > https://lore.kernel.org/linux-arm-kernel/20251121092342.3393318-1-zhengtian10@huawei.com/
> > >
> > > v2->v3 changes:
> > > - Remove the ARM64_HDBSS configuration option and ensure this feature
> > > is only enabled in VHE mode.
> > > - Move HDBSS-related variables to the arch-independent portion of the
> > > kvm structure.
> > > - Remove error messages during HDBSS enable/disable operations
> > > - Change HDBSS buffer flushing from handle_exit to vcpu_put,
> > > check_vcpu_requests, and kvm_handle_guest_abort.
> > > - Add fault handling for HDBSS including buffer full, external abort,
> > > and general protection fault (GPF).
> > > - Add support for a 4KB HDBSS buffer size, mapped to the value 0b0000.
> > > - Add a second argument to the ioctl to turn HDBSS on or off.
> > >
> > > Tian Zheng (1):
> > > KVM: arm64: Document HDBSS ioctl
> > >
> > > eillon (4):
> > > arm64/sysreg: Add HDBSS related register information
> > > KVM: arm64: Add support to set the DBM attr during memory abort
> > > KVM: arm64: Add support for FEAT_HDBSS
> > > KVM: arm64: Enable HDBSS support and handle HDBSSF events
> > >
> > > Documentation/virt/kvm/api.rst | 16 +++++
> > > arch/arm64/include/asm/cpufeature.h | 5 ++
> > > arch/arm64/include/asm/esr.h | 7 ++
> > > arch/arm64/include/asm/kvm_host.h | 17 +++++
> > > arch/arm64/include/asm/kvm_mmu.h | 1 +
> > > arch/arm64/include/asm/kvm_pgtable.h | 4 ++
> > > arch/arm64/include/asm/sysreg.h | 11 +++
> > > arch/arm64/kernel/cpufeature.c | 12 ++++
> > > arch/arm64/kvm/arm.c | 102 +++++++++++++++++++++++++++
> > > arch/arm64/kvm/hyp/pgtable.c | 6 ++
> > > arch/arm64/kvm/hyp/vhe/switch.c | 19 +++++
> > > arch/arm64/kvm/mmu.c | 70 ++++++++++++++++++
> > > arch/arm64/kvm/reset.c | 3 +
> > > arch/arm64/tools/cpucaps | 1 +
> > > arch/arm64/tools/sysreg | 29 ++++++++
> > > include/uapi/linux/kvm.h | 1 +
> > > tools/include/uapi/linux/kvm.h | 1 +
> > > 17 files changed, 305 insertions(+)
> > >
> > > --
> > > 2.33.0
> > >
> >
> > Hi Tian,
> >
> > I was thinking: maybe instead of putting the HDBSS (and HACDBS) stuff
> > across a bunch of KVM files, we should try to focus them all on a single
> > arch/arm64/kvm/dirty_bit.c file (plus a header such as
> > arch/arm64/include/asm/kvm_dirty_bit.h).
> >
> > What is your opinion on that?
> >
> > Thanks!
> > Leo
>
>
> Sorry for the late reply. Yes, I had the same thought before. In the next
> version, I will
>
> move all the HDBSS-related content into the same file, such as
> arch/arm64/kvm/dirty_bit.c
>
> and arch/arm64/include/asm/kvm_dirty_bit.h.
>
>
> Tian
>
>
> >
> >
Awesome! Then I will work my HACDBS enablement that way as well.
Thanks!
Leo
^ permalink raw reply
* Re: [PATCH 6.1.y 5/8] nvme-apple: remove an extra queue reference
From: Heyne, Maximilian @ 2026-04-02 12:31 UTC (permalink / raw)
To: Fedor Pchelkin
Cc: Christoph Hellwig, Sagi Grimberg, stable@vger.kernel.org,
Sven Peter, Chaitanya Kulkarni, Keith Busch, Jens Axboe,
Hector Martin, Alyssa Rosenzweig, James E.J. Bottomley,
Martin K. Petersen, Alim Akhtar, Avri Altman, Bart Van Assche,
Sasha Levin, Peter Wang, Greg Kroah-Hartman, Seunghui Lee,
Sanjeev Yadav, Wonkon Kim, Brian Kao, Hannes Reinecke, Ming Lei,
linux-block@vger.kernel.org, linux-kernel@vger.kernel.org,
asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-nvme@lists.infradead.org, linux-scsi@vger.kernel.org
In-Reply-To: <20260401232116-53765a086f3855a30962fb81-pchelkin@ispras>
On Wed, Apr 01, 2026 at 11:45:57PM +0300, Fedor Pchelkin wrote:
> Hello,
>
> "Heyne, Maximilian" <mheyne@amazon.de> wrote:
> > From: Christoph Hellwig <hch@lst.de>
> >
> > [ Upstream commit 941f7298c70c7668416e7845fa76eb72c07d966b ]
> >
> > Now that blk_mq_destroy_queue does not release the queue reference, there
> > is no need for a second admin queue reference to be held by the
> > apple_nvme structure.
>
> This patch is probably buggy in upstream. It removes extra reference
> ->get, but doesn't remove the corresponding ->put which is located
> inside apple_nvme_free_ctrl().
Now I'm seeing this as well. Has the same problem as the pci driver in
6.1 where blk_put_queue is called from nvme_free_ctrl() and again from
apple_nvme_free_ctrl(). Thank you for catching this. I don't have the
hardware to test this.
Are you going to send a fix upstream? It's looks to be broken on master,
too.
>
> I'm reporting here currently just for the heads up - was looking at the
> same nvme regression problem at 6.1.y, found this thread, and the
> nvme-apple changes appeared suspicious.
>
> nvme-apple patch is not required to fix the regression (this also holds
> true for [PATCH 6.1.y 3/8] scsi: remove an extra queue reference). Maybe
> they shouldn't go to stable.
I think, I'll send a v2 of the patch set without these 2 patches. It's
probably easier for Greg to apply.
>
> That said, the other part of the backport series FWIW looks good to me,
> and I've also verified it resolves the 6.1.y regression.
You may leave a Tested-by if you want ;-)
>
> Thanks.
>
> >
> > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
> > Reviewed-by: Sven Peter <sven@svenpeter.dev>
> > Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com>
> > Reviewed-by: Keith Busch <kbusch@kernel.org>
> > Link: https://lore.kernel.org/r/20221018135720.670094-5-hch@lst.de
> > Signed-off-by: Jens Axboe <axboe@kernel.dk>
> > Signed-off-by: Maximilian Heyne <mheyne@amazon.de>
> > ---
> > drivers/nvme/host/apple.c | 9 ---------
> > 1 file changed, 9 deletions(-)
> >
> > diff --git a/drivers/nvme/host/apple.c b/drivers/nvme/host/apple.c
> > index c5fc293c22123..c84ebfcfdeb88 100644
> > --- a/drivers/nvme/host/apple.c
> > +++ b/drivers/nvme/host/apple.c
> > @@ -1507,15 +1507,6 @@ static int apple_nvme_probe(struct platform_device *pdev)
> > goto put_dev;
> > }
> >
> > - if (!blk_get_queue(anv->ctrl.admin_q)) {
> > - nvme_start_admin_queue(&anv->ctrl);
> > - blk_mq_destroy_queue(anv->ctrl.admin_q);
> > - blk_put_queue(anv->ctrl.admin_q);
> > - anv->ctrl.admin_q = NULL;
> > - ret = -ENODEV;
> > - goto put_dev;
> > - }
> > -
> > nvme_reset_ctrl(&anv->ctrl);
> > async_schedule(apple_nvme_async_probe, anv);
> >
> > --
> > 2.50.1
Amazon Web Services Development Center Germany GmbH
Tamara-Danz-Str. 13
10243 Berlin
Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
Sitz: Berlin
Ust-ID: DE 365 538 597
^ permalink raw reply
* [PATCH v6 3/3] hwmon: emc2305: Support configurable fan PWM at shutdown
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
Some systems require fans to enter in a defined safe state during system
shutdown or reboot handoff.
Add support for the optional Device Tree property "fan-shutdown-percent"
to configure the shutdown PWM duty cycle per fan output.
If the property is present for a fan channel, the driver converts the
configured percentage value to the corresponding PWM duty cycle and
applies it during driver shutdown.
If the property is not present, the fan state remains unchanged.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
drivers/hwmon/emc2305.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c
index 0b42b82c8e22..dec3a79933c1 100644
--- a/drivers/hwmon/emc2305.c
+++ b/drivers/hwmon/emc2305.c
@@ -32,6 +32,7 @@
#define EMC2305_REG_DRIVE_PWM_OUT 0x2b
#define EMC2305_OPEN_DRAIN 0x0
#define EMC2305_PUSH_PULL 0x1
+#define EMC2305_PWM_SHUTDOWN_UNSET -1
#define EMC2305_PWM_DUTY2STATE(duty, max_state, pwm_max) \
DIV_ROUND_CLOSEST((duty) * (max_state), (pwm_max))
@@ -104,6 +105,7 @@ struct emc2305_cdev_data {
* @pwm_output_mask: PWM output mask
* @pwm_polarity_mask: PWM polarity mask
* @pwm_separate: separate PWM settings for every channel
+ * @pwm_shutdown: Set shutdown PWM.
* @pwm_min: array of minimum PWM per channel
* @pwm_freq: array of PWM frequency per channel
* @cdev_data: array of cooling devices data
@@ -116,6 +118,7 @@ struct emc2305_data {
u8 pwm_output_mask;
u8 pwm_polarity_mask;
bool pwm_separate;
+ s16 pwm_shutdown[EMC2305_PWM_MAX];
u8 pwm_min[EMC2305_PWM_MAX];
u16 pwm_freq[EMC2305_PWM_MAX];
struct emc2305_cdev_data cdev_data[EMC2305_PWM_MAX];
@@ -539,6 +542,7 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
struct device_node *child,
struct emc2305_data *data)
{ u32 ch;
+ u32 pwm_shutdown_percent;
int ret;
struct of_phandle_args args;
@@ -585,6 +589,16 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
}
of_node_put(args.np);
+
+ ret = of_property_read_u32(child, "fan-shutdown-percent",
+ &pwm_shutdown_percent);
+
+ if (!ret) {
+ pwm_shutdown_percent = clamp(pwm_shutdown_percent, 0, 100);
+ data->pwm_shutdown[ch] =
+ DIV_ROUND_CLOSEST(pwm_shutdown_percent * EMC2305_FAN_MAX, 100);
+ }
+
return 0;
}
@@ -637,6 +651,9 @@ static int emc2305_probe(struct i2c_client *client)
if (ret)
return ret;
+ for (i = 0; i < EMC2305_PWM_MAX; i++)
+ data->pwm_shutdown[i] = EMC2305_PWM_SHUTDOWN_UNSET;
+
pwm_childs = emc2305_probe_childs_from_dt(dev);
pdata = dev_get_platdata(&client->dev);
@@ -720,6 +737,23 @@ static int emc2305_probe(struct i2c_client *client)
return 0;
}
+static void emc2305_shutdown(struct i2c_client *client)
+{
+ int i;
+ int ret;
+ struct emc2305_data *data = i2c_get_clientdata(client);
+
+ for (i = 0; i < data->pwm_num; i++) {
+ if (data->pwm_shutdown[i] != EMC2305_PWM_SHUTDOWN_UNSET) {
+ ret = i2c_smbus_write_byte_data(client, EMC2305_REG_FAN_DRIVE(i),
+ data->pwm_shutdown[i]);
+ if (ret < 0)
+ dev_warn(&client->dev,
+ "Failed to set shutdown PWM for ch %d\n", i);
+ }
+ }
+}
+
static const struct of_device_id of_emc2305_match_table[] = {
{ .compatible = "microchip,emc2305", },
{},
@@ -732,6 +766,7 @@ static struct i2c_driver emc2305_driver = {
.of_match_table = of_emc2305_match_table,
},
.probe = emc2305_probe,
+ .shutdown = emc2305_shutdown,
.id_table = emc2305_ids,
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 2/3] dt-bindings: hwmon: emc2305: Add fan-shutdown-percent property
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
The EMC2305 fan controller supports multiple independent PWM fan
outputs. Some systems require fans to enter a defined safe state
during system shutdown or reboot handoff, until firmware or the next
boot stage reconfigures the controller.
Add an optional "fan-shutdown-percent" property to fan child nodes
allowing the PWM duty cycle applied during shutdown to be configured
per fan output.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
.../devicetree/bindings/hwmon/microchip,emc2305.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
index d3f06ebc19fa..8c2548539d7f 100644
--- a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
+++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
@@ -54,6 +54,12 @@ patternProperties:
The fan number used to determine the associated PWM channel.
maxItems: 1
+ fan-shutdown-percent:
+ description:
+ PWM duty cycle in percent applied to the fan during shutdown.
+ minimum: 0
+ maximum: 100
+
required:
- reg
@@ -80,12 +86,14 @@ examples:
fan@0 {
reg = <0x0>;
pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>;
+ fan-shutdown-percent = <100>;
#cooling-cells = <2>;
};
fan@1 {
reg = <0x1>;
pwms = <&fan_controller 26000 0 1>;
+ fan-shutdown-percent = <50>;
#cooling-cells = <2>;
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 1/3] hwmon: emc2305: Validate fan channel index
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260402122514.1811737-1-florin.leotescu@oss.nxp.com>
From: Florin Leotescu <florin.leotescu@nxp.com>
The fan channel index is used to access per-channel data structures.
Validate the index agains the number of available channels
before use to prevent out-of-bounds access if an invalid
value is provided.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
---
drivers/hwmon/emc2305.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/hwmon/emc2305.c b/drivers/hwmon/emc2305.c
index 64b213e1451e..0b42b82c8e22 100644
--- a/drivers/hwmon/emc2305.c
+++ b/drivers/hwmon/emc2305.c
@@ -548,6 +548,12 @@ static int emc2305_of_parse_pwm_child(struct device *dev,
return ret;
}
+ if (ch >= data->pwm_num) {
+ dev_err(dev, "invalid reg %u for node %pOF (valid range 0-%u)\n", ch, child,
+ data->pwm_num - 1);
+ return -EINVAL;
+ }
+
ret = of_parse_phandle_with_args(child, "pwms", "#pwm-cells", 0, &args);
if (ret)
--
2.34.1
^ permalink raw reply related
* [PATCH v6 0/3] hwmon: emc2305: Support configurable fan PWM at shutdown
From: florin.leotescu @ 2026-04-02 12:25 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel
Cc: daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
From: Florin Leotescu <florin.leotescu@nxp.com>
This series adds support for configuring the fan PWM duty cycle applied
during system shutdown for the EMC2305 fan controller.
Some platforms require fans to transition to a predefined safe state
during shutdown or reboot handoff until firmware or the next boot stage
reconfigures the controller.
The new optional Device Tree property "fan-shutdown-percent" allows the
shutdown PWM duty cycle to be configured per fan output.
Changes in v6:
- Split fan channel index validation into a separate patch.
Validate fan channel index agains the number of available channels.
- Refine dt-binding commit message to refer to PWM duty cycle
instead of fan speed.
Changes in v5:
- Add fan channel index bound check after reg property read
to prevent out-of-bounds access.
- Refine fan-shutdown-percent description.
Changes in v4:
- Initialize pwm_shudown array to EMC2305_PWM_SHUTDOWN_UNSET in probe,
to avoid treating unconfigured channels as valid and written 0
during shutdown
Changes in v3:
- Rebased on current upstream
- Dropped already upstreamed of_node_put(child) fix
Changes in v2:
- Address feedback from Guenter Roeck
- Make shutdown behavior configurable via Device Tree
- Add optional fan-shutdown-percent property
- Apply shutdown PWM only for channels defining the property
Florin Leotescu (3):
hwmon: emc2305: Validate fan channel index
dt-bindings: hwmon: emc2305: Add fan-shutdown-percent property
hwmon: emc2305: Support configurable fan PWM at shutdown
.../bindings/hwmon/microchip,emc2305.yaml | 8 ++++
drivers/hwmon/emc2305.c | 41 +++++++++++++++++++
2 files changed, 49 insertions(+)
--
2.34.1
^ permalink raw reply
* Re: [GIT PULL 6/7] arm64: tegra: Device tree changes for v7.1-rc1
From: Thierry Reding @ 2026-04-02 12:02 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-6-thierry.reding@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 2779 bytes --]
On Sun, Mar 29, 2026 at 05:10:43PM +0200, Thierry Reding wrote:
> From: Thierry Reding <thierry.reding@gmail.com>
>
> Hi ARM SoC maintainers,
>
> The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
>
> Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-arm64-dt
>
> for you to fetch changes up to c70e6bc11d2008fbb19695394b69fd941ab39030:
>
> arm64: tegra: Add Tegra264 GPIO controllers (2026-03-28 01:36:46 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> arm64: tegra: Device tree changes for v7.1-rc1
>
> Various fixes and new additions across a number of devices. GPIO and PCI
> are enabled on Tegra264 and the Jetson AGX Thor Developer Kit, allowing
> it to boot via network and mass storage.
>
> ----------------------------------------------------------------
> Diogo Ivo (1):
> arm64: tegra: smaug: Enable SPI-NOR flash
>
> Jon Hunter (1):
> arm64: tegra: Fix RTC aliases
>
> Prathamesh Shete (1):
> arm64: tegra: Add Tegra264 GPIO controllers
>
> Thierry Reding (6):
> dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
> Merge branch for-7.1/dt-bindings into for-7.1/pci
> arm64: tegra: Fix snps,blen properties
> arm64: tegra: Drop redundant clock and reset names for TSEC
> arm64: tegra: Add PCI controllers on Tegra264
> arm64: tegra: Add Jetson AGX Thor Developer Kit support
>
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 149 +++++++++
> arch/arm64/boot/dts/nvidia/Makefile | 2 +
> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 +
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 -
> arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 1 +
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 6 +-
> .../dts/nvidia/tegra264-p4071-0000+p3834-0008.dts | 11 +
> .../boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 12 +
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 336 +++++++++++++++++++--
> 10 files changed, 500 insertions(+), 32 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> create mode 100644 arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts
> create mode 100644 arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
Hi ARM SoC maintainers,
DT maintainers objected to the way I wanted to handle the DT bindings
dependency here, so I'll drop the whole PCI stuff from this and redo the
PR.
Thierry
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^ permalink raw reply
* Re: [GIT PULL 1/7] dt-bindings: Changes for v7.1-rc1
From: Thierry Reding @ 2026-04-02 12:00 UTC (permalink / raw)
To: arm, soc; +Cc: Thierry Reding, Jon Hunter, linux-tegra, linux-arm-kernel
In-Reply-To: <20260329151045.1443133-1-thierry.reding@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 3308 bytes --]
On Sun, Mar 29, 2026 at 05:10:38PM +0200, Thierry Reding wrote:
> From: Thierry Reding <thierry.reding@gmail.com>
>
> Hi ARM SoC maintainers,
>
> The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
>
> Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-7.1-dt-bindings
>
> for you to fetch changes up to bed2f5b4de6c6fd8f8928f6373ad92e8795c370f:
>
> dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit (2026-03-28 01:05:24 +0100)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> dt-bindings: Changes for v7.1-rc1
>
> This contains a few conversions to DT schema along with various
> additions and fixes to reduce the amount of validation warnings.
>
> Included are also a new binding for the PCIe controller found on
> Tegra264 as well as compatible strings for the Jetson AGX Thor
> Developer Kit.
>
> ----------------------------------------------------------------
> Sumit Gupta (1):
> dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings
>
> Svyatoslav Ryhel (1):
> dt-bindings: display: tegra: Document Tegra20 HDMI port
>
> Thierry Reding (9):
> dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
> dt-bindings: phy: tegra-xusb: Document Type C support
> dt-bindings: clock: tegra124-dfll: Convert to json-schema
> dt-bindings: interrupt-controller: tegra: Fix reg entries
> dt-bindings: arm: tegra: Add missing compatible strings
> dt-bindings: phy: tegra: Document Tegra210 USB PHY
> dt-bindings: memory: Add Tegra210 memory controller bindings
> dt-bindings: memory: tegra210: Mark EMC as cooling device
> dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit
>
> Documentation/devicetree/bindings/arm/tegra.yaml | 56 +++-
> .../bindings/arm/tegra/nvidia,tegra234-cbb.yaml | 4 +
> .../bindings/clock/nvidia,tegra124-dfll.txt | 155 -----------
> .../bindings/clock/nvidia,tegra124-dfll.yaml | 290 +++++++++++++++++++++
> .../display/tegra/nvidia,tegra20-hdmi.yaml | 13 +-
> .../interrupt-controller/nvidia,tegra20-ictlr.yaml | 23 +-
> .../memory-controllers/nvidia,tegra210-emc.yaml | 6 +-
> .../memory-controllers/nvidia,tegra210-mc.yaml | 77 ++++++
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 149 +++++++++++
> .../bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 39 ++-
> .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 1 +
> 11 files changed, 649 insertions(+), 164 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
Hi ARM SoC maintainers,
Please ignore this for now. I'm dropping my set of patches from this
because they upset the DT maintainers. I'll send another version with
only Sumit and Svyatoslav's patches.
Thierry
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^ permalink raw reply
* Re: [DMARC error]Re: [PATCH 0/2] Add PWM support Amlogic S7 S7D S6
From: George Stark @ 2026-04-02 11:46 UTC (permalink / raw)
To: Xianwei Zhao, Martin Blumenstingl
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, linux-pwm, devicetree, linux-kernel,
linux-arm-kernel, linux-amlogic, Junyi Zhao
In-Reply-To: <78e05060-6f25-4d78-8b0d-35b8fca0cecb@amlogic.com>
Hello Xianwei Zhao
On 3/31/26 10:59, Xianwei Zhao wrote:
> Hi George,
>
> On 2026/3/31 15:33, George Stark wrote:
>> Hello Martin, Xianwei
>>
>>
>> On 3/31/26 10:10, Xianwei Zhao wrote:
>>> Hi Martin,
>>> I confirmed with Junyi Zhao that the current implementation counts
>>> from zero, so this submission is correct.
>>> We agree this should be fixed and will address it in a follow-up patch.
>>> Thanks for pointing it out.
>>>
>>> On 2026/3/31 05:54, Martin Blumenstingl wrote:
>>>> Hi Xianwei Zhao,
>>>>
>>>> thanks for your contribution!
>>>>
>>>> On Thu, Mar 26, 2026 at 7:35 AM Xianwei Zhao via B4 Relay
>>>> <devnull+xianwei.zhao.amlogic.com@kernel.org> wrote:
>>>>> Add bindings and driver support Amlogic S7/S7D/S6 SoCs.
>>>> There is an old report that got lost, stating that the current
>>
>> Xianwei Zhao thanks for the confirmation.
>> I am the author of the old report and the corresponding patch and it's
>> not lost. So if the patch is correct I'll be glad to add relevant
>> tested-by tags.
>>
>
> I will use your patch and won't send a separate one.
> Do you mean I should add a Tested-by tag to your patch?
Yes since you've confirmed the problem exists then your tested-by tag
would be appropriate. And I'm ok if you resend the patch. Thanks.
>>>> pwm-meson driver has an off-by-one error with the hi and lo fields:
>>>> [0]
>>>> Since you are working on bringing up a new platform: is this something
>>>> you can verify in your lab?
>>>> To be clear: I'm not expecting you to work on this ad-hoc or bring a
>>>> patch into this series. However, it would be great if you could verify
>>>> if the findings from [0] are correct and send an updated patch in
>>>> future.
>>>>
>>>> Thank you and best regards
>>>> Martin
--
Best regards
George
^ permalink raw reply
* [PATCH v2] firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
From: Sebastian Ene @ 2026-04-02 11:39 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, android-kvm; +Cc: sudeep.holla, Sebastian Ene
Don't use the discovered buffer size from an FFA_FEATURES call directly
since we can run on a system that has the PAGE_SIZE larger than the
returned size which makes the alloc_pages_exact for the buffer to be
rounded up.
Fixes: 61824feae5c0 ("firmware: arm_ffa: Fetch the Rx/Tx buffer size using ffa_features()")
Signed-off-by: Sebastian Ene <sebastianene@google.com>
---
v1 -> v2:
* use the correct macro PAGE_ALIGN when calculating the size of the buffer
---
drivers/firmware/arm_ffa/driver.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
index f2f94d4d533e..eb2782848283 100644
--- a/drivers/firmware/arm_ffa/driver.c
+++ b/drivers/firmware/arm_ffa/driver.c
@@ -2078,7 +2078,7 @@ static int __init ffa_init(void)
ret = ffa_rxtx_map(virt_to_phys(drv_info->tx_buffer),
virt_to_phys(drv_info->rx_buffer),
- rxtx_bufsz / FFA_PAGE_SIZE);
+ PAGE_ALIGN(rxtx_bufsz) / FFA_PAGE_SIZE);
if (ret) {
pr_err("failed to register FFA RxTx buffers\n");
goto free_pages;
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply related
* Re: [PATCH v1 07/27] KVM: arm64: Provide arm64 KVM API for non-native architectures
From: Christian Borntraeger @ 2026-04-02 11:26 UTC (permalink / raw)
To: Marc Zyngier, Steffen Eiden
Cc: kvm, kvmarm, linux-arm-kernel, linux-kernel, linux-s390,
Andreas Grapentin, Arnd Bergmann, Catalin Marinas,
Claudio Imbrenda, David Hildenbrand, Gautam Gala,
Hendrik Brueckner, Janosch Frank, Joey Gouly,
Nina Schoetterl-Glausch, Oliver Upton, Paolo Bonzini,
Suzuki K Poulose, Ulrich Weigand, Will Deacon, Zenghui Yu
In-Reply-To: <86y0j53caf.wl-maz@kernel.org>
Am 02.04.26 um 12:08 schrieb Marc Zyngier:
>> +static inline bool kvm_supports_32bit_el0(void)
>> +{
>> + return false;
>> +}
>> +
>
> This looks wrong. The original file still has:
>
> #define kvm_supports_32bit_el0() \
> (system_supports_32bit_el0() && \
> !static_branch_unlikely(&arm64_mismatched_32bit_el0))
Thanks for spotting.
Yes, we will fix. Seems to be a leftover when sorting patches.
Christian
^ permalink raw reply
* [PATCH v3 7/7] futex: Use runtime constants for __futex_hash() hot path
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Borislav Petkov, Dave Hansen, x86,
Catalin Marinas, Will Deacon, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Heiko Carstens, Vasily Gorbik, Alexander Gordeev,
Christian Borntraeger, Arnd Bergmann, David Laight,
Samuel Holland
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
From: Peter Zijlstra <peterz@infradead.org>
Runtime constify the read-only after init data __futex_shift(shift_32),
__futex_mask(mask_32), and __futex_queues(ptr) used in __futex_hash()
hot path to avoid referencing global variable.
This also allows __futex_queues to be allocated dynamically to
"nr_node_ids" slots instead of reserving config dependent MAX_NUMNODES
(1 << CONFIG_NODES_SHIFT) worth of slots upfront.
No functional chages intended.
[ prateek: Dynamically allocate __futex_queues, mark the global data
__ro_after_init since they are constified after futex_init(). ]
Link: https://patch.msgid.link/20260227161841.GH606826@noisy.programming.kicks-ass.net
Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> # MAX_NUMNODES bloat
Not-yet-signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o No changes.
---
include/asm-generic/vmlinux.lds.h | 5 +++-
kernel/futex/core.c | 42 +++++++++++++++++--------------
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 1e1580febe4b..86f99fa6ae24 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -975,7 +975,10 @@
RUNTIME_CONST(shift, d_hash_shift) \
RUNTIME_CONST(ptr, dentry_hashtable) \
RUNTIME_CONST(ptr, __dentry_cache) \
- RUNTIME_CONST(ptr, __names_cache)
+ RUNTIME_CONST(ptr, __names_cache) \
+ RUNTIME_CONST(shift, __futex_shift) \
+ RUNTIME_CONST(mask, __futex_mask) \
+ RUNTIME_CONST(ptr, __futex_queues)
/* Alignment must be consistent with (kunit_suite *) in include/kunit/test.h */
#define KUNIT_TABLE() \
diff --git a/kernel/futex/core.c b/kernel/futex/core.c
index ff2a4fb2993f..73eade7184dc 100644
--- a/kernel/futex/core.c
+++ b/kernel/futex/core.c
@@ -45,23 +45,19 @@
#include <linux/mempolicy.h>
#include <linux/mmap_lock.h>
+#include <asm/runtime-const.h>
+
#include "futex.h"
#include "../locking/rtmutex_common.h"
-/*
- * The base of the bucket array and its size are always used together
- * (after initialization only in futex_hash()), so ensure that they
- * reside in the same cacheline.
- */
-static struct {
- unsigned long hashmask;
- unsigned int hashshift;
- struct futex_hash_bucket *queues[MAX_NUMNODES];
-} __futex_data __read_mostly __aligned(2*sizeof(long));
+static u32 __futex_mask __ro_after_init;
+static u32 __futex_shift __ro_after_init;
+static struct futex_hash_bucket **__futex_queues __ro_after_init;
-#define futex_hashmask (__futex_data.hashmask)
-#define futex_hashshift (__futex_data.hashshift)
-#define futex_queues (__futex_data.queues)
+static __always_inline struct futex_hash_bucket **futex_queues(void)
+{
+ return runtime_const_ptr(__futex_queues);
+}
struct futex_private_hash {
int state;
@@ -439,14 +435,14 @@ __futex_hash(union futex_key *key, struct futex_private_hash *fph)
* NOTE: this isn't perfectly uniform, but it is fast and
* handles sparse node masks.
*/
- node = (hash >> futex_hashshift) % nr_node_ids;
+ node = runtime_const_shift_right_32(hash, __futex_shift) % nr_node_ids;
if (!node_possible(node)) {
node = find_next_bit_wrap(node_possible_map.bits,
nr_node_ids, node);
}
}
- return &futex_queues[node][hash & futex_hashmask];
+ return &futex_queues()[node][runtime_const_mask_32(hash, __futex_mask)];
}
/**
@@ -1916,7 +1912,7 @@ int futex_hash_allocate_default(void)
* 16 <= threads * 4 <= global hash size
*/
buckets = roundup_pow_of_two(4 * threads);
- buckets = clamp(buckets, 16, futex_hashmask + 1);
+ buckets = clamp(buckets, 16, __futex_mask + 1);
if (current_buckets >= buckets)
return 0;
@@ -1986,10 +1982,19 @@ static int __init futex_init(void)
hashsize = max(4, hashsize);
hashsize = roundup_pow_of_two(hashsize);
#endif
- futex_hashshift = ilog2(hashsize);
+ __futex_mask = hashsize - 1;
+ __futex_shift = ilog2(hashsize);
size = sizeof(struct futex_hash_bucket) * hashsize;
order = get_order(size);
+ __futex_queues = kcalloc(nr_node_ids, sizeof(*__futex_queues), GFP_KERNEL);
+
+ runtime_const_init(shift, __futex_shift);
+ runtime_const_init(mask, __futex_mask);
+ runtime_const_init(ptr, __futex_queues);
+
+ BUG_ON(!futex_queues());
+
for_each_node(n) {
struct futex_hash_bucket *table;
@@ -2003,10 +2008,9 @@ static int __init futex_init(void)
for (i = 0; i < hashsize; i++)
futex_hash_bucket_init(&table[i], NULL);
- futex_queues[n] = table;
+ futex_queues()[n] = table;
}
- futex_hashmask = hashsize - 1;
pr_info("futex hash table entries: %lu (%lu bytes on %d NUMA nodes, total %lu KiB, %s).\n",
hashsize, size, num_possible_nodes(), size * num_possible_nodes() / 1024,
order > MAX_PAGE_ORDER ? "vmalloc" : "linear");
--
2.34.1
^ permalink raw reply related
* [PATCH v3 6/7] asm-generic/runtime-const: Add dummy runtime_const_mask_32()
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Arnd Bergmann
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
From: Peter Zijlstra <peterz@infradead.org>
Add a dummy runtime_const_mask_32() for all the architectures that do
not support runtime-const.
Link: https://patch.msgid.link/20260227161841.GH606826@noisy.programming.kicks-ass.net
Not-yet-signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o No changes.
---
include/asm-generic/runtime-const.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/asm-generic/runtime-const.h b/include/asm-generic/runtime-const.h
index 670499459514..03e6e3e02401 100644
--- a/include/asm-generic/runtime-const.h
+++ b/include/asm-generic/runtime-const.h
@@ -10,6 +10,7 @@
*/
#define runtime_const_ptr(sym) (sym)
#define runtime_const_shift_right_32(val, sym) ((u32)(val)>>(sym))
+#define runtime_const_mask_32(val, sym) ((u32)(val)&(sym))
#define runtime_const_init(type,sym) do { } while (0)
#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v3 5/7] s390/runtime-const: Introduce runtime_const_mask_32()
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Heiko Carstens, Vasily Gorbik,
Alexander Gordeev, Christian Borntraeger
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak, Sven Schnelle
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
Futex hash computation requires a mask operation with read-only after
init data that will be converted to a runtime constant in the subsequent
commit.
Introduce runtime_const_mask_32 to further optimize the mask operation
in the futex hash computation hot path.
GCC generates a:
nilf %r1,<imm32>
to tackle arbitrary 32-bit masks and the same is implemented here.
Immediate patching pattern for __runtime_fixup_mask() has been adopted
from __runtime_fixup_ptr().
Acked-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o Collected Ack from Heiko after folding in the suggested diff. (Thanks
a ton!)
---
arch/s390/include/asm/runtime-const.h | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/s390/include/asm/runtime-const.h b/arch/s390/include/asm/runtime-const.h
index 17878b1d048c..7b71156031ec 100644
--- a/arch/s390/include/asm/runtime-const.h
+++ b/arch/s390/include/asm/runtime-const.h
@@ -33,6 +33,20 @@
__ret; \
})
+#define runtime_const_mask_32(val, sym) \
+({ \
+ unsigned int __ret = (val); \
+ \
+ asm_inline( \
+ "0: nilf %[__ret],12\n" \
+ ".pushsection runtime_mask_" #sym ",\"a\"\n" \
+ ".long 0b - .\n" \
+ ".popsection" \
+ : [__ret] "+d" (__ret) \
+ : : "cc"); \
+ __ret; \
+})
+
#define runtime_const_init(type, sym) do { \
extern s32 __start_runtime_##type##_##sym[]; \
extern s32 __stop_runtime_##type##_##sym[]; \
@@ -43,12 +57,12 @@
__stop_runtime_##type##_##sym); \
} while (0)
-/* 32-bit immediate for iihf and iilf in bits in I2 field */
static inline void __runtime_fixup_32(u32 *p, unsigned int val)
{
s390_kernel_write(p, &val, sizeof(val));
}
+/* 32-bit immediate for iihf and iilf in bits in I2 field */
static inline void __runtime_fixup_ptr(void *where, unsigned long val)
{
__runtime_fixup_32(where + 2, val >> 32);
@@ -65,6 +79,12 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
s390_kernel_write(where, &insn, sizeof(insn));
}
+/* 32-bit immediate for nilf in bits in I2 field */
+static inline void __runtime_fixup_mask(void *where, unsigned long val)
+{
+ __runtime_fixup_32(where + 2, val);
+}
+
static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
unsigned long val, s32 *start, s32 *end)
{
--
2.34.1
^ permalink raw reply related
* [PATCH v3 4/7] riscv/runtime-const: Introduce runtime_const_mask_32()
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Samuel Holland, David Laight
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak, Alexandre Ghiti, Charlie Jenkins,
Charles Mirabile
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
Futex hash computation requires a mask operation with read-only after
init data that will be converted to a runtime constant in the subsequent
commit.
Introduce runtime_const_mask_32 to further optimize the mask operation
in the futex hash computation hot path. GCC generates a:
lui a0, 0x12346 # upper; +0x800 then >>12 for correct rounding
addi a0, a0, 0x678 # lower 12 bits
and a1, a1, a0 # a1 = a1 & a0
pattern to tackle arbitrary 32-bit masks and the same was also suggested
by Claude which is implemented here. The (__mask & val) operation is
intentionally placed outside of asm block to allow compilers to further
optimize it if possible.
__runtime_fixup_ptr() already patches a "lui + addi" sequence which has
been reused to patch the same sequence for __runtime_fixup_mask().
Assisted-by: Claude:claude-sonnet-4-5
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o Moved the "&" operation outside the inline asm block to allow for
compilers to further optimize it if possible. (Based on David's
comment on ARM64 bits).
---
arch/riscv/include/asm/runtime-const.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/asm/runtime-const.h
index d766e2b9e6df..85efba8ecf12 100644
--- a/arch/riscv/include/asm/runtime-const.h
+++ b/arch/riscv/include/asm/runtime-const.h
@@ -153,6 +153,22 @@
__ret; \
})
+#define runtime_const_mask_32(val, sym) \
+({ \
+ u32 __mask; \
+ asm_inline(".option push\n\t" \
+ ".option norvc\n\t" \
+ "1:\t" \
+ "lui %[__mask],0x89abd\n\t" \
+ "addi %[__mask],%[__mask],-0x211\n\t" \
+ ".option pop\n\t" \
+ ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \
+ ".long 1b - .\n\t" \
+ ".popsection" \
+ : [__mask] "=r" (__mask)); \
+ (__mask & val); \
+})
+
#define runtime_const_init(type, sym) do { \
extern s32 __start_runtime_##type##_##sym[]; \
extern s32 __stop_runtime_##type##_##sym[]; \
@@ -256,6 +272,12 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
mutex_unlock(&text_mutex);
}
+static inline void __runtime_fixup_mask(void *where, unsigned long val)
+{
+ __runtime_fixup_32(where, where + 4, val);
+ __runtime_fixup_caches(where, 2);
+}
+
static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
unsigned long val, s32 *start, s32 *end)
{
--
2.34.1
^ permalink raw reply related
* [PATCH v3 3/7] arm64/runtime-const: Introduce runtime_const_mask_32()
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Catalin Marinas, Will Deacon,
David Laight
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak, Jisheng Zhang
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
Futex hash computation requires a mask operation with read-only after
init data that will be converted to a runtime constant in the subsequent
commit.
Introduce runtime_const_mask_32 to further optimize the mask operation
in the futex hash computation hot path. GCC generates a:
movz w1, #lo16, lsl #0 // w1 = bits [15:0]
movk w1, #hi16, lsl #16 // w1 = full 32-bit value
and w0, w0, w1 // w0 = w0 & w1
pattern to tackle arbitrary 32-bit masks and the same was also suggested
by Claude which is implemented here. The (__mask & value) operation is
intentiaonally placed outside of asm block to allow compilers to further
optimize it if possible.
__runtime_fixup_ptr() already patches a "movz, + movk lsl #16" sequence
which has been reused to patch the same sequence for
__runtime_fixup_mask().
Assisted-by: Claude:claude-sonnet-4-5
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o Reordered this to come after the text patching fixes for ARM64.
(David)
o Moved the "&" operation outside the inline asm block to allow for
compilers to further optimize it if possible. (David)
---
arch/arm64/include/asm/runtime-const.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/runtime-const.h
index a3106f80912b..21f817eb5951 100644
--- a/arch/arm64/include/asm/runtime-const.h
+++ b/arch/arm64/include/asm/runtime-const.h
@@ -36,6 +36,17 @@
:"r" (0u+(val))); \
__ret; })
+#define runtime_const_mask_32(val, sym) ({ \
+ unsigned long __mask; \
+ asm_inline("1:\t" \
+ "movz %w0, #0xcdef\n\t" \
+ "movk %w0, #0x89ab, lsl #16\n\t" \
+ ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \
+ ".long 1b - .\n\t" \
+ ".popsection" \
+ :"=r" (__mask)); \
+ (__mask & val); })
+
#define runtime_const_init(type, sym) do { \
extern s32 __start_runtime_##type##_##sym[]; \
extern s32 __stop_runtime_##type##_##sym[]; \
@@ -73,6 +84,14 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
aarch64_insn_patch_text_nosync(p, insn);
}
+/* Immediate value is 6 bits starting at bit #16 */
+static inline void __runtime_fixup_mask(void *where, unsigned long val)
+{
+ __le32 *p = lm_alias(where);
+ __runtime_fixup_16(p, val);
+ __runtime_fixup_16(p+1, val >> 16);
+}
+
static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
unsigned long val, s32 *start, s32 *end)
{
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/7] arm64/runtime-const: Use aarch64_insn_patch_text_nosync() for patching
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Catalin Marinas, Will Deacon,
David Laight
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak, Jisheng Zhang
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
The current scheme to directly patch the kernel text for runtime
constants runs into the following issue with futex adapted to using
runtime constants on arm64:
Unable to handle kernel write to read-only memory at virtual address ...
The pc points to the *p assignment in the following call chain:
futex_init()
runtime_const_init(shift, __futex_shift)
__runtime_fixup_shift()
*p = cpu_to_le32(insn);
which suggests that core_initcall() is too late to patch the kernel text
directly unlike the "d_hash_shift" which is initialized during
vfs_caches_init_early() before the protections are in place.
Use aarch64_insn_patch_text_nosync() to patch the runtime constants
instead of doing it directly to allow runtime_const_init() slightly
later into the boot.
Since aarch64_insn_patch_text_nosync() calls caches_clean_inval_pou()
internally, __runtime_fixup_caches() ends up being redundant.
runtime_const_init() are rare and the overheads of multiple calls to
caches_clean_inval_pou() instead of batching them together should be
negligible in practice.
The cpu_to_le32() conversion of instruction isn't necessary since it is
handled later in the aarch64_insn_patch_text_nosync() call-chain:
aarch64_insn_patch_text_nosync(addr, insn)
aarch64_insn_write(addr, insn)
__aarch64_insn_write(addr, cpu_to_le32(insn))
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o Reordered this to come before the introduction of
runtime_const_mask_32(). (David)
o Trimmed down the commit message to be more precise.
---
arch/arm64/include/asm/runtime-const.h | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/runtime-const.h
index c3dbd3ae68f6..a3106f80912b 100644
--- a/arch/arm64/include/asm/runtime-const.h
+++ b/arch/arm64/include/asm/runtime-const.h
@@ -7,6 +7,7 @@
#endif
#include <asm/cacheflush.h>
+#include <asm/text-patching.h>
/* Sigh. You can still run arm64 in BE mode */
#include <asm/byteorder.h>
@@ -50,13 +51,7 @@ static inline void __runtime_fixup_16(__le32 *p, unsigned int val)
u32 insn = le32_to_cpu(*p);
insn &= 0xffe0001f;
insn |= (val & 0xffff) << 5;
- *p = cpu_to_le32(insn);
-}
-
-static inline void __runtime_fixup_caches(void *where, unsigned int insns)
-{
- unsigned long va = (unsigned long)where;
- caches_clean_inval_pou(va, va + 4*insns);
+ aarch64_insn_patch_text_nosync(p, insn);
}
static inline void __runtime_fixup_ptr(void *where, unsigned long val)
@@ -66,7 +61,6 @@ static inline void __runtime_fixup_ptr(void *where, unsigned long val)
__runtime_fixup_16(p+1, val >> 16);
__runtime_fixup_16(p+2, val >> 32);
__runtime_fixup_16(p+3, val >> 48);
- __runtime_fixup_caches(where, 4);
}
/* Immediate value is 6 bits starting at bit #16 */
@@ -76,8 +70,7 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
u32 insn = le32_to_cpu(*p);
insn &= 0xffc0ffff;
insn |= (val & 63) << 16;
- *p = cpu_to_le32(insn);
- __runtime_fixup_caches(where, 1);
+ aarch64_insn_patch_text_nosync(p, insn);
}
static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/7] x86/runtime-const: Introduce runtime_const_mask_32()
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Borislav Petkov, Dave Hansen, x86
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak
In-Reply-To: <20260402112250.2138-1-kprateek.nayak@amd.com>
From: Peter Zijlstra <peterz@infradead.org>
Futex hash computation requires a mask operation with read-only after
init data that will be converted to a runtime constant in the subsequent
commit.
Introduce runtime_const_mask_32 to further optimize the mask operation
in the futex hash computation hot path.
[ prateek: Broke off the x86 chunk, commit message. ]
Link: https://patch.msgid.link/20260227161841.GH606826@noisy.programming.kicks-ass.net
Not-yet-signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: K Prateek Nayak <kprateek.nayak@amd.com>
---
Changelog v2..v3:
o No changes.
---
arch/x86/include/asm/runtime-const.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/runtime-const.h b/arch/x86/include/asm/runtime-const.h
index 4cd94fdcb45e..b13f7036c1c9 100644
--- a/arch/x86/include/asm/runtime-const.h
+++ b/arch/x86/include/asm/runtime-const.h
@@ -41,6 +41,15 @@
:"+r" (__ret)); \
__ret; })
+#define runtime_const_mask_32(val, sym) ({ \
+ typeof(0u+(val)) __ret = (val); \
+ asm_inline("and $0x12345678, %k0\n1:\n" \
+ ".pushsection runtime_mask_" #sym ",\"a\"\n\t"\
+ ".long 1b - 4 - .\n" \
+ ".popsection" \
+ : "+r" (__ret)); \
+ __ret; })
+
#define runtime_const_init(type, sym) do { \
extern s32 __start_runtime_##type##_##sym[]; \
extern s32 __stop_runtime_##type##_##sym[]; \
@@ -65,6 +74,11 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val)
*(unsigned char *)where = val;
}
+static inline void __runtime_fixup_mask(void *where, unsigned long val)
+{
+ *(unsigned int *)where = val;
+}
+
static inline void runtime_const_fixup(void (*fn)(void *, unsigned long),
unsigned long val, s32 *start, s32 *end)
{
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/7] futex: Use runtime constants for futex_hash computation
From: K Prateek Nayak @ 2026-04-02 11:22 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Peter Zijlstra,
Sebastian Andrzej Siewior, Borislav Petkov, Dave Hansen, x86,
Catalin Marinas, Will Deacon, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Heiko Carstens, Vasily Gorbik, Alexander Gordeev,
Christian Borntraeger, Arnd Bergmann, David Laight,
Samuel Holland
Cc: Darren Hart, Davidlohr Bueso, André Almeida, linux-arch,
linux-kernel, linux-s390, linux-riscv, linux-arm-kernel,
K Prateek Nayak
tl;dr
This series introduces runtime_const_mask_32() and uses runtime
constants for __ro_after_init data in futex_hash() hot path. More
information can be found on v2 [1].
Comments that have *not* been addressed in this version
=======================================================
Samuel had an observation on v2 that __futex_mask is always of the form
((1 << bits) - 1) /* Only lower bits set; bits > 1. */
and ARM64 and RISC-V can use a single ubfx (ARM64), or slli+srli pattern
(RISC-V) for the mask operation respectively but this had the main
limitation of runtime_const_mask_32() only working with masks of such
form and others would fail runtime_const_init() at boot.
RISC-V does generated a "addi + slli" pattern with CONFIG_BASE_SMALL=y
where the futex_hash_mask can be computed at compile time.
The old scheme is retained for now since it is equivalent to the
generated asm for !CONFIG_BASE_SMALL and can handle any arbitrary masks
allowing for all future use cases.
If there is enough interest, please let me know, and I can look into
further optimization to runtime_const_mask_32() based on the current use
case for __futex_hash.
Testing
=======
Apart from x86, which was build and boot tested on baremetal, all the
other architectures have been build and boot tested with cross-compile +
QEMU with some light sanity testing on each.
Patches are based on:
git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git master
at commit 1086b33a3f64 ("Merge branch into tip/master: 'x86/vdso'")
(2026-04-02)
Everyone has been Cc'd on the cover-letter and the futex bits for the
context. Respective arch maintainers, reviewers, and whoever got lucky
with get_maintainer.pl have been Cc'd on their respective arch specific
changes. Futex maintainers and the lists will be receiving the whole
series (sorry in advance!)
---
changelog rfc v2..v3:
o Collected Ack from Heiko for s390 bits after folding in their
suggested changes (Thanks a ton!)
o Reordered Patch 2 and Patch 3 to allow for runtime_const_init() at
late_initcall() first before introducing runtime_const_mask_32() on
ARM64. (David)
o Moved the "&" operation outside the inline asm block on ARM64 and
RISC-V which allows the compiler to optimize it further if possible.
(David)
o Dropped the RFC tag.
v2: https://lore.kernel.org/lkml/20260316052401.18910-1-kprateek.nayak@amd.com/ [1]
changelog rfc v1..rfc v2:
o Use runtime constants to avoid the dereference overheads for
dynamically allocated futex_queues.
o arch/ side plumbings for runtime_const_mask_32()
v1: https://lore.kernel.org/all/20260128101358.20954-1-kprateek.nayak@amd.com/
---
K Prateek Nayak (4):
arm64/runtime-const: Use aarch64_insn_patch_text_nosync() for patching
arm64/runtime-const: Introduce runtime_const_mask_32()
riscv/runtime-const: Introduce runtime_const_mask_32()
s390/runtime-const: Introduce runtime_const_mask_32()
Peter Zijlstra (3):
x86/runtime-const: Introduce runtime_const_mask_32()
asm-generic/runtime-const: Add dummy runtime_const_mask_32()
futex: Use runtime constants for __futex_hash() hot path
arch/arm64/include/asm/runtime-const.h | 32 ++++++++++++++------
arch/riscv/include/asm/runtime-const.h | 22 ++++++++++++++
arch/s390/include/asm/runtime-const.h | 22 +++++++++++++-
arch/x86/include/asm/runtime-const.h | 14 +++++++++
include/asm-generic/runtime-const.h | 1 +
include/asm-generic/vmlinux.lds.h | 5 ++-
kernel/futex/core.c | 42 ++++++++++++++------------
7 files changed, 107 insertions(+), 31 deletions(-)
base-commit: 1086b33a3f644c3bc37abefd699defc45accced1
--
2.34.1
^ permalink raw reply
* [PATCH 3/5] arm64: dts: freescale: imx93-phycore-som: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyCORE-i.MX93 SoM.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../boot/dts/freescale/imx93-phycore-som.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index ebc57841f27f..94eb04ace96e 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -90,6 +90,28 @@ ethphy1: ethernet-phy@1 {
};
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "I2C3_SDA", "I2C3_SCL";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "", "PMIC_IRQ_B";
+};
+
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: freescale: imx93-phyboard-segin: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Segin-i.MX93.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx93-phyboard-segin.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index a982606de1ee..4e4356397ba0 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -145,6 +145,24 @@ &flexcan1 {
status = "okay";
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
+};
+
+&gpio3 {
+ gpio-line-names = "SD1_nCD", "", "", "", "",
+ "", "", "SD1_nRESET";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "CAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 2/5] arm64: dts: freescale: imx91-phyboard-segin: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Segin-i.MX91.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx91-phyboard-segin.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
index 7b18a58024f5..8b19fc17eacd 100644
--- a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
@@ -137,6 +137,24 @@ ethphy2: ethernet-phy@2 {
};
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
+};
+
+&gpio3 {
+ gpio-line-names = "SD1_nCD", "", "", "", "",
+ "", "", "SD1_nRESET";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "CAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* CAN */
&flexcan1 {
pinctrl-names = "default";
--
2.43.0
^ permalink raw reply related
* [PATCH 4/5] arm64: dts: freescale: imx93-phyboard-nash: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Nash-i.MX93.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx93-phyboard-nash.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
index eac389ed30f3..b82192f25498 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
@@ -141,6 +141,37 @@ &flexcan1 {
status = "okay";
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C2_SCL", "I2C2_SDA";
+};
+
+&gpio2 {
+ gpio-line-names = "SPI6_CS0", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "TPM_nIRQ", "", "",
+ "", "", "", "", "",
+ "", "", "", "I2C3_SDA", "I2C3_SCL";
+};
+
+&gpio3 {
+ gpio-line-names = "SD2_nCD", "", "", "", "",
+ "", "", "SD2_nRESET", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "nENET1_INT";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "nCAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
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