* Re: [PATCH v4] crypto: testmgr - Add test vectors for authenc(hmac(md5),cbc(aes))
From: Herbert Xu @ 2026-04-03 1:03 UTC (permalink / raw)
To: Aleksander Jan Bajkowski
Cc: davem, mcoquelin.stm32, alexandre.torgue, linux-crypto,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260303184916.69132-1-olek2@wp.pl>
On Tue, Mar 03, 2026 at 07:48:44PM +0100, Aleksander Jan Bajkowski wrote:
> Test vectors were generated starting from existing CBC(AES) test vectors
> (RFC3602, NIST SP800-38A) and adding HMAC(MD5) computed with Python
> script. Then, the results were double-checked on Mediatek MT7981 (safexcel)
> and NXP P2020 (talitos). Both platforms pass self-tests.
>
> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
> ---
> v4:
> - rename aes-generic -> aes-lib
> v3:
> - correct sha384 -> md5 in description
> v2:
> - rebase and resolve conflicts
> ---
> crypto/testmgr.c | 7 ++
> crypto/testmgr.h | 255 +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 262 insertions(+)
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH v5 2/3] arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro
From: Andrew Lunn @ 2026-04-03 0:53 UTC (permalink / raw)
To: Dennis Gilmore
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
FUKAUMI Naoki, Hsun Lai, Jonas Karlman, Chaoyi Chen, John Clark,
Michael Opdenacker, Quentin Schulz, Chukun Pan, Alexey Charkov,
Peter Robinson, Michael Riesch, Mykola Kvach, Jimmy Hon,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <CAABkxwvnv7i=xg53qu4JDapBs6ATaMGh9iXZfi+od=CCxRxQUA@mail.gmail.com>
On Wed, Apr 01, 2026 at 08:27:30AM -0500, Dennis Gilmore wrote:
> Hi Andrew,
>
> On Wed, Apr 1, 2026 at 6:52 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > +&gmac1 {
> > > + clock_in_out = "output";
> > > + phy-handle = <&rgmii_phy1>;
> > > + phy-mode = "rgmii-rxid";
> > > + pinctrl-0 = <&gmac1_miim
> > > + &gmac1_tx_bus2
> > > + &gmac1_rx_bus2
> > > + &gmac1_rgmii_clk
> > > + &gmac1_rgmii_bus>;
> > > + pinctrl-names = "default";
> > > + tx_delay = <0x42>;
> >
> > phy-mode = "rgmii-rxid" means the PCB provides the 2ns delay for
> > TX. This is unlikely to be correct. Please try "rgmii-id" and delete
> > the tx_delay.
>
> As I mentioned to you in v2 I do not have the affected hardware to
> test any changes. This patch is just moving the existing definition
> from the common dtsi to the two devices that have gmac1 wired up. I
> am not comfortable making changes here that I can not verify if they
> work or not.
Yes, sorry.
Please add this to the commit message, so i don't make the same point
again.
Andrew
^ permalink raw reply
* [PATCH v3 9/9] driver core: Replace dev->offline + ->offline_disabled with DEV_FLAGs
From: Douglas Anderson @ 2026-04-03 0:49 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern
Cc: Robin Murphy, Leon Romanovsky, Paul Burton, Saravana Kannan,
Alexander Lobakin, Eric Dumazet, Toshi Kani, Christoph Hellwig,
Alexey Kardashevskiy, Johan Hovold, Douglas Anderson, ardb,
broonie, catalin.marinas, chleroy, david, driver-core, kees,
kevin.brodsky, lenb, linux-acpi, linux-arm-kernel, linux-cxl,
linux-kernel, linux-mm, linuxppc-dev, maddy, maz, miko.lenczewski,
mpe, npiggin, osalvador, oupton, peterz, tglx, will, yangyicong,
yeoreum.yun
In-Reply-To: <20260403005005.30424-1-dianders@chromium.org>
In C, bitfields are not necessarily safe to modify from multiple
threads without locking. Switch "offline" and "offline_disabled" over
to the "flags" field so modifications are safe.
Cc: Rafael J. Wysocki <rafael@kernel.org>
Cc: Toshi Kani <toshi.kani@hp.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Not fixing any known bugs; problem is theoretical and found by code
inspection. Change is done somewhat manually and only lightly tested
(mostly compile-time tested).
Changes in v3:
- New
arch/arm64/kernel/cpufeature.c | 2 +-
.../platforms/pseries/hotplug-memory.c | 4 ++--
drivers/acpi/scan.c | 3 ++-
drivers/base/core.c | 19 ++++++++++---------
drivers/base/cpu.c | 4 ++--
drivers/base/memory.c | 2 +-
include/linux/device.h | 9 ++++-----
kernel/cpu.c | 4 ++--
8 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 32c2dbcc0c64..f6f7c35b7a93 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -4042,7 +4042,7 @@ static int enable_mismatched_32bit_el0(unsigned int cpu)
*/
lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
cpu_active_mask);
- get_cpu_device(lucky_winner)->offline_disabled = true;
+ set_bit(DEV_FLAG_OFFLINE_DISABLED, &get_cpu_device(lucky_winner)->flags);
setup_elf_hwcaps(compat_elf_hwcaps);
elf_hwcap_fixup();
pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index b2f14db59034..d9a0a75ada46 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -213,9 +213,9 @@ static int dlpar_change_lmb_state(struct drmem_lmb *lmb, bool online)
return -EINVAL;
}
- if (online && mem_block->dev.offline)
+ if (online && test_bit(DEV_FLAG_OFFLINE, &mem_block->dev.flags))
rc = device_online(&mem_block->dev);
- else if (!online && !mem_block->dev.offline)
+ else if (!online && !test_bit(DEV_FLAG_OFFLINE, &mem_block->dev.flags))
rc = device_offline(&mem_block->dev);
else
rc = 0;
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index e8cdbdb46fdb..f2707b704468 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -122,7 +122,8 @@ bool acpi_scan_is_offline(struct acpi_device *adev, bool uevent)
mutex_lock_nested(&adev->physical_node_lock, SINGLE_DEPTH_NESTING);
list_for_each_entry(pn, &adev->physical_node_list, node)
- if (device_supports_offline(pn->dev) && !pn->dev->offline) {
+ if (device_supports_offline(pn->dev) &&
+ !test_bit(DEV_FLAG_OFFLINE, &pn->dev->flags)) {
if (uevent)
kobject_uevent_env(&pn->dev->kobj, KOBJ_CHANGE, envp);
diff --git a/drivers/base/core.c b/drivers/base/core.c
index a87bd40499b6..63d724ece384 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -2789,7 +2789,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr,
bool val;
device_lock(dev);
- val = !dev->offline;
+ val = !test_bit(DEV_FLAG_OFFLINE, &dev->flags);
device_unlock(dev);
return sysfs_emit(buf, "%u\n", val);
}
@@ -2914,7 +2914,7 @@ static int device_add_attrs(struct device *dev)
if (error)
goto err_remove_type_groups;
- if (device_supports_offline(dev) && !dev->offline_disabled) {
+ if (device_supports_offline(dev) && !test_bit(DEV_FLAG_OFFLINE_DISABLED, &dev->flags)) {
error = device_create_file(dev, &dev_attr_online);
if (error)
goto err_remove_dev_groups;
@@ -4179,7 +4179,8 @@ static int device_check_offline(struct device *dev, void *not_used)
if (ret)
return ret;
- return device_supports_offline(dev) && !dev->offline ? -EBUSY : 0;
+ return device_supports_offline(dev) &&
+ !test_bit(DEV_FLAG_OFFLINE, &dev->flags) ? -EBUSY : 0;
}
/**
@@ -4197,7 +4198,7 @@ int device_offline(struct device *dev)
{
int ret;
- if (dev->offline_disabled)
+ if (test_bit(DEV_FLAG_OFFLINE_DISABLED, &dev->flags))
return -EPERM;
ret = device_for_each_child(dev, NULL, device_check_offline);
@@ -4206,13 +4207,13 @@ int device_offline(struct device *dev)
device_lock(dev);
if (device_supports_offline(dev)) {
- if (dev->offline) {
+ if (test_bit(DEV_FLAG_OFFLINE, &dev->flags)) {
ret = 1;
} else {
ret = dev->bus->offline(dev);
if (!ret) {
kobject_uevent(&dev->kobj, KOBJ_OFFLINE);
- dev->offline = true;
+ set_bit(DEV_FLAG_OFFLINE, &dev->flags);
}
}
}
@@ -4237,11 +4238,11 @@ int device_online(struct device *dev)
device_lock(dev);
if (device_supports_offline(dev)) {
- if (dev->offline) {
+ if (test_bit(DEV_FLAG_OFFLINE, &dev->flags)) {
ret = dev->bus->online(dev);
if (!ret) {
kobject_uevent(&dev->kobj, KOBJ_ONLINE);
- dev->offline = false;
+ clear_bit(DEV_FLAG_OFFLINE, &dev->flags);
}
} else {
ret = 1;
@@ -4715,7 +4716,7 @@ static int device_attrs_change_owner(struct device *dev, kuid_t kuid,
if (error)
return error;
- if (device_supports_offline(dev) && !dev->offline_disabled) {
+ if (device_supports_offline(dev) && !test_bit(DEV_FLAG_OFFLINE_DISABLED, &dev->flags)) {
/* Change online device attributes of @dev to @kuid/@kgid. */
error = sysfs_file_change_owner(kobj, dev_attr_online.attr.name,
kuid, kgid);
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 875abdc9942e..e4e6a399def4 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -422,8 +422,8 @@ int register_cpu(struct cpu *cpu, int num)
cpu->dev.id = num;
cpu->dev.bus = &cpu_subsys;
cpu->dev.release = cpu_device_release;
- cpu->dev.offline_disabled = !cpu->hotpluggable;
- cpu->dev.offline = !cpu_online(num);
+ assign_bit(DEV_FLAG_OFFLINE_DISABLED, &cpu->dev.flags, !cpu->hotpluggable);
+ assign_bit(DEV_FLAG_OFFLINE, &cpu->dev.flags, !cpu_online(num));
cpu->dev.of_node = of_get_cpu_node(num, NULL);
cpu->dev.groups = common_cpu_attr_groups;
if (cpu->hotpluggable)
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index a3091924918b..7f42727dde81 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -697,7 +697,7 @@ static int __add_memory_block(struct memory_block *memory)
memory->dev.id = memory->start_section_nr / sections_per_block;
memory->dev.release = memory_block_release;
memory->dev.groups = memory_memblk_attr_groups;
- memory->dev.offline = memory->state == MEM_OFFLINE;
+ assign_bit(DEV_FLAG_OFFLINE, &memory->dev.flags, memory->state == MEM_OFFLINE);
ret = device_register(&memory->dev);
if (ret) {
diff --git a/include/linux/device.h b/include/linux/device.h
index f6ca067bacca..fd53aa04cad9 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -484,6 +484,8 @@ struct device_physical_location {
* architecture supports non-coherent devices.
* @DEV_FLAG_OF_NODE_REUSED: Set if the device-tree node is shared with an
* ancestor device.
+ * @DEV_FLAG_OFFLINE_DISABLED: If set, the device is permanently online.
+ * @DEV_FLAG_OFFLINE: Set after successful invocation of bus type's .offline().
*/
enum struct_device_flags {
DEV_FLAG_READY_TO_PROBE,
@@ -494,6 +496,8 @@ enum struct_device_flags {
DEV_FLAG_STATE_SYNCED,
DEV_FLAG_DMA_COHERENT,
DEV_FLAG_OF_NODE_REUSED,
+ DEV_FLAG_OFFLINE_DISABLED,
+ DEV_FLAG_OFFLINE,
};
/**
@@ -571,8 +575,6 @@ enum struct_device_flags {
* should be set by the subsystem / bus driver that discovered
* the device.
*
- * @offline_disabled: If set, the device is permanently online.
- * @offline: Set after successful invocation of bus type's .offline().
* @flags: DEV_FLAG_XXX flags. Use atomic bitfield operations to modify.
*
* At the lowest level, every device in a Linux system is represented by an
@@ -677,9 +679,6 @@ struct device {
enum device_removable removable;
- bool offline_disabled:1;
- bool offline:1;
-
unsigned long flags;
};
diff --git a/kernel/cpu.c b/kernel/cpu.c
index bc4f7a9ba64e..15a873ad8025 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -2639,7 +2639,7 @@ static void cpuhp_offline_cpu_device(unsigned int cpu)
{
struct device *dev = get_cpu_device(cpu);
- dev->offline = true;
+ set_bit(DEV_FLAG_OFFLINE, &dev->flags);
/* Tell user space about the state change */
kobject_uevent(&dev->kobj, KOBJ_OFFLINE);
}
@@ -2648,7 +2648,7 @@ static void cpuhp_online_cpu_device(unsigned int cpu)
{
struct device *dev = get_cpu_device(cpu);
- dev->offline = false;
+ clear_bit(DEV_FLAG_OFFLINE, &dev->flags);
/* Tell user space about the state change */
kobject_uevent(&dev->kobj, KOBJ_ONLINE);
}
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply related
* [PATCH v3 8/9] driver core: Replace dev->of_node_reused with DEV_FLAG_OF_NODE_REUSED
From: Douglas Anderson @ 2026-04-03 0:49 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern
Cc: Robin Murphy, Leon Romanovsky, Paul Burton, Saravana Kannan,
Alexander Lobakin, Eric Dumazet, Toshi Kani, Christoph Hellwig,
Alexey Kardashevskiy, Johan Hovold, Douglas Anderson,
alexander.stein, andrew, andrew, andriy.shevchenko, astewart,
bhelgaas, brgl, broonie, davem, devicetree, driver-core,
hkallweit1, jirislaby, joel, kees, kuba, lgirdwood,
linux-arm-kernel, linux-aspeed, linux-kernel, linux-pci,
linux-serial, linux-usb, linux, mani, netdev, pabeni, robh
In-Reply-To: <20260403005005.30424-1-dianders@chromium.org>
In C, bitfields are not necessarily safe to modify from multiple
threads without locking. Switch "of_node_reused" over to the "flags"
field so modifications are safe.
Cc: Johan Hovold <johan@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Not fixing any known bugs; problem is theoretical and found by code
inspection. Change is done somewhat manually and only lightly tested
(mostly compile-time tested).
Changes in v3:
- New
drivers/base/core.c | 2 +-
drivers/base/pinctrl.c | 2 +-
drivers/base/platform.c | 2 +-
drivers/net/pcs/pcs-xpcs-plat.c | 2 +-
drivers/of/device.c | 6 +++---
drivers/pci/of.c | 2 +-
drivers/pci/pwrctrl/core.c | 2 +-
drivers/regulator/bq257xx-regulator.c | 2 +-
drivers/regulator/rk808-regulator.c | 2 +-
drivers/tty/serial/serial_base_bus.c | 2 +-
drivers/usb/gadget/udc/aspeed-vhub/dev.c | 2 +-
include/linux/device.h | 6 +++---
12 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 00005777c21f..a87bd40499b6 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -5282,7 +5282,7 @@ void device_set_of_node_from_dev(struct device *dev, const struct device *dev2)
{
of_node_put(dev->of_node);
dev->of_node = of_node_get(dev2->of_node);
- dev->of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags);
}
EXPORT_SYMBOL_GPL(device_set_of_node_from_dev);
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
index 6e250272c843..62c228c75d50 100644
--- a/drivers/base/pinctrl.c
+++ b/drivers/base/pinctrl.c
@@ -24,7 +24,7 @@ int pinctrl_bind_pins(struct device *dev)
{
int ret;
- if (dev->of_node_reused)
+ if (test_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags))
return 0;
dev->pins = devm_kzalloc(dev, sizeof(*(dev->pins)), GFP_KERNEL);
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index d44591d52e36..5128ff7e5e78 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -856,7 +856,7 @@ struct platform_device *platform_device_register_full(
pdev->dev.parent = pdevinfo->parent;
pdev->dev.fwnode = pdevinfo->fwnode;
pdev->dev.of_node = of_node_get(to_of_node(pdev->dev.fwnode));
- pdev->dev.of_node_reused = pdevinfo->of_node_reused;
+ assign_bit(DEV_FLAG_OF_NODE_REUSED, &pdev->dev.flags, pdevinfo->of_node_reused);
if (pdevinfo->dma_mask) {
pdev->platform_dma_mask = pdevinfo->dma_mask;
diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c
index b8c48f9effbf..c2722d8bd98a 100644
--- a/drivers/net/pcs/pcs-xpcs-plat.c
+++ b/drivers/net/pcs/pcs-xpcs-plat.c
@@ -349,7 +349,7 @@ static int xpcs_plat_init_dev(struct dw_xpcs_plat *pxpcs)
* up later. Make sure DD-core is aware of the OF-node being re-used.
*/
device_set_node(&mdiodev->dev, fwnode_handle_get(dev_fwnode(dev)));
- mdiodev->dev.of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &mdiodev->dev.flags);
/* Pass the data further so the DW XPCS driver core could use it */
mdiodev->dev.platform_data = (void *)device_get_match_data(dev);
diff --git a/drivers/of/device.c b/drivers/of/device.c
index f7e75e527667..fd77295a8c0f 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -26,7 +26,7 @@
const struct of_device_id *of_match_device(const struct of_device_id *matches,
const struct device *dev)
{
- if (!matches || !dev->of_node || dev->of_node_reused)
+ if (!matches || !dev->of_node || test_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags))
return NULL;
return of_match_node(matches, dev->of_node);
}
@@ -192,7 +192,7 @@ ssize_t of_device_modalias(struct device *dev, char *str, ssize_t len)
{
ssize_t sl;
- if (!dev || !dev->of_node || dev->of_node_reused)
+ if (!dev || !dev->of_node || test_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags))
return -ENODEV;
sl = of_modalias(dev->of_node, str, len - 2);
@@ -254,7 +254,7 @@ int of_device_uevent_modalias(const struct device *dev, struct kobj_uevent_env *
{
int sl;
- if ((!dev) || (!dev->of_node) || dev->of_node_reused)
+ if ((!dev) || (!dev->of_node) || test_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags))
return -ENODEV;
/* Devicetree modalias is tricky, we add it in 2 steps */
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 9f8eb5df279e..197b60c5a660 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -38,7 +38,7 @@ int pci_set_of_node(struct pci_dev *dev)
struct device *pdev __free(put_device) =
bus_find_device_by_of_node(&platform_bus_type, node);
if (pdev)
- dev->bus->dev.of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &dev->bus->dev.flags);
device_set_node(&dev->dev, of_fwnode_handle(no_free_ptr(node)));
return 0;
diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c
index 7754baed67f2..cfbe9b615b88 100644
--- a/drivers/pci/pwrctrl/core.c
+++ b/drivers/pci/pwrctrl/core.c
@@ -39,7 +39,7 @@ static int pci_pwrctrl_notify(struct notifier_block *nb, unsigned long action,
* If we got here then the PCI device is the second after the
* power control platform device. Mark its OF node as reused.
*/
- dev->of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags);
break;
}
diff --git a/drivers/regulator/bq257xx-regulator.c b/drivers/regulator/bq257xx-regulator.c
index dab8f1ab4450..01d3139e1d87 100644
--- a/drivers/regulator/bq257xx-regulator.c
+++ b/drivers/regulator/bq257xx-regulator.c
@@ -143,7 +143,7 @@ static int bq257xx_regulator_probe(struct platform_device *pdev)
struct regulator_config cfg = {};
pdev->dev.of_node = pdev->dev.parent->of_node;
- pdev->dev.of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &pdev->dev.flags);
pdata = devm_kzalloc(&pdev->dev, sizeof(struct bq257xx_reg_data), GFP_KERNEL);
if (!pdata)
diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
index e66408f23bb6..375ea7861134 100644
--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
@@ -2115,7 +2115,7 @@ static int rk808_regulator_probe(struct platform_device *pdev)
int ret, i, nregulators;
pdev->dev.of_node = pdev->dev.parent->of_node;
- pdev->dev.of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &pdev->dev.flags);
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap)
diff --git a/drivers/tty/serial/serial_base_bus.c b/drivers/tty/serial/serial_base_bus.c
index a12935f6b992..86c6003bbebb 100644
--- a/drivers/tty/serial/serial_base_bus.c
+++ b/drivers/tty/serial/serial_base_bus.c
@@ -74,7 +74,7 @@ static int serial_base_device_init(struct uart_port *port,
dev->parent = parent_dev;
dev->bus = &serial_base_bus_type;
dev->release = release;
- dev->of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &dev->flags);
device_set_node(dev, fwnode_handle_get(dev_fwnode(parent_dev)));
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/dev.c b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
index 2ecd049dacc2..57048e3aa6bb 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/dev.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
@@ -593,7 +593,7 @@ int ast_vhub_init_dev(struct ast_vhub *vhub, unsigned int idx)
d->gadget.max_speed = USB_SPEED_HIGH;
d->gadget.speed = USB_SPEED_UNKNOWN;
d->gadget.dev.of_node = vhub->pdev->dev.of_node;
- d->gadget.dev.of_node_reused = true;
+ set_bit(DEV_FLAG_OF_NODE_REUSED, &d->gadget.dev.flags);
rc = usb_add_gadget_udc(d->port_dev, &d->gadget);
if (rc != 0)
diff --git a/include/linux/device.h b/include/linux/device.h
index c2a6dba7a036..f6ca067bacca 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -482,6 +482,8 @@ struct device_physical_location {
* driver/bus sync_state() callback.
* @DEV_FLAG_DMA_COHERENT: This particular device is dma coherent, even if the
* architecture supports non-coherent devices.
+ * @DEV_FLAG_OF_NODE_REUSED: Set if the device-tree node is shared with an
+ * ancestor device.
*/
enum struct_device_flags {
DEV_FLAG_READY_TO_PROBE,
@@ -491,6 +493,7 @@ enum struct_device_flags {
DEV_FLAG_DMA_OPS_BYPASS,
DEV_FLAG_STATE_SYNCED,
DEV_FLAG_DMA_COHERENT,
+ DEV_FLAG_OF_NODE_REUSED,
};
/**
@@ -570,8 +573,6 @@ enum struct_device_flags {
*
* @offline_disabled: If set, the device is permanently online.
* @offline: Set after successful invocation of bus type's .offline().
- * @of_node_reused: Set if the device-tree node is shared with an ancestor
- * device.
* @flags: DEV_FLAG_XXX flags. Use atomic bitfield operations to modify.
*
* At the lowest level, every device in a Linux system is represented by an
@@ -678,7 +679,6 @@ struct device {
bool offline_disabled:1;
bool offline:1;
- bool of_node_reused:1;
unsigned long flags;
};
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply related
* [PATCH v3 7/9] driver core: Replace dev->dma_coherent with DEV_FLAG_DMA_COHERENT
From: Douglas Anderson @ 2026-04-03 0:49 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rafael J . Wysocki, Danilo Krummrich,
Alan Stern
Cc: Robin Murphy, Leon Romanovsky, Paul Burton, Saravana Kannan,
Alexander Lobakin, Eric Dumazet, Toshi Kani, Christoph Hellwig,
Alexey Kardashevskiy, Johan Hovold, Douglas Anderson, Frank.Li,
alex, andre.przywara, andrew, aou, catalin.marinas, dmaengine,
driver-core, gregory.clement, iommu, jgg, kees, linux-arm-kernel,
linux-kernel, linux-mips, linux-riscv, linux-snps-arc, linux,
m.szyprowski, palmer, peter.ujfalusi, pjw, sebastian.hesselbarth,
tsbogend, vgupta, vkoul, will, willy
In-Reply-To: <20260403005005.30424-1-dianders@chromium.org>
In C, bitfields are not necessarily safe to modify from multiple
threads without locking. Switch "dma_coherent" over to the "flags"
field so modifications are safe.
Cc: Christoph Hellwig <hch@lst.de>
Cc: Paul Burton <paul.burton@mips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Not fixing any known bugs; problem is theoretical and found by code
inspection. Change is done somewhat manually and only lightly tested
(mostly compile-time tested).
NOTE: even though previously we only took up a bit if
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE, CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU,
or CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL, in this change I reserve the
bit unconditionally. While we could get the "dynamic" behavior by
changing the flags definition to be an "enum", it doesn't seem worth
it at this point.
Changes in v3:
- New
arch/arc/mm/dma.c | 4 ++--
arch/arm/mach-highbank/highbank.c | 2 +-
arch/arm/mach-mvebu/coherency.c | 2 +-
arch/arm/mm/dma-mapping-nommu.c | 4 ++--
arch/arm/mm/dma-mapping.c | 30 ++++++++++++++++--------------
arch/arm64/mm/dma-mapping.c | 2 +-
arch/mips/mm/dma-noncoherent.c | 2 +-
arch/riscv/mm/dma-noncoherent.c | 2 +-
drivers/base/core.c | 2 +-
drivers/dma/ti/k3-udma-glue.c | 6 +++---
drivers/dma/ti/k3-udma.c | 6 +++---
include/linux/device.h | 10 +++-------
include/linux/dma-map-ops.h | 2 +-
13 files changed, 36 insertions(+), 38 deletions(-)
diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 6b85e94f3275..3d56878cb6a2 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -98,8 +98,8 @@ void arch_setup_dma_ops(struct device *dev, bool coherent)
* DMA buffers.
*/
if (is_isa_arcv2() && ioc_enable && coherent)
- dev->dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &dev->flags);
dev_info(dev, "use %scoherent DMA ops\n",
- dev->dma_coherent ? "" : "non");
+ test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) ? "" : "non");
}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 47335c7dadf8..ffa3f591f57a 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -98,7 +98,7 @@ static int highbank_platform_notifier(struct notifier_block *nb,
if (of_property_read_bool(dev->of_node, "dma-coherent")) {
val = readl(sregs_base + reg);
writel(val | 0xff01, sregs_base + reg);
- dev->dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &dev->flags);
}
return NOTIFY_OK;
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index fa2c1e1aeb96..8391303a6a17 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -95,7 +95,7 @@ static int mvebu_hwcc_notifier(struct notifier_block *nb,
if (event != BUS_NOTIFY_ADD_DEVICE)
return NOTIFY_DONE;
- dev->dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &dev->flags);
return NOTIFY_OK;
}
diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
index fecac107fd0d..ac0a976e30a0 100644
--- a/arch/arm/mm/dma-mapping-nommu.c
+++ b/arch/arm/mm/dma-mapping-nommu.c
@@ -42,11 +42,11 @@ void arch_setup_dma_ops(struct device *dev, bool coherent)
* enough to check if MPU is in use or not since in absence of
* MPU system memory map is used.
*/
- dev->dma_coherent = cacheid ? coherent : true;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, cacheid ? coherent : true);
} else {
/*
* Assume coherent DMA in case MMU/MPU has not been set up.
*/
- dev->dma_coherent = (get_cr() & CR_M) ? coherent : true;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, (get_cr() & CR_M) ? coherent : true);
}
}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index f304037d1c34..9c2c635d7ac0 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1076,7 +1076,7 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
struct page **pages;
void *addr = NULL;
- int coherent_flag = dev->dma_coherent ? COHERENT : NORMAL;
+ int coherent_flag = test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) ? COHERENT : NORMAL;
*handle = DMA_MAPPING_ERROR;
size = PAGE_ALIGN(size);
@@ -1124,7 +1124,7 @@ static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
if (vma->vm_pgoff >= nr_pages)
return -ENXIO;
- if (!dev->dma_coherent)
+ if (!test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags))
vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
err = vm_map_pages(vma, pages, nr_pages);
@@ -1141,7 +1141,7 @@ static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
static void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
dma_addr_t handle, unsigned long attrs)
{
- int coherent_flag = dev->dma_coherent ? COHERENT : NORMAL;
+ int coherent_flag = test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) ? COHERENT : NORMAL;
struct page **pages;
size = PAGE_ALIGN(size);
@@ -1202,7 +1202,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
phys_addr_t phys = page_to_phys(sg_page(s));
unsigned int len = PAGE_ALIGN(s->offset + s->length);
- if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+ if (!test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) &&
+ !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
arch_sync_dma_for_device(sg_phys(s), s->length, dir);
prot = __dma_info_to_prot(dir, attrs);
@@ -1304,7 +1305,8 @@ static void arm_iommu_unmap_sg(struct device *dev,
if (sg_dma_len(s))
__iommu_remove_mapping(dev, sg_dma_address(s),
sg_dma_len(s));
- if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+ if (!test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) &&
+ !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
arch_sync_dma_for_cpu(sg_phys(s), s->length, dir);
}
}
@@ -1323,7 +1325,7 @@ static void arm_iommu_sync_sg_for_cpu(struct device *dev,
struct scatterlist *s;
int i;
- if (dev->dma_coherent)
+ if (test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags))
return;
for_each_sg(sg, s, nents, i)
@@ -1345,7 +1347,7 @@ static void arm_iommu_sync_sg_for_device(struct device *dev,
struct scatterlist *s;
int i;
- if (dev->dma_coherent)
+ if (test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags))
return;
for_each_sg(sg, s, nents, i)
@@ -1371,7 +1373,7 @@ static dma_addr_t arm_iommu_map_phys(struct device *dev, phys_addr_t phys,
dma_addr_t dma_addr;
int ret, prot;
- if (!dev->dma_coherent &&
+ if (!test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) &&
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
arch_sync_dma_for_device(phys, size, dir);
@@ -1412,7 +1414,7 @@ static void arm_iommu_unmap_phys(struct device *dev, dma_addr_t handle,
if (!iova)
return;
- if (!dev->dma_coherent &&
+ if (!test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) &&
!(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO))) {
phys_addr_t phys = iommu_iova_to_phys(mapping->domain, iova);
@@ -1431,7 +1433,7 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
unsigned int offset = handle & ~PAGE_MASK;
phys_addr_t phys;
- if (dev->dma_coherent || !iova)
+ if (test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) || !iova)
return;
phys = iommu_iova_to_phys(mapping->domain, iova);
@@ -1446,7 +1448,7 @@ static void arm_iommu_sync_single_for_device(struct device *dev,
unsigned int offset = handle & ~PAGE_MASK;
phys_addr_t phys;
- if (dev->dma_coherent || !iova)
+ if (test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags) || !iova)
return;
phys = iommu_iova_to_phys(mapping->domain, iova);
@@ -1701,13 +1703,13 @@ static void arm_teardown_iommu_dma_ops(struct device *dev) { }
void arch_setup_dma_ops(struct device *dev, bool coherent)
{
/*
- * Due to legacy code that sets the ->dma_coherent flag from a bus
- * notifier we can't just assign coherent to the ->dma_coherent flag
+ * Due to legacy code that sets DEV_FLAG_DMA_COHERENT from a bus
+ * notifier we can't just assign coherent to DEV_FLAG_DMA_COHERENT
* here, but instead have to make sure we only set but never clear it
* for now.
*/
if (coherent)
- dev->dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &dev->flags);
/*
* Don't override the dma_ops if they have already been set. Ideally
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index b2b5792b2caa..256c7631aff5 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -48,7 +48,7 @@ void arch_setup_dma_ops(struct device *dev, bool coherent)
dev_driver_string(dev), dev_name(dev),
ARCH_DMA_MINALIGN, cls);
- dev->dma_coherent = coherent;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, coherent);
xen_setup_dma_ops(dev);
}
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index ab4f2a75a7d0..496bf5f4999c 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -139,6 +139,6 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
void arch_setup_dma_ops(struct device *dev, bool coherent)
{
- dev->dma_coherent = coherent;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, coherent);
}
#endif
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index cb89d7e0ba88..3b793a1cc607 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -140,7 +140,7 @@ void arch_setup_dma_ops(struct device *dev, bool coherent)
"%s %s: device non-coherent but no non-coherent operations supported",
dev_driver_string(dev), dev_name(dev));
- dev->dma_coherent = coherent;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, coherent);
}
void riscv_noncoherent_supported(void)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 8dbb7a9c7aab..00005777c21f 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -3174,7 +3174,7 @@ void device_initialize(struct device *dev)
#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
- dev->dma_coherent = dma_default_coherent;
+ assign_bit(DEV_FLAG_DMA_COHERENT, &dev->flags, dma_default_coherent);
#endif
swiotlb_dev_init(dev);
}
diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
index f87d244cc2d6..cda8f4a8f440 100644
--- a/drivers/dma/ti/k3-udma-glue.c
+++ b/drivers/dma/ti/k3-udma-glue.c
@@ -312,7 +312,7 @@ k3_udma_glue_request_tx_chn_common(struct device *dev,
if (xudma_is_pktdma(tx_chn->common.udmax)) {
/* prepare the channel device as coherent */
- tx_chn->common.chan_dev.dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &tx_chn->common.chan_dev.flags);
dma_coerce_mask_and_coherent(&tx_chn->common.chan_dev,
DMA_BIT_MASK(48));
}
@@ -1003,7 +1003,7 @@ k3_udma_glue_request_rx_chn_priv(struct device *dev, const char *name,
if (xudma_is_pktdma(rx_chn->common.udmax)) {
/* prepare the channel device as coherent */
- rx_chn->common.chan_dev.dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &rx_chn->common.chan_dev.flags);
dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev,
DMA_BIT_MASK(48));
}
@@ -1104,7 +1104,7 @@ k3_udma_glue_request_remote_rx_chn_common(struct k3_udma_glue_rx_channel *rx_chn
if (xudma_is_pktdma(rx_chn->common.udmax)) {
/* prepare the channel device as coherent */
- rx_chn->common.chan_dev.dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &rx_chn->common.chan_dev.flags);
dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev,
DMA_BIT_MASK(48));
rx_chn->single_fdq = false;
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index c964ebfcf3b6..770aae467fc5 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -428,18 +428,18 @@ static void k3_configure_chan_coherency(struct dma_chan *chan, u32 asel)
/* No special handling for the channel */
chan->dev->chan_dma_dev = false;
- chan_dev->dma_coherent = false;
+ clear_bit(DEV_FLAG_DMA_COHERENT, &chan_dev->flags);
chan_dev->dma_parms = NULL;
} else if (asel == 14 || asel == 15) {
chan->dev->chan_dma_dev = true;
- chan_dev->dma_coherent = true;
+ set_bit(DEV_FLAG_DMA_COHERENT, &chan_dev->flags);
dma_coerce_mask_and_coherent(chan_dev, DMA_BIT_MASK(48));
chan_dev->dma_parms = chan_dev->parent->dma_parms;
} else {
dev_warn(chan->device->dev, "Invalid ASEL value: %u\n", asel);
- chan_dev->dma_coherent = false;
+ clear_bit(DEV_FLAG_DMA_COHERENT, &chan_dev->flags);
chan_dev->dma_parms = NULL;
}
}
diff --git a/include/linux/device.h b/include/linux/device.h
index 6c961dac9fdb..c2a6dba7a036 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -480,6 +480,8 @@ struct device_physical_location {
* @DEV_FLAG_STATE_SYNCED: The hardware state of this device has been synced to
* match the software state of this device by calling the
* driver/bus sync_state() callback.
+ * @DEV_FLAG_DMA_COHERENT: This particular device is dma coherent, even if the
+ * architecture supports non-coherent devices.
*/
enum struct_device_flags {
DEV_FLAG_READY_TO_PROBE,
@@ -488,6 +490,7 @@ enum struct_device_flags {
DEV_FLAG_DMA_SKIP_SYNC,
DEV_FLAG_DMA_OPS_BYPASS,
DEV_FLAG_STATE_SYNCED,
+ DEV_FLAG_DMA_COHERENT,
};
/**
@@ -569,8 +572,6 @@ enum struct_device_flags {
* @offline: Set after successful invocation of bus type's .offline().
* @of_node_reused: Set if the device-tree node is shared with an ancestor
* device.
- * @dma_coherent: this particular device is dma coherent, even if the
- * architecture supports non-coherent devices.
* @flags: DEV_FLAG_XXX flags. Use atomic bitfield operations to modify.
*
* At the lowest level, every device in a Linux system is represented by an
@@ -678,11 +679,6 @@ struct device {
bool offline_disabled:1;
bool offline:1;
bool of_node_reused:1;
-#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
- defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
- defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
- bool dma_coherent:1;
-#endif
unsigned long flags;
};
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index 4d9d1fe3277c..91d34678657c 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -230,7 +230,7 @@ int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
extern bool dma_default_coherent;
static inline bool dev_is_dma_coherent(struct device *dev)
{
- return dev->dma_coherent;
+ return test_bit(DEV_FLAG_DMA_COHERENT, &dev->flags);
}
#else
#define dma_default_coherent true
--
2.53.0.1213.gd9a14994de-goog
^ permalink raw reply related
* Re: [PATCH net v4 0/2] stmmac crash/stall fixes when under memory pressure
From: Jakub Kicinski @ 2026-04-03 0:40 UTC (permalink / raw)
To: Sam Edwards
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Paolo Abeni,
Maxime Coquelin, Alexandre Torgue, Russell King (Oracle),
Maxime Chevallier, Ovidiu Panait, Vladimir Oltean, Baruch Siach,
Serge Semin, Giuseppe Cavallaro, netdev, linux-stm32,
linux-arm-kernel, linux-kernel
In-Reply-To: <CAH5Ym4j5peYXc5c9ycJzimy26Tv+4x18hyy+j-H4v7PyWuWhtA@mail.gmail.com>
On Thu, 2 Apr 2026 09:53:43 -0700 Sam Edwards wrote:
> On Thu, Apr 2, 2026 at 8:05 AM Jakub Kicinski <kuba@kernel.org> wrote:
> > I meant we need both a threshold, and a delay :(
>
> Hi Jakub - got it: when the critical threshold is reached, allow the
> NAPI instance to sleep and start a timer instead.
>
> 1) We'd either have to leave interrupts masked or let them race
> against the timer. Either one is manageable, but I feel like those
> interactions carry *just* enough regression risk to bump that patch to
> -next.
>
> 2) Could you point out which NAPI driver best handles this situation?
> I'd like to replicate its approach.
Not sure, the last few NICs I worked on had the ability for SW
to trigger IRQs exactly because of the Rx buffer depletion issue.
fbnic_napi_depletion_check() for example.
But let's not overthink it.. say we arm a timer and let the IRQ
be unmasked. The timer just runs napi_schedule(). napi_schedule()
is thread-safe, if IRQ fires with the timer armed - no problem.
^ permalink raw reply
* Re: [PATCH 0/5] crc64: Tweak intrinsics code and enable it for ARM
From: Eric Biggers @ 2026-04-02 23:40 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: linux-crypto, linux-arm-kernel, Demian Shulhan
In-Reply-To: <dc424b4a-11b5-475f-a53a-987b5813bac5@app.fastmail.com>
On Thu, Apr 02, 2026 at 10:52:17AM +0200, Ard Biesheuvel wrote:
>
> On Wed, 1 Apr 2026, at 21:59, Eric Biggers wrote:
> > On Mon, Mar 30, 2026 at 04:46:31PM +0200, Ard Biesheuvel wrote:
> >> Apply some tweaks to the new arm64 crc64 NEON intrinsics code, and wire
> >> it up for the 32-bit ARM build. Note that true 32-bit ARM CPUs usually
> >> don't implement the prerequisite 64x64 PMULL instructions, but 32-bit
> >> kernels are commonly used on 64-bit capable hardware too, which do
> >> implement the 32-bit versions of the crypto instructions if they are
> >> implemented for the 64-bit ISA (as per the architecture).
> >>
> >> Cc: Demian Shulhan <demyansh@gmail.com>
> >> Cc: Eric Biggers <ebiggers@kernel.org>
> >>
> >> Ard Biesheuvel (5):
> >> lib/crc: arm64: Drop unnecessary chunking logic from crc64
> >> lib/crc: arm64: Use existing macros for kernel-mode FPU cflags
> >> ARM: Add a neon-intrinsics.h header like on arm64
> >> lib/crc: arm64: Simplify intrinsics implementation
> >> lib/crc: arm: Enable arm64's NEON intrinsics implementation of crc64
> >
> > I think patches 3 and 4 should be swapped, so it's cleanups first (which
> > make sense regardless of the 32-bit ARM support) and then the 32-bit ARM
> > support.
> >
>
> Ok.
I can also apply patches 1-2 and 4 now if you want. Let me know if I
should do that or if a new version is coming.
- Eric
^ permalink raw reply
* RE: [PATCH v6 00/40] arm_mpam: Add KVM/arm64 and resctrl glue code
From: Rose, Charles @ 2026-04-02 23:38 UTC (permalink / raw)
To: Ben Horgan
Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com,
baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com,
dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com,
fenghuay@nvidia.com, gshan@redhat.com, james.morse@arm.com,
jonathan.cameron@huawei.com, kobak@nvidia.com,
lcherian@marvell.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, peternewman@google.com,
punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com,
reinette.chatre@intel.com, rohit.mathew@arm.com,
scott@os.amperecomputing.com, sdonthineni@nvidia.com,
tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com,
catalin.marinas@arm.com, will@kernel.org, corbet@lwn.net,
maz@kernel.org, oupton@kernel.org, joey.gouly@arm.com,
suzuki.poulose@arm.com, kvmarm@lists.linux.dev,
zengheng4@huawei.com, linux-doc@vger.kernel.org
In-Reply-To: <20260313144617.3420416-1-ben.horgan@arm.com>
Hi Ben,
> This version of the mpam missing pieces series sees a couple of things
> dropped or hidden. Memory bandwith utilization with free-running counters
> is dropped in preference of just always using 'mbm_event' mode (ABMC
> emulation) which simplifies the code and allows for, in the future,
> filtering by read/write traffic. So, for the interim, there is no memory
> bandwidth utilization support. CDP is hidden behind config expert as
> remount of resctrl fs could potentially lead to out of range PARTIDs being
> used and the fix requires a change in fs/resctrl. The setting of MPAM2_EL2
> (for pkvm/nvhe) is dropped as too expensive a write for not much value.
>
> There are a couple of 'fixes' at the start of the series which address
> problems in the base driver but are only user visible due to this series.
>
I tested cache occupancy and memory bandwidth allocation on a Dell PowerEdge XE8712 with NVIDIA Grace A02P. Both seem to work as expected.
For the series:
Tested-by: Charles Rose <charles.rose@dell.com>
Thanks,
Charles
Internal Use - Confidential
^ permalink raw reply
* Re: [PATCH] lib/crc: arm64: Assume a little-endian kernel
From: Eric Biggers @ 2026-04-02 23:14 UTC (permalink / raw)
To: linux-kernel; +Cc: linux-crypto, Ard Biesheuvel, linux-arm-kernel
In-Reply-To: <20260401004431.151432-1-ebiggers@kernel.org>
On Tue, Mar 31, 2026 at 05:44:31PM -0700, Eric Biggers wrote:
> Since support for big-endian arm64 kernels was removed, the CPU_LE()
> macro now unconditionally emits the code it is passed, and the CPU_BE()
> macro now unconditionally discards the code it is passed.
>
> Simplify the assembly code in lib/crc/arm64/ accordingly.
>
> Signed-off-by: Eric Biggers <ebiggers@kernel.org>
> ---
>
> This patch is targeting crc-next
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git/log/?h=crc-next
- Eric
^ permalink raw reply
* Re: [PATCH] lib/crypto: arm64: Assume a little-endian kernel
From: Eric Biggers @ 2026-04-02 23:12 UTC (permalink / raw)
To: linux-crypto
Cc: linux-kernel, Ard Biesheuvel, Jason A . Donenfeld, Herbert Xu,
linux-arm-kernel
In-Reply-To: <20260401003331.144065-1-ebiggers@kernel.org>
On Tue, Mar 31, 2026 at 05:33:31PM -0700, Eric Biggers wrote:
> Since support for big-endian arm64 kernels was removed, the CPU_LE()
> macro now unconditionally emits the code it is passed, and the CPU_BE()
> macro now unconditionally discards the code it is passed.
>
> Simplify the assembly code in lib/crypto/arm64/ accordingly.
>
> Signed-off-by: Eric Biggers <ebiggers@kernel.org>
> ---
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git/log/?h=libcrypto-next
- Eric
^ permalink raw reply
* Re: [PATCH 0/9] lib/crypto: arm64: Remove obsolete chunking logic
From: Eric Biggers @ 2026-04-02 23:12 UTC (permalink / raw)
To: linux-crypto
Cc: linux-kernel, Ard Biesheuvel, Jason A . Donenfeld, Herbert Xu,
linux-arm-kernel
In-Reply-To: <20260401000548.133151-1-ebiggers@kernel.org>
On Tue, Mar 31, 2026 at 05:05:39PM -0700, Eric Biggers wrote:
> Since commit aefbab8e77eb ("arm64: fpsimd: Preserve/restore kernel mode
> NEON at context switch"), kernel-mode NEON sections have been
> preemptible on arm64. And since commit 7dadeaa6e851 ("sched: Further
> restrict the preemption modes"), voluntary preemption is no longer
> supported on arm64 either. Therefore, there's no longer any need to
> limit the length of kernel-mode NEON sections on arm64.
>
> This series simplifies the code in lib/crypto/arm64/ accordingly by
> using longer kernel-mode NEON sections instead of multiple shorter ones.
>
> This series is targeting libcrypto-next.
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git/log/?h=libcrypto-next
- Eric
^ permalink raw reply
* Re: (subset) [PATCH v3 0/2] dt-bindings: power: reset: cortina: Convert to DT schema and rename node
From: Sebastian Reichel @ 2026-04-02 22:54 UTC (permalink / raw)
To: sre, robh, krzk+dt, conor+dt, ulli.kroll, linusw,
Khushal Chitturi
Cc: daniel.baluta, simona.toaca, d-gole, m-chawdhry, linux-pm,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260330110135.10316-1-khushalchitturi@gmail.com>
On Mon, 30 Mar 2026 16:31:33 +0530, Khushal Chitturi wrote:
> Convert the Cortina Systems Gemini Poweroff Controller bindings to
> DT schema and update corresponding dtsi file with new node name
>
Applied, thanks!
[1/2] dt-bindings: power: reset: cortina,gemini-power-controller: convert to DT schema
commit: 64a97c98f93e344be00d4ff10fef4119973938bd
Best regards,
--
Sebastian Reichel <sebastian.reichel@collabora.com>
^ permalink raw reply
* Re: (subset) [PATCH v2 0/9] gpio: remove uneeded Kconfig dependencies on OF_GPIO
From: Sebastian Reichel @ 2026-04-02 22:54 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Linus Walleij, Lee Jones, Pavel Machek,
Wim Van Sebroeck, Guenter Roeck, Mauro Carvalho Chehab,
Greg Kroah-Hartman, Sebastian Reichel, Bartosz Golaszewski
Cc: brgl, linux-arm-kernel, linux-kernel, netdev, linux-gpio,
linux-leds, linux-watchdog, linux-media, linux-staging, linux-pm
In-Reply-To: <20260316-gpio-of-kconfig-v2-0-de2f4b00a0e4@oss.qualcomm.com>
On Mon, 16 Mar 2026 10:45:20 +0100, Bartosz Golaszewski wrote:
> NOTE: Each patch in this series can be picked up independently into
> maintainer trees.
>
> CONFIG_OF_GPIO is a switch that enables the compilation of the gpiolib-of
> module. The module itself handles GPIO lookup via the OF-node tree and
> is automatically enabled on all OF systems. It does not export any
> public symbols to drivers. There is no reason for them to select or
> depend on it in Kconfig.
>
> [...]
Applied, thanks!
[8/9] power: reset: drop unneeded dependencies on OF_GPIO
commit: 0629c33fe1873a48e1e06078409de76c5a159fdb
Best regards,
--
Sebastian Reichel <sebastian.reichel@collabora.com>
^ permalink raw reply
* Re: [PATCH] iommu: Always fill in gather when unmapping
From: Jason Gunthorpe @ 2026-04-02 22:51 UTC (permalink / raw)
To: Robin Murphy
Cc: Alexandre Ghiti, AngeloGioacchino Del Regno, Albert Ou, asahi,
Baolin Wang, iommu, Janne Grunau, Jernej Skrabec, Joerg Roedel,
Jean-Philippe Brucker, linux-arm-kernel, linux-mediatek,
linux-riscv, linux-sunxi, Matthias Brugger, Neal Gompa,
Orson Zhai, Palmer Dabbelt, Paul Walmsley, Samuel Holland,
Sven Peter, virtualization, Chen-Yu Tsai, Will Deacon, Yong Wu,
Chunyan Zhang, Lu Baolu, Janusz Krzysztofik, Joerg Roedel,
Jon Hunter, patches, Samiullah Khawaja, stable, Vasant Hegde
In-Reply-To: <ec51ef14-e360-43a6-ae62-44a939ec8027@arm.com>
On Thu, Apr 02, 2026 at 07:11:13PM +0100, Robin Murphy wrote:
> > > @@ -2714,6 +2714,10 @@ static size_t __iommu_unmap(struct iommu_domain *domain,
> > > pr_debug("unmapped: iova 0x%lx size 0x%zx\n",
> > > iova, unmapped_page);
> > > + /* If the driver itself isn't using the gather, mark it used */
> > > + if (iotlb_gather->end <= iotlb_gather->start)
> > > + iommu_iotlb_gather_add_range(&iotlb_gather, iova, unmapped_page);
> >
> > The gathers can be joined across unmaps and now we are inviting subtly
> > ill-formed gathers as only the first unmap will get included.
> > We do have error cases where the gather is legitimately empty, and
> > this would squash that, it probably needs to check unmapped_page for 0
> > too, at least.
>
> Maybe try looking at the rest of the code around these lines...
Okay, well lets do this one, do you want to send it since it is your
idea?
Jason
^ permalink raw reply
* Re: [GIT PULL 1/2] arm64: dts: ti: K3 updates for v7.1
From: Arnd Bergmann @ 2026-04-02 22:00 UTC (permalink / raw)
To: Vignesh Raghavendra, SoC, arm
Cc: SoC list, linux-arm-kernel, linux-kernel, Tero Kristo,
Nishanth Menon
In-Reply-To: <e724f95d-09d0-4ede-9ed4-0ce782d81058@ti.com>
On Wed, Apr 1, 2026, at 19:14, Vignesh Raghavendra wrote:
Hi Vignesh,
I've merged this now, but I see that there are a number of
patches that look like they should have been part of an
earlier pull request for 7.0 and possibly backports:
> Generic Fixes/Cleanups:
> - ti,min-output-impedance addition to all K3 board DT files
>
> AM69 Aquila:
> - Fix DP regulator enable GPIO
>
> AM62A7-SK:
> - Fix pin name in comment from M19 to N22
>
> AM62L3 EVM:
> - Disable MMC1 internal pulls on data pins
>
> AM62P:
> - SK: Disable MMC1 internal pulls on data pins and enable Main UART
Can you have a look to see if my intuition is right on these
ones, and make sure they get merged more quickly in the future?
Arnd
^ permalink raw reply
* Re: [GIT PULL] ARM: dts: updates for ti/omap for v7.1
From: Arnd Bergmann @ 2026-04-02 21:48 UTC (permalink / raw)
To: Kevin Hilman, soc; +Cc: Linux-OMAP, linux-arm-kernel
In-Reply-To: <7hqzoytlms.fsf@baylibre.com>
On Wed, Apr 1, 2026, at 23:29, Kevin Hilman wrote:
>
> ----------------------------------------------------------------
> ARM: dts: updates for ti/omap for v7.1
>
Hi Kevin,
I applied this one, but I noticed two problems:
There is no long form changelog text, please add
more information about what is in the branch in
the future. I've added a short paragraph while
applying.
> +-
> arch/arm/boot/dts/ti/omap/omap4-samsung-espresso-common.dtsi | 744
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/ti/omap/omap4-samsung-espresso10.dts | 101
> +++++++++++++++++++++
> arch/arm/boot/dts/ti/omap/omap4-samsung-espresso7.dts | 70
> +++++++++++++++
> arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2
Something went wrong with the overly long lines here.
Arnd
^ permalink raw reply
* [PATCH net-next v9 1/4] net: stmmac: Add DW25GMAC support in stmmac core driver
From: Jitendra Vegiraju @ 2026-04-02 21:36 UTC (permalink / raw)
To: netdev
Cc: alexandre.torgue, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
jitendra.vegiraju, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rmk+kernel, rohan.g.thomas,
linux-kernel, linux-stm32, linux-arm-kernel, bpf, andrew+netdev,
horms, sdf, me, siyanteng, prabhakar.mahadev-lad.rj, weishangjuan,
wens, vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha
In-Reply-To: <20260402213629.1996133-1-jitendra.vegiraju@broadcom.com>
From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for
virtualization scalability. This is realized by decoupling physical DMA
channels(PDMA) from potentially large number of virtual DMA channels(VDMA).
The VDMAs provide software abstraction to driver that map to PDMAs for
frame transmission and reception.
Since 25GMAC is a derivative of XGMAC, majority of IP is common to both.
To add support for the HDMA in 25GMAC, a new instance of dma_ops,
dw25gmac400_dma_ops is introduced.
To support the current needs, a simple one-to-one mapping of dw25gmac's
logical VDMA (channel) to TC to PDMAs is used. Most of the other dma
operation functions in existing dwxgamc2_dma.c file are reused whereever
applicable.
Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 12 +-
.../net/ethernet/stmicro/stmmac/dw25gmac.c | 161 ++++++++++++++++++
.../net/ethernet/stmicro/stmmac/dw25gmac.h | 92 ++++++++++
.../net/ethernet/stmicro/stmmac/dwxgmac2.h | 1 +
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 59 ++++---
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 51 ++++++
drivers/net/ethernet/stmicro/stmmac/hwif.h | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 35 ++++
include/linux/stmmac.h | 1 +
10 files changed, 391 insertions(+), 24 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index a1cea2f57252..dc55aec915a2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \
dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
- stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \
+ stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o dw25gmac.o \
stmmac_pcs.o $(stmmac-y)
stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 927ea6230073..84bbed87a563 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -42,13 +42,18 @@
#define DWXGMAC_CORE_2_20 0x22
#define DWXLGMAC_CORE_2_00 0x20
+#define DW25GMAC_CORE_3_20 0x32
+#define DW25GMAC_CORE_4_00 0x40
+
/* Device ID */
#define DWXGMAC_ID 0x76
+#define DW25GMAC_ID 0x55
#define DWXLGMAC_ID 0x27
static inline bool dwmac_is_xmac(enum dwmac_core_type core_type)
{
- return core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC;
+ return core_type == DWMAC_CORE_GMAC4 || core_type == DWMAC_CORE_XGMAC ||
+ core_type == DWMAC_CORE_25GMAC;
}
#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
@@ -325,6 +330,9 @@ struct stmmac_safety_stats {
#define PHY_INTF_GMII 0
#define PHY_INTF_RGMII 1
+/* DW25GMAC uses different encoding - defaults to XGMII */
+#define PHY_INTF_DW25GMAC_XGMII 0
+
/* MSI defines */
#define STMMAC_MSI_VEC_MAX 32
@@ -593,6 +601,7 @@ struct mac_link {
u32 speed2500;
u32 speed5000;
u32 speed10000;
+ u32 speed25000;
} xgmii;
struct {
u32 speed25000;
@@ -651,6 +660,7 @@ int dwmac100_setup(struct stmmac_priv *priv);
int dwmac1000_setup(struct stmmac_priv *priv);
int dwmac4_setup(struct stmmac_priv *priv);
int dwxgmac2_setup(struct stmmac_priv *priv);
+int dw25gmac_setup(struct stmmac_priv *priv);
int dwxlgmac2_setup(struct stmmac_priv *priv);
void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
new file mode 100644
index 000000000000..82eb22bff73e
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024-2026 Broadcom Corporation
+ */
+#include "stmmac.h"
+#include "dwxgmac2.h"
+#include "dw25gmac.h"
+
+u32 dw25gmac_decode_vdma_count(u32 regval)
+{
+ /* compressed encoding for vdma count */
+ if (regval < 16) /* Direct mapping */
+ return regval + 1;
+ else if (regval < 20) /* 20, 24, 28, 32 */
+ return 20 + (regval - 16) * 4;
+ else if (regval < 24) /* 40, 48, 56, 64 */
+ return 40 + (regval - 20) * 8;
+ else if (regval < 28) /* 80, 96, 112, 128 */
+ return 80 + (regval - 24) * 16;
+ else /* not defined */
+ return 0;
+}
+
+static int rd_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel)
+{
+ u32 reg_val = 0;
+
+ reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
+ reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
+ reg_val |= XXVGMAC_CMD_TYPE | XXVGMAC_OB;
+ writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
+ return readl(ioaddr + XXVGMAC_DMA_CH_IND_DATA);
+}
+
+static void wr_dma_ch_ind(void __iomem *ioaddr, u8 mode, u32 channel, u32 val)
+{
+ u32 reg_val = 0;
+
+ writel(val, ioaddr + XXVGMAC_DMA_CH_IND_DATA);
+ reg_val |= FIELD_PREP(XXVGMAC_MODE_SELECT, mode);
+ reg_val |= FIELD_PREP(XXVGMAC_ADDR_OFFSET, channel);
+ reg_val |= XGMAC_OB;
+ writel(reg_val, ioaddr + XXVGMAC_DMA_CH_IND_CONTROL);
+}
+
+void dw25gmac_dma_init(void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg)
+{
+ u32 tx_pdmas, rx_pdmas;
+ u32 hw_cap;
+ u32 value;
+ u32 i;
+
+ value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
+ value &= ~(XGMAC_AAL | XGMAC_EAME);
+ if (dma_cfg->aal)
+ value |= XGMAC_AAL;
+ if (dma_cfg->eame)
+ value |= XGMAC_EAME;
+ writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
+
+ /* Get PDMA counts from HW */
+ hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
+ tx_pdmas = FIELD_GET(XGMAC_HWFEAT_TXQCNT, hw_cap) + 1;
+ rx_pdmas = FIELD_GET(XGMAC_HWFEAT_RXQCNT, hw_cap) + 1;
+
+ /* Initialize all PDMAs with burst length fields */
+ for (i = 0; i < tx_pdmas; i++) {
+ value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i);
+ value &= ~(XXVGMAC_TXPBL | XXVGMAC_TPBLX8_MODE);
+ if (dma_cfg->pblx8)
+ value |= XXVGMAC_TPBLX8_MODE;
+ value |= FIELD_PREP(XXVGMAC_TXPBL, dma_cfg->pbl);
+ wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, i, value);
+ }
+
+ for (i = 0; i < rx_pdmas; i++) {
+ value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i);
+ value &= ~(XXVGMAC_RXPBL | XXVGMAC_RPBLX8_MODE);
+ if (dma_cfg->pblx8)
+ value |= XXVGMAC_RPBLX8_MODE;
+ value |= FIELD_PREP(XXVGMAC_RXPBL, dma_cfg->pbl);
+ wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, i, value);
+ }
+}
+
+void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ dma_addr_t dma_addr, u32 chan)
+{
+ u32 value;
+ u32 tc;
+
+ /* Descriptor cache size and prefetch threshold size */
+ value = rd_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan);
+ value &= ~XXVGMAC_TXDCSZ;
+ value |= FIELD_PREP(XXVGMAC_TXDCSZ,
+ XXVGMAC_TXDCSZ_256BYTES);
+ value &= ~XXVGMAC_TDPS;
+ value |= FIELD_PREP(XXVGMAC_TDPS, XXVGMAC_TDPS_HALF);
+ wr_dma_ch_ind(ioaddr, MODE_TXDESCCTRL, chan, value);
+
+ /* Use one-to-one mapping between VDMA, TC, and PDMA. */
+ tc = chan;
+
+ /* 1-to-1 PDMA to TC mapping */
+ value = rd_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan);
+ value &= ~XXVGMAC_TP2TCMP;
+ value |= FIELD_PREP(XXVGMAC_TP2TCMP, tc);
+ wr_dma_ch_ind(ioaddr, MODE_TXEXTCFG, chan, value);
+
+ /* 1-to-1 VDMA to TC mapping */
+ value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
+ value &= ~XXVGMAC_TVDMA2TCMP;
+ value |= FIELD_PREP(XXVGMAC_TVDMA2TCMP, tc);
+ writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
+
+ writel(upper_32_bits(dma_addr),
+ ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
+ writel(lower_32_bits(dma_addr),
+ ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
+}
+
+void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ dma_addr_t dma_addr, u32 chan)
+{
+ u32 value;
+ u32 tc;
+
+ /* Descriptor cache size and prefetch threshold size */
+ value = rd_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan);
+ value &= ~XXVGMAC_RXDCSZ;
+ value |= FIELD_PREP(XXVGMAC_RXDCSZ,
+ XXVGMAC_RXDCSZ_256BYTES);
+ value &= ~XXVGMAC_RDPS;
+ value |= FIELD_PREP(XXVGMAC_RDPS, XXVGMAC_RDPS_HALF);
+ wr_dma_ch_ind(ioaddr, MODE_RXDESCCTRL, chan, value);
+
+ /* Use one-to-one mapping between VDMA, TC, and PDMA. */
+ tc = chan;
+
+ /* 1-to-1 PDMA to TC mapping */
+ value = rd_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan);
+ value &= ~XXVGMAC_RP2TCMP;
+ value |= FIELD_PREP(XXVGMAC_RP2TCMP, tc);
+ wr_dma_ch_ind(ioaddr, MODE_RXEXTCFG, chan, value);
+
+ /* 1-to-1 VDMA to TC mapping */
+ value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
+ value &= ~XXVGMAC_RVDMA2TCMP;
+ value |= FIELD_PREP(XXVGMAC_RVDMA2TCMP, tc);
+ writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
+
+ writel(upper_32_bits(dma_addr),
+ ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
+ writel(lower_32_bits(dma_addr),
+ ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
new file mode 100644
index 000000000000..b2eee66f04d5
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2024-2026 Broadcom Corporation
+ * DW25GMAC definitions.
+ */
+#ifndef __STMMAC_DW25GMAC_H__
+#define __STMMAC_DW25GMAC_H__
+
+/* Hardware features */
+#define XXVGMAC_HWFEAT_VDMA_RXCNT GENMASK(16, 12)
+#define XXVGMAC_HWFEAT_VDMA_TXCNT GENMASK(22, 18)
+
+/* DMA Indirect Registers*/
+#define XXVGMAC_DMA_CH_IND_CONTROL 0x00003080
+#define XXVGMAC_MODE_SELECT GENMASK(27, 24)
+enum dma_ch_ind_modes {
+ MODE_TXEXTCFG = 0x0, /* Tx Extended Config */
+ MODE_RXEXTCFG = 0x1, /* Rx Extended Config */
+ MODE_TXDBGSTS = 0x2, /* Tx Debug Status */
+ MODE_RXDBGSTS = 0x3, /* Rx Debug Status */
+ MODE_TXDESCCTRL = 0x4, /* Tx Descriptor control */
+ MODE_RXDESCCTRL = 0x5, /* Rx Descriptor control */
+};
+
+#define XXVGMAC_ADDR_OFFSET GENMASK(14, 8)
+#define XXVGMAC_AUTO_INCR GENMASK(5, 4)
+#define XXVGMAC_CMD_TYPE BIT(1)
+#define XXVGMAC_OB BIT(0)
+#define XXVGMAC_DMA_CH_IND_DATA 0x00003084
+
+/* TX Config definitions */
+#define XXVGMAC_TXPBL GENMASK(29, 24)
+#define XXVGMAC_TPBLX8_MODE BIT(19)
+#define XXVGMAC_TP2TCMP GENMASK(18, 16)
+#define XXVGMAC_ORRQ GENMASK(13, 8)
+
+/* RX Config definitions */
+#define XXVGMAC_RXPBL GENMASK(29, 24)
+#define XXVGMAC_RPBLX8_MODE BIT(19)
+#define XXVGMAC_RP2TCMP GENMASK(18, 16)
+#define XXVGMAC_OWRQ GENMASK(13, 8)
+
+/* Tx Descriptor control */
+#define XXVGMAC_TXDCSZ GENMASK(2, 0)
+#define XXVGMAC_TXDCSZ_0BYTES 0
+#define XXVGMAC_TXDCSZ_64BYTES 1
+#define XXVGMAC_TXDCSZ_128BYTES 2
+#define XXVGMAC_TXDCSZ_256BYTES 3
+#define XXVGMAC_TDPS GENMASK(5, 3)
+#define XXVGMAC_TDPS_ZERO 0
+#define XXVGMAC_TDPS_1_8TH 1
+#define XXVGMAC_TDPS_1_4TH 2
+#define XXVGMAC_TDPS_HALF 3
+#define XXVGMAC_TDPS_3_4TH 4
+
+/* Rx Descriptor control */
+#define XXVGMAC_RXDCSZ GENMASK(2, 0)
+#define XXVGMAC_RXDCSZ_0BYTES 0
+#define XXVGMAC_RXDCSZ_64BYTES 1
+#define XXVGMAC_RXDCSZ_128BYTES 2
+#define XXVGMAC_RXDCSZ_256BYTES 3
+#define XXVGMAC_RDPS GENMASK(5, 3)
+#define XXVGMAC_RDPS_ZERO 0
+#define XXVGMAC_RDPS_1_8TH 1
+#define XXVGMAC_RDPS_1_4TH 2
+#define XXVGMAC_RDPS_HALF 3
+#define XXVGMAC_RDPS_3_4TH 4
+
+/* DWCXG_DMA_CH(#i) Registers*/
+#define XXVGMAC_DSL GENMASK(20, 18)
+#define XXVGMAC_MSS GENMASK(13, 0)
+#define XXVGMAC_TFSEL GENMASK(30, 29)
+#define XXVGMAC_TQOS GENMASK(27, 24)
+#define XXVGMAC_IPBL BIT(15)
+#define XXVGMAC_TVDMA2TCMP GENMASK(6, 4)
+#define XXVGMAC_RPF BIT(31)
+#define XXVGMAC_RVDMA2TCMP GENMASK(30, 28)
+#define XXVGMAC_RQOS GENMASK(27, 24)
+
+u32 dw25gmac_decode_vdma_count(u32 regval);
+
+void dw25gmac_dma_init(void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg);
+
+void dw25gmac_dma_init_tx_chan(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ dma_addr_t dma_addr, u32 chan);
+void dw25gmac_dma_init_rx_chan(struct stmmac_priv *priv,
+ void __iomem *ioaddr,
+ struct stmmac_dma_cfg *dma_cfg,
+ dma_addr_t dma_addr, u32 chan);
+#endif /* __STMMAC_DW25GMAC_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 51943705a2b0..eb302a885dd3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -17,6 +17,7 @@
#define XGMAC_CONFIG_SS_OFF 29
#define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)
#define XGMAC_CONFIG_SS_10000 (0x0 << XGMAC_CONFIG_SS_OFF)
+#define XGMAC_CONFIG_SS_25000 (0x1 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_2500_GMII (0x2 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_1000_GMII (0x3 << XGMAC_CONFIG_SS_OFF)
#define XGMAC_CONFIG_SS_100_MII (0x4 << XGMAC_CONFIG_SS_OFF)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index f02b434bbd50..64c38de294da 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -13,6 +13,7 @@
#include "stmmac_vlan.h"
#include "dwxlgmac2.h"
#include "dwxgmac2.h"
+#include "dw25gmac.h"
static void dwxgmac2_core_init(struct mac_device_info *hw,
struct net_device *dev)
@@ -1519,11 +1520,11 @@ const struct stmmac_ops dwxlgmac2_ops = {
.fpe_map_preemption_class = dwxgmac3_fpe_map_preemption_class,
};
-int dwxgmac2_setup(struct stmmac_priv *priv)
+static void dwxgmac2_common_setup(struct stmmac_priv *priv, char *mac_name)
{
struct mac_device_info *mac = priv->hw;
- dev_info(priv->device, "\tXGMAC2\n");
+ dev_info(priv->device, "\t%s\n", mac_name);
priv->dev->priv_flags |= IFF_UNICAST_FLT;
mac->pcsr = priv->ioaddr;
@@ -1534,6 +1535,19 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
if (mac->multicast_filter_bins)
mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
+ mac->mii.addr = XGMAC_MDIO_ADDR;
+ mac->mii.data = XGMAC_MDIO_DATA;
+ mac->mii.addr_mask = GENMASK_U32(20, 16);
+ mac->mii.reg_mask = GENMASK_U32(15, 0);
+ mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
+}
+
+int dwxgmac2_setup(struct stmmac_priv *priv)
+{
+ struct mac_device_info *mac = priv->hw;
+
+ dwxgmac2_common_setup(priv, "XGMAC2");
+
mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000FD |
MAC_2500FD | MAC_5000FD | MAC_10000FD;
@@ -1547,30 +1561,37 @@ int dwxgmac2_setup(struct stmmac_priv *priv)
mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
- mac->mii.addr = XGMAC_MDIO_ADDR;
- mac->mii.data = XGMAC_MDIO_DATA;
- mac->mii.addr_mask = GENMASK_U32(20, 16);
- mac->mii.reg_mask = GENMASK_U32(15, 0);
- mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
mac->num_vlan = stmmac_get_num_vlan(priv->ioaddr);
return 0;
}
-int dwxlgmac2_setup(struct stmmac_priv *priv)
+int dw25gmac_setup(struct stmmac_priv *priv)
{
struct mac_device_info *mac = priv->hw;
- dev_info(priv->device, "\tXLGMAC\n");
+ dwxgmac2_common_setup(priv, "DW25GMAC");
- priv->dev->priv_flags |= IFF_UNICAST_FLT;
- mac->pcsr = priv->ioaddr;
- mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
- mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
- mac->mcast_bits_log2 = 0;
+ mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_1000FD | MAC_2500FD | MAC_5000FD |
+ MAC_10000FD | MAC_25000FD;
+ mac->link.duplex = 0;
+ mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
+ mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
+ mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
+ mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
+ mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
+ mac->link.xgmii.speed25000 = XGMAC_CONFIG_SS_25000;
+ mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
- if (mac->multicast_filter_bins)
- mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
+ return 0;
+}
+
+int dwxlgmac2_setup(struct stmmac_priv *priv)
+{
+ struct mac_device_info *mac = priv->hw;
+
+ dwxgmac2_common_setup(priv, "XLGMAC");
mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_1000FD | MAC_2500FD | MAC_5000FD |
@@ -1587,11 +1608,5 @@ int dwxlgmac2_setup(struct stmmac_priv *priv)
mac->link.xlgmii.speed100000 = XLGMAC_CONFIG_SS_100G;
mac->link.speed_mask = XLGMAC_CONFIG_SS;
- mac->mii.addr = XGMAC_MDIO_ADDR;
- mac->mii.data = XGMAC_MDIO_DATA;
- mac->mii.addr_mask = GENMASK_U32(20, 16);
- mac->mii.reg_mask = GENMASK_U32(15, 0);
- mac->mii.clk_csr_mask = GENMASK_U32(21, 19);
-
return 0;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index 03437f1cf3df..99f5b5598fcf 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -7,6 +7,7 @@
#include <linux/iopoll.h>
#include "stmmac.h"
#include "dwxgmac2.h"
+#include "dw25gmac.h"
static int dwxgmac2_dma_reset(void __iomem *ioaddr)
{
@@ -470,6 +471,26 @@ static int dwxgmac2_get_hw_feature(void __iomem *ioaddr,
return 0;
}
+static int dw25gmac_get_hw_feature(void __iomem *ioaddr,
+ struct dma_features *dma_cap)
+{
+ u32 hw_cap;
+ int ret;
+
+ ret = dwxgmac2_get_hw_feature(ioaddr, dma_cap);
+
+ /* For DW25GMAC VDMA channel count is channel count */
+ hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
+ dma_cap->number_tx_channel =
+ dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_TXCNT,
+ hw_cap));
+ dma_cap->number_rx_channel =
+ dw25gmac_decode_vdma_count(FIELD_GET(XXVGMAC_HWFEAT_VDMA_RXCNT,
+ hw_cap));
+
+ return ret;
+}
+
static void dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
u32 riwt, u32 queue)
{
@@ -611,3 +632,33 @@ const struct stmmac_dma_ops dwxgmac210_dma_ops = {
.enable_sph = dwxgmac2_enable_sph,
.enable_tbs = dwxgmac2_enable_tbs,
};
+
+const struct stmmac_dma_ops dw25gmac400_dma_ops = {
+ .reset = dwxgmac2_dma_reset,
+ .init = dw25gmac_dma_init,
+ .init_chan = dwxgmac2_dma_init_chan,
+ .init_rx_chan = dw25gmac_dma_init_rx_chan,
+ .init_tx_chan = dw25gmac_dma_init_tx_chan,
+ .axi = dwxgmac2_dma_axi,
+ .dump_regs = dwxgmac2_dma_dump_regs,
+ .dma_rx_mode = dwxgmac2_dma_rx_mode,
+ .dma_tx_mode = dwxgmac2_dma_tx_mode,
+ .enable_dma_irq = dwxgmac2_enable_dma_irq,
+ .disable_dma_irq = dwxgmac2_disable_dma_irq,
+ .start_tx = dwxgmac2_dma_start_tx,
+ .stop_tx = dwxgmac2_dma_stop_tx,
+ .start_rx = dwxgmac2_dma_start_rx,
+ .stop_rx = dwxgmac2_dma_stop_rx,
+ .dma_interrupt = dwxgmac2_dma_interrupt,
+ .get_hw_feature = dw25gmac_get_hw_feature,
+ .rx_watchdog = dwxgmac2_rx_watchdog,
+ .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
+ .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
+ .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
+ .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
+ .enable_tso = dwxgmac2_enable_tso,
+ .qmode = dwxgmac2_qmode,
+ .set_bfsize = dwxgmac2_set_bfsize,
+ .enable_sph = dwxgmac2_enable_sph,
+ .enable_tbs = dwxgmac2_enable_tbs,
+};
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index e6317b94fff7..66c24bb033e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -686,6 +686,7 @@ extern const struct stmmac_dma_ops dwmac410_dma_ops;
extern const struct stmmac_ops dwmac510_ops;
extern const struct stmmac_tc_ops dwmac4_tc_ops;
extern const struct stmmac_tc_ops dwmac510_tc_ops;
+extern const struct stmmac_dma_ops dw25gmac400_dma_ops;
#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
#define GMAC4_VERSION 0x00000110 /* GMAC4+ CORE Version */
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index ce51b9c22129..8f2741cd693e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -144,6 +144,10 @@ static const char *stmmac_dwxgmac_phyif[4] = {
[PHY_INTF_RGMII] = "RGMII",
};
+static const char *stmmac_dw25gmac_phyif[2] = {
+ [PHY_INTF_DW25GMAC_XGMII] = "XGMII",
+};
+
static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
/* For MSI interrupts handling */
static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
@@ -1097,6 +1101,32 @@ static void stmmac_mac_link_up(struct phylink_config *config,
default:
return;
}
+ } else if (interface == PHY_INTERFACE_MODE_XGMII) {
+ switch (speed) {
+ case SPEED_25000:
+ ctrl |= priv->hw->link.xgmii.speed25000;
+ break;
+ case SPEED_10000:
+ ctrl |= priv->hw->link.xgmii.speed10000;
+ break;
+ case SPEED_5000:
+ ctrl |= priv->hw->link.xgmii.speed5000;
+ break;
+ case SPEED_2500:
+ ctrl |= priv->hw->link.xgmii.speed2500;
+ break;
+ case SPEED_1000:
+ ctrl |= priv->hw->link.speed1000;
+ break;
+ case SPEED_100:
+ ctrl |= priv->hw->link.speed100;
+ break;
+ case SPEED_10:
+ ctrl |= priv->hw->link.speed10;
+ break;
+ default:
+ return;
+ }
} else if (interface == PHY_INTERFACE_MODE_XLGMII) {
switch (speed) {
case SPEED_100000:
@@ -7291,6 +7321,11 @@ static void stmmac_print_actphyif(struct stmmac_priv *priv)
phyif_table = stmmac_dwxgmac_phyif;
phyif_table_size = ARRAY_SIZE(stmmac_dwxgmac_phyif);
break;
+
+ case DWMAC_CORE_25GMAC:
+ phyif_table = stmmac_dw25gmac_phyif;
+ phyif_table_size = ARRAY_SIZE(stmmac_dw25gmac_phyif);
+ break;
}
if (priv->dma_cap.actphyif < phyif_table_size)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 4430b967abde..e6a7e7b460fb 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -193,6 +193,7 @@ enum dwmac_core_type {
DWMAC_CORE_GMAC,
DWMAC_CORE_GMAC4,
DWMAC_CORE_XGMAC,
+ DWMAC_CORE_25GMAC,
};
#define STMMAC_FLAG_SPH_DISABLE BIT(1)
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v9 4/4] net: stmmac: Add BCM8958x driver to build system
From: Jitendra Vegiraju @ 2026-04-02 21:36 UTC (permalink / raw)
To: netdev
Cc: alexandre.torgue, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
jitendra.vegiraju, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rmk+kernel, rohan.g.thomas,
linux-kernel, linux-stm32, linux-arm-kernel, bpf, andrew+netdev,
horms, sdf, me, siyanteng, prabhakar.mahadev-lad.rj, weishangjuan,
wens, vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha
In-Reply-To: <20260402213629.1996133-1-jitendra.vegiraju@broadcom.com>
From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
Add PCI driver for BCM8958x to the linux build system and
update MAINTAINERS file.
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
MAINTAINERS | 8 ++++++++
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +++++++++++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
3 files changed, 20 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a2ffd9d37d5..0637b8a563ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5120,6 +5120,14 @@ N: brcmstb
N: bcm7038
N: bcm7120
+BROADCOM BCM8958X ETHERNET DRIVER
+M: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
+R: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
+L: netdev@vger.kernel.org
+S: Maintained
+F: drivers/net/ethernet/stmicro/stmmac/dw25gmac.*
+F: drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
+
BROADCOM BCMBCA ARM ARCHITECTURE
M: William Zhang <william.zhang@broadcom.com>
M: Anand Gore <anand.gore@broadcom.com>
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index c2cb530fd0a2..f6f8fa256bf5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -398,6 +398,17 @@ config DWMAC_LOONGSON
This selects the LOONGSON PCI bus support for the stmmac driver,
Support for ethernet controller on Loongson-2K1000 SoC and LS7A1000 bridge.
+config DWMAC_BRCM
+ tristate "Broadcom XGMAC support"
+ depends on STMMAC_ETH && PCI
+ depends on COMMON_CLK
+ select STMMAC_LIBPCI
+ help
+ Support for ethernet controllers on Broadcom BCM8958x SoCs.
+ This selects Broadcom XGMAC specific PCI bus support for the
+ stmmac driver. This driver provides the glue layer on top of the
+ stmmac driver required for the Broadcom BCM8958x SoC devices.
+
config DWMAC_MOTORCOMM
tristate "Motorcomm PCI DWMAC support"
depends on PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index dc55aec915a2..a1e39f65cd42 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -51,4 +51,5 @@ obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o
obj-$(CONFIG_DWMAC_INTEL) += dwmac-intel.o
obj-$(CONFIG_DWMAC_LOONGSON) += dwmac-loongson.o
obj-$(CONFIG_DWMAC_MOTORCOMM) += dwmac-motorcomm.o
+obj-$(CONFIG_DWMAC_BRCM) += dwmac-brcm.o
stmmac-pci-objs:= stmmac_pci.o
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v9 3/4] net: stmmac: Add PCI glue driver for BCM8958x
From: Jitendra Vegiraju @ 2026-04-02 21:36 UTC (permalink / raw)
To: netdev
Cc: alexandre.torgue, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
jitendra.vegiraju, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rmk+kernel, rohan.g.thomas,
linux-kernel, linux-stm32, linux-arm-kernel, bpf, andrew+netdev,
horms, sdf, me, siyanteng, prabhakar.mahadev-lad.rj, weishangjuan,
wens, vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha, Russell King
In-Reply-To: <20260402213629.1996133-1-jitendra.vegiraju@broadcom.com>
From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
Add PCI ethernet driver support for Broadcom BCM8958x SoC devices used
in automotive applications.
This SoC device has PCIe ethernet MAC attached to an integrated ethernet
switch using XGMII interface. The PCIe ethernet controller is presented to
the Linux host as PCI network device.
The following block diagram gives an overview of the application.
+=================================+
| Host CPU/Linux |
+=================================+
|| PCIe
||
+==========================================+
| +--------------+ |
| | PCIE Endpoint| |
| | Ethernet | |
| | Controller | |
| | DMA | |
| +--------------+ |
| | MAC | BCM8958X |
| +--------------+ SoC |
| || XGMII |
| || |
| +--------------+ |
| | Ethernet | |
| | switch | |
| +--------------+ |
| || || || || |
+==========================================+
|| || || || More external interfaces
The MAC IP block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
driver uses common dwxgmac2 code where applicable.
Driver functionality specific to this MAC is implemented in dw25gmac.c.
Management of integrated ethernet switch on this SoC is not handled via
the PCIe interface.
This SoC device has PCIe ethernet MAC directly attached to an integrated
ethernet switch using XGMII interface. Since device tree support is not
available on this platform, a software node is created to enable
fixed-link support using phylink driver.
Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-brcm.c | 360 ++++++++++++++++++
1 file changed, 360 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
new file mode 100644
index 000000000000..e8c6b4b618ac
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2024-2026 Broadcom Corporation
+ *
+ * PCI driver for ethernet interface of BCM8958X automotive switch chip.
+ *
+ * High level block diagram of the device.
+ * +=================================+
+ * | Host CPU/Linux |
+ * +=================================+
+ * || PCIe
+ * ||
+ * +==========================================+
+ * | +--------------+ |
+ * | | PCIE Endpoint| |
+ * | | Ethernet | |
+ * | | Controller | |
+ * | | DMA | |
+ * | +--------------+ |
+ * | | MAC | BCM8958X |
+ * | +--------------+ SoC |
+ * | || XGMII |
+ * | || |
+ * | +--------------+ |
+ * | | Ethernet | |
+ * | | switch | |
+ * | +--------------+ |
+ * | || || || || |
+ * +==========================================+
+ * || || || || More external interfaces
+ *
+ * This SoC device has PCIe ethernet MAC directly attached to an integrated
+ * ethernet switch using XGMII interface. Since devicetree support is not
+ * available on this platform, a software node is created to enable
+ * fixed-link support using phylink driver.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/dmi.h>
+#include <linux/pci.h>
+#include <linux/phy.h>
+#include <linux/of_mdio.h>
+#include "stmmac.h"
+#include "stmmac_libpci.h"
+#include "dwxgmac2.h"
+#include "dw25gmac.h"
+
+#define PCI_DEVICE_ID_BCM8958X 0xa00d
+#define BRCM_MAX_MTU 1500
+
+/* TX and RX Queue counts */
+#define BRCM_TX_Q_COUNT 4
+#define BRCM_RX_Q_COUNT 4
+
+#define BRCM_XGMAC_BAR0_MASK BIT(0)
+
+#define BRCM_XGMAC_IOMEM_MISC_REG_OFFSET 0x0
+#define BRCM_XGMAC_IOMEM_MBOX_REG_OFFSET 0x1000
+#define BRCM_XGMAC_IOMEM_CFG_REG_OFFSET 0x3000
+
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW 0x940
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE 0x00000001
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH 0x944
+#define XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE 0x88000000
+
+#define XGMAC_PCIE_MISC_MII_CTRL_OFFSET 0x4
+#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX BIT(0)
+#define XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX BIT(1)
+#define XGMAC_PCIE_MISC_MII_CTRL_LINK_UP BIT(2)
+#define XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET 0x8
+#define XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX BIT(9)
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET 0x90
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE 0x00000001
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET 0x94
+#define XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE 0x88000000
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET 0x700
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE 1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET 0x704
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE 1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET 0x728
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE 1
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET 0x740
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE 0
+
+/* MSIX Vector map register starting offsets */
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET 0x840
+#define XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET 0x890
+#define BRCM_XGMAC_MSI_MAC_VECTOR 0
+#define BRCM_PER_CH_INT_VECTOR_START 1
+#define BRCM_VECTOR_MAX (BRCM_RX_Q_COUNT + BRCM_TX_Q_COUNT + 1)
+
+static const struct property_entry fixed_link_properties[] = {
+ PROPERTY_ENTRY_U32("speed", 10000),
+ PROPERTY_ENTRY_BOOL("full-duplex"),
+ PROPERTY_ENTRY_BOOL("pause"),
+ { }
+};
+
+static const struct software_node parent_swnode = {
+ .name = "ethernet",
+};
+
+static const struct software_node fixed_link_swnode = {
+ .name = "fixed-link", /* MUST be named "fixed-link" */
+ .parent = &parent_swnode,
+ .properties = fixed_link_properties,
+};
+
+static const struct software_node *brcm_swnodes[] = {
+ &parent_swnode,
+ &fixed_link_swnode,
+ NULL
+};
+
+struct brcm_priv_data {
+ void __iomem *misc_regs; /* MISC Registers*/
+};
+
+static void misc_iowrite(struct brcm_priv_data *brcm_priv,
+ u32 reg, u32 val)
+{
+ iowrite32(val, brcm_priv->misc_regs + reg);
+}
+
+static void brcm_free_irq_vectors(void *data)
+{
+ struct pci_dev *pdev = data;
+
+ pci_free_irq_vectors(pdev);
+}
+
+static int brcm_config_multi_msi(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res)
+{
+ int vector;
+ int ret;
+ int i;
+
+ ret = pci_alloc_irq_vectors(pdev, BRCM_VECTOR_MAX, BRCM_VECTOR_MAX,
+ PCI_IRQ_MSI | PCI_IRQ_MSIX);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "%s: multi MSI enablement failed\n",
+ __func__);
+ return ret;
+ }
+
+ vector = BRCM_XGMAC_MSI_MAC_VECTOR;
+ res->irq = pci_irq_vector(pdev, vector++);
+ for (i = 0; i < BRCM_RX_Q_COUNT; i++, vector++)
+ res->rx_irq[i] = pci_irq_vector(pdev, vector);
+ for (i = 0; i < BRCM_TX_Q_COUNT; i++, vector++)
+ res->tx_irq[i] = pci_irq_vector(pdev, vector);
+
+ plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
+ plat->flags |= STMMAC_FLAG_TSO_EN;
+ plat->flags |= STMMAC_FLAG_SPH_DISABLE;
+
+ return devm_add_action_or_reset(&pdev->dev,
+ brcm_free_irq_vectors, pdev);
+}
+
+static int brcm_drv_init(struct device *dev, void *bsp_priv)
+{
+ struct brcm_priv_data *brcm_priv = (struct brcm_priv_data *)bsp_priv;
+ struct pci_dev *pdev = to_pci_dev(dev);
+ int vector;
+ int ret;
+
+ /* This device is directly attached to the switch chip internal to the
+ * SoC using XGMII interface. Since no MDIO is present, register
+ * fixed-link software_node to create phylink.
+ */
+ ret = software_node_register_node_group(brcm_swnodes);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to register software_node\n");
+ device_set_node(dev, software_node_fwnode(&parent_swnode));
+
+ pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LOW,
+ XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_LO_VALUE);
+ pci_write_config_dword(pdev, XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HIGH,
+ XGMAC_PCIE_CFG_MSIX_ADDR_MATCH_HI_VALUE);
+
+ misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_LO_VALUE);
+ misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_ADDR_MATCH_HI_VALUE);
+
+ /* SBD Interrupt */
+ misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_SBD_ALL_VALUE);
+ /* EP_DOORBELL Interrupt */
+ misc_iowrite(brcm_priv,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST_DBELL_VALUE);
+ /* EP_H0 Interrupt */
+ misc_iowrite(brcm_priv,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST0_VALUE);
+ /* EP_H1 Interrupt */
+ misc_iowrite(brcm_priv,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_OFFSET,
+ XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_EP2HOST1_VALUE);
+
+ vector = BRCM_PER_CH_INT_VECTOR_START;
+ for (int i = 0, offset = XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_RX0_PF0_OFFSET;
+ i < BRCM_RX_Q_COUNT; i++, vector++, offset += 4)
+ misc_iowrite(brcm_priv, offset, vector);
+ for (int i = 0, offset = XGMAC_PCIE_MISC_MSIX_VECTOR_MAP_TX0_PF0_OFFSET;
+ i < BRCM_TX_Q_COUNT; i++, vector++, offset += 4)
+ misc_iowrite(brcm_priv, offset, vector);
+
+ /* Enable Switch Link */
+ misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET,
+ XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX |
+ XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX |
+ XGMAC_PCIE_MISC_MII_CTRL_LINK_UP);
+ /* Enable MSI-X */
+ misc_iowrite(brcm_priv, XGMAC_PCIE_MISC_PCIESS_CTRL_OFFSET,
+ XGMAC_PCIE_MISC_PCIESS_CTRL_EN_MSI_MSIX);
+ return 0;
+}
+
+static void brcm_drv_exit_cleanup(struct device *dev, void *bsp_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+
+ device_set_node(&pdev->dev, NULL);
+ software_node_unregister_node_group(brcm_swnodes);
+}
+
+static int brcm_pci_resume(struct device *dev, void *bsp_priv)
+{
+ /* Enable Switch Link */
+ misc_iowrite(bsp_priv, XGMAC_PCIE_MISC_MII_CTRL_OFFSET,
+ XGMAC_PCIE_MISC_MII_CTRL_PAUSE_RX |
+ XGMAC_PCIE_MISC_MII_CTRL_PAUSE_TX |
+ XGMAC_PCIE_MISC_MII_CTRL_LINK_UP);
+
+ return stmmac_pci_plat_resume(dev, bsp_priv);
+}
+
+static struct plat_stmmacenet_data *
+brcm_plat_data_setup(struct pci_dev *pdev)
+{
+ struct plat_stmmacenet_data *plat;
+
+ plat = stmmac_plat_dat_alloc(&pdev->dev);
+ if (!plat)
+ return NULL;
+
+ plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
+ if (!plat->axi)
+ return NULL;
+
+ plat->core_type = DWMAC_CORE_25GMAC;
+ plat->phy_interface = PHY_INTERFACE_MODE_XGMII;
+
+ plat->dma_cfg->pbl = DEFAULT_DMA_PBL;
+ plat->dma_cfg->pblx8 = true;
+ plat->dma_cfg->eame = true;
+
+ plat->axi->axi_wr_osr_lmt = 31;
+ plat->axi->axi_rd_osr_lmt = 31;
+ plat->axi->axi_blen_regval = DMA_AXI_BLEN64;
+ plat->force_sf_dma_mode = true;
+ plat->mac_port_sel_speed = SPEED_10000;
+ plat->clk_ptp_rate = 125000000;
+ plat->clk_ref_rate = 250000000;
+ plat->tx_coe = true;
+ plat->rx_coe = STMMAC_RX_COE_TYPE1;
+ plat->rss_en = 1;
+ plat->max_speed = SPEED_10000;
+ plat->maxmtu = BRCM_MAX_MTU;
+
+ plat->tx_queues_to_use = BRCM_TX_Q_COUNT;
+ plat->rx_queues_to_use = BRCM_RX_Q_COUNT;
+ plat->tx_sched_algorithm = MTL_TX_ALGORITHM_SP;
+ plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
+
+ plat->init = brcm_drv_init;
+ plat->exit = brcm_drv_exit_cleanup;
+ plat->suspend = stmmac_pci_plat_suspend;
+ plat->resume = brcm_pci_resume;
+
+ return plat;
+}
+
+static int dwxgmac_brcm_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct plat_stmmacenet_data *plat;
+ struct brcm_priv_data *brcm_priv;
+ struct stmmac_resources res;
+ int ret;
+
+ brcm_priv = devm_kzalloc(&pdev->dev, sizeof(*brcm_priv), GFP_KERNEL);
+ if (!brcm_priv)
+ return -ENOMEM;
+
+ plat = brcm_plat_data_setup(pdev);
+ if (!plat)
+ return -ENOMEM;
+ plat->bsp_priv = brcm_priv;
+
+ /* Disable D3COLD as our device does not support it */
+ pci_d3cold_disable(pdev);
+
+ /* Enable PCI device */
+ ret = pcim_enable_device(pdev);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to enable device\n");
+
+ pci_set_master(pdev);
+
+ memset(&res, 0, sizeof(res));
+ res.addr = pcim_iomap_region(pdev, 0, pci_name(pdev));
+ if (IS_ERR(res.addr))
+ return dev_err_probe(&pdev->dev, PTR_ERR(res.addr),
+ "failed to map IO region\n");
+
+ /* MISC Regs */
+ brcm_priv->misc_regs = res.addr + BRCM_XGMAC_IOMEM_MISC_REG_OFFSET;
+ res.addr += BRCM_XGMAC_IOMEM_CFG_REG_OFFSET;
+
+ ret = brcm_config_multi_msi(pdev, plat, &res);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to configure IRQ\n");
+
+ return stmmac_dvr_probe(&pdev->dev, plat, &res);
+}
+
+static void dwxgmac_brcm_pci_remove(struct pci_dev *pdev)
+{
+ stmmac_dvr_remove(&pdev->dev);
+}
+
+static const struct pci_device_id dwxgmac_brcm_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM8958X) },
+ {}
+};
+
+MODULE_DEVICE_TABLE(pci, dwxgmac_brcm_id_table);
+
+static struct pci_driver dwxgmac_brcm_pci_driver = {
+ .name = "brcm-bcm8958x",
+ .id_table = dwxgmac_brcm_id_table,
+ .probe = dwxgmac_brcm_pci_probe,
+ .remove = dwxgmac_brcm_pci_remove,
+ .driver = {
+ .pm = &stmmac_simple_pm_ops,
+ },
+};
+
+module_pci_driver(dwxgmac_brcm_pci_driver);
+
+MODULE_DESCRIPTION("Broadcom 10G Automotive Ethernet PCIe driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v9 2/4] net: stmmac: Integrate dw25gmac into hwif handling
From: Jitendra Vegiraju @ 2026-04-02 21:36 UTC (permalink / raw)
To: netdev
Cc: alexandre.torgue, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
jitendra.vegiraju, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rmk+kernel, rohan.g.thomas,
linux-kernel, linux-stm32, linux-arm-kernel, bpf, andrew+netdev,
horms, sdf, me, siyanteng, prabhakar.mahadev-lad.rj, weishangjuan,
wens, vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha
In-Reply-To: <20260402213629.1996133-1-jitendra.vegiraju@broadcom.com>
From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
Integrate dw25gmac support into stmmac hardware interface handling.
Added a new entry to the stmmac_hw table in hwif.c.
Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
---
drivers/net/ethernet/stmicro/stmmac/hwif.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 511b0fd5e834..a69f558c0db0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -287,6 +287,26 @@ static const struct stmmac_hwif_entry {
.mmc = &dwxgmac_mmc_ops,
.est = &dwmac510_est_ops,
.setup = dwxlgmac2_setup,
+ }, {
+ .core_type = DWMAC_CORE_25GMAC,
+ .min_id = DW25GMAC_CORE_3_20,
+ .regs = {
+ .ptp_off = PTP_XGMAC_OFFSET,
+ .mmc_off = MMC_XGMAC_OFFSET,
+ .est_off = EST_XGMAC_OFFSET,
+ },
+ .desc = &dwxgmac210_desc_ops,
+ .dma = &dw25gmac400_dma_ops,
+ .mac = &dwxgmac210_ops,
+ .vlan = &dwxgmac210_vlan_ops,
+ .hwtimestamp = &stmmac_ptp,
+ .ptp = &stmmac_ptp_clock_ops,
+ .mode = NULL,
+ .tc = &dwmac510_tc_ops,
+ .mmc = &dwxgmac_mmc_ops,
+ .est = &dwmac510_est_ops,
+ .setup = dw25gmac_setup,
+ .quirks = NULL,
},
};
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v9 0/4] net: stmmac: Add PCI driver support for BCM8958x
From: Jitendra Vegiraju @ 2026-04-02 21:36 UTC (permalink / raw)
To: netdev
Cc: alexandre.torgue, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
jitendra.vegiraju, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rmk+kernel, rohan.g.thomas,
linux-kernel, linux-stm32, linux-arm-kernel, bpf, andrew+netdev,
horms, sdf, me, siyanteng, prabhakar.mahadev-lad.rj, weishangjuan,
wens, vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha
From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
This patchset adds basic PCI ethernet device driver support for Broadcom
BCM8958x Automotive Ethernet switch SoC devices.
This SoC device has PCIe ethernet MAC attached to an integrated ethernet
switch using XGMII interface. The PCIe ethernet controller is presented to
the Linux host as PCI network device.
Management of integrated ethernet switch on this SoC is not handled via
the PCIe interface.
The following block diagram gives an overview of the application.
+=================================+
| Host CPU/Linux |
+=================================+
|| PCIe
||
+==========================================+
| +--------------+ |
| | PCIE Endpoint| |
| | Ethernet | |
| | Controller | |
| | DMA | |
| +--------------+ |
| | MAC | BCM8958X |
| +--------------+ SoC |
| || XGMII |
| || |
| +--------------+ |
| | Ethernet | |
| | switch | |
| +--------------+ |
| || || || || |
+==========================================+
|| || || || More external interfaces
The MAC block on BCM8958x is based on Synopsis XGMAC 4.00a core. This
MAC IP introduces new DMA architecture called Hyper-DMA for virtualization
scalability.
Driver functionality specific to new MAC (DW25GMAC) is implemented in
new file dw25gmac.c.
v8->v9:
Patch1:
Merged patch1 and patch2 to avoid patchwork warning (Simon Horman)
Patch2:
Patch3 from v8.
Patch3:
Merged patch4 and patch5 from v8 (Russell King).
Addressed review comments from Russell King.
Removed redundant initialization of zero-initialized variables.
Allocate sequential interrupt vectors for per channel interrupts.
Remove device id based setup function in glue driver as currently
a single device id is supported.
Patch4:
Following the recent upstream patch, removed "depends on STMMAC_ETH"
statment in Kconfig.
v7->v8:
Addressed review comments from v7.
Patch2:
Add a helper function with common code for three setup functions
in dwxgmac2_core.c (Russell King).
Patch4:
Use stmmac_plat_dat_alloc() to allocate memory for
:plat_stmmacenet_data: (Russell King).
Changed few bool variable initialization to bool types in
dwxgmac_brcm_default_data().
Patch5:
Make use of plat->init, plat->exit handlers to cleanup
probe function error handling path (Russell King).
Use managed API to free irq vectors.
v6->v7:
Minor changes to v6 patchset adapting to recent changes net-next.
Patch1:
Make use of the core_type variable for MAC core identification.
Define enum value DWMAC_CORE_25GMAC and discard previous proposal to
add new variables in struct plat_stmmacenet_data.
Patch2:
Updated patch to latest net-next branch code base.
Patch3:
Modified hwif entry matching to use core_type DWMAC_CORE_25GMAC.
Patch4:
Adapted glue driver to match recent stmmac core changes.
Changed susped/resume functionality to use common framework.
https://lore.kernel.org/netdev/20260313222206.778760-1-jitendra.vegiraju@broadcom.com/
v5->v6:
Change summary to address comments/suggestions by Serge Semin.
Patch1:
Removed the complexity of hdma mapping in previous patch series and
use static DMA mapping.
Renamed plat_stmmacenet_data::snps_dev_id as dev_id and moved to
the beginning of the struct.
Patch2:
Added dw25gmac_get_hw_feature() for dw25gmac.
Use static one-to-one VDMA-TC-PDMA mapping.
Patch4:
Remove usage of plat_stmmacenet_data::msi_*_vec variables for
interrupt vector initialization.
Change phy_interface type to XGMII.
Cleanup unused macros.
https://lore.kernel.org/netdev/20241018205332.525595-1-jitendra.vegiraju@broadcom.com/
v4->v5:
Summary of changes in this patch series:
As suggested by Serge Semin, defined common setup function for dw25gmac.
To accommodate early adopter DW25GMAC used in BCM8958x device, provide
a mechanism to override snps_id and snps_dev_id used for driver entry
matching in hwif.c
Patch1:
Added plat_stmmacenet_data::snps_id,snps_dev_id fields - Serge Semin
Patch2:
Define common setup function for dw25gmac_setup() - Serge Semin
Support DW25GMAC IPs with varying VDMA/PDMA count - Abhishek Chauhan
Allocate and initialize hdma mapping configuration data dynamically
based on device's VDMA/PDMA feature capabilities in dw25gmac_setup().
Spelling errors in commit log, lower case 0x for hex -Amit Singh Tomar
Patch3:
Glue support in hwif.c for DW25GMAC in hwif.c - Serge Semin
Provide an option to override snps_id and snps_dev_id when the device
reports version info not conformant with driver's expectations as is
the case with BCM8958x device. - Serge Semin
Patch4:
Remove setup function in the glue driver - Serge Semin
Remove unnecessary calls pci_enable_device() and pci_set_master()
in dwxgmac_brcm_pci_resume() - Jakub Kicinski
Merge variable definitions to single line - Amit Singh Tomar
https://lore.kernel.org/netdev/20240904054815.1341712-1-jitendra.vegiraju@broadcom.com/
v3->v4:
Based on Serge's questions, received a confirmation from Synopsys that
the MAC IP is indeed the new 25GMAC design.
Renamed all references of XGMAC4 to 25GMAC.
The patch series is rearranged slightly as follows.
Patch1 (new): Define HDMA mapping data structure in kernel's stmmac.h
Patch2 (v3 Patch1): Adds dma_ops for dw25gmac in stmmac core
Renamed new files dwxgmac4.* to dw25gmac.* - Serge Semin
Defined new Synopsis version and device id macros for DW25GMAC.
Converted bit operations to FIELD_PREP macros - Russell King
Moved hwif.h to this patch, Sparse flagged warning - Simon Horman
Defined macros for hardcoded values TDPS etc - Serge Semin
Read number of PDMAs/VDMAs from hardware - Serge Semin
Patch3 (v3 Patch2): Hooks in hardware interface handling for dw25gmac
Resolved user_version quirks questions - Serge, Russell, Andrew
Added new stmmac_hw entry for DW25GMAC. - Serge
Added logic to override synopsis_dev_id by glue driver.
Patch4 (v3 Patch3): Adds PCI driver for BCM8958x device
Define bitmmap macros for hardcoded values - Andrew Lunn
Added per device software node - Andrew Lunn
Patch5(new/split): Adds BCM8958x driver to build system
https://lore.kernel.org/netdev/20240814221818.2612484-1-jitendra.vegiraju@broadcom.com/
v2->v3:
Addressed v2 comments from Andrew, Jakub, Russel and Simon.
Based on suggestion by Russel and Andrew, added software node to create
phylink in fixed-link mode.
Moved dwxgmac4 specific functions to new files dwxgmac4.c and dwxgmac4.h
in stmmac core module.
Reorganized the code to use the existing glue logic support for xgmac in
hwif.c and override ops functions for dwxgmac4 specific functions.
The patch is split into three parts.
Patch#1 Adds dma_ops for dwxgmac4 in stmmac core
Patch#2 Hooks in the hardware interface handling for dwxgmac4
Patch#3 Adds PCI driver for BCM8958x device
https://lore.kernel.org/netdev/20240802031822.1862030-1-jitendra.vegiraju@broadcom.com/
v1->v2:
Minor fixes to address coding style issues.
Sent v2 too soon by mistake, without waiting for review comments.
Received feedback on this version.
https://lore.kernel.org/netdev/20240511015924.41457-1-jitendra.vegiraju@broadcom.com/
v1:
https://lore.kernel.org/netdev/20240510000331.154486-1-jitendra.vegiraju@broadcom.com/
Jitendra Vegiraju (4):
Add DW25GMAC support in stmmac core driver
Integrate dw25gmac into hwif handling
Add PCI driver support for BCM8958x
Add BCM8958x driver to build system
MAINTAINERS | 8 +
drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 3 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 12 +-
.../net/ethernet/stmicro/stmmac/dw25gmac.c | 161 ++++++++
.../net/ethernet/stmicro/stmmac/dw25gmac.h | 92 +++++
.../net/ethernet/stmicro/stmmac/dwmac-brcm.c | 360 ++++++++++++++++++
.../net/ethernet/stmicro/stmmac/dwxgmac2.h | 1 +
.../ethernet/stmicro/stmmac/dwxgmac2_core.c | 59 +--
.../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 51 +++
drivers/net/ethernet/stmicro/stmmac/hwif.c | 20 +
drivers/net/ethernet/stmicro/stmmac/hwif.h | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 35 ++
include/linux/stmmac.h | 1 +
14 files changed, 791 insertions(+), 24 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.c
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dw25gmac.h
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-brcm.c
--
2.34.1
^ permalink raw reply
* Re: (subset) [PATCH v10 00/30] KVM: arm64: Implement support for SME
From: Catalin Marinas @ 2026-04-02 21:12 UTC (permalink / raw)
To: Marc Zyngier, Joey Gouly, Suzuki K Poulose, Will Deacon,
Paolo Bonzini, Jonathan Corbet, Shuah Khan, Oliver Upton,
Mark Brown
Cc: Dave Martin, Fuad Tabba, Mark Rutland, Ben Horgan,
linux-arm-kernel, kvmarm, linux-kernel, kvm, linux-doc,
linux-kselftest, Peter Maydell, Eric Auger
In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org>
On Fri, 06 Mar 2026 17:00:52 +0000, Mark Brown wrote:
> I've removed the RFC tag from this version of the series, but the items
> that I'm looking for feedback on remains the same:
>
> - The userspace ABI, in particular:
> - The vector length used for the SVE registers, access to the SVE
> registers and access to ZA and (if available) ZT0 depending on
> the current state of PSTATE.{SM,ZA}.
> - The use of a single finalisation for both SVE and SME.
>
> [...]
Applied to arm64 (for-next/sysreg), thanks!
[01/30] arm64/sysreg: Update SMIDR_EL1 to DDI0601 2025-06
https://git.kernel.org/arm64/c/85b6f920a869
I looked to add more core arch patches but they all look like
preparation for subsequent KVM support. If the subsequent patches will
have to change following review, I couldn't figure out whether the first
3-4 patches in this series will remain the same.
--
Catalin
^ permalink raw reply
* Re: [PATCH v2 0/3] Fix bugs for realm guest plus BBML2_NOABORT
From: Catalin Marinas @ 2026-04-02 21:11 UTC (permalink / raw)
To: Will Deacon, David Hildenbrand (Arm), Dev Jain, Yang Shi,
Suzuki K Poulose, Jinjiang Tu, Kevin Brodsky, Ryan Roberts
Cc: linux-arm-kernel, linux-kernel
In-Reply-To: <20260330161705.3349825-1-ryan.roberts@arm.com>
On Mon, 30 Mar 2026 17:17:01 +0100, Ryan Roberts wrote:
> This fixes a couple of bugs in the "large block mappings for linear map when we
> have BBML2_NOABORT" feature when used in conjunction with a CCA realm guest.
> While investigating I found and fixed some more general issues too. See commit
> logs for full explanations.
>
> Applies on top of v7.0-rc4.
>
> [...]
Applied to arm64 (for-next/bbml2-fixes), thanks! I had some comments on
the first patch, so I may rebase it or add something on top.
[1/3] arm64: mm: Fix rodata=full block mapping support for realm guests
https://git.kernel.org/arm64/c/f12b435de2f2
[2/3] arm64: mm: Handle invalid large leaf mappings correctly
https://git.kernel.org/arm64/c/15bfba1ad77f
[3/3] arm64: mm: Remove pmd_sect() and pud_sect()
https://git.kernel.org/arm64/c/1d37713fa837
^ permalink raw reply
* Re: [PATCH] arm64: clear_page[s] using memset
From: Catalin Marinas @ 2026-04-02 20:57 UTC (permalink / raw)
To: Linus Walleij
Cc: Will Deacon, Marc Zyngier, Oliver Upton, Joey Gouly,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, kvmarm
In-Reply-To: <20260306-aarch64-clear-pages-c-v1-1-77c1bb0f1c21@kernel.org>
On Fri, Mar 06, 2026 at 09:57:50AM +0100, Linus Walleij wrote:
> There is no need to try to second-guess the compiler when
> clearing memory. Just call memset() like everyone else.
Hmm, that "like everyone else" made me think - why not move this to
generic code and only the 1-2 platforms that need their own should
override it? Could we do the same with copy_page()?
Sorry, more work all of a sudden ;).
> Since memset() already has an architecture-local MOPS
> optimization, we do not need to do anything else to preserve
> the MOPS optimization.
The custom clear_page() had the (very small) advantage that it can skip
the length/alignment checks as they are always page-size.
> While at it, implement the shorthand for directly calling
> the new prototype clear_pages() for larger page chunks.
>
> No performance regressions can be seen, the fastpath
> benchmarks differences are in the noise.
I assume the benchmarks ran on real hardware (had to ask, last time you
mentioned qemu ;)).
--
Catalin
^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: mm: Fix rodata=full block mapping support for realm guests
From: Catalin Marinas @ 2026-04-02 20:43 UTC (permalink / raw)
To: Ryan Roberts
Cc: Will Deacon, David Hildenbrand (Arm), Dev Jain, Yang Shi,
Suzuki K Poulose, Jinjiang Tu, Kevin Brodsky, linux-arm-kernel,
linux-kernel, stable
In-Reply-To: <20260330161705.3349825-2-ryan.roberts@arm.com>
On Mon, Mar 30, 2026 at 05:17:02PM +0100, Ryan Roberts wrote:
> int split_kernel_leaf_mapping(unsigned long start, unsigned long end)
> {
> int ret;
>
> - /*
> - * !BBML2_NOABORT systems should not be trying to change permissions on
> - * anything that is not pte-mapped in the first place. Just return early
> - * and let the permission change code raise a warning if not already
> - * pte-mapped.
> - */
> - if (!system_supports_bbml2_noabort())
> - return 0;
> -
> /*
> * If the region is within a pte-mapped area, there is no need to try to
> * split. Additionally, CONFIG_DEBUG_PAGEALLOC and CONFIG_KFENCE may
> * change permissions from atomic context so for those cases (which are
> * always pte-mapped), we must not go any further because taking the
> - * mutex below may sleep.
> + * mutex below may sleep. Do not call force_pte_mapping() here because
> + * it could return a confusing result if called from a secondary cpu
> + * prior to finalizing caps. Instead, linear_map_requires_bbml2 gives us
> + * what we need.
> */
> - if (force_pte_mapping() || is_kfence_address((void *)start))
> + if (!linear_map_requires_bbml2 || is_kfence_address((void *)start))
> return 0;
>
> + if (!system_supports_bbml2_noabort()) {
> + /*
> + * !BBML2_NOABORT systems should not be trying to change
> + * permissions on anything that is not pte-mapped in the first
> + * place. Just return early and let the permission change code
> + * raise a warning if not already pte-mapped.
> + */
> + if (system_capabilities_finalized())
> + return 0;
> +
> + /*
> + * Boot-time: split_kernel_leaf_mapping_locked() allocates from
> + * page allocator. Can't split until it's available.
> + */
> + if (WARN_ON(!page_alloc_available))
> + return -EBUSY;
> +
> + /*
> + * Boot-time: Started secondary cpus but don't know if they
> + * support BBML2_NOABORT yet. Can't allow splitting in this
> + * window in case they don't.
> + */
> + if (WARN_ON(num_online_cpus() > 1))
> + return -EBUSY;
> + }
I think sashiko is over cautions here
(https://sashiko.dev/#/patchset/20260330161705.3349825-1-ryan.roberts@arm.com)
but it has a somewhat valid point from the perspective of
num_online_cpus() semantics. We have have num_online_cpus() == 1 while
having a secondary CPU just booted and with its MMU enabled. I don't
think we can have any asynchronous tasks running at that point to
trigger a spit though. Even async_init() is called after smp_init().
An option may be to attempt cpus_read_trylock() as this lock is taken by
_cpu_up(). If it fails, return -EBUSY, otherwise check num_online_cpus()
and unlock (and return -EBUSY if secondaries already started).
Another thing I couldn't get my head around - IIUC is_realm_world()
won't return true for map_mem() yet (if in a realm). Can we have realms
on hardware that does not support BBML2_NOABORT? We may not have
configuration with rodata_full set (it should be complementary to realm
support).
I'll add the patches to for-next/core to give them a bit of time in
-next but let's see next week if we ignore this (with an updated
comment) or we try to avoid the issue altogether.
--
Catalin
^ permalink raw reply
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