* [PATCH v4 0/6] arm64: Add support for FEAT_Debugv8p9
From: Rob Herring (Arm) @ 2026-04-07 14:29 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Catalin Marinas, Jonathan Corbet,
Shuah Khan
Cc: Anshuman Khandual, linux-arm-kernel, linux-perf-users,
linux-kernel, linux-doc, Marc Zyngier, kvmarm, Oliver Upton
This series enables FEAT_Debugv8p9 which extends the breakpoint and
watchpoint support from 16 up to 64. I've picked up this series from
Anshuman.
Changes in V4:
- Limit enabling of FEAT_Debugv8p9 to only when more than 16 breakpoints
or watchpoints are present.
- Add lockdep_assert_irqs_disabled() to document the constraints. Drop
unnecessary IRQ disabling.
- Add more kprobe blacklist annotations and disallow breakpoints in the
nokprobe code.
- Drop previously applied sysreg patches.
Prior versions from Anshuman:
Changes in V3:
https://lore.kernel.org/all/20241216040831.2448257-1-anshuman.khandual@arm.com/
- Marked ID_AA64DFR1_EL1.ABLE as FTR_NONSTRICT in ftr_id_aa64dfr1[]
- Dropped MDCR_EL3.TDA boot requirement from documentation (separate series)
- Dropped MDCR_EL2_EBWE definition as MDCR_EL2 is now defined in tools sysreg
- Used SYS_FIELD_PREP() in read_wb_reg() and write_wb_reg()
- Added MAX_PER_BANK based BUILD_BUG_ON() tests in arch_hw_breakpoint_init()
- Dropped local variables i.e mdsel_bank and index
- Derived bank and index from MAX_PER_BANK as required
Changes in V2:
https://lore.kernel.org/all/20241028053426.2486633-1-anshuman.khandual@arm.com/
Following changes have been made per review comments from Mark Rutland
- Orr MDCR_EL2_EBWE directly without an intermittent register
- Alphabetically order header files in debug-monitors.c
- Dropped embwe_ref_count mechanism
- Dropped preempt_enable() from AARCH64_DBG_READ
- Dropped preempt_disable() from AARCH64_DBG_WRITE
- Dropped set_bank_index()
- Renamed read/write_wb_reg() as __read/__write_wb_reg()
- Modified read/write_wb_reg() to have MDSELR_E1 based banked read/write
- Added required sysreg tools patches from KVM FEAT_FGT2 series for build
Changes in V1:
https://lore.kernel.org/all/20241001043602.1116991-1-anshuman.khandual@arm.com/
- Changed FTR_STRICT to FTR_NONSTRICT for the following ID_AA64DFR1_EL1
register fields - ABL_CMPs, DPFZS, PMICNTR, CTX_CMPs, WRPs and BRPs
Changes in RFC V2:
https://lore.kernel.org/linux-arm-kernel/20240620092607.267132-1-anshuman.khandual@arm.com/
- This series has been split from RFC V1 dealing only with arm64 breakpoints
- Restored back DBG_MDSCR_MASK definition (unrelated change)
- Added preempt_disable()/enable() blocks between selecting banks and registers
Changes in RFC:
https://lore.kernel.org/all/20240405080008.1225223-1-anshuman.khandual@arm.com/
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
Anshuman Khandual (3):
arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register
arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
arm64: hw_breakpoint: Enable FEAT_Debugv8p9
Rob Herring (Arm) (3):
arm64: hw_breakpoint: Disallow breakpoints in no kprobe code
arm64: hw_breakpoint: Add additional kprobe excluded functions
arm64: hw_breakpoint: Add lockdep_assert_irqs_disabled() on install/uninstall
Documentation/arch/arm64/booting.rst | 13 +++++++
arch/arm64/include/asm/el2_setup.h | 14 +++++++
arch/arm64/include/asm/hw_breakpoint.h | 47 ++++++++++++++++++-----
arch/arm64/kernel/cpufeature.c | 21 ++++++++---
arch/arm64/kernel/debug-monitors.c | 16 +++++---
arch/arm64/kernel/hw_breakpoint.c | 68 +++++++++++++++++++++++++++++-----
6 files changed, 150 insertions(+), 29 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260406-arm-debug-8-9-41f6f0e739b5
Best regards,
--
Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* [PATCH v5 4/4] firmware: ti_sci: add support for restoring clock context during resume
From: Thomas Richard (TI) @ 2026-04-07 14:25 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Prasanth Mantena,
Abhash Kumar, Thomas Petazzoni, linux-arm-kernel, linux-kernel,
linux-clk, Thomas Richard (TI), Dhruva Gole
In-Reply-To: <20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com>
Some DM-Firmware are not able to restore the clock rates and the clock
parents after a suspend-resume. The CLK_CONTEXT_LOST firmware capability
has been introduced to identify this characteristic. In this case the
responsibility is therefore delegated to the ti_sci driver, which uses
clk_restore_context() to trigger the context_restore() operation for all
registered clocks, including those managed by the sci-clk. The sci-clk
driver implements the context_restore() operation to ensure rates and clock
parents are correctly restored.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 9 +++++++--
drivers/firmware/ti_sci.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index b5c4324287b0..0148bafd71a0 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -9,6 +9,7 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/bitmap.h>
+#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
@@ -3981,6 +3982,9 @@ static int ti_sci_resume_noirq(struct device *dev)
return ret;
}
}
+
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST)
+ clk_restore_context();
break;
default:
break;
@@ -4141,14 +4145,15 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST ? " Clk-Context-Lost" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 67f16e8c69a1..2d75667a6723 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -152,6 +152,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
* MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
* MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ context
+ * MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST: DM is not able to restore Clock context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -166,6 +167,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
+#define MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST TI_SCI_MSG_FLAG(15)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v5 2/4] firmware: ti_sci: add support for restoring IRQs during resume
From: Thomas Richard (TI) @ 2026-04-07 14:25 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Prasanth Mantena,
Abhash Kumar, Thomas Petazzoni, linux-arm-kernel, linux-kernel,
linux-clk, Thomas Richard (TI), Dhruva Gole
In-Reply-To: <20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com>
Some DM-Firmware are not able to restore the IRQ context after a
suspend-resume. The IRQ_CONTEXT_LOST firmware capability has been
introduced to identify this characteristic. In this case the
responsibility is delegated to the ti_sci driver, which maintains an
internal list of all requested IRQs. This list is updated on each
set()/free() operation, and all IRQs are restored during the resume_noirq()
phase.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 153 ++++++++++++++++++++++++++++++++++++++++++----
drivers/firmware/ti_sci.h | 2 +
2 files changed, 144 insertions(+), 11 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index eaeaaae94142..b5c4324287b0 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -12,6 +12,7 @@
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
+#include <linux/hashtable.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
@@ -87,6 +88,16 @@ struct ti_sci_desc {
int max_msg_size;
};
+/**
+ * struct ti_sci_irq - Description of allocated irqs
+ * @node: Link to hash table
+ * @desc: Description of the irq
+ */
+struct ti_sci_irq {
+ struct hlist_node node;
+ struct ti_sci_msg_req_manage_irq desc;
+};
+
/**
* struct ti_sci_info - Structure representing a TI SCI instance
* @dev: Device pointer
@@ -101,6 +112,7 @@ struct ti_sci_desc {
* @chan_rx: Receive mailbox channel
* @minfo: Message info
* @node: list head
+ * @irqs: List of allocated irqs
* @host_id: Host ID
* @fw_caps: FW/SoC low power capabilities
* @users: Number of users of this instance
@@ -117,6 +129,7 @@ struct ti_sci_info {
struct mbox_chan *chan_tx;
struct mbox_chan *chan_rx;
struct ti_sci_xfers_info minfo;
+ DECLARE_HASHTABLE(irqs, 8);
struct list_head node;
u8 host_id;
u64 fw_caps;
@@ -2301,6 +2314,32 @@ static int ti_sci_manage_irq(const struct ti_sci_handle *handle,
return ret;
}
+/**
+ * ti_sci_irq_hash() - Helper API to compute irq hash for the hash table.
+ * @irq: irq to hash
+ *
+ * Return: the computed hash value.
+ */
+static int ti_sci_irq_hash(struct ti_sci_msg_req_manage_irq *irq)
+{
+ return irq->src_id ^ irq->src_index;
+}
+
+/**
+ * ti_sci_irq_equal() - Helper API to compare two irqs (generic headers are not
+ * compared)
+ * @irq_a: irq_a to compare
+ * @irq_b: irq_b to compare
+ *
+ * Return: true if the two irqs are equal, else false.
+ */
+static bool ti_sci_irq_equal(struct ti_sci_msg_req_manage_irq *irq_a,
+ struct ti_sci_msg_req_manage_irq *irq_b)
+{
+ return !memcmp(&irq_a->valid_params, &irq_b->valid_params,
+ sizeof(*irq_a) - sizeof(irq_a->hdr));
+}
+
/**
* ti_sci_set_irq() - Helper api to configure the irq route between the
* requested source and destination
@@ -2324,15 +2363,43 @@ static int ti_sci_set_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq *desc;
+ struct ti_sci_irq *irq;
+ int ret;
+
pr_debug("%s: IRQ set with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_SET_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_SET_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ return ret;
+
+ irq = kzalloc_obj(*irq, GFP_KERNEL);
+ if (!irq)
+ return -ENOMEM;
+
+ desc = &irq->desc;
+ desc->valid_params = valid_params;
+ desc->src_id = src_id;
+ desc->src_index = src_index;
+ desc->dst_id = dst_id;
+ desc->dst_host_irq = dst_host_irq;
+ desc->ia_id = ia_id;
+ desc->vint = vint;
+ desc->global_event = global_event;
+ desc->vint_status_bit = vint_status_bit;
+ desc->secondary_host = s_host;
+
+ hash_add(info->irqs, &irq->node, ti_sci_irq_hash(desc));
+
+ return 0;
}
/**
@@ -2358,15 +2425,46 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq irq_desc;
+ struct ti_sci_irq *this_irq;
+ struct hlist_node *tmp_node;
+ int ret;
+
pr_debug("%s: IRQ release with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_FREE_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_FREE_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ return ret;
+
+ irq_desc.valid_params = valid_params;
+ irq_desc.src_id = src_id;
+ irq_desc.src_index = src_index;
+ irq_desc.dst_id = dst_id;
+ irq_desc.dst_host_irq = dst_host_irq;
+ irq_desc.ia_id = ia_id;
+ irq_desc.vint = vint;
+ irq_desc.global_event = global_event;
+ irq_desc.vint_status_bit = vint_status_bit;
+ irq_desc.secondary_host = s_host;
+
+ hash_for_each_possible_safe(info->irqs, this_irq, tmp_node, node,
+ ti_sci_irq_hash(&irq_desc)) {
+ if (ti_sci_irq_equal(&irq_desc, &this_irq->desc)) {
+ hlist_del(&this_irq->node);
+ kfree(this_irq);
+ return 0;
+ }
+ }
+
+ return 0;
}
/**
@@ -3847,7 +3945,10 @@ static int ti_sci_suspend_noirq(struct device *dev)
static int ti_sci_resume_noirq(struct device *dev)
{
struct ti_sci_info *info = dev_get_drvdata(dev);
- int ret = 0;
+ struct ti_sci_msg_req_manage_irq *irq_desc;
+ struct ti_sci_irq *irq;
+ struct hlist_node *tmp_node;
+ int ret = 0, i;
u32 source;
u64 time;
u8 pin;
@@ -3859,6 +3960,32 @@ static int ti_sci_resume_noirq(struct device *dev)
return ret;
}
+ switch (pm_suspend_target_state) {
+ case PM_SUSPEND_MEM:
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST) {
+ hash_for_each_safe(info->irqs, i, tmp_node, irq, node) {
+ irq_desc = &irq->desc;
+ ret = ti_sci_manage_irq(&info->handle,
+ irq_desc->valid_params,
+ irq_desc->src_id,
+ irq_desc->src_index,
+ irq_desc->dst_id,
+ irq_desc->dst_host_irq,
+ irq_desc->ia_id,
+ irq_desc->vint,
+ irq_desc->global_event,
+ irq_desc->vint_status_bit,
+ irq_desc->secondary_host,
+ TI_SCI_MSG_SET_IRQ);
+ if (ret)
+ return ret;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
ret = ti_sci_msg_cmd_lpm_wake_reason(&info->handle, &source, &time, &pin, &mode);
/* Do not fail to resume on error as the wake reason is not critical */
if (!ret)
@@ -4014,13 +4141,14 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
);
ti_sci_setup_ops(info);
@@ -4053,6 +4181,9 @@ static int ti_sci_probe(struct platform_device *pdev)
list_add_tail(&info->node, &ti_sci_list);
mutex_unlock(&ti_sci_list_mutex);
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST)
+ hash_init(info->irqs);
+
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
dev_err(dev, "platform_populate failed %pe\n", ERR_PTR(ret));
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index d90de59e29eb..67f16e8c69a1 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -151,6 +151,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
* MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
+ * MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -164,6 +165,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
+#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v5 3/4] clk: keystone: sci-clk: add restore_context() operation
From: Thomas Richard (TI) @ 2026-04-07 14:25 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Prasanth Mantena,
Abhash Kumar, Thomas Petazzoni, linux-arm-kernel, linux-kernel,
linux-clk, Thomas Richard (TI), Dhruva Gole
In-Reply-To: <20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com>
Implement the restore_context() operation to restore the clock rate and the
clock parent state. The clock rate is saved in sci_clk struct during
set_rate() operation. The parent index is saved in sci_clk struct during
set_parent() operation. During clock registration, the core retrieves each
clock’s parent using get_parent() operation to ensure the internal clock
tree reflects the actual hardware state, including any configurations made
by the bootloader. So we also save the parent index in get_parent().
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/clk/keystone/sci-clk.c | 42 ++++++++++++++++++++++++++++++++++--------
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index 9d5071223f4c..428050a05de3 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -47,6 +47,8 @@ struct sci_clk_provider {
* @node: Link for handling clocks probed via DT
* @cached_req: Cached requested freq for determine rate calls
* @cached_res: Cached result freq for determine rate calls
+ * @parent_id: Parent index for this clock
+ * @rate: Clock rate
*/
struct sci_clk {
struct clk_hw hw;
@@ -58,6 +60,8 @@ struct sci_clk {
struct list_head node;
unsigned long cached_req;
unsigned long cached_res;
+ u8 parent_id;
+ unsigned long rate;
};
#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
@@ -210,10 +214,16 @@ static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
+
+ ret = clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+ clk->clk_id, rate / 10 * 9, rate,
+ rate / 10 * 11);
- return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
- clk->clk_id, rate / 10 * 9, rate,
- rate / 10 * 11);
+ if (!ret)
+ clk->rate = rate;
+
+ return ret;
}
/**
@@ -237,9 +247,9 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
return 0;
}
- parent_id = parent_id - clk->clk_id - 1;
+ clk->parent_id = (u8)(parent_id - clk->clk_id - 1);
- return (u8)parent_id;
+ return clk->parent_id;
}
/**
@@ -252,12 +262,27 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
clk->cached_req = 0;
- return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
- clk->clk_id,
- index + 1 + clk->clk_id);
+ ret = clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
+ clk->clk_id,
+ index + 1 + clk->clk_id);
+ if (!ret)
+ clk->parent_id = index;
+
+ return ret;
+}
+
+static void sci_clk_restore_context(struct clk_hw *hw)
+{
+ struct sci_clk *clk = to_sci_clk(hw);
+
+ sci_clk_set_parent(hw, clk->parent_id);
+
+ if (clk->rate)
+ sci_clk_set_rate(hw, clk->rate, 0);
}
static const struct clk_ops sci_clk_ops = {
@@ -269,6 +294,7 @@ static const struct clk_ops sci_clk_ops = {
.set_rate = sci_clk_set_rate,
.get_parent = sci_clk_get_parent,
.set_parent = sci_clk_set_parent,
+ .restore_context = sci_clk_restore_context,
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH v5 1/4] firmware: ti_sci: add BOARDCFG_MANAGED mode support
From: Thomas Richard (TI) @ 2026-04-07 14:25 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Prasanth Mantena,
Abhash Kumar, Thomas Petazzoni, linux-arm-kernel, linux-kernel,
linux-clk, Thomas Richard (TI), Dhruva Gole
In-Reply-To: <20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com>
In BOARDCFG_MANAGED mode, the low power mode configuration is done
statically for the DM via the boardcfg. Constraints are not supported, and
prepare_sleep() is not needed.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 10 +++++++---
drivers/firmware/ti_sci.h | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index dd9911b1cc11..eaeaaae94142 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3772,8 +3772,11 @@ static int ti_sci_prepare_system_suspend(struct ti_sci_info *info)
return ti_sci_cmd_prepare_sleep(&info->handle,
TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED,
0, 0, 0);
+ } else if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) {
+ /* Nothing to do in the BOARDCFG_MANAGED mode */
+ return 0;
} else {
- /* DM Managed is not supported by the firmware. */
+ /* DM Managed and BoardCfg Managed are not supported by the firmware. */
dev_err(info->dev, "Suspend to memory is not supported by the firmware\n");
return -EOPNOTSUPP;
}
@@ -4011,12 +4014,13 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
- info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : ""
+ info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 4616127e33ff..d90de59e29eb 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -150,6 +150,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM
* MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
+ * MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -162,6 +163,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5)
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
+#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v5 0/4] firmware: ti_sci: Introduce BOARDCFG_MANAGED mode for Jacinto family
From: Thomas Richard (TI) @ 2026-04-07 14:25 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Prasanth Mantena,
Abhash Kumar, Thomas Petazzoni, linux-arm-kernel, linux-kernel,
linux-clk, Thomas Richard (TI), Dhruva Gole
This is the 5th iteration of this series. Nothing new, I just rebased on
v7.0-rc7, added Dhruva's RB tags, and use kzalloc_obj() in Patch 2.
Best Regards,
Thomas
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
Changes in v5:
- rebase on v7.0-rc7.
- add Dhruva's RB tag.
- use kzalloc_obj() in ti_sci driver.
- Link to v4: https://lore.kernel.org/r/20260204-ti-sci-jacinto-s2r-restore-irq-v4-0-67820af39eac@bootlin.com
Changes in v4:
- rebase on linux-next next-20260202.
- fix BOARDCFG_MANAGED value.
- add MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST firmware capability.
- add MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST firmware capability.
- Link to v3: https://lore.kernel.org/r/20251205-ti-sci-jacinto-s2r-restore-irq-v3-0-d06963974ad4@bootlin.com
Changes in v3:
- rebased on linux-next
- sci-clk: context_restore() operation restores also rate.
- Link to v2: https://lore.kernel.org/r/20251127-ti-sci-jacinto-s2r-restore-irq-v2-0-a487fa3ff221@bootlin.com
Changes in v2:
- ti_sci: use hlist to store IRQs.
- sci-clk: add context_restore operation
- ti_sci: restore clock parents during resume
- Link to v1: https://lore.kernel.org/r/20251017-ti-sci-jacinto-s2r-restore-irq-v1-0-34d4339d247a@bootlin.com
---
Thomas Richard (TI) (4):
firmware: ti_sci: add BOARDCFG_MANAGED mode support
firmware: ti_sci: add support for restoring IRQs during resume
clk: keystone: sci-clk: add restore_context() operation
firmware: ti_sci: add support for restoring clock context during resume
drivers/clk/keystone/sci-clk.c | 42 +++++++++--
drivers/firmware/ti_sci.c | 164 ++++++++++++++++++++++++++++++++++++++---
drivers/firmware/ti_sci.h | 6 ++
3 files changed, 192 insertions(+), 20 deletions(-)
---
base-commit: d843b67129e266054d8fa2e41e270a9f779381bd
change-id: 20251010-ti-sci-jacinto-s2r-restore-irq-428e008fd10c
Best regards,
--
Thomas Richard (TI) <thomas.richard@bootlin.com>
^ permalink raw reply
* Re: (subset) [PATCH v5 0/4] ARM: omap1: use real firmware node lookup for GPIOs on Nokia 770
From: Andy Shevchenko @ 2026-04-07 14:16 UTC (permalink / raw)
To: Danilo Krummrich
Cc: Bartosz Golaszewski, Greg Kroah-Hartman, Rafael J. Wysocki,
Daniel Scally, Heikki Krogerus, Sakari Ailus, Aaro Koskinen,
Janusz Krzysztofik, Tony Lindgren, Russell King, Dmitry Torokhov,
Kevin Hilman, Arnd Bergmann, brgl, driver-core, linux-kernel,
linux-acpi, linux-arm-kernel, linux-omap
In-Reply-To: <DHKF135KLNW5.3LT0J6T5TE3JD@kernel.org>
On Sat, Apr 04, 2026 at 03:47:24PM +0200, Danilo Krummrich wrote:
> On Thu Apr 2, 2026 at 4:15 PM CEST, Bartosz Golaszewski wrote:
> [ Fix typo in the commit message: "s/merci/mercy/". - Danilo ]
Depends if Bart used French to sound that genuine.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2] iio: adc: xilinx-xadc: Fix sequencer mode in postdisable for dual mux
From: Christofer Jonason @ 2026-04-07 14:13 UTC (permalink / raw)
To: Erim, Salih, Simek, Michal, Jonathan Cameron,
O'Griofa, Conall
Cc: lars@metafoo.de, dlechner@baylibre.com, nuno.sa@analog.com,
andy@kernel.org, Victor Jonsson, linux-iio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
In-Reply-To: <IA1PR12MB7736AE6EEE95D5D184A15B9F9F50A@IA1PR12MB7736.namprd12.prod.outlook.com>
Hi Salih,
Thanks for the review.
Tested on a custom Zynq-7030 board with two TMUX1308APWR analog
multiplexers in dual external mux configuration. The XADC is
instantiated as an AXI XADC Wizard IP with xlnx,external-mux
set to "dual" and xlnx,external-mux-channel set to 1.
Verified by reading all 16 external mux channels via sysfs
(in_voltageN_raw) and comparing against known reference voltages
on the board. Before the fix, channels routed through ADC-B
returned incorrect values. After the fix, all channels return
the expected voltages matching the board schematic.
Thanks,
Christofer
________________________________________
From: Erim, Salih <Salih.Erim@amd.com>
Sent: Wednesday, April 1, 2026 3:11 PM
To: Simek, Michal <michal.simek@amd.com>; Jonathan Cameron <jic23@kernel.org>; Christofer Jonason <christofer.jonason@guidelinegeo.com>; O'Griofa, Conall <conall.ogriofa@amd.com>
Cc: lars@metafoo.de <lars@metafoo.de>; dlechner@baylibre.com <dlechner@baylibre.com>; nuno.sa@analog.com <nuno.sa@analog.com>; andy@kernel.org <andy@kernel.org>; Victor Jonsson <victor.jonsson@guidelinegeo.com>; linux-iio@vger.kernel.org <linux-iio@vger.kernel.org>; linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; stable@vger.kernel.org <stable@vger.kernel.org>
Subject: RE: [PATCH v2] iio: adc: xilinx-xadc: Fix sequencer mode in postdisable for dual mux
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christofer,
The code change looks correct to me - it aligns postdisable with
preenable by reusing xadc_get_seq_mode(), and the scope is limited
to dual external mux configurations.
Since this is targeting stable, could you please share what hardware/board
this was tested on and how you verified that VAUX[8-15] channels
return correct data with the fix applied?
Reviewed-by: Salih Emin <salih.emin@amd.com>
Thanks,
Salih
> -----Original Message-----
> From: Simek, Michal <michal.simek@amd.com>
> Sent: Tuesday, March 10, 2026 7:43 AM
> To: Jonathan Cameron <jic23@kernel.org>; Christofer Jonason
> <christofer.jonason@guidelinegeo.com>; Erim, Salih <Salih.Erim@amd.com>;
> O'Griofa, Conall <conall.ogriofa@amd.com>
> Cc: lars@metafoo.de; dlechner@baylibre.com; nuno.sa@analog.com;
> andy@kernel.org; victor.jonsson@guidelinegeo.com; linux-iio@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> stable@vger.kernel.org
> Subject: Re: [PATCH v2] iio: adc: xilinx-xadc: Fix sequencer mode in postdisable
> for dual mux
>
> +Salih, Conall,
>
> On 3/7/26 13:41, Jonathan Cameron wrote:
> > On Wed, 4 Mar 2026 10:07:27 +0100
> > Christofer Jonason <christofer.jonason@guidelinegeo.com> wrote:
> >
> >> xadc_postdisable() unconditionally sets the sequencer to continuous
> >> mode. For dual external multiplexer configurations this is incorrect:
> >> simultaneous sampling mode is required so that ADC-A samples through
> >> the mux on VAUX[0-7] while ADC-B simultaneously samples through the
> >> mux on VAUX[8-15]. In continuous mode only ADC-A is active, so
> >> VAUX[8-15] channels return incorrect data.
> >>
> >> Since postdisable is also called from xadc_probe() to set the initial
> >> idle state, the wrong sequencer mode is active from the moment the
> >> driver loads.
> >>
> >> The preenable path already uses xadc_get_seq_mode() which returns
> >> SIMULTANEOUS for dual mux. Fix postdisable to do the same.
> >>
> >> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver")
> >> Cc: stable@vger.kernel.org
> >> Signed-off-by: Christofer Jonason
> >> <christofer.jonason@guidelinegeo.com>
> >
> > I'll leave this on list for a little longer as I'd really like a
> > confirmation of this one from the AMD Xilinx folk.
>
> Salih/Conall: Please look at this patch and provide your comment or tag.
>
> Thanks,
> Michal
^ permalink raw reply
* Re: [PATCH net-next v9 1/4] net: stmmac: Add DW25GMAC support in stmmac core driver
From: Russell King (Oracle) @ 2026-04-07 14:09 UTC (permalink / raw)
To: Jitendra Vegiraju
Cc: netdev, alexandre.torgue, davem, edumazet, kuba, pabeni,
mcoquelin.stm32, bcm-kernel-feedback-list, richardcochran, ast,
daniel, hawk, john.fastabend, rohan.g.thomas, linux-kernel,
linux-stm32, linux-arm-kernel, bpf, andrew+netdev, horms, sdf, me,
siyanteng, prabhakar.mahadev-lad.rj, weishangjuan, wens,
vladimir.oltean, lizhi2, boon.khai.ng, maxime.chevallier,
chenchuangyu, yangtiezhu, ovidiu.panait.rb, chenhuacai,
florian.fainelli, quic_abchauha
In-Reply-To: <20260402213629.1996133-2-jitendra.vegiraju@broadcom.com>
Not withstanding my comment about the other Synopsys xlgmac driver that
we have in the kernel...
On Thu, Apr 02, 2026 at 02:36:26PM -0700, Jitendra Vegiraju wrote:
> From: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com>
>
> The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for
> virtualization scalability. This is realized by decoupling physical DMA
> channels(PDMA) from potentially large number of virtual DMA channels(VDMA).
> The VDMAs provide software abstraction to driver that map to PDMAs for
> frame transmission and reception.
> Since 25GMAC is a derivative of XGMAC, majority of IP is common to both.
>
> To add support for the HDMA in 25GMAC, a new instance of dma_ops,
> dw25gmac400_dma_ops is introduced.
> To support the current needs, a simple one-to-one mapping of dw25gmac's
> logical VDMA (channel) to TC to PDMAs is used. Most of the other dma
> operation functions in existing dwxgamc2_dma.c file are reused whereever
Typo: dwxgmac2_dma.c
> applicable.
> Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core.
In a previous review, I questioned the use of DWMAC_CORE_25GMAC and
asked about its version numberspace. I believe you indicated that the
version numberspace is the same as the existing XGMAC core.
I'm going to question the value of adding DWMAC_CORE_25GMAC.
1. What is the value of splitting DWMAC_CORE_25GMAC from
DWMAC_CORE_XGMAC given that it's in the same versioning numberspace
as XGMAC, and most tests (via dwmac_is_xgmac()) test for XGMAC or
25GMAC?
2. Have you reviewed all the places that explicitly test for
DWMAC_CORE_XGMAC, looking at their "false" paths (for non-XGMAC
cores) to determine whether they are suitable? For example:
if (priv->plat->core_type == DWMAC_CORE_XGMAC)
ndev->max_mtu = XGMAC_JUMBO_LEN;
else if (priv->plat->enh_desc || priv->synopsys_id >= DWMAC_CORE_4_00)
ndev->max_mtu = JUMBO_LEN;
else
ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
XGMAC can handle a max MTU of 16368, but with your code using
DWMAC_CORE_25GMAC, we fall back to the next test, which tests the
IP version against 0x40, and uses a max MTU of 9000. Given that
DWMAC_CORE_4_00 is a different "version number space" this seems
wrong.
3. Looking at the MDIO code, this looks very wrong if you're
introducing DWMAC_CORE_25GMAC. Have you tested MDIO accesses?
dwxgmac2_setup() is called for DWMAC_CORE_XGMAC core-type. In
stmmac_mdio_register(), DWMAC_CORE_XGMAC uses different functions
for MDIO bus access for C22 and C45 from other cores - it uses the
stmmac_xgmac2_mdio_* functions.
These use stmmac_xgmac2_c45_format() and stmmac_xgmac2_c22_format()
to format the register values which do not depend on mii.*_mask, but
do use mii.address and mii.data for the register offsets. Thus, is
there any point to setting mii.addr_mask and mii.reg_mask ?
For non-DWMAC_CORE_XGMAC cores, we fall back to the stmmac_mdio_*()
functions, which for non-DWMAC_CORE_GMAC4 will only support Clause
22 access, not Clause 45 - which would be very strange for a 25G
core.
4. What about the feature printing in
stmmac_main.c::stmmac_dma_cap_show() ?
5. What about similar tests in stmmac_est.c and stmmac_ethtool.c ?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* [PATCH v2 4/6] perf arm_spe: Turn event name mappings into an array
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark,
Leo Yan
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
This is so we can have a single function that prints events and can be
used with multiple mappings from different CPUs. Remove any bit that was
printed so that later we can print out the remaining unknown impdef
bits.
No functional changes intended.
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
.../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 88 +++++++++++-----------
1 file changed, 43 insertions(+), 45 deletions(-)
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index 718022aecec3..67ca356100e5 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -277,6 +277,48 @@ static int arm_spe_pkt_out_string(int *err, char **buf_p, size_t *blen,
return ret;
}
+struct ev_string {
+ u8 event;
+ const char *desc;
+};
+
+static const struct ev_string common_ev_strings[] = {
+ { .event = EV_EXCEPTION_GEN, .desc = "EXCEPTION-GEN" },
+ { .event = EV_RETIRED, .desc = "RETIRED" },
+ { .event = EV_L1D_ACCESS, .desc = "L1D-ACCESS" },
+ { .event = EV_L1D_REFILL, .desc = "L1D-REFILL" },
+ { .event = EV_TLB_ACCESS, .desc = "TLB-ACCESS" },
+ { .event = EV_TLB_WALK, .desc = "TLB-REFILL" },
+ { .event = EV_NOT_TAKEN, .desc = "NOT-TAKEN" },
+ { .event = EV_MISPRED, .desc = "MISPRED" },
+ { .event = EV_LLC_ACCESS, .desc = "LLC-ACCESS" },
+ { .event = EV_LLC_MISS, .desc = "LLC-REFILL" },
+ { .event = EV_REMOTE_ACCESS, .desc = "REMOTE-ACCESS" },
+ { .event = EV_ALIGNMENT, .desc = "ALIGNMENT" },
+ { .event = EV_TRANSACTIONAL, .desc = "TXN" },
+ { .event = EV_PARTIAL_PREDICATE, .desc = "SVE-PARTIAL-PRED" },
+ { .event = EV_EMPTY_PREDICATE, .desc = "SVE-EMPTY-PRED" },
+ { .event = EV_L2D_ACCESS, .desc = "L2D-ACCESS" },
+ { .event = EV_L2D_MISS, .desc = "L2D-MISS" },
+ { .event = EV_CACHE_DATA_MODIFIED, .desc = "HITM" },
+ { .event = EV_RECENTLY_FETCHED, .desc = "LFB" },
+ { .event = EV_DATA_SNOOPED, .desc = "SNOOPED" },
+ { .event = EV_STREAMING_SVE_MODE, .desc = "STREAMING-SVE" },
+ { .event = EV_SMCU, .desc = "SMCU" },
+ { .event = 0, .desc = NULL },
+};
+
+static u64 print_event_list(int *err, char **buf, size_t *buf_len,
+ const struct ev_string *ev_strings, u64 payload)
+{
+ for (const struct ev_string *ev = ev_strings; ev->desc != NULL; ev++) {
+ if (payload & BIT_ULL(ev->event))
+ arm_spe_pkt_out_string(err, buf, buf_len, " %s", ev->desc);
+ payload &= ~BIT_ULL(ev->event);
+ }
+ return payload;
+}
+
static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
char *buf, size_t buf_len)
{
@@ -284,51 +326,7 @@ static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
int err = 0;
arm_spe_pkt_out_string(&err, &buf, &buf_len, "EV");
-
- if (payload & BIT(EV_EXCEPTION_GEN))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " EXCEPTION-GEN");
- if (payload & BIT(EV_RETIRED))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " RETIRED");
- if (payload & BIT(EV_L1D_ACCESS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " L1D-ACCESS");
- if (payload & BIT(EV_L1D_REFILL))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " L1D-REFILL");
- if (payload & BIT(EV_TLB_ACCESS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " TLB-ACCESS");
- if (payload & BIT(EV_TLB_WALK))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " TLB-REFILL");
- if (payload & BIT(EV_NOT_TAKEN))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " NOT-TAKEN");
- if (payload & BIT(EV_MISPRED))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " MISPRED");
- if (payload & BIT(EV_LLC_ACCESS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " LLC-ACCESS");
- if (payload & BIT(EV_LLC_MISS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " LLC-REFILL");
- if (payload & BIT(EV_REMOTE_ACCESS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " REMOTE-ACCESS");
- if (payload & BIT(EV_ALIGNMENT))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " ALIGNMENT");
- if (payload & BIT(EV_TRANSACTIONAL))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " TXN");
- if (payload & BIT(EV_PARTIAL_PREDICATE))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " SVE-PARTIAL-PRED");
- if (payload & BIT(EV_EMPTY_PREDICATE))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " SVE-EMPTY-PRED");
- if (payload & BIT(EV_L2D_ACCESS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " L2D-ACCESS");
- if (payload & BIT(EV_L2D_MISS))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " L2D-MISS");
- if (payload & BIT(EV_CACHE_DATA_MODIFIED))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " HITM");
- if (payload & BIT(EV_RECENTLY_FETCHED))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " LFB");
- if (payload & BIT(EV_DATA_SNOOPED))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " SNOOPED");
- if (payload & BIT(EV_STREAMING_SVE_MODE))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " STREAMING-SVE");
- if (payload & BIT(EV_SMCU))
- arm_spe_pkt_out_string(&err, &buf, &buf_len, " SMCU");
+ print_event_list(&err, &buf, &buf_len, common_ev_strings, payload);
return err;
}
--
2.34.1
^ permalink raw reply related
* [PATCH v2 5/6] perf arm_spe: Decode Arm N1 IMPDEF events
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
From the TRM [1], N1 has one IMPDEF event which isn't covered by the
common list. Add a framework so that more cores can be added in the
future and that the N1 IMPDEF event can be decoded. Also increase the
size of the buffer because we're adding more strings and if it gets
truncated it falls back to a hex dump only.
[1]: https://developer.arm.com/documentation/100616/0401/Statistical-Profiling-Extension/implementation-defined-features-of-SPE
Suggested-by: Al Grant <al.grant@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
tools/perf/util/arm-spe-decoder/Build | 2 ++
.../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 39 +++++++++++++++++++++-
.../util/arm-spe-decoder/arm-spe-pkt-decoder.h | 2 +-
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/tools/perf/util/arm-spe-decoder/Build b/tools/perf/util/arm-spe-decoder/Build
index ab500e0efe24..97a298d1e279 100644
--- a/tools/perf/util/arm-spe-decoder/Build
+++ b/tools/perf/util/arm-spe-decoder/Build
@@ -1 +1,3 @@
perf-util-y += arm-spe-pkt-decoder.o arm-spe-decoder.o
+
+CFLAGS_arm-spe-pkt-decoder.o += -I$(srctree)/tools/arch/arm64/include/ -I$(OUTPUT)arch/arm64/include/generated/
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index 67ca356100e5..b74f887a48f2 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -15,6 +15,8 @@
#include "arm-spe-pkt-decoder.h"
+#include "../../arm64/include/asm/cputype.h"
+
static const char * const arm_spe_packet_name[] = {
[ARM_SPE_PAD] = "PAD",
[ARM_SPE_END] = "END",
@@ -308,6 +310,11 @@ static const struct ev_string common_ev_strings[] = {
{ .event = 0, .desc = NULL },
};
+static const struct ev_string n1_event_strings[] = {
+ { .event = 12, .desc = "LATE-PREFETCH" },
+ { .event = 0, .desc = NULL },
+};
+
static u64 print_event_list(int *err, char **buf, size_t *buf_len,
const struct ev_string *ev_strings, u64 payload)
{
@@ -319,6 +326,26 @@ static u64 print_event_list(int *err, char **buf, size_t *buf_len,
return payload;
}
+struct event_print_handle {
+ const struct midr_range *midr_ranges;
+ const struct ev_string *ev_strings;
+};
+
+#define EV_PRINT(range, strings) \
+ { \
+ .midr_ranges = range, \
+ .ev_strings = strings, \
+ }
+
+static const struct midr_range n1_event_encoding_cpus[] = {
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
+ {},
+};
+
+static const struct event_print_handle event_print_handles[] = {
+ EV_PRINT(n1_event_encoding_cpus, n1_event_strings),
+};
+
static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
char *buf, size_t buf_len)
{
@@ -326,7 +353,17 @@ static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
int err = 0;
arm_spe_pkt_out_string(&err, &buf, &buf_len, "EV");
- print_event_list(&err, &buf, &buf_len, common_ev_strings, payload);
+ payload = print_event_list(&err, &buf, &buf_len, common_ev_strings,
+ payload);
+
+ /* Try to decode IMPDEF bits for known CPUs */
+ for (unsigned int i = 0; i < ARRAY_SIZE(event_print_handles); i++) {
+ if (is_midr_in_range_list(packet->midr,
+ event_print_handles[i].midr_ranges))
+ payload = print_event_list(&err, &buf, &buf_len,
+ event_print_handles[i].ev_strings,
+ payload);
+ }
return err;
}
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
index a457821f3bcc..a3300bec4990 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
@@ -11,7 +11,7 @@
#include <stddef.h>
#include <stdint.h>
-#define ARM_SPE_PKT_DESC_MAX 256
+#define ARM_SPE_PKT_DESC_MAX 512
#define ARM_SPE_NEED_MORE_BYTES -1
#define ARM_SPE_BAD_PACKET -2
--
2.34.1
^ permalink raw reply related
* [PATCH v2 6/6] perf arm_spe: Print remaining IMPDEF event numbers
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
Any IMPDEF events not printed out from a known core's IMPDEF list or for
a completely unknown core will still not be shown to the user. Fix this
by printing the remaining bits as comma separated raw numbers, e.g.
"IMPDEF:1,2,3,4".
Suggested-by: Al Grant <al.grant@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index b74f887a48f2..c65b22a2179c 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -8,6 +8,7 @@
#include <string.h>
#include <endian.h>
#include <byteswap.h>
+#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <stdarg.h>
#include <linux/kernel.h>
@@ -365,6 +366,23 @@ static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
payload);
}
+ /*
+ * Print remaining IMPDEF bits that weren't printed above as raw
+ * "IMPDEF:1,2,3,4" etc.
+ */
+ if (payload) {
+ int i;
+
+ arm_spe_pkt_out_string(&err, &buf, &buf_len, " IMPDEF:");
+ for_each_set_bit(i, &payload, 64) {
+ const char *sep = payload & (payload - 1) ? "," : "";
+
+ arm_spe_pkt_out_string(&err, &buf, &buf_len, "%d%s", i,
+ sep);
+ payload &= ~BIT_ULL(i);
+ }
+ }
+
return err;
}
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/6] perf arm_spe: Store MIDR in arm_spe_pkt
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
The MIDR will affect printing of arm_spe_pkts, so store a copy of it
there. Technically it's constant for each decoder, but there is no
decoder when doing a raw dump, so it has to be stored in every packet.
It will only be used in raw dump mode and not in normal decoding for
now, but to avoid any surprises, set MIDR properly on the decoder too.
Having both the MIDR and the arm_spe_pkt (which has a copy of it) in the
decoder seemed a bit weird, so remove arm_spe_pkt from the decoder. The
packet is only short lived anyway so probably shouldn't have been there
in the first place.
Signed-off-by: James Clark <james.clark@linaro.org>
---
tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 17 ++++++++++-------
tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 3 +--
.../perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 3 ++-
.../perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h | 3 ++-
tools/perf/util/arm-spe.c | 21 +++++++++++++++------
5 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
index 9e02b2bdd117..7a3a4815fd37 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c
@@ -120,7 +120,8 @@ static int arm_spe_get_data(struct arm_spe_decoder *decoder)
return decoder->len;
}
-static int arm_spe_get_next_packet(struct arm_spe_decoder *decoder)
+static int arm_spe_get_next_packet(struct arm_spe_decoder *decoder,
+ struct arm_spe_pkt *packet)
{
int ret;
@@ -134,7 +135,8 @@ static int arm_spe_get_next_packet(struct arm_spe_decoder *decoder)
}
ret = arm_spe_get_packet(decoder->buf, decoder->len,
- &decoder->packet);
+ packet, decoder->midr);
+
if (ret <= 0) {
/* Move forward for 1 byte */
decoder->buf += 1;
@@ -144,7 +146,7 @@ static int arm_spe_get_next_packet(struct arm_spe_decoder *decoder)
decoder->buf += ret;
decoder->len -= ret;
- } while (decoder->packet.type == ARM_SPE_PAD);
+ } while (packet->type == ARM_SPE_PAD);
return 1;
}
@@ -154,19 +156,20 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder)
int err;
int idx;
u64 payload, ip;
+ struct arm_spe_pkt packet;
memset(&decoder->record, 0x0, sizeof(decoder->record));
decoder->record.context_id = (u64)-1;
while (1) {
- err = arm_spe_get_next_packet(decoder);
+ err = arm_spe_get_next_packet(decoder, &packet);
if (err <= 0)
return err;
- idx = decoder->packet.index;
- payload = decoder->packet.payload;
+ idx = packet.index;
+ payload = packet.payload;
- switch (decoder->packet.type) {
+ switch (packet.type) {
case ARM_SPE_TIMESTAMP:
decoder->record.timestamp = payload;
return 1;
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
index 3310e05122f0..0cbcb501edc9 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
@@ -147,8 +147,7 @@ struct arm_spe_decoder {
const unsigned char *buf;
size_t len;
-
- struct arm_spe_pkt packet;
+ u64 midr;
};
struct arm_spe_decoder *arm_spe_decoder_new(struct arm_spe_params *params);
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index 5769ba2f4140..718022aecec3 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -222,11 +222,12 @@ static int arm_spe_do_get_packet(const unsigned char *buf, size_t len,
}
int arm_spe_get_packet(const unsigned char *buf, size_t len,
- struct arm_spe_pkt *packet)
+ struct arm_spe_pkt *packet, u64 midr)
{
int ret;
ret = arm_spe_do_get_packet(buf, len, packet);
+ packet->midr = midr;
/* put multiple consecutive PADs on the same line, up to
* the fixed-width output format of 16 bytes per line.
*/
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
index adf4cde320aa..a457821f3bcc 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
@@ -35,6 +35,7 @@ struct arm_spe_pkt {
enum arm_spe_pkt_type type;
unsigned char index;
uint64_t payload;
+ uint64_t midr;
};
/* Short header (HEADER0) and extended header (HEADER1) */
@@ -184,7 +185,7 @@ enum arm_spe_events {
const char *arm_spe_pkt_name(enum arm_spe_pkt_type);
int arm_spe_get_packet(const unsigned char *buf, size_t len,
- struct arm_spe_pkt *packet);
+ struct arm_spe_pkt *packet, u64 midr);
int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, size_t len);
#endif
diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index fc11f32e4911..7fb33fe27693 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -134,8 +134,10 @@ struct data_source_handle {
.ds_synth = arm_spe__synth_##func, \
}
+static int arm_spe__get_midr(struct arm_spe *spe, int cpu, u64 *midr);
+
static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
- unsigned char *buf, size_t len)
+ unsigned char *buf, size_t len, u64 midr)
{
struct arm_spe_pkt packet;
size_t pos = 0;
@@ -148,7 +150,8 @@ static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
len);
while (len) {
- ret = arm_spe_get_packet(buf, len, &packet);
+ ret = arm_spe_get_packet(buf, len, &packet, midr);
+
if (ret > 0)
pkt_len = ret;
else
@@ -174,10 +177,10 @@ static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
}
static void arm_spe_dump_event(struct arm_spe *spe, unsigned char *buf,
- size_t len)
+ size_t len, u64 midr)
{
printf(".\n");
- arm_spe_dump(spe, buf, len);
+ arm_spe_dump(spe, buf, len, midr);
}
static int arm_spe_get_trace(struct arm_spe_buffer *b, void *data)
@@ -302,8 +305,10 @@ static void arm_spe_set_pid_tid_cpu(struct arm_spe *spe,
if (speq->thread) {
speq->pid = thread__pid(speq->thread);
- if (queue->cpu == -1)
+ if (queue->cpu == -1) {
speq->cpu = thread__cpu(speq->thread);
+ arm_spe__get_midr(spe, speq->cpu, &speq->decoder->midr);
+ }
}
}
@@ -1234,6 +1239,7 @@ static int arm_spe__setup_queue(struct arm_spe *spe,
if (queue->cpu != -1)
speq->cpu = queue->cpu;
+ arm_spe__get_midr(spe, queue->cpu, &speq->decoder->midr);
if (!speq->on_heap) {
int ret;
@@ -1476,8 +1482,11 @@ static int arm_spe_process_auxtrace_event(struct perf_session *session,
/* Dump here now we have copied a piped trace out of the pipe */
if (dump_trace) {
if (auxtrace_buffer__get_data(buffer, fd)) {
+ u64 midr = 0;
+
+ arm_spe__get_midr(spe, buffer->cpu.cpu, &midr);
arm_spe_dump_event(spe, buffer->data,
- buffer->size);
+ buffer->size, midr);
auxtrace_buffer__put_data(buffer);
}
}
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/6] perf arm_spe: Handle missing CPU IDs
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
Don't call strtol() with a null pointer to avoid undefined behavior.
I'm not sure of the exact scenario for missing CPU IDs but I don't think
it happens in practice. SPE decoding can continue without them with
reduced functionality, but print an error message anyway.
Signed-off-by: James Clark <james.clark@linaro.org>
---
tools/perf/util/arm-spe.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 7447b000f9cd..fc11f32e4911 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -968,16 +968,23 @@ static int arm_spe__get_midr(struct arm_spe *spe, int cpu, u64 *midr)
pr_warning_once("Old SPE metadata, re-record to improve decode accuracy\n");
cpuid = perf_env__cpuid(perf_session__env(spe->session));
+ if (!cpuid)
+ goto err;
+
*midr = strtol(cpuid, NULL, 16);
return 0;
}
metadata = arm_spe__get_metadata_by_cpu(spe, cpu);
if (!metadata)
- return -EINVAL;
+ goto err;
*midr = metadata[ARM_SPE_CPU_MIDR];
return 0;
+
+err:
+ pr_err("Failed to get MIDR for CPU %d\n", cpu);
+ return -EINVAL;
}
static void arm_spe__synth_ds(struct arm_spe_queue *speq,
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/6] perf arm_spe: Make a function to get the MIDR
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark,
Leo Yan
In-Reply-To: <20260407-james-spe-impdef-decode-v2-0-55d3ef997c48@linaro.org>
We'll need the MIDR to dump IMPDEF events in the next commits so extract
a function for it.
No functional changes intended.
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
tools/perf/util/arm-spe.c | 36 ++++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 70dd9bee47c7..7447b000f9cd 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -958,14 +958,9 @@ static void arm_spe__synth_memory_level(struct arm_spe_queue *speq,
}
}
-static void arm_spe__synth_ds(struct arm_spe_queue *speq,
- const struct arm_spe_record *record,
- union perf_mem_data_src *data_src)
+static int arm_spe__get_midr(struct arm_spe *spe, int cpu, u64 *midr)
{
- struct arm_spe *spe = speq->spe;
- u64 *metadata = NULL;
- u64 midr;
- unsigned int i;
+ u64 *metadata;
/* Metadata version 1 assumes all CPUs are the same (old behavior) */
if (spe->metadata_ver == 1) {
@@ -973,15 +968,28 @@ static void arm_spe__synth_ds(struct arm_spe_queue *speq,
pr_warning_once("Old SPE metadata, re-record to improve decode accuracy\n");
cpuid = perf_env__cpuid(perf_session__env(spe->session));
- midr = strtol(cpuid, NULL, 16);
- } else {
- metadata = arm_spe__get_metadata_by_cpu(spe, speq->cpu);
- if (!metadata)
- return;
-
- midr = metadata[ARM_SPE_CPU_MIDR];
+ *midr = strtol(cpuid, NULL, 16);
+ return 0;
}
+ metadata = arm_spe__get_metadata_by_cpu(spe, cpu);
+ if (!metadata)
+ return -EINVAL;
+
+ *midr = metadata[ARM_SPE_CPU_MIDR];
+ return 0;
+}
+
+static void arm_spe__synth_ds(struct arm_spe_queue *speq,
+ const struct arm_spe_record *record,
+ union perf_mem_data_src *data_src)
+{
+ u64 midr;
+ unsigned int i;
+
+ if (arm_spe__get_midr(speq->spe, speq->cpu, &midr))
+ return;
+
for (i = 0; i < ARRAY_SIZE(data_source_handles); i++) {
if (is_midr_in_range_list(midr, data_source_handles[i].midr_ranges)) {
return data_source_handles[i].ds_synth(record, data_src);
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/6] perf arm_spe: Dump IMPDEF events
From: James Clark @ 2026-04-07 14:05 UTC (permalink / raw)
To: John Garry, Will Deacon, Mike Leach, Leo Yan, Peter Zijlstra,
Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Al Grant
Cc: linux-arm-kernel, linux-perf-users, linux-kernel, James Clark,
Leo Yan
In the Arm SPE raw data dump, IMPDEF events aren't printed. Add the
ability to add names for some known events or print the raw event number
for unknown events.
For example:
$ perf report -D
... ARM SPE data: size 0xd000 bytes
00000000: b0 18 c6 32 80 00 80 ff a0 PC 0xff80008032c618 el1 ns=1
00000009: 64 e7 42 00 00 CONTEXT 0x42e7 el1
0000000e: 00 00 00 00 00 PAD
00000013: 49 00 LD GP-REG
00000015: 52 16 10 EV RETIRED L1D-ACCESS TLB-ACCESS
On N1 the event line becomes:
00000015: 52 16 10 EV RETIRED L1D-ACCESS TLB-ACCESS LATE-PREFETCH
Or on other cores it becomes:
00000015: 52 16 10 EV RETIRED L1D-ACCESS TLB-ACCESS IMPDEF:12
Signed-off-by: James Clark <james.clark@linaro.org>
---
Changes in v2:
- Put MIDR in arm_spe_pkt (Leo)
- Use for_each_set_bit() (Leo)
- Use BIT_ULL() to fix 32bit builds (Ian)
- Don't call strtol() with NULL (Ian)
- Link to v1: https://lore.kernel.org/r/20260401-james-spe-impdef-decode-v1-0-ad0d372c220c@linaro.org
---
James Clark (6):
perf arm_spe: Make a function to get the MIDR
perf arm_spe: Handle missing CPU IDs
perf arm_spe: Store MIDR in arm_spe_pkt
perf arm_spe: Turn event name mappings into an array
perf arm_spe: Decode Arm N1 IMPDEF events
perf arm_spe: Print remaining IMPDEF event numbers
tools/perf/util/arm-spe-decoder/Build | 2 +
tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 17 ++-
tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 3 +-
.../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 144 ++++++++++++++-------
.../util/arm-spe-decoder/arm-spe-pkt-decoder.h | 5 +-
tools/perf/util/arm-spe.c | 62 ++++++---
6 files changed, 158 insertions(+), 75 deletions(-)
---
base-commit: 74e2dbe7be5037a5e5eed6bc1ad562747ac88566
change-id: 20260331-james-spe-impdef-decode-d944f4fdcff7
Best regards,
--
James Clark <james.clark@linaro.org>
^ permalink raw reply
* Re: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset property in new Root Port binding
From: Manivannan Sadhasivam @ 2026-04-07 13:57 UTC (permalink / raw)
To: Sherry Sun
Cc: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, bhelgaas, hongxing.zhu, l.stach, imx,
linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260407104154.2842132-5-sherry.sun@nxp.com>
On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:
> The current DT binding for pci-imx6 specifies the 'reset-gpios' property
> in the host bridge node. However, the PERST# signal logically belongs to
> individual Root Ports rather than the host bridge itself. This becomes
> important when supporting PCIe KeyE connector and PCI power control
> framework for pci-imx6 driver, which requires properties to be specified
> in Root Port nodes.
>
> Add support for parsing 'reset-gpios' from Root Port child nodes using
> the common helper pci_host_common_parse_ports(), and update the reset
> GPIO handling to use the parsed port list from bridge->ports. To
> maintain DT backwards compatibility, fallback to the legacy method of
> parsing the host bridge node if the reset property is not present in the
> Root Port node.
>
> Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may be in
> input mode, using gpiod_direction_output() instead of
> gpiod_set_value_cansleep() to ensure the reset GPIO is properly
> configured as output before setting its value.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 75 +++++++++++++++++++++------
> 1 file changed, 60 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index d99da7e42590..dd8f9c0fcec4 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -34,6 +34,7 @@
> #include <linux/pm_runtime.h>
>
> #include "../../pci.h"
> +#include "../pci-host-common.h"
> #include "pcie-designware.h"
>
> #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
> @@ -152,7 +153,6 @@ struct imx_lut_data {
>
> struct imx_pcie {
> struct dw_pcie *pci;
> - struct gpio_desc *reset_gpiod;
> struct clk_bulk_data *clks;
> int num_clks;
> bool supports_clkreq;
> @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
> imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
> }
>
> +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
> +{
> + struct device *dev = pcie->pci->dev;
> + struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
> + struct pci_host_port *port;
> + struct gpio_desc *reset;
> +
> + reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
> + if (IS_ERR(reset))
> + return PTR_ERR(reset);
> +
> + if (!reset)
> + return 0;
> +
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + port->reset = reset;
> + INIT_LIST_HEAD(&port->list);
> + list_add_tail(&port->list, &bridge->ports);
> +
> + return devm_add_action_or_reset(dev, pci_host_common_delete_ports,
> + &bridge->ports);
> +}
> +
> static void imx_pcie_vpcie_aux_disable(void *data)
> {
> struct regulator *vpcie_aux = data;
> @@ -1233,13 +1259,22 @@ static void imx_pcie_vpcie_aux_disable(void *data)
>
> static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)
> {
> - if (assert) {
> - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
> - } else {
> - if (imx_pcie->reset_gpiod) {
> - msleep(PCIE_T_PVPERL_MS);
> - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
> - msleep(PCIE_RESET_CONFIG_WAIT_MS);
> + struct dw_pcie *pci = imx_pcie->pci;
> + struct pci_host_bridge *bridge = pci->pp.bridge;
> + struct pci_host_port *port;
> +
> + if (!bridge)
> + return;
> +
> + list_for_each_entry(port, &bridge->ports, list) {
> + if (assert) {
> + gpiod_direction_output(port->reset, 1);
> + } else {
> + if (port->reset) {
> + msleep(PCIE_T_PVPERL_MS);
> + gpiod_direction_output(port->reset, 0);
> + msleep(PCIE_RESET_CONFIG_WAIT_MS);
> + }
Sashiko flagged this loop:
```
Does this loop multiply the initialization delays?
If a controller has multiple Root Ports, the msleep calls will run
sequentially for each port, linearly increasing the delay. Could we optimize
this by asserting all reset GPIOs, waiting the pre-delay once, de-asserting
all GPIOs, and waiting the post-delay once for the entire bus?
```
Maybe you should do:
if (!list_empty(&bridge->ports) && !assert)
msleep(PCIE_T_PVPERL_MS);
list_for_each_entry(port, &bridge->ports, list) {
...
gpiod_direction_output(port->reset, 0);
...
}
if (!list_empty(&bridge->ports) && !assert)
msleep(PCIE_RESET_CONFIG_WAIT_MS);
And then this:
```
Also, since this function is called from imx_pcie_resume_noirq, which
executes with hardware interrupts disabled, does the use of msleep here
trigger a 'sleeping while atomic' bug?
```
This is a valid concern. You should use mdelay(). But I'd recommend
switching to IRQ enabled callback, resume() instead. There is no complelling
reason to use resume_noirq() in this driver and adding delays in noirq()
callbacks is not recommended as it may increase the overall system resume time.
I will submit a separate series to convert dw_pcie_resume_noirq() and its
callers to IRQ enabled callbacks since this dw_pcie_resume_noirq() could
potentially cause delay up to 1sec.
> }
> }
> }
> @@ -1249,8 +1284,25 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct device *dev = pci->dev;
> struct imx_pcie *imx_pcie = to_imx_pcie(pci);
> + struct pci_host_bridge *bridge = pp->bridge;
> int ret;
>
> + if (bridge && list_empty(&bridge->ports)) {
> + /* Parse Root Port nodes if present */
> + ret = pci_host_common_parse_ports(dev, bridge);
> + if (ret) {
> + if (ret != -ENOENT) {
> + dev_err(dev, "Failed to parse Root Port nodes: %d\n", ret);
> + return ret;
> + }
> +
> + /* Fallback to legacy binding for DT backwards compatibility */
> + ret = imx_pcie_parse_legacy_binding(imx_pcie);
This is also flagged by Sashiko:
```
Could this error handling corrupt the port state and trigger an invalid legacy
fallback?
If a device tree defines multiple Root Ports and one lacks the optional
reset GPIO, pci_host_common_parse_ports returns -ENOENT. This causes
the code to fall back to imx_pcie_parse_legacy_binding.
Since the already-parsed child ports remain in bridge->ports without
rollback, the legacy host bridge GPIO will be appended alongside them.
Valid child nodes are skipped, and both child and legacy GPIOs will be
toggled simultaneously.
```
You should try to cleanup Root Port resources if pci_host_common_parse_ports()
fails with -ENOENT.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* [PATCH 2/3] ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
From: Colin Huang @ 2026-04-07 13:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com>
This change introduces a development-phase devicetree for the
Facebook Anacapa BMC EVT1 hardware revision and updates the Anacapa
wrapper DTS to reference it.
A dedicated EVT1 DTS is added for revision-specific hardware while
keeping a single, Anacapa entrypoint used by the build and deployment
flow. The top-level aspeed-bmc-facebook-anacapa.dts
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1069 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1064 +------------------
2 files changed, 1070 insertions(+), 1063 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
new file mode 100644
index 000000000000..a29b7fa1155b
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
@@ -0,0 +1,1069 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc-evt1",
+ "facebook,anacapa-bmc",
+ "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ i2c16 = &i2c0mux0ch0;
+ i2c17 = &i2c0mux0ch1;
+ i2c18 = &i2c0mux0ch2;
+ i2c19 = &i2c0mux0ch3;
+ i2c20 = &i2c1mux0ch0;
+ i2c21 = &i2c1mux0ch1;
+ i2c22 = &i2c1mux0ch2;
+ i2c23 = &i2c1mux0ch3;
+ i2c24 = &i2c4mux0ch0;
+ i2c25 = &i2c4mux0ch1;
+ i2c26 = &i2c4mux0ch2;
+ i2c27 = &i2c4mux0ch3;
+ i2c28 = &i2c4mux0ch4;
+ i2c29 = &i2c4mux0ch5;
+ i2c30 = &i2c4mux0ch6;
+ i2c31 = &i2c4mux0ch7;
+ i2c32 = &i2c8mux0ch0;
+ i2c33 = &i2c8mux0ch1;
+ i2c34 = &i2c8mux0ch2;
+ i2c35 = &i2c8mux0ch3;
+ i2c36 = &i2c10mux0ch0;
+ i2c37 = &i2c10mux0ch1;
+ i2c38 = &i2c10mux0ch2;
+ i2c39 = &i2c10mux0ch3;
+ i2c40 = &i2c10mux0ch4;
+ i2c41 = &i2c10mux0ch5;
+ i2c42 = &i2c10mux0ch6;
+ i2c43 = &i2c10mux0ch7;
+ i2c44 = &i2c11mux0ch0;
+ i2c45 = &i2c11mux0ch1;
+ i2c46 = &i2c11mux0ch2;
+ i2c47 = &i2c11mux0ch3;
+ i2c48 = &i2c11mux0ch4;
+ i2c49 = &i2c11mux0ch5;
+ i2c50 = &i2c11mux0ch6;
+ i2c51 = &i2c11mux0ch7;
+ i2c52 = &i2c13mux0ch0;
+ i2c53 = &i2c13mux0ch1;
+ i2c54 = &i2c13mux0ch2;
+ i2c55 = &i2c13mux0ch3;
+ i2c56 = &i2c13mux0ch4;
+ i2c57 = &i2c13mux0ch5;
+ i2c58 = &i2c13mux0ch6;
+ i2c59 = &i2c13mux0ch7;
+ };
+
+ chosen {
+ stdout-path = "serial4:57600n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "bmc_heartbeat_amber";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "fp_id_amber";
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x02c00000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ p3v3_bmc_aux: regulator-p3v3-bmc-aux {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3_bmc_aux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spi_gpio: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&adc0 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+ status = "okay";
+};
+
+&adc1 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc10_default>;
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+
+ /*A0-A7*/
+ "","","","","","","","",
+
+ /*B0-B7*/
+ "BATTERY_DETECT", "", "", "BMC_READY",
+ "", "FM_ID_LED", "", "",
+
+ /*C0-C7*/
+ "","","","","","","","",
+
+ /*D0-D7*/
+ "","","","","","","","",
+
+ /*E0-E7*/
+ "","","","","","","","",
+
+ /*F0-F7*/
+ "","","","","","","","",
+
+ /*G0-G7*/
+ "FM_MUX1_SEL", "", "", "",
+ "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+
+ /*H0-H7*/
+ "","","","","","","","",
+
+ /*I0-I7*/
+ "", "", "", "",
+ "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
+
+ /*J0-J7*/
+ "","","","","","","","",
+
+ /*K0-K7*/
+ "","","","","","","","",
+
+ /*L0-L7*/
+ "","","","","","","","",
+
+ /*M0-M7*/
+ "", "BMC_FRU_WP", "", "",
+ "", "", "", "",
+
+ /*N0-N7*/
+ "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
+
+ /*O0-O7*/
+ "","","","","","","","",
+
+ /*P0-P7*/
+ "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
+ "PWR_LED", "", "", "BMC_HEARTBEAT_N",
+
+ /*Q0-Q7*/
+ "","","","","","","","",
+
+ /*R0-R7*/
+ "","","","","","","","",
+
+ /*S0-S7*/
+ "", "", "SYS_BMC_PWRBTN_N", "",
+ "", "", "", "RUN_POWER_FAULT",
+
+ /*T0-T7*/
+ "","","","","","","","",
+
+ /*U0-U7*/
+ "","","","","","","","",
+
+ /*V0-V7*/
+ "","","","","","","","",
+
+ /*W0-W7*/
+ "","","","","","","","",
+
+ /*X0-X7*/
+ "","","","","","","","",
+
+ /*Y0-Y7*/
+ "","","","","","","","",
+
+ /*Z0-Z7*/
+ "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
+ "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/
+ "","","","","","","","",
+
+ /*18B0-18B7*/
+ "","","","",
+ "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
+ "FM_BOARD_BMC_REV_ID2", "",
+
+ /*18C0-18C7*/
+ "","","","","","","","",
+
+ /*18D0-18D7*/
+ "","","","","","","","",
+
+ /*18E0-18E3*/
+ "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
+};
+
+// L Bridge Board
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c0mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// R Bridge Board
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c1mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// MB - E1.S
+&i2c4 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// AMC
+&i2c5 {
+ status = "okay";
+};
+
+// MB
+&i2c6 {
+ status = "okay";
+
+ // HPM FRU
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+// SCM
+&i2c7 {
+ status = "okay";
+
+
+};
+
+// MB - PDB
+&i2c8 {
+ status = "okay";
+
+ i2c-mux@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
+ "RPDB_FAN_CT_FAN_FAIL_R_N", "",
+ "", "",
+ "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
+ "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
+ "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
+ "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
+ "RPDB_PGD_P3V3_STBY_PWRGD_R",
+ "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
+ "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
+ "", "RPDB_FAN1_PRSNT_N_R",
+ "", "RPDB_FAN2_PRSNT_N_R",
+ "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
+ "", "";
+ };
+
+ // R-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
+ "LPDB_FAN_CT_FAN_FAIL_R_N","",
+ "","",
+ "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
+ "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
+ "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
+ "LPDB_PWRGD_P50V_HSC5_SYS_R","";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
+ "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
+ "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
+ "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
+ "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+
+ // L-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c8mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c9 {
+ status = "okay";
+
+ // SCM FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ // BSM FRU
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+// R Bridge Board
+&i2c10 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c10mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
+ "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
+ "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
+ "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // R Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c10mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// L Bridge Board
+&i2c11 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
+ "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
+ "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
+ "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // L Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c11mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// Debug Card
+&i2c12 {
+ status = "okay";
+};
+
+// MB
+&i2c13 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c13mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+ };
+ i2c13mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // HPM BRD ID FRU
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ };
+ };
+ i2c13mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&sgpiom0>;
+ interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+// SCM
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncsi3_default>;
+ use-ncsi;
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out - in - out */
+ /* A0-A7 line 0-15 */
+ "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
+ "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
+ "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
+ "", "", "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "",
+ "Channel5_leakage_EAM1", "",
+ "Channel6_leakage_CPU_DIMM", "",
+ "Channel7_leakage_EAM2", "",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "", "", "",
+ "", "", "", "",
+ "LEAK_DETECT_RMC_N", "", "", "",
+ "", "", "", "",
+
+ /* D0-D7 line 48-63 */
+ "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
+ "AMC_BRD_PRSNT_CPLD_L", "", "", "",
+ "", "", "", "",
+
+ /* E0-E7 line 64-79 */
+ "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* F0-F7 line 80-95 */
+ "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
+ "PWRGD_PVDDCR_CPU0_P0", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* G0-G7 line 96-111 */
+ "PWRGD_PVDDCR_SOC_P0", "",
+ "PWRGD_PVDDIO_P0", "",
+ "PWRGD_PVDDIO_MEM_S3_P0", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
+ "", "",
+
+ /* H0-H7 line 112-127 */
+ "PWRGD_P3V3", "",
+ "P12V_DDR_IP_PWRGD_R", "",
+ "P12V_DDR_AH_PWRGD_R", "",
+ "PWRGD_P12V_VRM1_CPLD_PG_R", "",
+ "PWRGD_P12V_VRM0_CPLD_PG_R", "",
+ "PWRGD_PDB_HSC4_CPLD_PG_R", "",
+ "PWRGD_PVDD18_S5_P0_PG", "",
+ "PWRGD_PVDD33_S5_P0_PG", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "EAM0_CPU_MOD_PWR_GD_R", "",
+ "EAM1_CPU_MOD_PWR_GD_R", "",
+ "EAM2_CPU_MOD_PWR_GD_R", "",
+ "EAM3_CPU_MOD_PWR_GD_R", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BIRDGE_R", "",
+ "PRSNT_R_BIRDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "", "", "", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "CPU0_SP7R1", "", "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "", "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "", "", "", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
+ "FM_CPU0_THERMTRIP_N", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "",
+ "FM_PWRGD_CPU0_PWROK", "",
+ "wS5_PWR_Ready", "",
+ "wS0_ON_N", "PWRGD_P1V0_AUX";
+ status = "okay";
+};
+
+// BIOS Flash
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ status = "okay";
+ reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "pnor";
+ spi-max-frequency = <12000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ status = "okay";
+ };
+};
+
+// HOST BIOS Debug
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+// BMC Debug Console
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&wdt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 2cb7bd128d24..980628af80b0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -1,1067 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
-#include "aspeed-g6.dtsi"
-#include <dt-bindings/gpio/aspeed-gpio.h>
-#include <dt-bindings/i2c/i2c.h>
+#include "aspeed-bmc-facebook-anacapa-evt1.dts"
-/ {
- model = "Facebook Anacapa BMC";
- compatible = "facebook,anacapa-bmc", "aspeed,ast2600";
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- i2c16 = &i2c0mux0ch0;
- i2c17 = &i2c0mux0ch1;
- i2c18 = &i2c0mux0ch2;
- i2c19 = &i2c0mux0ch3;
- i2c20 = &i2c1mux0ch0;
- i2c21 = &i2c1mux0ch1;
- i2c22 = &i2c1mux0ch2;
- i2c23 = &i2c1mux0ch3;
- i2c24 = &i2c4mux0ch0;
- i2c25 = &i2c4mux0ch1;
- i2c26 = &i2c4mux0ch2;
- i2c27 = &i2c4mux0ch3;
- i2c28 = &i2c4mux0ch4;
- i2c29 = &i2c4mux0ch5;
- i2c30 = &i2c4mux0ch6;
- i2c31 = &i2c4mux0ch7;
- i2c32 = &i2c8mux0ch0;
- i2c33 = &i2c8mux0ch1;
- i2c34 = &i2c8mux0ch2;
- i2c35 = &i2c8mux0ch3;
- i2c36 = &i2c10mux0ch0;
- i2c37 = &i2c10mux0ch1;
- i2c38 = &i2c10mux0ch2;
- i2c39 = &i2c10mux0ch3;
- i2c40 = &i2c10mux0ch4;
- i2c41 = &i2c10mux0ch5;
- i2c42 = &i2c10mux0ch6;
- i2c43 = &i2c10mux0ch7;
- i2c44 = &i2c11mux0ch0;
- i2c45 = &i2c11mux0ch1;
- i2c46 = &i2c11mux0ch2;
- i2c47 = &i2c11mux0ch3;
- i2c48 = &i2c11mux0ch4;
- i2c49 = &i2c11mux0ch5;
- i2c50 = &i2c11mux0ch6;
- i2c51 = &i2c11mux0ch7;
- i2c52 = &i2c13mux0ch0;
- i2c53 = &i2c13mux0ch1;
- i2c54 = &i2c13mux0ch2;
- i2c55 = &i2c13mux0ch3;
- i2c56 = &i2c13mux0ch4;
- i2c57 = &i2c13mux0ch5;
- i2c58 = &i2c13mux0ch6;
- i2c59 = &i2c13mux0ch7;
- };
-
- chosen {
- stdout-path = "serial4:57600n8";
- };
-
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
- <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
- <&adc1 2>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "bmc_heartbeat_amber";
- gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- label = "fp_id_amber";
- default-state = "off";
- gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- video_engine_memory: video {
- size = <0x02c00000>;
- alignment = <0x00100000>;
- compatible = "shared-dma-pool";
- reusable;
- };
-
- gfx_memory: framebuffer {
- size = <0x01000000>;
- alignment = <0x01000000>;
- compatible = "shared-dma-pool";
- reusable;
- };
- };
-
- p3v3_bmc_aux: regulator-p3v3-bmc-aux {
- compatible = "regulator-fixed";
- regulator-name = "p3v3_bmc_aux";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- spi_gpio: spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
- num-chipselects = <1>;
- status = "okay";
-
- tpm@0 {
- compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
- spi-max-frequency = <33000000>;
- reg = <0>;
- };
- };
-};
-
-&adc0 {
- aspeed,int-vref-microvolt = <2500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
- &pinctrl_adc2_default &pinctrl_adc3_default
- &pinctrl_adc4_default &pinctrl_adc5_default
- &pinctrl_adc6_default &pinctrl_adc7_default>;
- status = "okay";
-};
-
-&adc1 {
- aspeed,int-vref-microvolt = <2500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc10_default>;
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&fmc {
- status = "okay";
-
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
- spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-128.dtsi"
- };
-
- flash@1 {
- status = "okay";
- m25p,fast-read;
- label = "alt-bmc";
- spi-max-frequency = <50000000>;
- };
-};
-
-&gfx {
- status = "okay";
- memory-region = <&gfx_memory>;
-};
-
-&gpio0 {
- gpio-line-names =
-
- /*A0-A7*/
- "","","","","","","","",
-
- /*B0-B7*/
- "BATTERY_DETECT", "", "", "BMC_READY",
- "", "FM_ID_LED", "", "",
-
- /*C0-C7*/
- "","","","","","","","",
-
- /*D0-D7*/
- "","","","","","","","",
-
- /*E0-E7*/
- "","","","","","","","",
-
- /*F0-F7*/
- "","","","","","","","",
-
- /*G0-G7*/
- "FM_MUX1_SEL", "", "", "",
- "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
-
- /*H0-H7*/
- "","","","","","","","",
-
- /*I0-I7*/
- "", "", "", "",
- "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
-
- /*J0-J7*/
- "","","","","","","","",
-
- /*K0-K7*/
- "","","","","","","","",
-
- /*L0-L7*/
- "","","","","","","","",
-
- /*M0-M7*/
- "", "BMC_FRU_WP", "", "",
- "", "", "", "",
-
- /*N0-N7*/
- "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
- "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
-
- /*O0-O7*/
- "","","","","","","","",
-
- /*P0-P7*/
- "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
- "PWR_LED", "", "", "BMC_HEARTBEAT_N",
-
- /*Q0-Q7*/
- "","","","","","","","",
-
- /*R0-R7*/
- "","","","","","","","",
-
- /*S0-S7*/
- "", "", "SYS_BMC_PWRBTN_N", "",
- "", "", "", "RUN_POWER_FAULT",
-
- /*T0-T7*/
- "","","","","","","","",
-
- /*U0-U7*/
- "","","","","","","","",
-
- /*V0-V7*/
- "","","","","","","","",
-
- /*W0-W7*/
- "","","","","","","","",
-
- /*X0-X7*/
- "","","","","","","","",
-
- /*Y0-Y7*/
- "","","","","","","","",
-
- /*Z0-Z7*/
- "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
- "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
-};
-
-&gpio1 {
- gpio-line-names =
- /*18A0-18A7*/
- "","","","","","","","",
-
- /*18B0-18B7*/
- "","","","",
- "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
- "FM_BOARD_BMC_REV_ID2", "",
-
- /*18C0-18C7*/
- "","","","","","","","",
-
- /*18D0-18D7*/
- "","","","","","","","",
-
- /*18E0-18E3*/
- "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
-};
-
-// L Bridge Board
-&i2c0 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c2048";
- reg = <0x50>;
- pagesize = <128>;
- };
-
- i2c-mux@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c0mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// R Bridge Board
-&i2c1 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c2048";
- reg = <0x50>;
- pagesize = <128>;
- };
-
- i2c-mux@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c1mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// MB - E1.S
-&i2c4 {
- status = "okay";
-
- i2c-mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c4mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// AMC
-&i2c5 {
- status = "okay";
-};
-
-// MB
-&i2c6 {
- status = "okay";
-
- // HPM FRU
- eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
-
-// SCM
-&i2c7 {
- status = "okay";
-
-
-};
-
-// MB - PDB
-&i2c8 {
- status = "okay";
-
- i2c-mux@72 {
- compatible = "nxp,pca9546";
- reg = <0x72>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c8mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc@1f {
- compatible = "ti,adc128d818";
- reg = <0x1f>;
- ti,mode = /bits/ 8 <1>;
- };
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
- "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
- "RPDB_FAN_CT_FAN_FAIL_R_N", "",
- "", "",
- "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
- "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
- "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
- "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
- "RPDB_PGD_P3V3_STBY_PWRGD_R",
- "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
- };
-
- gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
- "RPDB_PWRGD_P50V_HSC4_SYS_R",
- "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
- "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
- "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
- "", "RPDB_FAN1_PRSNT_N_R",
- "", "RPDB_FAN2_PRSNT_N_R",
- "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
- "", "";
- };
-
- // R-PDB FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
- };
- i2c8mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
- "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
- "LPDB_FAN_CT_FAN_FAIL_R_N","",
- "","",
- "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
- "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
- "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
- "LPDB_PWRGD_P50V_HSC5_SYS_R","";
- };
-
- gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
- "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
- "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
- "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
- "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
- "","",
- "","",
- "","";
- };
-
- // L-PDB FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
- };
- i2c8mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c8mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// SCM
-&i2c9 {
- status = "okay";
-
- // SCM FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
-
- // BSM FRU
- eeprom@56 {
- compatible = "atmel,24c64";
- reg = <0x56>;
- };
-};
-
-// R Bridge Board
-&i2c10 {
- status = "okay";
-
- i2c-mux@71 {
- compatible = "nxp,pca9548";
- reg = <0x71>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c10mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "","",
- "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
- "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
- "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
- "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
- "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
- "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
- "","";
- };
-
- // R Bridge Board FRU
- eeprom@52 {
- compatible = "atmel,24c256";
- reg = <0x52>;
- };
- };
- i2c10mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// L Bridge Board
-&i2c11 {
- status = "okay";
-
- i2c-mux@71 {
- compatible = "nxp,pca9548";
- reg = <0x71>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c11mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "","",
- "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
- "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
- "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
- "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
- "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
- "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
- "","";
- };
-
- // L Bridge Board FRU
- eeprom@52 {
- compatible = "atmel,24c256";
- reg = <0x52>;
- };
- };
- i2c11mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// Debug Card
-&i2c12 {
- status = "okay";
-};
-
-// MB
-&i2c13 {
- status = "okay";
-
- i2c-mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c13mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc@1f {
- compatible = "ti,adc128d818";
- reg = <0x1f>;
- ti,mode = /bits/ 8 <1>;
- };
- };
- i2c13mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- // HPM BRD ID FRU
- eeprom@51 {
- compatible = "atmel,24c256";
- reg = <0x51>;
- };
- };
- i2c13mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- nfc@28 {
- compatible = "nxp,nxp-nci-i2c";
- reg = <0x28>;
-
- interrupt-parent = <&sgpiom0>;
- interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
-
- enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
- };
- };
- };
-};
-
-// SCM
-&i2c14 {
- status = "okay";
-};
-
-&i2c15 {
- status = "okay";
-};
-
-&kcs2 {
- aspeed,lpc-io-reg = <0xca8>;
- status = "okay";
-};
-
-&kcs3 {
- aspeed,lpc-io-reg = <0xca2>;
- status = "okay";
-};
-
-&lpc_ctrl {
- status = "okay";
-};
-
-&mac2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ncsi3_default>;
- use-ncsi;
-};
-
-&sgpiom0 {
- ngpios = <128>;
- bus-frequency = <2000000>;
- gpio-line-names =
- /*in - out - in - out */
- /* A0-A7 line 0-15 */
- "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
- "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
- "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
- "", "", "", "",
-
- /* B0-B7 line 16-31 */
- "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
- "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
- "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
- "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
- "Channel4_leakage_Manifold2", "",
- "Channel5_leakage_EAM1", "",
- "Channel6_leakage_CPU_DIMM", "",
- "Channel7_leakage_EAM2", "",
-
- /* C0-C7 line 32-47 */
- "RSVD_RMC_GPIO3", "", "", "",
- "", "", "", "",
- "LEAK_DETECT_RMC_N", "", "", "",
- "", "", "", "",
-
- /* D0-D7 line 48-63 */
- "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
- "AMC_BRD_PRSNT_CPLD_L", "", "", "",
- "", "", "", "",
-
- /* E0-E7 line 64-79 */
- "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
- "", "", "", "",
- "", "", "", "",
-
- /* F0-F7 line 80-95 */
- "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
- "PWRGD_PVDDCR_CPU0_P0", "",
- "", "", "", "",
- "", "", "", "",
-
- /* G0-G7 line 96-111 */
- "PWRGD_PVDDCR_SOC_P0", "",
- "PWRGD_PVDDIO_P0", "",
- "PWRGD_PVDDIO_MEM_S3_P0", "",
- "PWRGD_CHMP_CPU0_FPGA", "",
- "PWRGD_CHIL_CPU0_FPGA", "",
- "PWRGD_CHEH_CPU0_FPGA", "",
- "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
- "", "",
-
- /* H0-H7 line 112-127 */
- "PWRGD_P3V3", "",
- "P12V_DDR_IP_PWRGD_R", "",
- "P12V_DDR_AH_PWRGD_R", "",
- "PWRGD_P12V_VRM1_CPLD_PG_R", "",
- "PWRGD_P12V_VRM0_CPLD_PG_R", "",
- "PWRGD_PDB_HSC4_CPLD_PG_R", "",
- "PWRGD_PVDD18_S5_P0_PG", "",
- "PWRGD_PVDD33_S5_P0_PG", "",
-
- /* I0-I7 line 128-143 */
- "EAM0_BRD_PRSNT_R_L", "",
- "EAM1_BRD_PRSNT_R_L", "",
- "EAM2_BRD_PRSNT_R_L", "",
- "EAM3_BRD_PRSNT_R_L", "",
- "EAM0_CPU_MOD_PWR_GD_R", "",
- "EAM1_CPU_MOD_PWR_GD_R", "",
- "EAM2_CPU_MOD_PWR_GD_R", "",
- "EAM3_CPU_MOD_PWR_GD_R", "",
-
- /* J0-J7 line 144-159 */
- "PRSNT_L_BIRDGE_R", "",
- "PRSNT_R_BIRDGE_R", "",
- "BRIDGE_L_MAIN_PG_R", "",
- "BRIDGE_R_MAIN_PG_R", "",
- "BRIDGE_L_STBY_PG_R", "",
- "BRIDGE_R_STBY_PG_R", "",
- "", "", "", "",
-
- /* K0-K7 line 160-175 */
- "ADC_I2C_ALERT_N", "",
- "TEMP_I2C_ALERT_R_L", "",
- "CPU0_VR_SMB_ALERT_CPLD_N", "",
- "COVER_INTRUDER_R_N", "",
- "HANDLE_INTRUDER_CPLD_N", "",
- "IRQ_MCIO_CPLD_WAKE_R_N", "",
- "APML_CPU0_ALERT_R_N", "",
- "PDB_ALERT_R_N", "",
-
- /* L0-L7 line 176-191 */
- "CPU0_SP7R1", "", "CPU0_SP7R2", "",
- "CPU0_SP7R3", "", "CPU0_SP7R4", "",
- "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
- "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
-
- /* M0-M7 line 192-207 */
- "EAM0_SMERR_CPLD_R_L", "",
- "EAM1_SMERR_CPLD_R_L", "",
- "EAM2_SMERR_CPLD_R_L", "",
- "EAM3_SMERR_CPLD_R_L", "",
- "CPU0_SMERR_N_R", "",
- "CPU0_NV_SAVE_N_R", "",
- "PDB_PWR_LOSS_CPLD_N", "",
- "IRQ_BMC_SMI_ACTIVE_R_N", "",
-
- /* N0-N7 line 208-223 */
- "AMCROT_BMC_S5_RDY_R", "",
- "AMC_RDY_R", "",
- "AMC_STBY_PGOOD_R", "",
- "CPU_AMC_SLP_S5_R_L", "",
- "AMC_CPU_EAMPG_R", "",
- "", "", "", "",
-
- /* O0-O7 line 224-239 */
- "HPM_PWR_FAIL", "Port80_b0",
- "FM_DIMM_IP_FAIL", "Port80_b1",
- "FM_DIMM_AH_FAIL", "Port80_b2",
- "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
- "FM_CPU0_THERMTRIP_N", "Port80_b4",
- "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
- "CPLD_SGPIO_RDY", "Port80_b6",
- "", "Port80_b7",
-
- /* P0-P7 line 240-255 */
- "CPU0_SLP_S5_N_R", "NFC_VEN",
- "CPU0_SLP_S3_N_R", "",
- "FM_CPU0_PWRGD", "",
- "PWRGD_RMC", "",
- "FM_RST_CPU0_RESET_N", "",
- "FM_PWRGD_CPU0_PWROK", "",
- "wS5_PWR_Ready", "",
- "wS0_ON_N", "PWRGD_P1V0_AUX";
- status = "okay";
-};
-
-// BIOS Flash
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2_default>;
- status = "okay";
- reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- label = "pnor";
- spi-max-frequency = <12000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- status = "okay";
- };
-};
-
-// HOST BIOS Debug
-&uart1 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-// BMC Debug Console
-&uart5 {
- status = "okay";
-};
-
-&uart_routing {
- status = "okay";
-};
-
-&uhci {
- status = "okay";
-};
-
-&vhub {
- status = "okay";
- pinctrl-names = "default";
-};
-
-&video {
- status = "okay";
- memory-region = <&video_engine_memory>;
-};
-
-&wdt1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdtrst1_default>;
- aspeed,reset-type = "soc";
- aspeed,external-signal;
- aspeed,ext-push-pull;
- aspeed,ext-active-high;
- aspeed,ext-pulse-duration = <256>;
- status = "okay";
-};
--
2.34.1
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: aspeed: anacapa: add EVT2 devicetree and update wrapper
From: Colin Huang @ 2026-04-07 13:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com>
Add a development-phase devicetree for the Facebook Anacapa BMC EVT2
hardware revision and update the Anacapa wrapper DTS to reference
it.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 1125 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +-
2 files changed, 1126 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
new file mode 100644
index 000000000000..665bcd010d3e
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
@@ -0,0 +1,1125 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc-evt2",
+ "facebook,anacapa-bmc",
+ "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ i2c16 = &i2c0mux0ch0;
+ i2c17 = &i2c0mux0ch1;
+ i2c18 = &i2c0mux0ch2;
+ i2c19 = &i2c0mux0ch3;
+ i2c20 = &i2c1mux0ch0;
+ i2c21 = &i2c1mux0ch1;
+ i2c22 = &i2c1mux0ch2;
+ i2c23 = &i2c1mux0ch3;
+ i2c24 = &i2c4mux0ch0;
+ i2c25 = &i2c4mux0ch1;
+ i2c26 = &i2c4mux0ch2;
+ i2c27 = &i2c4mux0ch3;
+ i2c28 = &i2c4mux0ch4;
+ i2c29 = &i2c4mux0ch5;
+ i2c30 = &i2c4mux0ch6;
+ i2c31 = &i2c4mux0ch7;
+ i2c32 = &i2c8mux0ch0;
+ i2c33 = &i2c8mux0ch1;
+ i2c34 = &i2c8mux0ch2;
+ i2c35 = &i2c8mux0ch3;
+ i2c36 = &i2c10mux0ch0;
+ i2c37 = &i2c10mux0ch1;
+ i2c38 = &i2c10mux0ch2;
+ i2c39 = &i2c10mux0ch3;
+ i2c40 = &i2c10mux0ch4;
+ i2c41 = &i2c10mux0ch5;
+ i2c42 = &i2c10mux0ch6;
+ i2c43 = &i2c10mux0ch7;
+ i2c44 = &i2c11mux0ch0;
+ i2c45 = &i2c11mux0ch1;
+ i2c46 = &i2c11mux0ch2;
+ i2c47 = &i2c11mux0ch3;
+ i2c48 = &i2c11mux0ch4;
+ i2c49 = &i2c11mux0ch5;
+ i2c50 = &i2c11mux0ch6;
+ i2c51 = &i2c11mux0ch7;
+ i2c52 = &i2c13mux0ch0;
+ i2c53 = &i2c13mux0ch1;
+ i2c54 = &i2c13mux0ch2;
+ i2c55 = &i2c13mux0ch3;
+ i2c56 = &i2c13mux0ch4;
+ i2c57 = &i2c13mux0ch5;
+ i2c58 = &i2c13mux0ch6;
+ i2c59 = &i2c13mux0ch7;
+ };
+
+ chosen {
+ stdout-path = "serial4:57600n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "bmc_heartbeat_amber";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "fp_id_amber";
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x02c00000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ p3v3_bmc_aux: regulator-p3v3-bmc-aux {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3_bmc_aux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spi_gpio: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&adc0 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+ status = "okay";
+};
+
+&adc1 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc10_default>;
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+
+ /*A0-A7*/
+ "","","","","","","","",
+
+ /*B0-B7*/
+ "BATTERY_DETECT", "",
+ "BMC_I2C1_FPGA_ALERT", "BMC_READY",
+ "IOEXP_INT_3V3", "FM_ID_LED",
+ "", "",
+
+ /*C0-C7*/
+ "","","","",
+ "PMBUS_REQ_N", "PSU_FW_UPDATE_REQ_N",
+ "", "",
+
+ /*D0-D7*/
+ "","","","","","","","",
+
+ /*E0-E7*/
+ "","","","","","","","",
+
+ /*F0-F7*/
+ "","","","","","","","",
+
+ /*G0-G7*/
+ "FM_MUX1_SEL", "",
+ "", "", "", "",
+ "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+
+ /*H0-H7*/
+ "","","","","","","","",
+
+ /*I0-I7*/
+ "","","","",
+ "", "FLASH_WP_STATUS",
+ "BMC_JTAG_MUX_SEL", "",
+
+ /*J0-J7*/
+ "","","","","","","","",
+
+ /*K0-K7*/
+ "","","","","","","","",
+
+ /*L0-L7*/
+ "","","","","","","","",
+
+ /*M0-M7*/
+ "PCIE_EP_RST_EN", "BMC_FRU_WP",
+ "SCM_HPM_STBY_RST_N", "SCM_HPM_STBY_EN",
+ "STBY_POWER_PG_3V3", "TH500_SHDN_OK",
+ "", "",
+
+ /*N0-N7*/
+ "LED_POSTCODE_0", "LED_POSTCODE_1",
+ "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5",
+ "LED_POSTCODE_6", "LED_POSTCODE_7",
+
+ /*O0-O7*/
+ "RUN_POWER_PG", "PWR_BRAKE",
+ "CHASSIS_AC_LOSS", "BSM_PRSNT_N",
+ "PSU_SMB_ALERT", "FM_TPM_PRSNT_0_N",
+ "PSU_FW_UPDATING_N", "",
+
+ /*P0-P7*/
+ "PWR_BTN_BMC_BUF_N", "IPEX_CABLE_PRSNT",
+ "ID_RST_BTN_BMC_N", "RST_BMC_RSTBTN_OUT_N",
+ "PWR_LED", "RUN_POWER_EN",
+ "SHDN_FORCE", "BMC_HEARTBEAT_N",
+
+ /*Q0-Q7*/
+ "IRQ_PCH_TPM_SPI_LV3_N", "USB_OC0_REAR_N",
+ "UART_MUX_SEL", "I2C_MUX_RESET",
+ "RSVD_NV_PLT_DETECT", "SPI_TPM_INT",
+ "CPU_JTAG_MUX_SELECT", "THERM_BB_OVERT",
+
+ /*R0-R7*/
+ "THERM_BB_WARN", "SPI_BMC_FPGA_INT",
+ "CPU_BOOT_DONE", "PMBUS_GNT",
+ "CHASSIS_PWR_BRK", "PCIE_WAKE",
+ "PDB_THERM_OVERT", "SHDN_REQ",
+
+ /*S0-S7*/
+ "", "",
+ "SYS_BMC_PWRBTN_N", "FM_TPM_PRSNT_1_N",
+ "FM_BMC_DEBUG_SW_N", "UID_LED_N",
+ "SYS_FAULT_LED_N", "RUN_POWER_FAULT",
+
+ /*T0-T7*/
+ "","","","","","","","",
+
+ /*U0-U7*/
+ "","","","","","","","",
+
+ /*V0-V7*/
+ "L2_RST_REQ_OUT", "L0L1_RST_REQ_OUT",
+ "BMC_ID_BEEP_SEL", "BMC_I2C0_FPGA_ALERT",
+ "SMB_BMC_TMP_ALERT", "PWR_LED_N",
+ "SYS_RST_OUT", "IRQ_TPM_SPI_N",
+
+ /*W0-W7*/
+ "","","","","","","","",
+
+ /*X0-X7*/
+ "","","","","","","","",
+
+ /*Y0-Y7*/
+ "RST_WDTRST_PLD_N", "RST_BMC_SELF_HW",
+ "FM_FLASH_LATCH_N", "BMC_EMMC_RST_N",
+ "","","","",
+
+ /*Z0-Z7*/
+ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/
+ "","","","","","","","",
+
+ /*18B0-18B7*/
+ "","","","",
+ "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
+ "FM_BOARD_BMC_REV_ID2", "",
+
+ /*18C0-18C7*/
+ "", "", "SPI_BMC_BIOS_ROM_IRQ0_N", "",
+ "", "", "", "",
+
+ /*18D0-18D7*/
+ "","","","","","","","",
+
+ /*18E0-18E3*/
+ "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
+};
+
+// L Bridge Board
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c0mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// R Bridge Board
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c1mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// MB - E1.S
+&i2c4 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// AMC
+&i2c5 {
+ status = "okay";
+};
+
+// MB
+&i2c6 {
+ status = "okay";
+
+ // HPM FRU
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+// SCM
+&i2c7 {
+ status = "okay";
+
+
+};
+
+// MB - PDB
+&i2c8 {
+ status = "okay";
+
+ i2c-mux@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
+ "RPDB_FAN_CT_FAN_FAIL_R_N", "",
+ "", "",
+ "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
+ "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
+ "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
+ "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
+ "RPDB_PGD_P3V3_STBY_PWRGD_R",
+ "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
+ "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
+ "", "RPDB_FAN1_PRSNT_N_R",
+ "", "RPDB_FAN2_PRSNT_N_R",
+ "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
+ "", "";
+ };
+
+ // R-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
+ "LPDB_FAN_CT_FAN_FAIL_R_N","",
+ "","",
+ "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
+ "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
+ "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
+ "LPDB_PWRGD_P50V_HSC5_SYS_R","";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
+ "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
+ "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
+ "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
+ "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+
+ // L-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c8mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c9 {
+ status = "okay";
+
+ // SCM FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ // BSM FRU
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+// R Bridge Board
+&i2c10 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c10mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
+ "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
+ "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
+ "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // R Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c10mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// L Bridge Board
+&i2c11 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
+ "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
+ "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
+ "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // L Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c11mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// Debug Card
+&i2c12 {
+ status = "okay";
+};
+
+// MB
+&i2c13 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c13mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+ };
+ i2c13mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // HPM BRD ID FRU
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ };
+ };
+ i2c13mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&sgpiom0>;
+ interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+// SCM
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncsi3_default>;
+ use-ncsi;
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out */
+ /* A0-A7 line 0-15 */
+ "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N",
+ "L_BNIC0_FLT", "CPU0_KBRST_N",
+ "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N",
+ "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0",
+ "L_BNIC3_FLT", "Force_I3C_SEL",
+ "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle",
+ "", "",
+ "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L",
+ "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L",
+ "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330",
+ "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "RTM_MUX_L",
+ "LEAK_DETECT_RMC_N", "RTM_MUX_R",
+ "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N",
+ "No_Leak_Sensor_flag", "whdt_sel",
+ "", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* D0-D7 line 48-63 */
+ "PWRGD_CHAD_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "AMC_BRD_PRSNT_CPLD_L", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* E0-E7 line 64-79 */
+ "L_PRSNT_B_FENIC_R2_N", "",
+ "L_PRSNT_B_BENIC0_R2_N", "",
+ "L_PRSNT_B_BENIC1_R2_N", "",
+ "L_PRSNT_B_BENIC2_R2_N", "",
+ "L_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* F0-F7 line 80-95 */
+ "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY",
+ "R_PRSNT_B_BENIC0_R2_N", "",
+ "R_PRSNT_B_BENIC1_R2_N", "",
+ "R_PRSNT_B_BENIC2_R2_N", "",
+ "R_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* G0-G7 line 96-111 */
+ "L_PRSNT_EDSFF2_N", "",
+ "L_PRSNT_EDSFF3_N", "",
+ "R_PRSNT_EDSFF2_N", "",
+ "R_PRSNT_EDSFF3_N", "",
+ "", "",
+ "", "",
+ "", "",
+ "PRSNT_NFC_BOARD_R", "",
+
+ /* H0-H7 line 112-127 */
+ "R_FNIC_FLT", "",
+ "R_BNIC0_FLT", "",
+ "R_BNIC1_FLT", "",
+ "R_BNIC2_FLT", "",
+ "R_BNIC3_FLT", "",
+ "R_RTM_SW_FLT", "",
+ "", "",
+ "", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "FM_TPM_PRSNT_R_N", "",
+ "PDB_PRSNT_R_N", "",
+ "PRSNT_EDSFF0_N", "",
+ "PRSNT_CPU0_N", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BRIDGE_R", "",
+ "PRSNT_R_BRIDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "IRQ_NFC_BOARD_R", "",
+ "RSMRST_N", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "CPU0_SP7R1", "",
+ "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "",
+ "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "",
+ "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "",
+ "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "DIMM_PMIC_PG_TIMEOUT", "",
+ "EAM_MOD_PWR_GD_TIMEOUT", "",
+ "CPLD_AMC_STBY_PWR_EN", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
+ "cpu_thermtrip_detect", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST",
+ "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST",
+ "AMC_FAIL", "HPM_CPLD_RISCV_RST",
+ "wS0_ON_N", "";
+ status = "okay";
+};
+
+// BIOS Flash
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ status = "okay";
+ reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "pnor";
+ spi-max-frequency = <12000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ status = "okay";
+ };
+};
+
+// HOST BIOS Debug
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+// BMC Debug Console
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&wdt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 980628af80b0..18b6a7525178 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
-#include "aspeed-bmc-facebook-anacapa-evt1.dts"
+#include "aspeed-bmc-facebook-anacapa-evt2.dts"
--
2.34.1
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 board
From: Colin Huang @ 2026-04-07 13:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com>
Document Anacapa BMC EVT1 and EVT2 compatibles.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 8ec7a3e74a21..c4b87c014941 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -84,6 +84,8 @@ properties:
- asus,ast2600-kommando-ipmi-card
- asus,x4tf-bmc
- facebook,anacapa-bmc
+ - facebook,anacapa-bmc-evt1
+ - facebook,anacapa-bmc-evt2
- facebook,bletchley-bmc
- facebook,catalina-bmc
- facebook,clemente-bmc
--
2.34.1
^ permalink raw reply related
* [PATCH 0/3] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
From: Colin Huang @ 2026-04-07 13:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
This series refactors the Anacapa BMC devicetree layout to better support
development-phase hardware revisions (EVT1/EVT2) while keeping a platform
entrypoint.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
Colin Huang (3):
dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 board
ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
ARM: dts: aspeed: anacapa: add EVT2 devicetree and update wrapper
.../devicetree/bindings/arm/aspeed/aspeed.yaml | 2 +
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1069 +++++++++++++++++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 1125 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1064 +-----------------
4 files changed, 2197 insertions(+), 1063 deletions(-)
---
base-commit: cd44dc5ead3042f2873244b0598e39a16dc7b940
change-id: 20260407-anacapa-devlop-phase-devicetree-4101d3f312c0
Best regards,
--
Colin Huang <u8813345@gmail.com>
^ permalink raw reply
* Re: [PATCH] arm64: clear_page[s] using memset
From: Catalin Marinas @ 2026-04-07 13:47 UTC (permalink / raw)
To: Linus Walleij
Cc: Will Deacon, Marc Zyngier, Oliver Upton, Joey Gouly,
Suzuki K Poulose, Zenghui Yu, linux-arm-kernel, kvmarm
In-Reply-To: <CAD++jL=G81=ueo7djqUETToE459kpFGniWvBwnYbJtmXrm8MFw@mail.gmail.com>
On Tue, Apr 07, 2026 at 11:25:55AM +0200, Linus Walleij wrote:
> Quoting my own commit message hehe:
>
> > No performance regressions can be seen, the fastpath
> > benchmarks differences are in the noise.
>
> This was tested on hardware with Ryan Robert's fastpath tool.
BTW, have you tried the perf bench mmap test again with the new
clear_page? Both with single page and multiple pages scenarios. And
ideally on more than one platform.
Will pointed out (in a private chat) that current clear_page() uses
non-temporal stores while memset() doesn't. It may not make any
difference in practice but it would be good to have some numbers.
--
Catalin
^ permalink raw reply
* Re: [PATCH] dmaengine: lpc18xx-dmamux: simplify allocation
From: Vladimir Zapolskiy @ 2026-04-07 13:46 UTC (permalink / raw)
To: Rosen Penev, dmaengine
Cc: Vinod Koul, Frank Li, Kees Cook, Gustavo A. R. Silva,
moderated list:ARM/LPC18XX ARCHITECTURE, open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be)?b
In-Reply-To: <20260407035132.99037-1-rosenp@gmail.com>
On 4/7/26 06:51, Rosen Penev wrote:
> Use a flexible array member to combine allocations. Requires
> preparation, aka reshuffling before the actual allocation to get the
> proper size.
>
> Add __counted_by for extra runtime analysis.
>
> Signed-off-by: Rosen Penev <rosenp@gmail.com>
> ---
> drivers/dma/lpc18xx-dmamux.c | 42 +++++++++++++++++-------------------
> 1 file changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/dma/lpc18xx-dmamux.c b/drivers/dma/lpc18xx-dmamux.c
> index d3ff521951b8..5dfefbc496da 100644
> --- a/drivers/dma/lpc18xx-dmamux.c
> +++ b/drivers/dma/lpc18xx-dmamux.c
> @@ -32,11 +32,11 @@ struct lpc18xx_dmamux {
>
> struct lpc18xx_dmamux_data {
> struct dma_router dmarouter;
> - struct lpc18xx_dmamux *muxes;
> u32 dma_master_requests;
> u32 dma_mux_requests;
> struct regmap *reg;
> spinlock_t lock;
> + struct lpc18xx_dmamux muxes[] __counted_by(dma_master_requests);
> };
>
> static void lpc18xx_dmamux_free(struct device *dev, void *route_data)
> @@ -122,12 +122,30 @@ static int lpc18xx_dmamux_probe(struct platform_device *pdev)
> {
> struct device_node *dma_np, *np = pdev->dev.of_node;
> struct lpc18xx_dmamux_data *dmamux;
> + u32 dma_master_requests;
> int ret;
>
> - dmamux = devm_kzalloc(&pdev->dev, sizeof(*dmamux), GFP_KERNEL);
> + dma_np = of_parse_phandle(np, "dma-masters", 0);
> + if (!dma_np) {
> + dev_err(&pdev->dev, "can't get dma master\n");
> + return -ENODEV;
> + }
> +
> + ret = of_property_read_u32(dma_np, "dma-requests",
> + &dma_master_requests);
> + of_node_put(dma_np);
> + if (ret) {
> + dev_err(&pdev->dev, "missing master dma-requests property\n");
> + return ret;
> + }
> +
> + dmamux = devm_kzalloc(&pdev->dev, struct_size(dmamux, muxes, dma_master_requests),
> + GFP_KERNEL);
> if (!dmamux)
> return -ENOMEM;
>
> + dmamux->dma_master_requests = dma_master_requests;
> +
> dmamux->reg = syscon_regmap_lookup_by_compatible("nxp,lpc1850-creg");
> if (IS_ERR(dmamux->reg)) {
> dev_err(&pdev->dev, "syscon lookup failed\n");
> @@ -141,26 +159,6 @@ static int lpc18xx_dmamux_probe(struct platform_device *pdev)
> return ret;
> }
>
> - dma_np = of_parse_phandle(np, "dma-masters", 0);
> - if (!dma_np) {
> - dev_err(&pdev->dev, "can't get dma master\n");
> - return -ENODEV;
> - }
> -
> - ret = of_property_read_u32(dma_np, "dma-requests",
> - &dmamux->dma_master_requests);
> - of_node_put(dma_np);
> - if (ret) {
> - dev_err(&pdev->dev, "missing master dma-requests property\n");
> - return ret;
> - }
> -
> - dmamux->muxes = devm_kcalloc(&pdev->dev, dmamux->dma_master_requests,
> - sizeof(struct lpc18xx_dmamux),
> - GFP_KERNEL);
> - if (!dmamux->muxes)
> - return -ENOMEM;
> -
> spin_lock_init(&dmamux->lock);
> platform_set_drvdata(pdev, dmamux);
> dmamux->dmarouter.dev = &pdev->dev;
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
--
Best wishes,
Vladimir
^ permalink raw reply
* Re: [PATCH] Bluetooth: Add Broadcom channel priority commands
From: Luiz Augusto von Dentz @ 2026-04-07 13:40 UTC (permalink / raw)
To: fnkl.kernel
Cc: Sven Peter, Janne Grunau, Neal Gompa, Marcel Holtmann,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, linux-kernel, asahi, linux-arm-kernel,
linux-bluetooth, netdev
In-Reply-To: <20260407-brcm-prio-v1-1-f38b17376640@gmail.com>
Hi,
On Tue, Apr 7, 2026 at 8:09 AM Sasha Finkelstein via B4 Relay
<devnull+fnkl.kernel.gmail.com@kernel.org> wrote:
>
> From: Sasha Finkelstein <fnkl.kernel@gmail.com>
>
> Certain Broadcom bluetooth chips (bcm4377/bcm4378/bcm438) need ACL
> streams carrying audio to be set as "high priority" using a vendor
> specific command to prevent 10-ish second-long dropouts whenever
> something does a device scan. This series adds an ioctl to control
> the priorities and hooks it up for the relevant chips.
>
> Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
> ---
> MAINTAINERS | 2 ++
> drivers/bluetooth/hci_bcm4377.c | 2 ++
> include/net/bluetooth/hci_core.h | 12 ++++++++++++
> include/net/bluetooth/hci_sock.h | 7 +++++++
> net/bluetooth/Kconfig | 7 +++++++
> net/bluetooth/Makefile | 1 +
> net/bluetooth/brcm.c | 29 +++++++++++++++++++++++++++++
> net/bluetooth/brcm.h | 17 +++++++++++++++++
> net/bluetooth/hci_conn.c | 11 +++++++++++
> net/bluetooth/hci_sock.c | 4 ++++
> 10 files changed, 92 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c3fe46d7c4bc..81be021367ec 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2562,6 +2562,8 @@ F: include/dt-bindings/pinctrl/apple.h
> F: include/linux/mfd/macsmc.h
> F: include/linux/soc/apple/*
> F: include/uapi/drm/asahi_drm.h
> +F: net/bluetooth/brcm.c
> +F: net/bluetooth/brcm.h
>
> ARM/ARTPEC MACHINE SUPPORT
> M: Jesper Nilsson <jesper.nilsson@axis.com>
> diff --git a/drivers/bluetooth/hci_bcm4377.c b/drivers/bluetooth/hci_bcm4377.c
> index 925d0a635945..5f79920c0306 100644
> --- a/drivers/bluetooth/hci_bcm4377.c
> +++ b/drivers/bluetooth/hci_bcm4377.c
> @@ -2397,6 +2397,8 @@ static int bcm4377_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (bcm4377->hw->broken_le_ext_adv_report_phy)
> hci_set_quirk(hdev, HCI_QUIRK_FIXUP_LE_EXT_ADV_REPORT_PHY);
>
> + hci_set_brcm_capable(hdev);
> +
> pci_set_drvdata(pdev, bcm4377);
> hci_set_drvdata(hdev, bcm4377);
> SET_HCIDEV_DEV(hdev, &pdev->dev);
> diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
> index a7bffb908c1e..ef3b5433203c 100644
> --- a/include/net/bluetooth/hci_core.h
> +++ b/include/net/bluetooth/hci_core.h
> @@ -642,6 +642,10 @@ struct hci_dev {
> bool aosp_quality_report;
> #endif
>
> +#if IS_ENABLED(CONFIG_BT_BRCMEXT)
> + bool brcm_capable;
> +#endif
> +
> int (*open)(struct hci_dev *hdev);
> int (*close)(struct hci_dev *hdev);
> int (*flush)(struct hci_dev *hdev);
> @@ -1791,6 +1795,13 @@ static inline void hci_set_aosp_capable(struct hci_dev *hdev)
> #endif
> }
>
> +static inline void hci_set_brcm_capable(struct hci_dev *hdev)
> +{
> +#if IS_ENABLED(CONFIG_BT_BRCMEXT)
> + hdev->brcm_capable = true;
> +#endif
> +}
> +
> static inline void hci_devcd_setup(struct hci_dev *hdev)
> {
> #ifdef CONFIG_DEV_COREDUMP
> @@ -1812,6 +1823,7 @@ int hci_get_conn_list(void __user *arg);
> int hci_get_conn_info(struct hci_dev *hdev, void __user *arg);
> int hci_get_auth_info(struct hci_dev *hdev, void __user *arg);
> int hci_inquiry(void __user *arg);
> +int hci_set_acl_prio(struct hci_dev *hdev, void __user *arg);
>
> struct bdaddr_list *hci_bdaddr_list_lookup(struct list_head *list,
> bdaddr_t *bdaddr, u8 type);
> diff --git a/include/net/bluetooth/hci_sock.h b/include/net/bluetooth/hci_sock.h
> index 13e8cd4414a1..95d156ac4cae 100644
> --- a/include/net/bluetooth/hci_sock.h
> +++ b/include/net/bluetooth/hci_sock.h
> @@ -91,6 +91,8 @@ struct hci_ufilter {
>
> #define HCIINQUIRY _IOR('H', 240, int)
>
> +#define HCISETACLPRIO _IOW('H', 250, int)
Nack, not going to introduce an ioctl command for this.
> /* Ioctl requests structures */
> struct hci_dev_stats {
> __u32 err_rx;
> @@ -171,6 +173,11 @@ struct hci_inquiry_req {
> __u8 length;
> __u8 num_rsp;
> };
> +
> +struct hci_acl_prio_req {
> + __u16 handle;
> + __u8 high_prio;
> +};
> #define IREQ_CACHE_FLUSH 0x0001
>
> #endif /* __HCI_SOCK_H */
> diff --git a/net/bluetooth/Kconfig b/net/bluetooth/Kconfig
> index 6b2b65a66700..0f2a5fbcafc5 100644
> --- a/net/bluetooth/Kconfig
> +++ b/net/bluetooth/Kconfig
> @@ -110,6 +110,13 @@ config BT_AOSPEXT
> This options enables support for the Android Open Source
> Project defined HCI vendor extensions.
>
> +config BT_BRCMEXT
> + bool "Enable Broadcom extensions"
> + depends on BT
> + help
> + This option enables support for the Broadcom defined HCI
> + vendor extensions.
> +
> config BT_DEBUGFS
> bool "Export Bluetooth internals in debugfs"
> depends on BT && DEBUG_FS
> diff --git a/net/bluetooth/Makefile b/net/bluetooth/Makefile
> index a7eede7616d8..b4c9013a46ce 100644
> --- a/net/bluetooth/Makefile
> +++ b/net/bluetooth/Makefile
> @@ -24,5 +24,6 @@ bluetooth-$(CONFIG_BT_LE) += iso.o
> bluetooth-$(CONFIG_BT_LEDS) += leds.o
> bluetooth-$(CONFIG_BT_MSFTEXT) += msft.o
> bluetooth-$(CONFIG_BT_AOSPEXT) += aosp.o
> +bluetooth-$(CONFIG_BT_BRCMEXT) += brcm.o
> bluetooth-$(CONFIG_BT_DEBUGFS) += hci_debugfs.o
> bluetooth-$(CONFIG_BT_SELFTEST) += selftest.o
> diff --git a/net/bluetooth/brcm.c b/net/bluetooth/brcm.c
> new file mode 100644
> index 000000000000..d03d2af5dc7e
> --- /dev/null
> +++ b/net/bluetooth/brcm.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2026 The Asahi Linux Contributors
> + */
> +
> +#include <net/bluetooth/bluetooth.h>
> +#include <net/bluetooth/hci_core.h>
> +
> +#include "brcm.h"
> +
> +int brcm_set_high_priority(struct hci_dev *hdev, u16 handle, bool enable)
> +{
> + struct sk_buff *skb;
> + u8 cmd[3];
> +
> + if (!hdev->brcm_capable)
> + return -EOPNOTSUPP;
> +
> + cmd[0] = handle;
> + cmd[1] = handle >> 8;
> + cmd[2] = !!enable;
> +
> + skb = hci_cmd_sync(hdev, 0xfc57, sizeof(cmd), cmd, HCI_CMD_TIMEOUT);
> + if (IS_ERR(skb))
> + return PTR_ERR(skb);
> +
> + kfree_skb(skb);
> + return 0;
> +}
> diff --git a/net/bluetooth/brcm.h b/net/bluetooth/brcm.h
> new file mode 100644
> index 000000000000..a501f2988a96
> --- /dev/null
> +++ b/net/bluetooth/brcm.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2026 The Asahi Linux Contributors
> + */
> +
> +#if IS_ENABLED(CONFIG_BT_BRCMEXT)
> +
> +int brcm_set_high_priority(struct hci_dev *hdev, u16 handle, bool enable);
> +
> +#else
> +
> +static inline int brcm_set_high_priority(struct hci_dev *hdev, u16 handle, bool enable)
> +{
> + return -EOPNOTSUPP;
> +}
> +
> +#endif
> diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
> index 11d3ad8d2551..b2c7414a9c5b 100644
> --- a/net/bluetooth/hci_conn.c
> +++ b/net/bluetooth/hci_conn.c
> @@ -35,6 +35,7 @@
> #include <net/bluetooth/iso.h>
> #include <net/bluetooth/mgmt.h>
>
> +#include "brcm.h"
> #include "smp.h"
> #include "eir.h"
>
> @@ -2775,6 +2776,16 @@ int hci_get_auth_info(struct hci_dev *hdev, void __user *arg)
> return copy_to_user(arg, &req, sizeof(req)) ? -EFAULT : 0;
> }
>
> +int hci_set_acl_prio(struct hci_dev *hdev, void __user *arg)
> +{
> + struct hci_acl_prio_req req;
> +
> + if (copy_from_user(&req, arg, sizeof(req)))
> + return -EFAULT;
> +
> + return brcm_set_high_priority(hdev, req.handle, req.high_prio);
> +}
> +
> struct hci_chan *hci_chan_create(struct hci_conn *conn)
> {
> struct hci_dev *hdev = conn->hdev;
> diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c
> index 0290dea081f6..4be6aeeb6bad 100644
> --- a/net/bluetooth/hci_sock.c
> +++ b/net/bluetooth/hci_sock.c
> @@ -1035,6 +1035,9 @@ static int hci_sock_bound_ioctl(struct sock *sk, unsigned int cmd,
> if (!capable(CAP_NET_ADMIN))
> return -EPERM;
> return hci_sock_reject_list_del(hdev, (void __user *)arg);
> +
> + case HCISETACLPRIO:
> + return hci_set_acl_prio(hdev, (void __user *)arg);
> }
>
> return -ENOIOCTLCMD;
> @@ -1072,6 +1075,7 @@ static int hci_sock_ioctl(struct socket *sock, unsigned int cmd,
> case HCIGETAUTHINFO:
> case HCIBLOCKADDR:
> case HCIUNBLOCKADDR:
> + case HCISETACLPRIO:
> break;
> default:
> return -ENOIOCTLCMD;
>
> ---
> base-commit: bfe62a454542cfad3379f6ef5680b125f41e20f4
> change-id: 20260407-brcm-prio-b630e6cc3834
>
> Best regards,
> --
> Sasha Finkelstein <fnkl.kernel@gmail.com>
The simple solution would be for the driver to set all ACL connections
with high priority since in most cases we do want connections having
higher priority than scanning. That said, we may need to identify
which connections are performing audio versus those that are not. For
the audio connections, perhaps we could use skb->priority to set their
priority (provided userspace sets it for audio).
--
Luiz Augusto von Dentz
^ permalink raw reply
* Re: [PATCH 1/7] dt-bindings: clock: qcom: Add video clock controller on Eliza SoC
From: Krzysztof Kozlowski @ 2026-04-07 13:40 UTC (permalink / raw)
To: Taniya Das, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Vladimir Zapolskiy
Cc: Ajit Pandey, Imran Shaik, Jagadeesh Kona, linux-arm-msm,
linux-clk, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20260317-eliza_mm_clock_controllers_v1-v1-1-4696eeda8cfb@oss.qualcomm.com>
On 17/03/2026 18:14, Taniya Das wrote:
> Add compatible string for Eliza video clock controller and the bindings
> for Eliza Qualcomm SoC.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8450-videocc.yaml | 16 ++++++++++
> include/dt-bindings/clock/qcom,eliza-videocc.h | 37 ++++++++++++++++++++++
> 2 files changed, 53 insertions(+)
>
Although I already suggested that this was not tested (and you never
replied where did you test it), but I also checked and this fails checks
- constraints are mismatched now.
Best regards,
Krzysztof
^ permalink raw reply
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