* Re: [PATCH 0/5] Exynos850 APM-to-AP mailbox support
From: Alexey Klimov @ 2026-04-15 14:32 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar, Sam Protsenko,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley,
Tudor Ambarus, Jassi Brar, Krzysztof Kozlowski, Peter Griffin,
linux-samsung-soc, linux-arm-kernel, linux-clk, devicetree,
linux-kernel
In-Reply-To: <5d645bb0-22cd-4e96-b8b6-15c4bb83d87d@kernel.org>
On Thu Apr 2, 2026 at 7:43 AM BST, Krzysztof Kozlowski wrote:
> On 02/04/2026 04:19, Alexey Klimov wrote:
>> On Sat Mar 21, 2026 at 10:44 AM GMT, Krzysztof Kozlowski wrote:
>>> On Fri, Mar 20, 2026 at 09:15:12PM +0000, Alexey Klimov wrote:
>>>> Hi all,
>>>>
>>>> This patch series introduces support for the APM-to-AP mailbox on the
>>>> Exynos850 SoC. This mailbox is required for communicating with the APM
>>>> co-processor using ACPM.
>>>>
>>>> The Exynos850 mailbox operates similarly to the existing gs101
>>>> implementation, but the register offsets and IRQ mask bits differ.
>>>> This series abstracts these differences into platform-specific data
>>>> structures matched via the device tree.
>>>>
>>>> Also, it requires APM-to-AP mailbox clock in CMU_APM block.
>>>>
>>>> In theory this can be split into two series with correct dependecies:
>>>> device tree node requires clock changes to be merged. The suggestion
>>>> is to let this go through Samsung SoC tree with corresponding acks
>>>> if it is okay.
>>>
>>> I don't understand why this cannot be split into two seris
>>> *practically*. What is exactly the dependency between mailbox and DTS,
>>> that it had to be combined here?
>>
>> Do you suggest to send 3 single patches with proper dependencies
>> description? DT bindings change first, then mailbox change that specifically
>> depends on dt-bindings change and then dts update (which will depend on both)?
>>
>> I thought that mbox driver change depends implicitly on bindings update?
>
> Please don't answer to a question with a question. Actually three
> questions. If you cannot give argument why there is a dependency, feels
> to me like you send something you do not understand.
Sorry. You're right on the first part. Couldn't say anything about last part.
So I saw series where DTS enablement changes are included in the series
after changes in drivers were introduced. I guess it is more preferred
to split out DTS changes (also considering that kernel without these
changes should be able to boot with new DTS and vice versa). I can split
out DTS change(s), yes. There should/must be no dependency. Thanks.
Best regards,
Alexey
^ permalink raw reply
* Re: [PATCH 2/3] arm64: dts: amlogic: t7: Add UART controllers nodes
From: Ronald Claveau @ 2026-04-15 14:32 UTC (permalink / raw)
To: Xianwei Zhao
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <68577e42-2fdb-4b66-84a4-610acb8b975b@amlogic.com>
Hi Xianwei,
On 4/15/26 1:38 PM, Xianwei Zhao wrote:
> Hi Ronald,
>
> On 2026/4/15 19:16, Ronald Claveau wrote:
>> Add device tree nodes for UART B through F (serial@7a000 to
>> serial@82000), completing the UART controller description for the T7
>> SoC. Each node includes the peripheral clock.
>>
>> While at it, move the uart_a node to its correct position in the
>> bus address order (0x78000) to comply with the DT requirement that
>> nodes be sorted by their reg address. Complete the
>> uart_a node with its peripheral clock (CLKID_SYS_UART_A) and the
>> associated clock-names, matching the vendor default clock assignment,
>> consistent with the other UART nodes.
>>
>> Signed-off-by: Ronald Claveau<linux-kernel-dev@aliel.fr>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 61 +++++++++++++++++++
>> ++++++----
>> 1 file changed, 54 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/
>> boot/dts/amlogic/amlogic-t7.dtsi
>> index 531931cc1437c..56b015cfbd6d1 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -577,13 +577,6 @@ gpio_intc: interrupt-controller@4080 {
>> <10 11 12 13 14 15 16 17 18
>> 19 20 21>;
>> };
>>
>> - uart_a: serial@78000 {
>> - compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> - reg = <0x0 0x78000 0x0 0x18>;
>> - interrupts = <GIC_SPI 168
>> IRQ_TYPE_EDGE_RISING>;
>> - status = "disabled";
>> - };
>> -
>> gp0: clock-controller@8080 {
>> compatible = "amlogic,t7-gp0-pll";
>> reg = <0x0 0x8080 0x0 0x20>;
>> @@ -713,6 +706,60 @@ pwm_ao_cd: pwm@60000 {
>> status = "disabled";
>> };
>>
>> + uart_a: serial@78000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x78000 0x0 0x18>;
>> + interrupts = <GIC_SPI 168
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_A>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>
> The xtal clock is defined in the board-level DTS file, while it is
> referenced in the DTSI file, which seems a bit unusual.
>
> On other chips, the xtal clock is usually defined directly in the DTSI
> file.
>
Thanks for your feedback.
I have tested with clock removed in the DTS, and it is ok.
I will send the modification in V2.
>> + status = "disabled";
>> + };
>> +
>> + uart_b: serial@7a000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x7a000 0x0 0x18>;
>> + interrupts = <GIC_SPI 169
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_B>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + uart_c: serial@7c000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x7c000 0x0 0x18>;
>> + interrupts = <GIC_SPI 170
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_C>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + uart_d: serial@7e000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x7e000 0x0 0x18>;
>> + interrupts = <GIC_SPI 171
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_D>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + uart_e: serial@80000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x80000 0x0 0x18>;
>> + interrupts = <GIC_SPI 172
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_E>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> + uart_f: serial@82000 {
>> + compatible = "amlogic,t7-uart",
>> "amlogic,meson-s4-uart";
>> + reg = <0x0 0x82000 0x0 0x18>;
>> + interrupts = <GIC_SPI 173
>> IRQ_TYPE_EDGE_RISING>;
>> + clocks = <&xtal>, <&clkc_periphs
>> CLKID_SYS_UART_F>, <&xtal>;
>> + clock-names = "xtal", "pclk", "baud";
>> + status = "disabled";
>> + };
>> +
>> sd_emmc_a: mmc@88000 {
>> compatible = "amlogic,t7-mmc",
>> "amlogic,meson-axg-mmc";
>> reg = <0x0 0x88000 0x0 0x800>;
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH RFC v2 02/11] ASoC: meson: aiu-encoder-i2s: use gx_iface and gx_stream structures
From: Jerome Brunet @ 2026-04-15 14:28 UTC (permalink / raw)
To: Mark Brown
Cc: Valerio Setti, Liam Girdwood, Jaroslav Kysela, Takashi Iwai,
Neil Armstrong, Kevin Hilman, Martin Blumenstingl, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-kernel, linux-sound,
linux-arm-kernel, linux-amlogic, devicetree
In-Reply-To: <58d1df89-7c97-4e2f-af15-93d1f7bce5a7@sirena.org.uk>
On mar. 14 avril 2026 at 17:13, Mark Brown <broonie@kernel.org> wrote:
> On Sat, Apr 11, 2026 at 04:57:27PM +0200, Valerio Setti wrote:
>
>> @@ -200,13 +200,17 @@ static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
>
>> - aiu_encoder_i2s_divider_enable(component, true);
>> + ret = gx_stream_set_cont_clocks(ts, iface->fmt);
>> + if (ret)
>> + dev_err(dai->dev, "failed to apply continuous clock setting\n");
>> +
>> + aiu_encoder_i2s_divider_enable(component, 1);
>
> If we're checking the error here we should probably return it as well.
> Including the error code in the log message is also generally helpful.
>
>> @@ -214,16 +218,20 @@ static int aiu_encoder_i2s_hw_params(struct snd_pcm_substream *substream,
>> static int aiu_encoder_i2s_hw_free(struct snd_pcm_substream *substream,
>> struct snd_soc_dai *dai)
>> {
>> + struct gx_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
>> struct snd_soc_component *component = dai->component;
>>
>> - aiu_encoder_i2s_divider_enable(component, false);
>> -
>> - return 0;
>> + /* This is the last substream open and that is going to be closed. */
>> + if (snd_soc_dai_active(dai) <= 1)
>> + aiu_encoder_i2s_divider_enable(component, 0);
>> + return gx_stream_set_cont_clocks(ts, 0);
>> }
>
> Note that we only hw_free() if we preprared, but we enable in
> hw_params().
Huh interresting, I had not thought of that. Valerio and I discussed the
clock part a lot for this rework. It is the crux since since the
interface and clock setting lives in the AIU subsys but serves both the
AIU and AUDIN subsys.
Valerio maybe you could keep function above just to set the rate, but
enabling the clocks through a DAPM supply widget ? This is kind of what
the AXG is doing.
what do you think ?
(actually in the AXG the each formatter widget call CCF
clk_prepare_enable() but a supply widget poking the register would do
the same thing)
>
>> @@ -284,6 +295,8 @@ static int aiu_encoder_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
>> if (ret)
>> dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
>>
>> + aiu->i2s.iface.mclk_rate = freq;
>> +
>> return ret;
>> }
>
> This means we store the new rate even if the set above failed.
--
Jerome
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: rockchip: Replace deprecated snps,* props for NanoPi R5S
From: Diederik de Haas @ 2026-04-15 14:23 UTC (permalink / raw)
To: Diederik de Haas, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner
Cc: Arnd Bergmann, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Quentin Schulz, Jonas Karlman, Tianling Shen
In-Reply-To: <20260401131551.734456-3-diederik@cknow-tech.com>
On Wed Apr 1, 2026 at 3:11 PM CEST, Diederik de Haas wrote:
> The various snps,reset-* properties are deprecated, so convert them into
> their replacements.
>
> Signed-off-by: Diederik de Haas <diederik@cknow-tech.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> index 90ce6f0e1dcf..92d044ec696b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> @@ -85,10 +85,6 @@ &gmac0_tx_bus2
> &gmac0_rx_bus2
> &gmac0_rgmii_clk
> &gmac0_rgmii_bus>;
> - snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
> - snps,reset-active-low;
> - /* Reset time is 15ms, 50ms for rtl8211f */
> - snps,reset-delays-us = <0 15000 50000>;
> tx_delay = <0x3c>;
> rx_delay = <0x2f>;
> status = "okay";
> @@ -100,6 +96,9 @@ rgmii_phy0: ethernet-phy@1 {
> reg = <1>;
> pinctrl-0 = <&gmac0_rstn_gpio0_c5_pin>;
> pinctrl-names = "default";
> + reset-assert-us = <15000>;
> + reset-deassert-us = <50000>;
> + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
> };
> };
>
Please disregard/drop this patch.
I was recently made aware of 'sashiko.dev' and checked whether it had
also checked my patch, which it did:
https://sashiko.dev/#/patchset/20260401131551.734456-1-diederik%40cknow-tech.com
And it turns out that the concern raised is valid (thanks Quentin!), so
this patch could introduce a regression.
So it looks like staying with the deprecated properties is actually
better (in this case?).
Cheers,
Diederik
^ permalink raw reply
* [PATCH] drm/rockchip: dw-mipi-dsi2: add sentinel to rk3588_chip_data table
From: Renjun Wang @ 2026-04-15 14:05 UTC (permalink / raw)
To: hjc, heiko, andy.yan, maarten.lankhorst, mripard, tzimmermann,
airlied, simona
Cc: dri-devel, linux-arm-kernel, linux-rockchip, linux-kernel,
Renjun Wang
The while loop walks rockchip_dw_dsi2_chip_data entries until reg
is zero in function dw_mipi_dsi2_rockchip_probe(), so rk3588 needs
the same sentinel termination as rk3576 to avoid reading past the
end of the array.
Signed-off-by: Renjun Wang <renjunw0@foxmail.com>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
index 0aea764e29b2..8fd4653520df 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
@@ -483,7 +483,8 @@ static const struct rockchip_dw_dsi2_chip_data rk3588_chip_data[] = {
.reg = 0xfde30000,
.grf_regs = rk3588_dsi1_grf_reg_fields,
.max_bit_rate_per_lane = 4500000ULL,
- }
+ },
+ { /* sentinel */ }
};
static const struct of_device_id dw_mipi_dsi2_rockchip_dt_ids[] = {
--
2.47.3
^ permalink raw reply related
* [PATCH v3 2/2] media: verisilicon: Clean up messy include
From: Benjamin Gaignard @ 2026-04-15 14:04 UTC (permalink / raw)
To: nicolas.dufresne, p.zabel, mchehab, Frank.Li, s.hauer, kernel,
festevam, heiko, mcoquelin.stm32, alexandre.torgue, wens,
jernej.skrabec, samuel
Cc: linux-kernel, linux-media, linux-rockchip, imx, linux-arm-kernel,
linux-stm32, linux-sunxi, kernel, Benjamin Gaignard
In-Reply-To: <20260415140420.282084-1-benjamin.gaignard@collabora.com>
Over time all codecs specific functions and structures have been
added in hantro_hw.h file.
Moving them into dedicated files clean up hantro_hw.h where only
hardware specific functions should remain and, while at it, reorder
them.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/media/platform/verisilicon/hantro.h | 14 +-
.../media/platform/verisilicon/hantro_av1.h | 86 +++++
.../platform/verisilicon/hantro_g1_h264_dec.c | 1 +
.../verisilicon/hantro_g1_mpeg2_dec.c | 2 +-
.../platform/verisilicon/hantro_g1_vp8_dec.c | 2 +-
.../platform/verisilicon/hantro_g2_hevc_dec.c | 2 +-
.../media/platform/verisilicon/hantro_h264.c | 2 +-
.../media/platform/verisilicon/hantro_h264.h | 65 ++++
.../media/platform/verisilicon/hantro_hevc.c | 2 +-
.../media/platform/verisilicon/hantro_hevc.h | 66 ++++
.../media/platform/verisilicon/hantro_hw.h | 352 +-----------------
.../media/platform/verisilicon/hantro_mpeg2.c | 1 +
.../media/platform/verisilicon/hantro_mpeg2.h | 27 ++
.../media/platform/verisilicon/hantro_v4l2.c | 7 +-
.../media/platform/verisilicon/hantro_vp8.c | 1 +
.../media/platform/verisilicon/hantro_vp8.h | 29 ++
.../media/platform/verisilicon/hantro_vp9.h | 86 +++++
.../media/platform/verisilicon/imx8m_vpu_hw.c | 5 +
.../verisilicon/rockchip_vpu2_hw_h264_dec.c | 2 +-
.../verisilicon/rockchip_vpu2_hw_mpeg2_dec.c | 2 +-
.../verisilicon/rockchip_vpu2_hw_vp8_dec.c | 2 +-
.../platform/verisilicon/rockchip_vpu_hw.c | 3 +
.../platform/verisilicon/stm32mp25_vpu_hw.c | 2 +
.../media/platform/verisilicon/sunxi_vpu_hw.c | 1 +
24 files changed, 413 insertions(+), 349 deletions(-)
create mode 100644 drivers/media/platform/verisilicon/hantro_mpeg2.h
create mode 100644 drivers/media/platform/verisilicon/hantro_vp8.h
diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
index c4ceb9c99016..91e04df6463e 100644
--- a/drivers/media/platform/verisilicon/hantro.h
+++ b/drivers/media/platform/verisilicon/hantro.h
@@ -25,7 +25,12 @@
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
-#include "hantro_hw.h"
+#include "hantro_av1.h"
+#include "hantro_h264.h"
+#include "hantro_hevc.h"
+#include "hantro_mpeg2.h"
+#include "hantro_vp8.h"
+#include "hantro_vp9.h"
struct hantro_ctx;
struct hantro_codec_ops;
@@ -520,4 +525,11 @@ dma_addr_t hantro_mv_get_buf_addr(struct hantro_ctx *ctx, int index);
dma_addr_t hantro_rfc_get_luma_buf_addr(struct hantro_ctx *ctx, int index);
dma_addr_t hantro_rfc_get_chroma_buf_addr(struct hantro_ctx *ctx, int index);
+void hantro_watchdog(struct work_struct *work);
+void hantro_run(struct hantro_ctx *ctx);
+void hantro_irq_done(struct hantro_dev *vpu,
+ enum vb2_buffer_state result);
+void hantro_start_prepare_run(struct hantro_ctx *ctx);
+void hantro_end_prepare_run(struct hantro_ctx *ctx);
+
#endif /* HANTRO_H_ */
diff --git a/drivers/media/platform/verisilicon/hantro_av1.h b/drivers/media/platform/verisilicon/hantro_av1.h
index bc4a0887f8e7..8f0a001b9750 100644
--- a/drivers/media/platform/verisilicon/hantro_av1.h
+++ b/drivers/media/platform/verisilicon/hantro_av1.h
@@ -3,6 +3,10 @@
#ifndef _HANTRO_AV1_H_
#define _HANTRO_AV1_H_
+#include "hantro_av1_entropymode.h"
+#include "hantro_av1_filmgrain.h"
+#include "hantro_hw.h"
+
#define AV1_PRIMARY_REF_NONE 7
#define AV1_REF_SCALE_SHIFT 14
#define MAX_FRAME_DISTANCE 31
@@ -36,6 +40,88 @@
#define ALT2_BUF_IDX (V4L2_AV1_REF_ALTREF2_FRAME - V4L2_AV1_REF_LAST_FRAME)
#define ALT_BUF_IDX (V4L2_AV1_REF_ALTREF_FRAME - V4L2_AV1_REF_LAST_FRAME)
+#define AV1_MAX_FRAME_BUF_COUNT (V4L2_AV1_TOTAL_REFS_PER_FRAME + 1)
+
+
+/**
+ * struct hantro_av1_dec_ctrls
+ * @sequence: AV1 Sequence
+ * @tile_group_entry: AV1 Tile Group entry
+ * @frame: AV1 Frame Header OBU
+ * @film_grain: AV1 Film Grain
+ */
+struct hantro_av1_dec_ctrls {
+ const struct v4l2_ctrl_av1_sequence *sequence;
+ const struct v4l2_ctrl_av1_tile_group_entry *tile_group_entry;
+ const struct v4l2_ctrl_av1_frame *frame;
+ const struct v4l2_ctrl_av1_film_grain *film_grain;
+};
+
+struct hantro_av1_frame_ref {
+ int width;
+ int height;
+ int mi_cols;
+ int mi_rows;
+ u64 timestamp;
+ enum v4l2_av1_frame_type frame_type;
+ bool used;
+ u32 order_hint;
+ u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME];
+ struct vb2_v4l2_buffer *vb2_ref;
+};
+
+/**
+ * struct hantro_av1_dec_hw_ctx
+ * @db_data_col: db tile col data buffer
+ * @db_ctrl_col: db tile col ctrl buffer
+ * @cdef_col: cdef tile col buffer
+ * @sr_col: sr tile col buffer
+ * @lr_col: lr tile col buffer
+ * @global_model: global model buffer
+ * @tile_info: tile info buffer
+ * @segment: segmentation info buffer
+ * @film_grain: film grain buffer
+ * @prob_tbl: probability table
+ * @prob_tbl_out: probability table output
+ * @tile_buf: tile buffer
+ * @ctrls: V4L2 controls attached to a run
+ * @frame_refs: reference frames info slots
+ * @ref_frame_sign_bias: array of sign bias
+ * @num_tile_cols_allocated: number of allocated tiles
+ * @cdfs: current probabilities structure
+ * @cdfs_ndvc: current mv probabilities structure
+ * @default_cdfs: default probabilities structure
+ * @default_cdfs_ndvc: default mv probabilties structure
+ * @cdfs_last: stored probabilities structures
+ * @cdfs_last_ndvc: stored mv probabilities structures
+ * @current_frame_index: index of the current in frame_refs array
+ */
+struct hantro_av1_dec_hw_ctx {
+ struct hantro_aux_buf db_data_col;
+ struct hantro_aux_buf db_ctrl_col;
+ struct hantro_aux_buf cdef_col;
+ struct hantro_aux_buf sr_col;
+ struct hantro_aux_buf lr_col;
+ struct hantro_aux_buf global_model;
+ struct hantro_aux_buf tile_info;
+ struct hantro_aux_buf segment;
+ struct hantro_aux_buf film_grain;
+ struct hantro_aux_buf prob_tbl;
+ struct hantro_aux_buf prob_tbl_out;
+ struct hantro_aux_buf tile_buf;
+ struct hantro_av1_dec_ctrls ctrls;
+ struct hantro_av1_frame_ref frame_refs[AV1_MAX_FRAME_BUF_COUNT];
+ u32 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME];
+ unsigned int num_tile_cols_allocated;
+ struct av1cdfs *cdfs;
+ struct mvcdfs *cdfs_ndvc;
+ struct av1cdfs default_cdfs;
+ struct mvcdfs default_cdfs_ndvc;
+ struct av1cdfs cdfs_last[NUM_REF_FRAMES];
+ struct mvcdfs cdfs_last_ndvc[NUM_REF_FRAMES];
+ int current_frame_index;
+};
+
int hantro_av1_get_frame_index(struct hantro_ctx *ctx, int ref);
int hantro_av1_get_order_hint(struct hantro_ctx *ctx, int ref);
int hantro_av1_frame_ref(struct hantro_ctx *ctx, u64 timestamp);
diff --git a/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c b/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c
index ad5c1a6634f5..a1da2adda5eb 100644
--- a/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g1_h264_dec.c
@@ -16,6 +16,7 @@
#include <media/v4l2-mem2mem.h>
#include "hantro_g1_regs.h"
+#include "hantro_h264.h"
#include "hantro_hw.h"
#include "hantro_v4l2.h"
diff --git a/drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c b/drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
index e0d6bd0a6e44..7c2f0697295d 100644
--- a/drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
@@ -9,8 +9,8 @@
#include <linux/bitfield.h>
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
-#include "hantro_hw.h"
#include "hantro_g1_regs.h"
+#include "hantro_mpeg2.h"
#define G1_SWREG(nr) ((nr) * 4)
diff --git a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
index 851eb67f19f5..e155d9868b32 100644
--- a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c
@@ -11,9 +11,9 @@
#include <media/v4l2-mem2mem.h>
-#include "hantro_hw.h"
#include "hantro.h"
#include "hantro_g1_regs.h"
+#include "hantro_vp8.h"
/* DCT partition base address regs */
static const struct hantro_reg vp8_dec_dct_base[8] = {
diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
index d0af9fb882ba..39f271e570f7 100644
--- a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
@@ -5,7 +5,7 @@
* Copyright (C) 2020 Safran Passenger Innovations LLC
*/
-#include "hantro_hw.h"
+#include "hantro_hevc.h"
#include "hantro_g2_regs.h"
static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
diff --git a/drivers/media/platform/verisilicon/hantro_h264.c b/drivers/media/platform/verisilicon/hantro_h264.c
index 2414782f1eb6..5e684389f04f 100644
--- a/drivers/media/platform/verisilicon/hantro_h264.c
+++ b/drivers/media/platform/verisilicon/hantro_h264.c
@@ -15,7 +15,7 @@
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
-#include "hantro_hw.h"
+#include "hantro_h264.h"
/* Size with u32 units. */
#define CABAC_INIT_BUFFER_SIZE (460 * 2)
diff --git a/drivers/media/platform/verisilicon/hantro_h264.h b/drivers/media/platform/verisilicon/hantro_h264.h
index 89348203a712..d94e4b21d991 100644
--- a/drivers/media/platform/verisilicon/hantro_h264.h
+++ b/drivers/media/platform/verisilicon/hantro_h264.h
@@ -5,6 +5,63 @@
* Copyright (C) 2026 Collabora Ltd.
*/
+#ifndef _HANTRO_H264_H_
+#define _HANTRO_H264_H_
+
+#include "hantro_hw.h"
+
+/* Max. number of entries in the DPB (HW limitation). */
+#define HANTRO_H264_DPB_SIZE 16
+
+/**
+ * struct hantro_h264_dec_ctrls
+ *
+ * @decode: Decode params
+ * @scaling: Scaling info
+ * @sps: SPS info
+ * @pps: PPS info
+ */
+struct hantro_h264_dec_ctrls {
+ const struct v4l2_ctrl_h264_decode_params *decode;
+ const struct v4l2_ctrl_h264_scaling_matrix *scaling;
+ const struct v4l2_ctrl_h264_sps *sps;
+ const struct v4l2_ctrl_h264_pps *pps;
+};
+
+/**
+ * struct hantro_h264_dec_reflists
+ *
+ * @p: P reflist
+ * @b0: B0 reflist
+ * @b1: B1 reflist
+ */
+struct hantro_h264_dec_reflists {
+ struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN];
+ struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN];
+ struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN];
+};
+
+/**
+ * struct hantro_h264_dec_hw_ctx
+ *
+ * @priv: Private auxiliary buffer for hardware.
+ * @dpb: DPB
+ * @reflists: P/B0/B1 reflists
+ * @ctrls: V4L2 controls attached to a run
+ * @dpb_longterm: DPB long-term
+ * @dpb_valid: DPB valid
+ * @cur_poc: Current picture order count
+ */
+struct hantro_h264_dec_hw_ctx {
+ struct hantro_aux_buf priv;
+ struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
+ struct hantro_h264_dec_reflists reflists;
+ struct hantro_h264_dec_ctrls ctrls;
+ u32 dpb_longterm;
+ u32 dpb_valid;
+ s32 cur_poc;
+};
+
static inline size_t
hantro_h264_mv_size(unsigned int width, unsigned int height)
{
@@ -31,3 +88,11 @@ hantro_h264_mv_size(unsigned int width, unsigned int height)
*/
return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
}
+
+dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx);
+u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx);
+int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
+int hantro_h264_dec_init(struct hantro_ctx *ctx);
+void hantro_h264_dec_exit(struct hantro_ctx *ctx);
+
+#endif
diff --git a/drivers/media/platform/verisilicon/hantro_hevc.c b/drivers/media/platform/verisilicon/hantro_hevc.c
index eea4d9e6fde0..04a694cd19f9 100644
--- a/drivers/media/platform/verisilicon/hantro_hevc.c
+++ b/drivers/media/platform/verisilicon/hantro_hevc.c
@@ -9,7 +9,7 @@
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
-#include "hantro_hw.h"
+#include "hantro_hevc.h"
#define VERT_FILTER_RAM_SIZE 8 /* bytes per pixel row */
/*
diff --git a/drivers/media/platform/verisilicon/hantro_hevc.h b/drivers/media/platform/verisilicon/hantro_hevc.h
index cfaeb8662473..71e17054743d 100644
--- a/drivers/media/platform/verisilicon/hantro_hevc.h
+++ b/drivers/media/platform/verisilicon/hantro_hevc.h
@@ -5,6 +5,60 @@
* Copyright (C) 2026 Collabora Ltd.
*/
+#ifndef _HANTRO_HEVC_H_
+#define _HANTRO_HEVC_H_
+
+#include "hantro_hw.h"
+
+#define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1)
+
+/**
+ * struct hantro_hevc_dec_ctrls
+ * @decode_params: Decode params
+ * @scaling: Scaling matrix
+ * @sps: SPS info
+ * @pps: PPS info
+ * @hevc_hdr_skip_length: the number of data (in bits) to skip in the
+ * slice segment header syntax after 'slice type'
+ * token
+ */
+struct hantro_hevc_dec_ctrls {
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ u32 hevc_hdr_skip_length;
+};
+
+/**
+ * struct hantro_hevc_dec_hw_ctx
+ * @tile_sizes: Tile sizes buffer
+ * @tile_filter: Tile vertical filter buffer
+ * @tile_sao: Tile SAO buffer
+ * @tile_bsd: Tile BSD control buffer
+ * @ref_bufs: Internal reference buffers
+ * @scaling_lists: Scaling lists buffer
+ * @ref_bufs_poc: Internal reference buffers picture order count
+ * @ref_bufs_used: Bitfield of used reference buffers
+ * @ctrls: V4L2 controls attached to a run
+ * @num_tile_cols_allocated: number of allocated tiles
+ * @use_compression: use reference buffer compression
+ */
+struct hantro_hevc_dec_hw_ctx {
+ struct hantro_aux_buf tile_sizes;
+ struct hantro_aux_buf tile_filter;
+ struct hantro_aux_buf tile_sao;
+ struct hantro_aux_buf tile_bsd;
+ struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
+ struct hantro_aux_buf scaling_lists;
+ s32 ref_bufs_poc[NUM_REF_PICTURES];
+ u32 ref_bufs_used;
+ struct vb2_v4l2_buffer *ref_vb2[NUM_REF_PICTURES];
+ struct hantro_hevc_dec_ctrls ctrls;
+ unsigned int num_tile_cols_allocated;
+ bool use_compression;
+};
+
static inline size_t
hantro_hevc_mv_size(unsigned int width, unsigned int height, int depth)
{
@@ -14,3 +68,15 @@ hantro_hevc_mv_size(unsigned int width, unsigned int height, int depth)
*/
return DIV_ROUND_UP(width * height * depth / 8, 16);
}
+
+int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
+void hantro_hevc_ref_init(struct hantro_ctx *ctx);
+dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc,
+ dma_addr_t addr,
+ struct vb2_v4l2_buffer *vb2);
+int hantro_hevc_get_ref_buf_index(struct hantro_ctx *ctx, s32 poc);
+int hantro_hevc_dec_init(struct hantro_ctx *ctx);
+void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
+
+#endif
diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h
index 6903af119345..6d6944088c8e 100644
--- a/drivers/media/platform/verisilicon/hantro_hw.h
+++ b/drivers/media/platform/verisilicon/hantro_hw.h
@@ -15,9 +15,6 @@
#include <media/v4l2-vp9.h>
#include <media/videobuf2-core.h>
-#include "hantro_av1_entropymode.h"
-#include "hantro_av1_filmgrain.h"
-
#define DEC_8190_ALIGN_MASK 0x07U
#define MB_DIM 16
@@ -36,19 +33,8 @@
#define FMT_4K_WIDTH 4096
#define FMT_4K_HEIGHT 2304
-#define NUM_REF_PICTURES (V4L2_HEVC_DPB_ENTRIES_NUM_MAX + 1)
-
-#define AV1_MAX_FRAME_BUF_COUNT (V4L2_AV1_TOTAL_REFS_PER_FRAME + 1)
-
#define MAX_POSTPROC_BUFFERS 64
-#define CBS_SIZE 16 /* compression table size in bytes */
-#define CBS_LUMA 8 /* luminance CBS is composed of 1 8x8 coded block */
-#define CBS_CHROMA_W (8 * 2) /* chrominance CBS is composed of two 8x4 coded
- * blocks, with Cb CB first then Cr CB following
- */
-#define CBS_CHROMA_H 4
-
struct hantro_dev;
struct hantro_ctx;
struct hantro_buf;
@@ -69,279 +55,6 @@ struct hantro_aux_buf {
unsigned long attrs;
};
-/* Max. number of entries in the DPB (HW limitation). */
-#define HANTRO_H264_DPB_SIZE 16
-
-/**
- * struct hantro_h264_dec_ctrls
- *
- * @decode: Decode params
- * @scaling: Scaling info
- * @sps: SPS info
- * @pps: PPS info
- */
-struct hantro_h264_dec_ctrls {
- const struct v4l2_ctrl_h264_decode_params *decode;
- const struct v4l2_ctrl_h264_scaling_matrix *scaling;
- const struct v4l2_ctrl_h264_sps *sps;
- const struct v4l2_ctrl_h264_pps *pps;
-};
-
-/**
- * struct hantro_h264_dec_reflists
- *
- * @p: P reflist
- * @b0: B0 reflist
- * @b1: B1 reflist
- */
-struct hantro_h264_dec_reflists {
- struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN];
- struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN];
- struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN];
-};
-
-/**
- * struct hantro_h264_dec_hw_ctx
- *
- * @priv: Private auxiliary buffer for hardware.
- * @dpb: DPB
- * @reflists: P/B0/B1 reflists
- * @ctrls: V4L2 controls attached to a run
- * @dpb_longterm: DPB long-term
- * @dpb_valid: DPB valid
- * @cur_poc: Current picture order count
- */
-struct hantro_h264_dec_hw_ctx {
- struct hantro_aux_buf priv;
- struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
- struct hantro_h264_dec_reflists reflists;
- struct hantro_h264_dec_ctrls ctrls;
- u32 dpb_longterm;
- u32 dpb_valid;
- s32 cur_poc;
-};
-
-/**
- * struct hantro_hevc_dec_ctrls
- * @decode_params: Decode params
- * @scaling: Scaling matrix
- * @sps: SPS info
- * @pps: PPS info
- * @hevc_hdr_skip_length: the number of data (in bits) to skip in the
- * slice segment header syntax after 'slice type'
- * token
- */
-struct hantro_hevc_dec_ctrls {
- const struct v4l2_ctrl_hevc_decode_params *decode_params;
- const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
- const struct v4l2_ctrl_hevc_sps *sps;
- const struct v4l2_ctrl_hevc_pps *pps;
- u32 hevc_hdr_skip_length;
-};
-
-/**
- * struct hantro_hevc_dec_hw_ctx
- * @tile_sizes: Tile sizes buffer
- * @tile_filter: Tile vertical filter buffer
- * @tile_sao: Tile SAO buffer
- * @tile_bsd: Tile BSD control buffer
- * @ref_bufs: Internal reference buffers
- * @scaling_lists: Scaling lists buffer
- * @ref_bufs_poc: Internal reference buffers picture order count
- * @ref_bufs_used: Bitfield of used reference buffers
- * @ctrls: V4L2 controls attached to a run
- * @num_tile_cols_allocated: number of allocated tiles
- * @use_compression: use reference buffer compression
- */
-struct hantro_hevc_dec_hw_ctx {
- struct hantro_aux_buf tile_sizes;
- struct hantro_aux_buf tile_filter;
- struct hantro_aux_buf tile_sao;
- struct hantro_aux_buf tile_bsd;
- struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
- struct hantro_aux_buf scaling_lists;
- s32 ref_bufs_poc[NUM_REF_PICTURES];
- u32 ref_bufs_used;
- struct vb2_v4l2_buffer *ref_vb2[NUM_REF_PICTURES];
- struct hantro_hevc_dec_ctrls ctrls;
- unsigned int num_tile_cols_allocated;
- bool use_compression;
-};
-
-/**
- * struct hantro_mpeg2_dec_hw_ctx
- *
- * @qtable: Quantization table
- */
-struct hantro_mpeg2_dec_hw_ctx {
- struct hantro_aux_buf qtable;
-};
-
-/**
- * struct hantro_vp8_dec_hw_ctx
- *
- * @segment_map: Segment map buffer.
- * @prob_tbl: Probability table buffer.
- */
-struct hantro_vp8_dec_hw_ctx {
- struct hantro_aux_buf segment_map;
- struct hantro_aux_buf prob_tbl;
-};
-
-/**
- * struct hantro_vp9_frame_info
- *
- * @valid: frame info valid flag
- * @frame_context_idx: index of frame context
- * @reference_mode: inter prediction type
- * @tx_mode: transform mode
- * @interpolation_filter: filter selection for inter prediction
- * @flags: frame flags
- * @timestamp: frame timestamp
- */
-struct hantro_vp9_frame_info {
- u32 valid : 1;
- u32 frame_context_idx : 2;
- u32 reference_mode : 2;
- u32 tx_mode : 3;
- u32 interpolation_filter : 3;
- u32 flags;
- u64 timestamp;
-};
-
-#define MAX_SB_COLS 64
-#define MAX_SB_ROWS 34
-
-/**
- * struct hantro_vp9_dec_hw_ctx
- *
- * @tile_edge: auxiliary DMA buffer for tile edge processing
- * @segment_map: auxiliary DMA buffer for segment map
- * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters
- * @cnts: vp9 library struct for abstracting hw counters access
- * @probability_tables: VP9 probability tables implied by the spec
- * @frame_context: VP9 frame contexts
- * @cur: current frame information
- * @last: last frame information
- * @bsd_ctrl_offset: bsd offset into tile_edge
- * @segment_map_size: size of segment map
- * @ctx_counters_offset: hw counters offset into misc
- * @tile_info_offset: tile info offset into misc
- * @tile_r_info: per-tile information array
- * @tile_c_info: per-tile information array
- * @last_tile_r: last number of tile rows
- * @last_tile_c: last number of tile cols
- * @last_sbs_r: last number of superblock rows
- * @last_sbs_c: last number of superblock cols
- * @active_segment: number of active segment (alternating between 0 and 1)
- * @feature_enabled: segmentation feature enabled flags
- * @feature_data: segmentation feature data
- */
-struct hantro_vp9_dec_hw_ctx {
- struct hantro_aux_buf tile_edge;
- struct hantro_aux_buf segment_map;
- struct hantro_aux_buf misc;
- struct v4l2_vp9_frame_symbol_counts cnts;
- struct v4l2_vp9_frame_context probability_tables;
- struct v4l2_vp9_frame_context frame_context[4];
- struct hantro_vp9_frame_info cur;
- struct hantro_vp9_frame_info last;
-
- unsigned int bsd_ctrl_offset;
- unsigned int segment_map_size;
- unsigned int ctx_counters_offset;
- unsigned int tile_info_offset;
-
- unsigned short tile_r_info[MAX_SB_ROWS];
- unsigned short tile_c_info[MAX_SB_COLS];
- unsigned int last_tile_r;
- unsigned int last_tile_c;
- unsigned int last_sbs_r;
- unsigned int last_sbs_c;
-
- unsigned int active_segment;
- u8 feature_enabled[8];
- s16 feature_data[8][4];
-};
-
-/**
- * struct hantro_av1_dec_ctrls
- * @sequence: AV1 Sequence
- * @tile_group_entry: AV1 Tile Group entry
- * @frame: AV1 Frame Header OBU
- * @film_grain: AV1 Film Grain
- */
-struct hantro_av1_dec_ctrls {
- const struct v4l2_ctrl_av1_sequence *sequence;
- const struct v4l2_ctrl_av1_tile_group_entry *tile_group_entry;
- const struct v4l2_ctrl_av1_frame *frame;
- const struct v4l2_ctrl_av1_film_grain *film_grain;
-};
-
-struct hantro_av1_frame_ref {
- int width;
- int height;
- int mi_cols;
- int mi_rows;
- u64 timestamp;
- enum v4l2_av1_frame_type frame_type;
- bool used;
- u32 order_hint;
- u32 order_hints[V4L2_AV1_TOTAL_REFS_PER_FRAME];
- struct vb2_v4l2_buffer *vb2_ref;
-};
-
-/**
- * struct hantro_av1_dec_hw_ctx
- * @db_data_col: db tile col data buffer
- * @db_ctrl_col: db tile col ctrl buffer
- * @cdef_col: cdef tile col buffer
- * @sr_col: sr tile col buffer
- * @lr_col: lr tile col buffer
- * @global_model: global model buffer
- * @tile_info: tile info buffer
- * @segment: segmentation info buffer
- * @film_grain: film grain buffer
- * @prob_tbl: probability table
- * @prob_tbl_out: probability table output
- * @tile_buf: tile buffer
- * @ctrls: V4L2 controls attached to a run
- * @frame_refs: reference frames info slots
- * @ref_frame_sign_bias: array of sign bias
- * @num_tile_cols_allocated: number of allocated tiles
- * @cdfs: current probabilities structure
- * @cdfs_ndvc: current mv probabilities structure
- * @default_cdfs: default probabilities structure
- * @default_cdfs_ndvc: default mv probabilties structure
- * @cdfs_last: stored probabilities structures
- * @cdfs_last_ndvc: stored mv probabilities structures
- * @current_frame_index: index of the current in frame_refs array
- */
-struct hantro_av1_dec_hw_ctx {
- struct hantro_aux_buf db_data_col;
- struct hantro_aux_buf db_ctrl_col;
- struct hantro_aux_buf cdef_col;
- struct hantro_aux_buf sr_col;
- struct hantro_aux_buf lr_col;
- struct hantro_aux_buf global_model;
- struct hantro_aux_buf tile_info;
- struct hantro_aux_buf segment;
- struct hantro_aux_buf film_grain;
- struct hantro_aux_buf prob_tbl;
- struct hantro_aux_buf prob_tbl_out;
- struct hantro_aux_buf tile_buf;
- struct hantro_av1_dec_ctrls ctrls;
- struct hantro_av1_frame_ref frame_refs[AV1_MAX_FRAME_BUF_COUNT];
- u32 ref_frame_sign_bias[V4L2_AV1_TOTAL_REFS_PER_FRAME];
- unsigned int num_tile_cols_allocated;
- struct av1cdfs *cdfs;
- struct mvcdfs *cdfs_ndvc;
- struct av1cdfs default_cdfs;
- struct mvcdfs default_cdfs_ndvc;
- struct av1cdfs cdfs_last[NUM_REF_FRAMES];
- struct mvcdfs cdfs_last_ndvc[NUM_REF_FRAMES];
- int current_frame_index;
-};
/**
* struct hantro_postproc_ctx
*
@@ -425,68 +138,29 @@ extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
extern const struct hantro_postproc_ops rockchip_vpu981_postproc_ops;
-extern const u32 hantro_vp8_dec_mc_filter[8][6];
-
-void hantro_watchdog(struct work_struct *work);
-void hantro_run(struct hantro_ctx *ctx);
-void hantro_irq_done(struct hantro_dev *vpu,
- enum vb2_buffer_state result);
-void hantro_start_prepare_run(struct hantro_ctx *ctx);
-void hantro_end_prepare_run(struct hantro_ctx *ctx);
-
irqreturn_t hantro_g1_irq(int irq, void *dev_id);
void hantro_g1_reset(struct hantro_ctx *ctx);
-
-int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
-int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx);
-void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx);
-void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx);
-
-dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
- unsigned int dpb_idx);
-u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx,
- unsigned int dpb_idx);
-int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx);
-int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx);
int hantro_g1_h264_dec_run(struct hantro_ctx *ctx);
-int hantro_h264_dec_init(struct hantro_ctx *ctx);
-void hantro_h264_dec_exit(struct hantro_ctx *ctx);
-
-int hantro_hevc_dec_init(struct hantro_ctx *ctx);
-void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
-int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
-int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
-void hantro_hevc_ref_init(struct hantro_ctx *ctx);
-dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
-int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc,
- dma_addr_t addr,
- struct vb2_v4l2_buffer *vb2);
-int hantro_hevc_get_ref_buf_index(struct hantro_ctx *ctx, s32 poc);
-
-int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx);
-
-size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx);
-
int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
-int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
-void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
- const struct v4l2_ctrl_mpeg2_quantisation *ctrl);
-int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
-void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
-
int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx);
-int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx);
-int hantro_vp8_dec_init(struct hantro_ctx *ctx);
-void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
-void hantro_vp8_prob_update(struct hantro_ctx *ctx,
- const struct v4l2_ctrl_vp8_frame *hdr);
+int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
+size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx);
int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx);
void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx);
-int hantro_vp9_dec_init(struct hantro_ctx *ctx);
-void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
void hantro_g2_check_idle(struct hantro_dev *vpu);
void hantro_g2_reset(struct hantro_ctx *ctx);
irqreturn_t hantro_g2_irq(int irq, void *dev_id);
+int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
+void hantro_h1_jpeg_enc_done(struct hantro_ctx *ctx);
+
+int rockchip_vpu2_jpeg_enc_run(struct hantro_ctx *ctx);
+void rockchip_vpu2_jpeg_enc_done(struct hantro_ctx *ctx);
+int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx);
+int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
+int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx);
+
+int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx);
+
#endif /* HANTRO_HW_H_ */
diff --git a/drivers/media/platform/verisilicon/hantro_mpeg2.c b/drivers/media/platform/verisilicon/hantro_mpeg2.c
index 04e545eb0a83..e6ad39a2d18c 100644
--- a/drivers/media/platform/verisilicon/hantro_mpeg2.c
+++ b/drivers/media/platform/verisilicon/hantro_mpeg2.c
@@ -6,6 +6,7 @@
*/
#include "hantro.h"
+#include "hantro_mpeg2.h"
static const u8 zigzag[64] = {
0, 1, 8, 16, 9, 2, 3, 10,
diff --git a/drivers/media/platform/verisilicon/hantro_mpeg2.h b/drivers/media/platform/verisilicon/hantro_mpeg2.h
new file mode 100644
index 000000000000..df86f5be3152
--- /dev/null
+++ b/drivers/media/platform/verisilicon/hantro_mpeg2.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Hantro MPEG2 codec driver
+ *
+ * Copyright (C) 2026 Collabora Ltd.
+ */
+
+#ifndef _HANTRO_MPEG2_H_
+#define _HANTRO_MPEG2_H_
+
+#include "hantro_hw.h"
+
+/**
+ * struct hantro_mpeg2_dec_hw_ctx
+ *
+ * @qtable: Quantization table
+ */
+struct hantro_mpeg2_dec_hw_ctx {
+ struct hantro_aux_buf qtable;
+};
+
+void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
+ const struct v4l2_ctrl_mpeg2_quantisation *ctrl);
+int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
+void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
+
+#endif
diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c
index bbc1e9e2840e..fdb15a8a85f2 100644
--- a/drivers/media/platform/verisilicon/hantro_v4l2.c
+++ b/drivers/media/platform/verisilicon/hantro_v4l2.c
@@ -26,13 +26,18 @@
#include "hantro.h"
#include "hantro_av1.h"
-#include "hantro_hw.h"
#include "hantro_h264.h"
#include "hantro_hevc.h"
#include "hantro_v4l2.h"
#include "hantro_vp9.h"
#define HANTRO_DEFAULT_BIT_DEPTH 8
+#define CBS_SIZE 16 /* compression table size in bytes */
+#define CBS_LUMA 8 /* luminance CBS is composed of 1 8x8 coded block */
+#define CBS_CHROMA_W (8 * 2) /* chrominance CBS is composed of two 8x4 coded
+ * blocks, with Cb CB first then Cr CB following
+ */
+#define CBS_CHROMA_H 4
static int hantro_set_fmt_out(struct hantro_ctx *ctx,
struct v4l2_pix_format_mplane *pix_mp,
diff --git a/drivers/media/platform/verisilicon/hantro_vp8.c b/drivers/media/platform/verisilicon/hantro_vp8.c
index 381bc1d3bfda..e03ab933c9a3 100644
--- a/drivers/media/platform/verisilicon/hantro_vp8.c
+++ b/drivers/media/platform/verisilicon/hantro_vp8.c
@@ -6,6 +6,7 @@
*/
#include "hantro.h"
+#include "hantro_vp8.h"
/*
* probs table with packed
diff --git a/drivers/media/platform/verisilicon/hantro_vp8.h b/drivers/media/platform/verisilicon/hantro_vp8.h
new file mode 100644
index 000000000000..0307d78380d2
--- /dev/null
+++ b/drivers/media/platform/verisilicon/hantro_vp8.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Hantro VP8 codec driver
+ *
+ * Copyright (C) 2026 Collabora Ltd.
+ */
+#ifndef _HANTRO_VP8_H_
+#define _HANTRO_VP8_H_
+
+#include "hantro_hw.h"
+
+extern const u32 hantro_vp8_dec_mc_filter[8][6];
+
+/**
+ * struct hantro_vp8_dec_hw_ctx
+ *
+ * @segment_map: Segment map buffer.
+ * @prob_tbl: Probability table buffer.
+ */
+struct hantro_vp8_dec_hw_ctx {
+ struct hantro_aux_buf segment_map;
+ struct hantro_aux_buf prob_tbl;
+};
+
+int hantro_vp8_dec_init(struct hantro_ctx *ctx);
+void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
+void hantro_vp8_prob_update(struct hantro_ctx *ctx,
+ const struct v4l2_ctrl_vp8_frame *hdr);
+#endif
diff --git a/drivers/media/platform/verisilicon/hantro_vp9.h b/drivers/media/platform/verisilicon/hantro_vp9.h
index fcdad2242f78..85633987d86e 100644
--- a/drivers/media/platform/verisilicon/hantro_vp9.h
+++ b/drivers/media/platform/verisilicon/hantro_vp9.h
@@ -5,6 +5,11 @@
* Copyright (C) 2021 Collabora Ltd.
*/
+#ifndef _HANTRO_VP9_H_
+#define _HANTRO_VP9_H_
+
+#include "hantro_hw.h"
+
struct hantro_g2_mv_probs {
u8 joint[3];
u8 sign[2];
@@ -101,6 +106,82 @@ struct symbol_counts {
u32 count_eobs[4][2][2][6][6];
};
+/**
+ * struct hantro_vp9_frame_info
+ *
+ * @valid: frame info valid flag
+ * @frame_context_idx: index of frame context
+ * @reference_mode: inter prediction type
+ * @tx_mode: transform mode
+ * @interpolation_filter: filter selection for inter prediction
+ * @flags: frame flags
+ * @timestamp: frame timestamp
+ */
+struct hantro_vp9_frame_info {
+ u32 valid : 1;
+ u32 frame_context_idx : 2;
+ u32 reference_mode : 2;
+ u32 tx_mode : 3;
+ u32 interpolation_filter : 3;
+ u32 flags;
+ u64 timestamp;
+};
+
+#define MAX_SB_COLS 64
+#define MAX_SB_ROWS 34
+
+/**
+ * struct hantro_vp9_dec_hw_ctx
+ *
+ * @tile_edge: auxiliary DMA buffer for tile edge processing
+ * @segment_map: auxiliary DMA buffer for segment map
+ * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters
+ * @cnts: vp9 library struct for abstracting hw counters access
+ * @probability_tables: VP9 probability tables implied by the spec
+ * @frame_context: VP9 frame contexts
+ * @cur: current frame information
+ * @last: last frame information
+ * @bsd_ctrl_offset: bsd offset into tile_edge
+ * @segment_map_size: size of segment map
+ * @ctx_counters_offset: hw counters offset into misc
+ * @tile_info_offset: tile info offset into misc
+ * @tile_r_info: per-tile information array
+ * @tile_c_info: per-tile information array
+ * @last_tile_r: last number of tile rows
+ * @last_tile_c: last number of tile cols
+ * @last_sbs_r: last number of superblock rows
+ * @last_sbs_c: last number of superblock cols
+ * @active_segment: number of active segment (alternating between 0 and 1)
+ * @feature_enabled: segmentation feature enabled flags
+ * @feature_data: segmentation feature data
+ */
+struct hantro_vp9_dec_hw_ctx {
+ struct hantro_aux_buf tile_edge;
+ struct hantro_aux_buf segment_map;
+ struct hantro_aux_buf misc;
+ struct v4l2_vp9_frame_symbol_counts cnts;
+ struct v4l2_vp9_frame_context probability_tables;
+ struct v4l2_vp9_frame_context frame_context[4];
+ struct hantro_vp9_frame_info cur;
+ struct hantro_vp9_frame_info last;
+
+ unsigned int bsd_ctrl_offset;
+ unsigned int segment_map_size;
+ unsigned int ctx_counters_offset;
+ unsigned int tile_info_offset;
+
+ unsigned short tile_r_info[MAX_SB_ROWS];
+ unsigned short tile_c_info[MAX_SB_COLS];
+ unsigned int last_tile_r;
+ unsigned int last_tile_c;
+ unsigned int last_sbs_r;
+ unsigned int last_sbs_c;
+
+ unsigned int active_segment;
+ u8 feature_enabled[8];
+ s16 feature_data[8][4];
+};
+
static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)
{
return (dimension + 63) / 64;
@@ -118,3 +199,8 @@ hantro_vp9_mv_size(unsigned int width, unsigned int height)
num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
return (num_ctbs * 64) * 16;
}
+
+int hantro_vp9_dec_init(struct hantro_ctx *ctx);
+void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
+
+#endif
diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c
index fa4224de4b99..406a755634bc 100644
--- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c
@@ -12,6 +12,11 @@
#include "hantro_jpeg.h"
#include "hantro_g1_regs.h"
#include "hantro_g2_regs.h"
+#include "hantro_h264.h"
+#include "hantro_hevc.h"
+#include "hantro_mpeg2.h"
+#include "hantro_vp8.h"
+#include "hantro_vp9.h"
#define CTRL_SOFT_RESET 0x00
#define RESET_G1 BIT(1)
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
index 6da87f5184bc..0d86490a3a6e 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
@@ -15,7 +15,7 @@
#include <media/v4l2-mem2mem.h>
-#include "hantro_hw.h"
+#include "hantro_h264.h"
#include "hantro_v4l2.h"
#define VDPU_SWREG(nr) ((nr) * 4)
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
index 50a3a3eeaa00..355c4d7697a3 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
@@ -9,7 +9,7 @@
#include <linux/bitfield.h>
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
-#include "hantro_hw.h"
+#include "hantro_mpeg2.h"
#define VDPU_SWREG(nr) ((nr) * 4)
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c
index d079075448c9..819967de8e96 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu2_hw_vp8_dec.c
@@ -14,9 +14,9 @@
#include <media/v4l2-mem2mem.h>
-#include "hantro_hw.h"
#include "hantro.h"
#include "hantro_g1_regs.h"
+#include "hantro_vp8.h"
#define VDPU_REG_DEC_CTRL0 0x0c8
#define VDPU_REG_STREAM_LEN 0x0cc
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
index f50a3e38097e..42176b0fd83c 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
@@ -13,6 +13,9 @@
#include "hantro_jpeg.h"
#include "hantro_g1_regs.h"
#include "hantro_h1_regs.h"
+#include "hantro_h264.h"
+#include "hantro_mpeg2.h"
+#include "hantro_vp8.h"
#include "rockchip_vpu2_regs.h"
#include "rockchip_vpu981_regs.h"
diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c
index 833821120b20..1d317942daa5 100644
--- a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c
@@ -11,6 +11,8 @@
#include "hantro.h"
#include "hantro_jpeg.h"
#include "hantro_h1_regs.h"
+#include "hantro_h264.h"
+#include "hantro_vp8.h"
/*
* Supported formats.
diff --git a/drivers/media/platform/verisilicon/sunxi_vpu_hw.c b/drivers/media/platform/verisilicon/sunxi_vpu_hw.c
index 02ce8b064a8f..2f95f9a681ee 100644
--- a/drivers/media/platform/verisilicon/sunxi_vpu_hw.c
+++ b/drivers/media/platform/verisilicon/sunxi_vpu_hw.c
@@ -8,6 +8,7 @@
#include <linux/clk.h>
#include "hantro.h"
+#include "hantro_vp9.h"
static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = {
{
--
2.43.0
^ permalink raw reply related
* [PATCH v3 1/2] media: verisilicon: Simplify motion vectors and rfc buffers allocation
From: Benjamin Gaignard @ 2026-04-15 14:04 UTC (permalink / raw)
To: nicolas.dufresne, p.zabel, mchehab, Frank.Li, s.hauer, kernel,
festevam, heiko, mcoquelin.stm32, alexandre.torgue, wens,
jernej.skrabec, samuel
Cc: linux-kernel, linux-media, linux-rockchip, imx, linux-arm-kernel,
linux-stm32, linux-sunxi, kernel, Benjamin Gaignard
In-Reply-To: <20260415140420.282084-1-benjamin.gaignard@collabora.com>
Until now we reserve the space needed for motion vectors and reference
frame compression at the end of the frame buffer.
Disentanglement mv and rfc from frame buffers by allocating
distinct buffers for each purpose.
That simplify the code by removing lot of offset computation.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/media/platform/verisilicon/hantro.h | 17 +-
.../media/platform/verisilicon/hantro_av1.c | 7 -
.../media/platform/verisilicon/hantro_av1.h | 14 +-
.../media/platform/verisilicon/hantro_g2.c | 36 ---
.../platform/verisilicon/hantro_g2_hevc_dec.c | 24 +-
.../platform/verisilicon/hantro_g2_vp9_dec.c | 12 +-
.../media/platform/verisilicon/hantro_h264.h | 33 +++
.../media/platform/verisilicon/hantro_hevc.c | 35 ++-
.../media/platform/verisilicon/hantro_hevc.h | 16 ++
.../media/platform/verisilicon/hantro_hw.h | 104 +------
.../platform/verisilicon/hantro_postproc.c | 29 +-
.../media/platform/verisilicon/hantro_v4l2.c | 255 ++++++++++++++++--
.../media/platform/verisilicon/hantro_vp9.h | 18 ++
.../verisilicon/rockchip_vpu981_hw_av1_dec.c | 16 +-
14 files changed, 388 insertions(+), 228 deletions(-)
create mode 100644 drivers/media/platform/verisilicon/hantro_h264.h
create mode 100644 drivers/media/platform/verisilicon/hantro_hevc.h
diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/platform/verisilicon/hantro.h
index 0353de154a1e..c4ceb9c99016 100644
--- a/drivers/media/platform/verisilicon/hantro.h
+++ b/drivers/media/platform/verisilicon/hantro.h
@@ -31,6 +31,9 @@ struct hantro_ctx;
struct hantro_codec_ops;
struct hantro_postproc_ops;
+#define MAX_MV_BUFFERS MAX_POSTPROC_BUFFERS
+#define MAX_RFC_BUFFERS MAX_POSTPROC_BUFFERS
+
#define HANTRO_JPEG_ENCODER BIT(0)
#define HANTRO_ENCODERS 0x0000ffff
#define HANTRO_MPEG2_DECODER BIT(16)
@@ -237,6 +240,9 @@ struct hantro_dev {
* @need_postproc: Set to true if the bitstream features require to
* use the post-processor.
*
+ * @dec_mv: motion vectors buffers for the context.
+ * @dec_rfc: reference frame compression buffers for the context.
+ *
* @codec_ops: Set of operations related to codec mode.
* @postproc: Post-processing context.
* @h264_dec: H.264-decoding context.
@@ -264,6 +270,9 @@ struct hantro_ctx {
int jpeg_quality;
int bit_depth;
+ struct hantro_aux_buf dec_mv[MAX_MV_BUFFERS];
+ struct hantro_aux_buf dec_rfc[MAX_RFC_BUFFERS];
+
const struct hantro_codec_ops *codec_ops;
struct hantro_postproc_ctx postproc;
bool need_postproc;
@@ -334,14 +343,14 @@ struct hantro_vp9_decoded_buffer_info {
unsigned short width;
unsigned short height;
size_t chroma_offset;
- size_t mv_offset;
+ dma_addr_t mv_addr;
u32 bit_depth : 4;
};
struct hantro_av1_decoded_buffer_info {
/* Info needed when the decoded frame serves as a reference frame. */
size_t chroma_offset;
- size_t mv_offset;
+ dma_addr_t mv_addr;
};
struct hantro_decoded_buffer {
@@ -507,4 +516,8 @@ void hantro_postproc_free(struct hantro_ctx *ctx);
int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
struct v4l2_frmsizeenum *fsize);
+dma_addr_t hantro_mv_get_buf_addr(struct hantro_ctx *ctx, int index);
+dma_addr_t hantro_rfc_get_luma_buf_addr(struct hantro_ctx *ctx, int index);
+dma_addr_t hantro_rfc_get_chroma_buf_addr(struct hantro_ctx *ctx, int index);
+
#endif /* HANTRO_H_ */
diff --git a/drivers/media/platform/verisilicon/hantro_av1.c b/drivers/media/platform/verisilicon/hantro_av1.c
index 5a51ac877c9c..3a80a7994f67 100644
--- a/drivers/media/platform/verisilicon/hantro_av1.c
+++ b/drivers/media/platform/verisilicon/hantro_av1.c
@@ -222,13 +222,6 @@ size_t hantro_av1_luma_size(struct hantro_ctx *ctx)
return ctx->ref_fmt.plane_fmt[0].bytesperline * ctx->ref_fmt.height;
}
-size_t hantro_av1_chroma_size(struct hantro_ctx *ctx)
-{
- size_t cr_offset = hantro_av1_luma_size(ctx);
-
- return ALIGN((cr_offset * 3) / 2, 64);
-}
-
static void hantro_av1_tiles_free(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
diff --git a/drivers/media/platform/verisilicon/hantro_av1.h b/drivers/media/platform/verisilicon/hantro_av1.h
index 4e2122b95cdd..bc4a0887f8e7 100644
--- a/drivers/media/platform/verisilicon/hantro_av1.h
+++ b/drivers/media/platform/verisilicon/hantro_av1.h
@@ -41,7 +41,6 @@ int hantro_av1_get_order_hint(struct hantro_ctx *ctx, int ref);
int hantro_av1_frame_ref(struct hantro_ctx *ctx, u64 timestamp);
void hantro_av1_clean_refs(struct hantro_ctx *ctx);
size_t hantro_av1_luma_size(struct hantro_ctx *ctx);
-size_t hantro_av1_chroma_size(struct hantro_ctx *ctx);
void hantro_av1_exit(struct hantro_ctx *ctx);
int hantro_av1_init(struct hantro_ctx *ctx);
int hantro_av1_prepare_run(struct hantro_ctx *ctx);
@@ -59,4 +58,17 @@ void hantro_av1_set_prob(struct hantro_ctx *ctx);
int hantro_av1_get_hardware_mcomp_filt_type(int interpolation_filter);
int hantro_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode);
+static inline unsigned short hantro_av1_num_sbs(unsigned short dimension)
+{
+ return DIV_ROUND_UP(dimension, 64);
+}
+
+static inline size_t
+hantro_av1_mv_size(unsigned int width, unsigned int height)
+{
+ size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height);
+
+ return ALIGN(num_sbs * 384, 16) * 2 + 512;
+}
+
#endif
diff --git a/drivers/media/platform/verisilicon/hantro_g2.c b/drivers/media/platform/verisilicon/hantro_g2.c
index 318673b66da8..4ae7df53dcb1 100644
--- a/drivers/media/platform/verisilicon/hantro_g2.c
+++ b/drivers/media/platform/verisilicon/hantro_g2.c
@@ -99,39 +99,3 @@ size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx)
{
return ctx->ref_fmt.plane_fmt[0].bytesperline * ctx->ref_fmt.height;
}
-
-size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx)
-{
- size_t cr_offset = hantro_g2_chroma_offset(ctx);
-
- return ALIGN((cr_offset * 3) / 2, G2_ALIGN);
-}
-
-static size_t hantro_g2_mv_size(struct hantro_ctx *ctx)
-{
- const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
- const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
- unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
- unsigned int max_log2_ctb_size;
-
- max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
- sps->log2_diff_max_min_luma_coding_block_size;
- pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
- (1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;
- pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)
- >> max_log2_ctb_size;
-
- return pic_width_in_ctbs * pic_height_in_ctbs * (1 << (2 * (max_log2_ctb_size - 4))) * 16;
-}
-
-size_t hantro_g2_luma_compress_offset(struct hantro_ctx *ctx)
-{
- return hantro_g2_motion_vectors_offset(ctx) +
- hantro_g2_mv_size(ctx);
-}
-
-size_t hantro_g2_chroma_compress_offset(struct hantro_ctx *ctx)
-{
- return hantro_g2_luma_compress_offset(ctx) +
- hantro_hevc_luma_compressed_size(ctx->dst_fmt.width, ctx->dst_fmt.height);
-}
diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
index e8c2e83379de..d0af9fb882ba 100644
--- a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
@@ -383,9 +383,6 @@ static int set_ref(struct hantro_ctx *ctx)
struct vb2_v4l2_buffer *vb2_dst;
struct hantro_decoded_buffer *dst;
size_t cr_offset = hantro_g2_chroma_offset(ctx);
- size_t mv_offset = hantro_g2_motion_vectors_offset(ctx);
- size_t compress_luma_offset = hantro_g2_luma_compress_offset(ctx);
- size_t compress_chroma_offset = hantro_g2_chroma_compress_offset(ctx);
u32 max_ref_frames;
u16 dpb_longterm_e;
static const struct hantro_reg cur_poc[] = {
@@ -453,14 +450,17 @@ static int set_ref(struct hantro_ctx *ctx)
dpb_longterm_e = 0;
for (i = 0; i < decode_params->num_active_dpb_entries &&
i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
+ int index = hantro_hevc_get_ref_buf_index(ctx, dpb[i].pic_order_cnt_val);
luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt_val);
if (!luma_addr)
return -ENOMEM;
chroma_addr = luma_addr + cr_offset;
- mv_addr = luma_addr + mv_offset;
- compress_luma_addr = luma_addr + compress_luma_offset;
- compress_chroma_addr = luma_addr + compress_chroma_offset;
+ mv_addr = hantro_mv_get_buf_addr(ctx, index);
+ if (ctx->hevc_dec.use_compression) {
+ compress_luma_addr = hantro_rfc_get_luma_buf_addr(ctx, index);
+ compress_chroma_addr = hantro_rfc_get_chroma_buf_addr(ctx, index);
+ }
if (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
@@ -478,13 +478,17 @@ static int set_ref(struct hantro_ctx *ctx)
if (!luma_addr)
return -ENOMEM;
- if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))
+ if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr, vb2_dst))
return -EINVAL;
chroma_addr = luma_addr + cr_offset;
- mv_addr = luma_addr + mv_offset;
- compress_luma_addr = luma_addr + compress_luma_offset;
- compress_chroma_addr = luma_addr + compress_chroma_offset;
+ mv_addr = hantro_mv_get_buf_addr(ctx, dst->base.vb.vb2_buf.index);
+ if (ctx->hevc_dec.use_compression) {
+ compress_luma_addr =
+ hantro_rfc_get_luma_buf_addr(ctx, dst->base.vb.vb2_buf.index);
+ compress_chroma_addr =
+ hantro_rfc_get_chroma_buf_addr(ctx, dst->base.vb.vb2_buf.index);
+ }
hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
diff --git a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
index 56c79e339030..1e96d0fce72a 100644
--- a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
+++ b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
@@ -129,7 +129,7 @@ static void config_output(struct hantro_ctx *ctx,
struct hantro_decoded_buffer *dst,
const struct v4l2_ctrl_vp9_frame *dec_params)
{
- dma_addr_t luma_addr, chroma_addr, mv_addr;
+ dma_addr_t luma_addr, chroma_addr;
hantro_reg_write(ctx->dev, &g2_out_dis, 0);
if (!ctx->dev->variant->legacy_regs)
@@ -142,9 +142,8 @@ static void config_output(struct hantro_ctx *ctx,
hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr);
dst->vp9.chroma_offset = hantro_g2_chroma_offset(ctx);
- mv_addr = luma_addr + hantro_g2_motion_vectors_offset(ctx);
- hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr);
- dst->vp9.mv_offset = hantro_g2_motion_vectors_offset(ctx);
+ dst->vp9.mv_addr = hantro_mv_get_buf_addr(ctx, dst->base.vb.vb2_buf.index);
+ hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, dst->vp9.mv_addr);
}
struct hantro_vp9_ref_reg {
@@ -215,15 +214,12 @@ static void config_ref_registers(struct hantro_ctx *ctx,
.c_base = G2_REF_CHROMA_ADDR(5),
},
};
- dma_addr_t mv_addr;
config_ref(ctx, dst, &ref_regs[0], dec_params, dec_params->last_frame_ts);
config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts);
config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts);
- mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) +
- mv_ref->vp9.mv_offset;
- hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr);
+ hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_ref->vp9.mv_addr);
hantro_reg_write(ctx->dev, &vp9_last_sign_bias,
dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0);
diff --git a/drivers/media/platform/verisilicon/hantro_h264.h b/drivers/media/platform/verisilicon/hantro_h264.h
new file mode 100644
index 000000000000..89348203a712
--- /dev/null
+++ b/drivers/media/platform/verisilicon/hantro_h264.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Hantro H264 codec driver
+ *
+ * Copyright (C) 2026 Collabora Ltd.
+ */
+
+static inline size_t
+hantro_h264_mv_size(unsigned int width, unsigned int height)
+{
+ /*
+ * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
+ * 448 bytes per macroblock with additional 32 bytes on
+ * multi-core variants.
+ *
+ * The H264 decoder needs extra space on the output buffers
+ * to store motion vectors. This is needed for reference
+ * frames and only if the format is non-post-processed NV12.
+ *
+ * Memory layout is as follow:
+ *
+ * +---------------------------+
+ * | Y-plane 256 bytes x MBs |
+ * +---------------------------+
+ * | UV-plane 128 bytes x MBs |
+ * +---------------------------+
+ * | MV buffer 64 bytes x MBs |
+ * +---------------------------+
+ * | MC sync 32 bytes |
+ * +---------------------------+
+ */
+ return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
+}
diff --git a/drivers/media/platform/verisilicon/hantro_hevc.c b/drivers/media/platform/verisilicon/hantro_hevc.c
index 83cd12b0ddd6..eea4d9e6fde0 100644
--- a/drivers/media/platform/verisilicon/hantro_hevc.c
+++ b/drivers/media/platform/verisilicon/hantro_hevc.c
@@ -44,30 +44,49 @@ dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
int i;
/* Find the reference buffer in already known ones */
- for (i = 0; i < NUM_REF_PICTURES; i++) {
+ for (i = 0; i < NUM_REF_PICTURES; i++) {
if (hevc_dec->ref_bufs_poc[i] == poc) {
hevc_dec->ref_bufs_used |= 1 << i;
return hevc_dec->ref_bufs[i].dma;
}
}
-
return 0;
}
-int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr)
+int hantro_hevc_get_ref_buf_index(struct hantro_ctx *ctx, s32 poc)
{
struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
int i;
- /* Add a new reference buffer */
+ /* Find the reference buffer in already known ones */
for (i = 0; i < NUM_REF_PICTURES; i++) {
- if (!(hevc_dec->ref_bufs_used & 1 << i)) {
+ if (hevc_dec->ref_bufs_poc[i] == poc) {
hevc_dec->ref_bufs_used |= 1 << i;
- hevc_dec->ref_bufs_poc[i] = poc;
- hevc_dec->ref_bufs[i].dma = addr;
- return 0;
+ return hevc_dec->ref_vb2[i]->vb2_buf.index;
}
}
+ return 0;
+}
+
+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx,
+ int poc,
+ dma_addr_t addr,
+ struct vb2_v4l2_buffer *vb2)
+{
+ struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
+ int i;
+
+ /* Add a new reference buffer */
+ for (i = 0; i < NUM_REF_PICTURES; i++) {
+ if (hevc_dec->ref_bufs_used & (1 << i))
+ continue;
+
+ hevc_dec->ref_bufs_used |= 1 << i;
+ hevc_dec->ref_bufs_poc[i] = poc;
+ hevc_dec->ref_bufs[i].dma = addr;
+ hevc_dec->ref_vb2[i] = vb2;
+ return 0;
+ }
return -EINVAL;
}
diff --git a/drivers/media/platform/verisilicon/hantro_hevc.h b/drivers/media/platform/verisilicon/hantro_hevc.h
new file mode 100644
index 000000000000..cfaeb8662473
--- /dev/null
+++ b/drivers/media/platform/verisilicon/hantro_hevc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Hantro H264 codec driver
+ *
+ * Copyright (C) 2026 Collabora Ltd.
+ */
+
+static inline size_t
+hantro_hevc_mv_size(unsigned int width, unsigned int height, int depth)
+{
+ /*
+ * A CTB can be 64x64, 32x32 or 16x16.
+ * Allocated memory for the "worse" case: 16x16
+ */
+ return DIV_ROUND_UP(width * height * depth / 8, 16);
+}
diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h
index d1d39d1df5d2..6903af119345 100644
--- a/drivers/media/platform/verisilicon/hantro_hw.h
+++ b/drivers/media/platform/verisilicon/hantro_hw.h
@@ -162,6 +162,7 @@ struct hantro_hevc_dec_hw_ctx {
struct hantro_aux_buf scaling_lists;
s32 ref_bufs_poc[NUM_REF_PICTURES];
u32 ref_bufs_used;
+ struct vb2_v4l2_buffer *ref_vb2[NUM_REF_PICTURES];
struct hantro_hevc_dec_ctrls ctrls;
unsigned int num_tile_cols_allocated;
bool use_compression;
@@ -457,109 +458,14 @@ int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
void hantro_hevc_ref_init(struct hantro_ctx *ctx);
dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
-int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);
+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc,
+ dma_addr_t addr,
+ struct vb2_v4l2_buffer *vb2);
+int hantro_hevc_get_ref_buf_index(struct hantro_ctx *ctx, s32 poc);
int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx);
-static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)
-{
- return (dimension + 63) / 64;
-}
-
-static inline size_t
-hantro_vp9_mv_size(unsigned int width, unsigned int height)
-{
- int num_ctbs;
-
- /*
- * There can be up to (CTBs x 64) number of blocks,
- * and the motion vector for each block needs 16 bytes.
- */
- num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
- return (num_ctbs * 64) * 16;
-}
-
-static inline size_t
-hantro_h264_mv_size(unsigned int width, unsigned int height)
-{
- /*
- * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
- * 448 bytes per macroblock with additional 32 bytes on
- * multi-core variants.
- *
- * The H264 decoder needs extra space on the output buffers
- * to store motion vectors. This is needed for reference
- * frames and only if the format is non-post-processed NV12.
- *
- * Memory layout is as follow:
- *
- * +---------------------------+
- * | Y-plane 256 bytes x MBs |
- * +---------------------------+
- * | UV-plane 128 bytes x MBs |
- * +---------------------------+
- * | MV buffer 64 bytes x MBs |
- * +---------------------------+
- * | MC sync 32 bytes |
- * +---------------------------+
- */
- return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
-}
-
-static inline size_t
-hantro_hevc_mv_size(unsigned int width, unsigned int height)
-{
- /*
- * A CTB can be 64x64, 32x32 or 16x16.
- * Allocated memory for the "worse" case: 16x16
- */
- return width * height / 16;
-}
-
-static inline size_t
-hantro_hevc_luma_compressed_size(unsigned int width, unsigned int height)
-{
- u32 pic_width_in_cbsy =
- round_up((width + CBS_LUMA - 1) / CBS_LUMA, CBS_SIZE);
- u32 pic_height_in_cbsy = (height + CBS_LUMA - 1) / CBS_LUMA;
-
- return round_up(pic_width_in_cbsy * pic_height_in_cbsy, CBS_SIZE);
-}
-
-static inline size_t
-hantro_hevc_chroma_compressed_size(unsigned int width, unsigned int height)
-{
- u32 pic_width_in_cbsc =
- round_up((width + CBS_CHROMA_W - 1) / CBS_CHROMA_W, CBS_SIZE);
- u32 pic_height_in_cbsc = (height / 2 + CBS_CHROMA_H - 1) / CBS_CHROMA_H;
-
- return round_up(pic_width_in_cbsc * pic_height_in_cbsc, CBS_SIZE);
-}
-
-static inline size_t
-hantro_hevc_compressed_size(unsigned int width, unsigned int height)
-{
- return hantro_hevc_luma_compressed_size(width, height) +
- hantro_hevc_chroma_compressed_size(width, height);
-}
-
-static inline unsigned short hantro_av1_num_sbs(unsigned short dimension)
-{
- return DIV_ROUND_UP(dimension, 64);
-}
-
-static inline size_t
-hantro_av1_mv_size(unsigned int width, unsigned int height)
-{
- size_t num_sbs = hantro_av1_num_sbs(width) * hantro_av1_num_sbs(height);
-
- return ALIGN(num_sbs * 384, 16) * 2 + 512;
-}
-
size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx);
-size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx);
-size_t hantro_g2_luma_compress_offset(struct hantro_ctx *ctx);
-size_t hantro_g2_chroma_compress_offset(struct hantro_ctx *ctx);
int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c b/drivers/media/platform/verisilicon/hantro_postproc.c
index e94d1ba5ef10..2409353c16e4 100644
--- a/drivers/media/platform/verisilicon/hantro_postproc.c
+++ b/drivers/media/platform/verisilicon/hantro_postproc.c
@@ -196,36 +196,11 @@ void hantro_postproc_free(struct hantro_ctx *ctx)
}
}
-static unsigned int hantro_postproc_buffer_size(struct hantro_ctx *ctx)
-{
- unsigned int buf_size;
-
- buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
- if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
- buf_size += hantro_h264_mv_size(ctx->ref_fmt.width,
- ctx->ref_fmt.height);
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
- buf_size += hantro_vp9_mv_size(ctx->ref_fmt.width,
- ctx->ref_fmt.height);
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
- buf_size += hantro_hevc_mv_size(ctx->ref_fmt.width,
- ctx->ref_fmt.height);
- if (ctx->hevc_dec.use_compression)
- buf_size += hantro_hevc_compressed_size(ctx->ref_fmt.width,
- ctx->ref_fmt.height);
- }
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME)
- buf_size += hantro_av1_mv_size(ctx->ref_fmt.width,
- ctx->ref_fmt.height);
-
- return buf_size;
-}
-
static int hantro_postproc_alloc(struct hantro_ctx *ctx, int index)
{
struct hantro_dev *vpu = ctx->dev;
struct hantro_aux_buf *priv = &ctx->postproc.dec_q[index];
- unsigned int buf_size = hantro_postproc_buffer_size(ctx);
+ unsigned int buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
if (!buf_size)
return -EINVAL;
@@ -267,7 +242,7 @@ dma_addr_t
hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index)
{
struct hantro_aux_buf *priv = &ctx->postproc.dec_q[index];
- unsigned int buf_size = hantro_postproc_buffer_size(ctx);
+ unsigned int buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
struct hantro_dev *vpu = ctx->dev;
int ret;
diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/media/platform/verisilicon/hantro_v4l2.c
index fcf3bd9bcda2..bbc1e9e2840e 100644
--- a/drivers/media/platform/verisilicon/hantro_v4l2.c
+++ b/drivers/media/platform/verisilicon/hantro_v4l2.c
@@ -25,8 +25,12 @@
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
+#include "hantro_av1.h"
#include "hantro_hw.h"
+#include "hantro_h264.h"
+#include "hantro_hevc.h"
#include "hantro_v4l2.h"
+#include "hantro_vp9.h"
#define HANTRO_DEFAULT_BIT_DEPTH 8
@@ -36,6 +40,9 @@ static int hantro_set_fmt_out(struct hantro_ctx *ctx,
static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
struct v4l2_pix_format_mplane *pix_mp);
+static void hantro_mv_free(struct hantro_ctx *ctx);
+static void hantro_rfc_free(struct hantro_ctx *ctx);
+
static const struct hantro_fmt *
hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts, bool need_postproc)
{
@@ -362,26 +369,6 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx,
/* Fill remaining fields */
v4l2_fill_pixfmt_mp(pix_mp, fmt->fourcc, pix_mp->width,
pix_mp->height);
- if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE &&
- !hantro_needs_postproc(ctx, fmt))
- pix_mp->plane_fmt[0].sizeimage +=
- hantro_h264_mv_size(pix_mp->width,
- pix_mp->height);
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME &&
- !hantro_needs_postproc(ctx, fmt))
- pix_mp->plane_fmt[0].sizeimage +=
- hantro_vp9_mv_size(pix_mp->width,
- pix_mp->height);
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE &&
- !hantro_needs_postproc(ctx, fmt))
- pix_mp->plane_fmt[0].sizeimage +=
- hantro_hevc_mv_size(pix_mp->width,
- pix_mp->height);
- else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME &&
- !hantro_needs_postproc(ctx, fmt))
- pix_mp->plane_fmt[0].sizeimage +=
- hantro_av1_mv_size(pix_mp->width,
- pix_mp->height);
} else if (!pix_mp->plane_fmt[0].sizeimage) {
/*
* For coded formats the application can specify
@@ -984,6 +971,9 @@ static void hantro_stop_streaming(struct vb2_queue *q)
ctx->codec_ops->exit(ctx);
}
+ hantro_mv_free(ctx);
+ hantro_rfc_free(ctx);
+
/*
* The mem2mem framework calls v4l2_m2m_cancel_job before
* .stop_streaming, so there isn't any job running and
@@ -1025,3 +1015,228 @@ const struct vb2_ops hantro_queue_ops = {
.start_streaming = hantro_start_streaming,
.stop_streaming = hantro_stop_streaming,
};
+
+static void hantro_mv_free(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ int i;
+
+ for (i = 0; i < MAX_MV_BUFFERS; i++) {
+ struct hantro_aux_buf *mv = &ctx->dec_mv[i];
+
+ if (!mv->cpu)
+ continue;
+
+ dma_free_attrs(vpu->dev, mv->size, mv->cpu,
+ mv->dma, mv->attrs);
+ mv->cpu = NULL;
+ }
+}
+
+static unsigned int hantro_mv_buffer_size(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ int fourcc = ctx->vpu_src_fmt->fourcc;
+ int width = ctx->ref_fmt.width;
+ int height = ctx->ref_fmt.height;
+
+ switch (fourcc) {
+ case V4L2_PIX_FMT_H264_SLICE:
+ return hantro_h264_mv_size(width, height);
+ case V4L2_PIX_FMT_VP9_FRAME:
+ return hantro_vp9_mv_size(width, height);
+ case V4L2_PIX_FMT_HEVC_SLICE:
+ return hantro_hevc_mv_size(width, height, ctx->bit_depth);
+ case V4L2_PIX_FMT_AV1_FRAME:
+ return hantro_av1_mv_size(width, height);
+ }
+
+ /* Should not happen */
+ dev_warn(vpu->dev, "Invalid motion vectors size\n");
+ return 0;
+}
+
+static int hantro_mv_buffer_alloc(struct hantro_ctx *ctx, int index)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ struct hantro_aux_buf *mv = &ctx->dec_mv[index];
+ unsigned int buf_size = hantro_mv_buffer_size(ctx);
+
+ if (!buf_size)
+ return -EINVAL;
+
+ /*
+ * Motion vectors buffers are only read and write by the
+ * hardware so no mapping is needed.
+ */
+ mv->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
+ mv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &mv->dma,
+ GFP_KERNEL, mv->attrs);
+ if (!mv->cpu)
+ return -ENOMEM;
+ mv->size = buf_size;
+
+ return 0;
+}
+
+dma_addr_t
+hantro_mv_get_buf_addr(struct hantro_ctx *ctx, int index)
+{
+ struct hantro_aux_buf *mv = &ctx->dec_mv[index];
+ unsigned int buf_size = hantro_mv_buffer_size(ctx);
+ struct hantro_dev *vpu = ctx->dev;
+ int ret;
+
+ if (mv->size < buf_size && mv->cpu) {
+ /* buffer is too small, release it */
+ dma_free_attrs(vpu->dev, mv->size, mv->cpu,
+ mv->dma, mv->attrs);
+ mv->cpu = NULL;
+ }
+
+ if (!mv->cpu) {
+ /* buffer not already allocated, try getting a new one */
+ ret = hantro_mv_buffer_alloc(ctx, index);
+ if (ret)
+ return 0;
+ }
+
+ if (!mv->cpu)
+ return 0;
+
+ return mv->dma;
+}
+
+static inline size_t
+hantro_hevc_luma_compressed_size(unsigned int width, unsigned int height)
+{
+ u32 pic_width_in_cbsy =
+ round_up((width + CBS_LUMA - 1) / CBS_LUMA, CBS_SIZE);
+ u32 pic_height_in_cbsy = (height + CBS_LUMA - 1) / CBS_LUMA;
+
+ return round_up(pic_width_in_cbsy * pic_height_in_cbsy, CBS_SIZE);
+}
+
+static inline size_t
+hantro_hevc_chroma_compressed_size(unsigned int width, unsigned int height)
+{
+ u32 pic_width_in_cbsc =
+ round_up((width + CBS_CHROMA_W - 1) / CBS_CHROMA_W, CBS_SIZE);
+ u32 pic_height_in_cbsc = (height / 2 + CBS_CHROMA_H - 1) / CBS_CHROMA_H;
+
+ return round_up(pic_width_in_cbsc * pic_height_in_cbsc, CBS_SIZE);
+}
+
+static inline size_t
+hantro_hevc_compressed_size(unsigned int width, unsigned int height)
+{
+ return hantro_hevc_luma_compressed_size(width, height) +
+ hantro_hevc_chroma_compressed_size(width, height);
+}
+
+static void hantro_rfc_free(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ int i;
+
+ for (i = 0; i < MAX_RFC_BUFFERS; i++) {
+ struct hantro_aux_buf *rfc = &ctx->dec_rfc[i];
+
+ if (!rfc->cpu)
+ continue;
+
+ dma_free_attrs(vpu->dev, rfc->size, rfc->cpu,
+ rfc->dma, rfc->attrs);
+ rfc->cpu = NULL;
+ }
+}
+
+static unsigned int hantro_rfc_buffer_size(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ int fourcc = ctx->vpu_src_fmt->fourcc;
+ int width = ctx->ref_fmt.width;
+ int height = ctx->ref_fmt.height;
+
+ switch (fourcc) {
+ case V4L2_PIX_FMT_HEVC_SLICE:
+ return hantro_hevc_compressed_size(width, height);
+ }
+
+ /* Should not happen */
+ dev_warn(vpu->dev, "Invalid rfc size\n");
+ return 0;
+}
+
+static int hantro_rfc_buffer_alloc(struct hantro_ctx *ctx, int index)
+{
+ struct hantro_dev *vpu = ctx->dev;
+ struct hantro_aux_buf *rfc = &ctx->dec_rfc[index];
+ unsigned int buf_size = hantro_rfc_buffer_size(ctx);
+
+ if (!buf_size)
+ return -EINVAL;
+
+ /*
+ * RFC buffers are only read and write by the
+ * hardware so no mapping is needed.
+ */
+ rfc->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
+ rfc->cpu = dma_alloc_attrs(vpu->dev, buf_size, &rfc->dma,
+ GFP_KERNEL, rfc->attrs);
+ if (!rfc->cpu)
+ return -ENOMEM;
+ rfc->size = buf_size;
+
+ return 0;
+}
+
+dma_addr_t
+hantro_rfc_get_luma_buf_addr(struct hantro_ctx *ctx, int index)
+{
+ struct hantro_aux_buf *rfc = &ctx->dec_rfc[index];
+ unsigned int buf_size = hantro_rfc_buffer_size(ctx);
+ struct hantro_dev *vpu = ctx->dev;
+ int ret;
+
+ if (rfc->size < buf_size && rfc->cpu) {
+ /* buffer is too small, release it */
+ dma_free_attrs(vpu->dev, rfc->size, rfc->cpu,
+ rfc->dma, rfc->attrs);
+ rfc->cpu = NULL;
+ }
+
+ if (!rfc->cpu) {
+ /* buffer not already allocated, try getting a new one */
+ ret = hantro_rfc_buffer_alloc(ctx, index);
+ if (ret)
+ return 0;
+ }
+
+ if (!rfc->cpu)
+ return 0;
+
+ return rfc->dma;
+}
+
+dma_addr_t
+hantro_rfc_get_chroma_buf_addr(struct hantro_ctx *ctx, int index)
+{
+ dma_addr_t luma_addr = hantro_rfc_get_luma_buf_addr(ctx, index);
+ struct hantro_dev *vpu = ctx->dev;
+ int fourcc = ctx->vpu_src_fmt->fourcc;
+ int width = ctx->ref_fmt.width;
+ int height = ctx->ref_fmt.height;
+
+ if (!luma_addr)
+ return -EINVAL;
+
+ switch (fourcc) {
+ case V4L2_PIX_FMT_HEVC_SLICE:
+ return luma_addr + hantro_hevc_luma_compressed_size(width, height);
+ }
+
+ /* Should not happen */
+ dev_warn(vpu->dev, "Invalid rfc chroma address\n");
+ return 0;
+}
diff --git a/drivers/media/platform/verisilicon/hantro_vp9.h b/drivers/media/platform/verisilicon/hantro_vp9.h
index 26b69275f098..fcdad2242f78 100644
--- a/drivers/media/platform/verisilicon/hantro_vp9.h
+++ b/drivers/media/platform/verisilicon/hantro_vp9.h
@@ -100,3 +100,21 @@ struct symbol_counts {
u32 count_eobs[4][2][2][6][6];
};
+
+static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension)
+{
+ return (dimension + 63) / 64;
+}
+
+static inline size_t
+hantro_vp9_mv_size(unsigned int width, unsigned int height)
+{
+ int num_ctbs;
+
+ /*
+ * There can be up to (CTBs x 64) number of blocks,
+ * and the motion vector for each block needs 16 bytes.
+ */
+ num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
+ return (num_ctbs * 64) * 16;
+}
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
index 990a5e6b5531..2cf4233d6888 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
@@ -62,7 +62,7 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
struct hantro_dev *vpu = ctx->dev;
struct hantro_decoded_buffer *dst;
- dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
+ dma_addr_t luma_addr, chroma_addr = 0;
int cur_width = frame->frame_width_minus_1 + 1;
int cur_height = frame->frame_height_minus_1 + 1;
int scale_width =
@@ -120,11 +120,10 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf);
luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
chroma_addr = luma_addr + dst->av1.chroma_offset;
- mv_addr = luma_addr + dst->av1.mv_offset;
hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr);
hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr);
- hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr);
+ hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), dst->av1.mv_addr);
return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) ||
(scale_height != (1 << AV1_REF_SCALE_SHIFT));
@@ -180,11 +179,10 @@ static void rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx)
if (idx >= 0) {
dma_addr_t luma_addr, mv_addr = 0;
struct hantro_decoded_buffer *seg;
- size_t mv_offset = hantro_av1_chroma_size(ctx);
seg = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf);
luma_addr = hantro_get_dec_buf_addr(ctx, &seg->base.vb.vb2_buf);
- mv_addr = luma_addr + mv_offset;
+ mv_addr = hantro_mv_get_buf_addr(ctx, seg->base.vb.vb2_buf.index);
hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr);
hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1);
@@ -1345,22 +1343,20 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx)
struct hantro_dev *vpu = ctx->dev;
struct hantro_decoded_buffer *dst;
struct vb2_v4l2_buffer *vb2_dst;
- dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
+ dma_addr_t luma_addr, chroma_addr = 0;
size_t cr_offset = hantro_av1_luma_size(ctx);
- size_t mv_offset = hantro_av1_chroma_size(ctx);
vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref;
dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
chroma_addr = luma_addr + cr_offset;
- mv_addr = luma_addr + mv_offset;
dst->av1.chroma_offset = cr_offset;
- dst->av1.mv_offset = mv_offset;
+ dst->av1.mv_addr = hantro_mv_get_buf_addr(ctx, dst->base.vb.vb2_buf.index);
hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr);
hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr);
- hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);
+ hantro_write_addr(vpu, AV1_TILE_OUT_MV, dst->av1.mv_addr);
}
int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx)
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/2] media: verisilicon: Simplification and clean up
From: Benjamin Gaignard @ 2026-04-15 14:04 UTC (permalink / raw)
To: nicolas.dufresne, p.zabel, mchehab, Frank.Li, s.hauer, kernel,
festevam, heiko, mcoquelin.stm32, alexandre.torgue, wens,
jernej.skrabec, samuel
Cc: linux-kernel, linux-media, linux-rockchip, imx, linux-arm-kernel,
linux-stm32, linux-sunxi, kernel, Benjamin Gaignard
Simplify motion vectors and reference allocation with common helpers.
Since it requires to move some of codecs specific functions and
structure in codecs header files add a patch to finish the clean up.
Benjamin Gaignard (2):
media: verisilicon: Simplify motion vectors and rfc buffers allocation
media: verisilicon: Clean up messy include
drivers/media/platform/verisilicon/hantro.h | 31 +-
.../media/platform/verisilicon/hantro_av1.c | 7 -
.../media/platform/verisilicon/hantro_av1.h | 100 +++-
.../platform/verisilicon/hantro_g1_h264_dec.c | 1 +
.../verisilicon/hantro_g1_mpeg2_dec.c | 2 +-
.../platform/verisilicon/hantro_g1_vp8_dec.c | 2 +-
.../media/platform/verisilicon/hantro_g2.c | 36 --
.../platform/verisilicon/hantro_g2_hevc_dec.c | 26 +-
.../platform/verisilicon/hantro_g2_vp9_dec.c | 12 +-
.../media/platform/verisilicon/hantro_h264.c | 2 +-
.../media/platform/verisilicon/hantro_h264.h | 98 ++++
.../media/platform/verisilicon/hantro_hevc.c | 37 +-
.../media/platform/verisilicon/hantro_hevc.h | 82 ++++
.../media/platform/verisilicon/hantro_hw.h | 446 +-----------------
.../media/platform/verisilicon/hantro_mpeg2.c | 1 +
.../media/platform/verisilicon/hantro_mpeg2.h | 27 ++
.../platform/verisilicon/hantro_postproc.c | 29 +-
.../media/platform/verisilicon/hantro_v4l2.c | 262 +++++++++-
.../media/platform/verisilicon/hantro_vp8.c | 1 +
.../media/platform/verisilicon/hantro_vp8.h | 29 ++
.../media/platform/verisilicon/hantro_vp9.h | 104 ++++
.../media/platform/verisilicon/imx8m_vpu_hw.c | 5 +
.../verisilicon/rockchip_vpu2_hw_h264_dec.c | 2 +-
.../verisilicon/rockchip_vpu2_hw_mpeg2_dec.c | 2 +-
.../verisilicon/rockchip_vpu2_hw_vp8_dec.c | 2 +-
.../verisilicon/rockchip_vpu981_hw_av1_dec.c | 16 +-
.../platform/verisilicon/rockchip_vpu_hw.c | 3 +
.../platform/verisilicon/stm32mp25_vpu_hw.c | 2 +
.../media/platform/verisilicon/sunxi_vpu_hw.c | 1 +
29 files changed, 796 insertions(+), 572 deletions(-)
create mode 100644 drivers/media/platform/verisilicon/hantro_h264.h
create mode 100644 drivers/media/platform/verisilicon/hantro_hevc.h
create mode 100644 drivers/media/platform/verisilicon/hantro_mpeg2.h
create mode 100644 drivers/media/platform/verisilicon/hantro_vp8.h
--
2.43.0
^ permalink raw reply
* Re: [PATCH RFC] ACPI: processor: idle: Do not propagate acpi_processor_ffh_lpi_probe() -ENODEV
From: Rafael J. Wysocki @ 2026-04-15 14:03 UTC (permalink / raw)
To: lihuisong (C)
Cc: Sudeep Holla, Rafael J. Wysocki, Breno Leitao, Len Brown,
lpieralisi, catalin.marinas, will, Rafael J. Wysocki, linux-acpi,
linux-kernel, pjaroszynski, guohanjun, linux-arm-kernel, rmikey,
kernel-team
In-Reply-To: <33c15199-25ea-4d39-bff9-91af0b49633e@huawei.com>
On Wed, Apr 15, 2026 at 3:32 AM lihuisong (C) <lihuisong@huawei.com> wrote:
>
>
> On 4/14/2026 8:25 PM, Sudeep Holla wrote:
> > On Tue, Apr 14, 2026 at 07:31:29PM +0800, lihuisong (C) wrote:
> >> On 4/14/2026 6:21 PM, Breno Leitao wrote:
> >>> Hello Huisong,
> >>>
> >>> On Tue, Apr 14, 2026 at 05:43:51PM +0800, lihuisong (C) wrote:
> >>>> But it is a real issue. Thanks for your report.
> >>>> I think the best way to fix your issue is that remove this verification in
> >>>> psci_acpi_cpu_init_idle().
> >>>> Because it is legal for platform to report one LPI state.
> >>>> This function just needs to verify the LPI states which are FFH.
> >>> Thank you for the prompt feedback.
> >>>
> >>> Would this approach work?
> >>>
> >>> commit 6c9d52840a4f778cc989838ba76ee51416e85de3
> >>> Author: Breno Leitao <leitao@debian.org>
> >>> Date: Tue Apr 14 03:16:08 2026 -0700
> >>>
> >>> ACPI: processor: idle: Allow platforms with only one LPI state
> >>> psci_acpi_cpu_init_idle() rejects platforms where power.count - 1 <= 0
> >>> by returning -ENODEV. However, having a single LPI state (WFI) is a
> >>> valid configuration. The function's purpose is to verify FFH idle states,
> >>> and when count is zero, there are simply no FFH states to validate —
> >>> this is not an error.
> >>> On NVIDIA Grace (aarch64) systems with PSCIv1.1, power.count is 1 for
> >>> all 72 CPUs, so the probe fails with -ENODEV. After commit cac173bea57d
> >>> ("ACPI: processor: idle: Rework the handling of
> >>> acpi_processor_ffh_lpi_probe()"), this failure propagates up and prevents
> >>> cpuidle registration entirely.
> >>> Change the check from (count <= 0) to (count < 0) so that platforms
> >>> with only WFI are accepted. The for loop naturally handles count == 0
> >>> by not iterating.
> >>> Fixes: cac173bea57d ("ACPI: processor: idle: Rework the handling of acpi_processor_ffh_lpi_probe()")
> >>> Signed-off-by: Breno Leitao <leitao@debian.org>
> >>>
> >>> diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c
> >>> index 801f9c4501425..7791b751042ce 100644
> >>> --- a/drivers/acpi/arm64/cpuidle.c
> >>> +++ b/drivers/acpi/arm64/cpuidle.c
> >>> @@ -31,7 +31,7 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu)
> >>> return -EOPNOTSUPP;
> >>> count = pr->power.count - 1;
> >>> - if (count <= 0)
> >>> + if (count < 0)
> >>> return -ENODEV;
> >>> for (i = 0; i < count; i++) {
> >> This count already verified in acpi_processor_get_lpi_info.
> >>
> >> I suggest modifing it as below:
> >>
> >> -->
> >>
> >> git diff
> >> diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c
> >> index 801f9c450142..c68a5db8ebba 100644
> >> --- a/drivers/acpi/arm64/cpuidle.c
> >> +++ b/drivers/acpi/arm64/cpuidle.c
> >> @@ -16,7 +16,7 @@
> >>
> >> static int psci_acpi_cpu_init_idle(unsigned int cpu)
> >> {
> >> - int i, count;
> >> + int i;
> >> struct acpi_lpi_state *lpi;
> >> struct acpi_processor *pr = per_cpu(processors, cpu);
> >>
> >> @@ -30,14 +30,10 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu)
> >> if (!psci_ops.cpu_suspend)
> >> return -EOPNOTSUPP;
> >>
> >> - count = pr->power.count - 1;
> >> - if (count <= 0)
> >> - return -ENODEV;
> >> -
> > It was intentionally designed this way, as there is little value in defining
> > only WFI in the _LPI tables. In the absence of a cpuidle driver/LPI entry,
> > arch_cpu_idle() is invoked, which is sufficient and avoids unnecessary
> > complexity, only to ultimately execute wfi() anyway.
> Yeah, it's correct. The code flow will be more simple and high-efficiency.
> This looks good to me.
>
>
> But cpuidle sysfs under per CPU is created when firmware just reports
> WFI state before
> my commit cac173bea57d ("ACPI: processor: idle: Rework the handling of
> acpi_processor_ffh_lpi_probe()").
> However, these platforms will no longer be created now and some
> statistics for state0 are also missing.
> This change in behavor is visiable to user space.I'm not sure if it is
> acceptable.
> What do you think, Rafael?
I think that it would be good to restore the previous behavior,
especially if it has been changed inadvertently.
^ permalink raw reply
* Re: [PATCH 1/3] arm64: dts: amlogic: t7: Add uart_c pinctrl pins group
From: Ronald Claveau @ 2026-04-15 13:44 UTC (permalink / raw)
To: Xianwei Zhao
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <956625df-0a80-4d0e-9bb7-8071d5797748@amlogic.com>
Hello Xianwei,
On 4/15/26 1:28 PM, Xianwei Zhao wrote:
>
>
> On 2026/4/15 19:16, Ronald Claveau wrote:
>> Add the pin multiplexing configuration for UART C (TX, RX, CTS, RTS)
>> in the T7 SoC pinctrl node, required to route the UART C signals
>> through the correct pads before enabling the controller.
>>
>> Signed-off-by: Ronald Claveau<linux-kernel-dev@aliel.fr>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/
>> boot/dts/amlogic/amlogic-t7.dtsi
>> index 7fe72c94ed623..531931cc1437c 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -553,6 +553,18 @@ mux {
>> bias-pull-up;
>> };
>> };
>> +
>> + uart_c_pins: uart_c {
> node name uart-c
I will change this, thank you for reminding me.
>> + mux {
>> + groups = "uart_c_tx",
>> + "uart_c_rx",
>> + "uart_c_cts",
>> + "uart_c_rts";
>> + bias-pull-up;
>> + output-high;
>> + function = "uart_c";
>> + };
>> + };
>> };
>>
>> gpio_intc: interrupt-controller@4080 {
--
Best regards,
Ronald
^ permalink raw reply
* Re: [EXTERNAL] Re: [PATCH 1/8] hv: Select CONFIG_SYSFB only for CONFIG_HYPERV_VMBUS
From: Thomas Zimmermann @ 2026-04-15 13:42 UTC (permalink / raw)
To: Saurabh Singh Sengar, javierm@redhat.com, arnd@arndb.de,
ardb@kernel.org, ilias.apalodimas@linaro.org,
chenhuacai@kernel.org, kernel@xen0n.name,
maarten.lankhorst@linux.intel.com, mripard@kernel.org,
airlied@gmail.com, simona@ffwll.ch, KY Srinivasan, Haiyang Zhang,
wei.liu@kernel.org, Dexuan Cui, Long Li, deller@gmx.de
Cc: linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev,
linux-efi@vger.kernel.org, linux-riscv@lists.infradead.org,
dri-devel@lists.freedesktop.org, linux-hyperv@vger.kernel.org,
linux-fbdev@vger.kernel.org, Michael Kelley, Saurabh Sengar,
stable@vger.kernel.org
In-Reply-To: <KUZP153MB1444885C302B353C02C2FA2FBE242@KUZP153MB1444.APCP153.PROD.OUTLOOK.COM>
Am 13.04.26 um 10:22 schrieb Saurabh Singh Sengar:
[...]
>>
>>> Reviewed-by: Saurabh Sengar <ssengar@linux.microsoft.com>
>> This fix is independent from the rest of the series. Do you want to merge it or
>> can I take it into DRM trees?
> Please feel free to take it via DRM tree.
Done now. Thanks a lot.
> CC : Wei Liu
>
> - Saurabh
>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com
GF: Jochen Jaser, Andrew McDonald, Werner Knoblich, (HRB 36809, AG Nürnberg)
^ permalink raw reply
* Re: [PATCH v12 2/2] arm: dts: aspeed: ventura: add Meta Ventura BMC
From: Andrew Lunn @ 2026-04-15 13:24 UTC (permalink / raw)
To: P.K. Lee
Cc: robh+dt, krzysztof.kozlowski+dt, conor+dt, joel, andrew,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Jason-Hsu, p.k.lee
In-Reply-To: <CAK8yEOAOhY25R5qt82LUkGifg_9HLia24-E=WxoEwCdbft1eMg@mail.gmail.com>
On Wed, Apr 15, 2026 at 06:05:32PM +0800, P.K. Lee wrote:
> > > > > > If there are no devices on the bus, why enable it?
> > > > >
> > > > > We intentionally enable it so user-space tools can access the switch
> > > > > registers. I have added a comment in v13 to clarify this.
> > > >
> > > > Why would user space want to access the switch registers for an
> > > > unmanaged switch? It sounds like you are using Marvells SDK in
> > > > userspace to manage the switch, rather than using DSA.
> > > >
> > >
> > > We do have a custom user-space daemon that configures the switch
> > > registers for our specific use case. Should I remove the &mdio0 node
> > > if it is only enabled and has no other configuration in the upstream
> > > device tree?
> >
> > Please just be truthful that you have a user space driver, so need the
> > bus enabled.
> >
> > I also guess you have some other kernel code that allows you to
> > actually use the bus from user space? The typical ethernet IOCTL
> > handler does not work for you, since you don't have an ethernet device
> > using this bus. Such code is unlikely to be accepted into mainline. We
> > don't like user space drivers when there is a perfectly good kernel
> > driver for this switch.
>
> Since the kernel driver for mv88e6xxx in kernel 6.6 used by this
> project does not support LED control, and this feature is only
> available starting from kernel 6.13, I had to initialize the LEDs of
> the 88E6393X from user space.
>
> In this case, should I remove the &mdio0 node?
I would keep it, and add a comment why it is there. And upgrade the
kernel to 6.18, or backport the LED code.
Andrew
^ permalink raw reply
* Re: [PATCH] KVM: arm64: pkvm: Adopt MARKER() to define host hypercall ranges
From: Marc Zyngier @ 2026-04-15 13:18 UTC (permalink / raw)
To: Fuad Tabba
Cc: kvmarm, linux-arm-kernel, Will Deacon, Vincent Donnefort,
Joey Gouly, Suzuki K Poulose, Oliver Upton, Zenghui Yu
In-Reply-To: <CA+EHjTxWAFKHqBUOCVkkqtzTKrMSU8HQDwoLMqD2HQPga7y_-w@mail.gmail.com>
On Wed, 15 Apr 2026 10:56:17 +0100,
Fuad Tabba <tabba@google.com> wrote:
>
> Hi Marc,
>
> On Tue, 14 Apr 2026 at 17:05, Marc Zyngier <maz@kernel.org> wrote:
> >
> > The EL2 code defines ranges of host hypercalls that are either
> > enabled at boot-time only, used by [nh]VHE KVM, or reserved to pKVM.
> >
> > The way these ranges are delineated is error prone, as the enum symbols
> > defining the limits are expressed in terms of actual function symbols.
> > This means that should a new function be added, special care must be
> > taken to also update the limit symbol.
> >
> > Improve this by reusing the mechanism introduced for the vcpu_sysreg
> > enum, which uses a MARKER() macro and some extra trickery to make
> > the limit symbol standalone. Crucially, the limit symbol has the
> > same value as the *following* symbol.
> >
> > The handle_host_hcall() function is then updated to make use of
> > the new limit definitions and get rid of the brittle default
> > upper limit. This allows for some more strict checks at build
> > time, and the removal of an comparison at run time.
>
> This is pretty neat. There is still the issue of a hole, i.e., adding
> an enum in the middle but forgetting to add a function, but that is
> caught in handle_host_hcall(). I can't think of an easy way to catch
> that though (xarray that initializes both?)
Yeah, there isn't a simple way to do that at compile-time,
unfortunately.
One thing that could be done is to have a blanket initialisation with
an illegal value, override all the entries you want, and then check at
KVM init time for the presence of the canary value. If you find it,
abort the KVM initialisation.
With that, you can drop the NULL test on the handling path.
> >
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
>
> Tested-by: Fuad Tabba <tabba@google.com>
> Reviewed-by: Fuad Tabba <tabba@google.com>
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* [PATCH v2 1/2] thermal/drivers/imx: Fix thermal zone leak on probe error path
From: Felix Gu @ 2026-04-15 13:10 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Oleksij Rempel
Cc: linux-pm, imx, linux-arm-kernel, linux-kernel, Felix Gu
In-Reply-To: <20260415-imx-v2-0-aeacff9e72b2@gmail.com>
If pm_runtime_resume_and_get() fails after the thermal zone has been
registered, the probe error path cleans up runtime PM but skips
thermal_zone_device_unregister(), leaking the thermal zone device.
Switch to use devm_thermal_of_zone_register() to fix the problem.
Fixes: 4cf2ddf16e17 ("thermal/drivers/imx: Implement runtime PM support")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
drivers/thermal/imx_thermal.c | 35 +++++++++++++++++++----------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 38c993d1bcb3..3729c3eac748 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -216,6 +216,20 @@ struct imx_thermal_data {
const char *temp_grade;
};
+static int imx_thermal_sync_zone_trip(struct thermal_trip *trip, void *arg)
+{
+ struct imx_thermal_data *data = arg;
+ int temp;
+
+ if (trip->type != THERMAL_TRIP_PASSIVE && trip->type != THERMAL_TRIP_CRITICAL)
+ return 0;
+
+ temp = trips[trip->type].temperature;
+ thermal_zone_set_trip_temp(data->tz, trip, temp);
+
+ return 0;
+}
+
static void imx_set_panic_temp(struct imx_thermal_data *data,
int panic_temp)
{
@@ -679,13 +693,8 @@ static int imx_thermal_probe(struct platform_device *pdev)
goto legacy_cleanup;
}
- data->tz = thermal_zone_device_register_with_trips("imx_thermal_zone",
- trips,
- ARRAY_SIZE(trips),
- data,
- &imx_tz_ops, NULL,
- IMX_PASSIVE_DELAY,
- IMX_POLLING_DELAY);
+ data->irq_enabled = true;
+ data->tz = devm_thermal_of_zone_register(dev, 0, data, &imx_tz_ops);
if (IS_ERR(data->tz)) {
ret = PTR_ERR(data->tz);
dev_err(dev, "failed to register thermal zone device %d\n",
@@ -693,6 +702,8 @@ static int imx_thermal_probe(struct platform_device *pdev)
goto clk_disable;
}
+ thermal_zone_for_each_trip(data->tz, imx_thermal_sync_zone_trip, data);
+
dev_info(dev, "%s CPU temperature grade - max:%dC"
" critical:%dC passive:%dC\n", data->temp_grade,
data->temp_max / 1000, trips[IMX_TRIP_CRITICAL].temperature / 1000,
@@ -724,25 +735,18 @@ static int imx_thermal_probe(struct platform_device *pdev)
if (ret < 0)
goto disable_runtime_pm;
- data->irq_enabled = true;
- ret = thermal_zone_device_enable(data->tz);
- if (ret)
- goto thermal_zone_unregister;
-
ret = devm_request_threaded_irq(dev, data->irq,
imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
0, "imx_thermal", data);
if (ret < 0) {
dev_err(dev, "failed to request alarm irq: %d\n", ret);
- goto thermal_zone_unregister;
+ goto disable_runtime_pm;
}
pm_runtime_put(data->dev);
return 0;
-thermal_zone_unregister:
- thermal_zone_device_unregister(data->tz);
disable_runtime_pm:
pm_runtime_put_noidle(data->dev);
pm_runtime_disable(data->dev);
@@ -761,7 +765,6 @@ static void imx_thermal_remove(struct platform_device *pdev)
pm_runtime_put_noidle(data->dev);
pm_runtime_disable(data->dev);
- thermal_zone_device_unregister(data->tz);
imx_thermal_unregister_legacy_cooling(data);
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 2/2] thermal/drivers/imxl:Fix runtime PM handling on early returns
From: Felix Gu @ 2026-04-15 13:10 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Oleksij Rempel
Cc: linux-pm, imx, linux-arm-kernel, linux-kernel, Felix Gu
In-Reply-To: <20260415-imx-v2-0-aeacff9e72b2@gmail.com>
Use PM_RUNTIME_ACQUIRE() in imx_get_temp() and imx_set_trip_temp() so
runtime PM references are released correctly even when the functions
return early on errors.
Fixes: 4cf2ddf16e17 ("thermal/drivers/imx: Implement runtime PM support")
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
drivers/thermal/imx_thermal.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 3729c3eac748..057dbab70266 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -274,8 +274,9 @@ static int imx_get_temp(struct thermal_zone_device *tz, int *temp)
u32 val;
int ret;
- ret = pm_runtime_resume_and_get(data->dev);
- if (ret < 0)
+ PM_RUNTIME_ACQUIRE(data->dev, pm);
+ ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
+ if (ret)
return ret;
regmap_read(map, soc_data->temp_data, &val);
@@ -316,8 +317,6 @@ static int imx_get_temp(struct thermal_zone_device *tz, int *temp)
enable_irq(data->irq);
}
- pm_runtime_put(data->dev);
-
return 0;
}
@@ -351,8 +350,9 @@ static int imx_set_trip_temp(struct thermal_zone_device *tz,
struct imx_thermal_data *data = thermal_zone_device_priv(tz);
int ret;
- ret = pm_runtime_resume_and_get(data->dev);
- if (ret < 0)
+ PM_RUNTIME_ACQUIRE(data->dev, pm);
+ ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
+ if (ret)
return ret;
/* do not allow passive to be set higher than critical */
@@ -362,8 +362,6 @@ static int imx_set_trip_temp(struct thermal_zone_device *tz,
imx_set_alarm_temp(data, temp);
trips[IMX_TRIP_PASSIVE].temperature = temp;
- pm_runtime_put(data->dev);
-
return 0;
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 0/2] thermal/drivers/imx: two fixes
From: Felix Gu @ 2026-04-15 13:10 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Oleksij Rempel
Cc: linux-pm, imx, linux-arm-kernel, linux-kernel, Felix Gu
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
Changes in v2:
- Switch to use devm_thermal_of_zone_register() to fix Frank and Daniel's comment.
- Collect Frank's Reviewed-by tag for patch 2.
- Link to v1: https://lore.kernel.org/r/20260412-imx-v1-0-cc3b45d63811@gmail.com
---
Felix Gu (2):
thermal/drivers/imx: Fix thermal zone leak on probe error path
thermal/drivers/imxl:Fix runtime PM handling on early returns
drivers/thermal/imx_thermal.c | 49 ++++++++++++++++++++++---------------------
1 file changed, 25 insertions(+), 24 deletions(-)
---
base-commit: 66672af7a095d89f082c5327f3b15bc2f93d558e
change-id: 20260411-imx-b022791ea1b9
Best regards,
--
Felix Gu <ustc.gu@gmail.com>
^ permalink raw reply
* Re: [PATCH v6 01/30] mm: Introduce kpkeys
From: David Hildenbrand (Arm) @ 2026-04-15 13:00 UTC (permalink / raw)
To: Kevin Brodsky, linux-hardening
Cc: linux-kernel, Andrew Morton, Andy Lutomirski, Catalin Marinas,
Dave Hansen, Ira Weiny, Jann Horn, Jeff Xu, Joey Gouly, Kees Cook,
Linus Walleij, Lorenzo Stoakes, Marc Zyngier, Mark Brown,
Matthew Wilcox, Maxwell Bland, Mike Rapoport (IBM),
Peter Zijlstra, Pierre Langlois, Quentin Perret, Rick Edgecombe,
Ryan Roberts, Thomas Gleixner, Vlastimil Babka, Will Deacon,
Yang Shi, Yeoreum Yun, linux-arm-kernel, linux-mm, x86
In-Reply-To: <20260227175518.3728055-2-kevin.brodsky@arm.com>
On 2/27/26 18:54, Kevin Brodsky wrote:
> kpkeys is a simple framework to enable the use of protection keys
> (pkeys) to harden the kernel itself. This patch introduces the basic
> API in <linux/kpkeys.h>: a couple of functions to set and restore
> the pkey register and macros to define guard objects.
>
> kpkeys introduces a new concept on top of pkeys: the kpkeys level.
> Each level is associated to a set of permissions for the pkeys
> managed by the kpkeys framework. kpkeys_set_level(lvl) sets those
> permissions according to lvl, and returns the original pkey
> register, to be later restored by kpkeys_restore_pkey_reg(). To
> start with, only KPKEYS_LVL_DEFAULT is available, which is meant
> to grant RW access to KPKEYS_PKEY_DEFAULT (i.e. all memory since
> this is the only available pkey for now).
>
> Because each architecture implementing pkeys uses a different
> representation for the pkey register, and may reserve certain pkeys
> for specific uses, support for kpkeys must be explicitly indicated
> by selecting ARCH_HAS_KPKEYS and defining the following functions in
> <asm/kpkeys.h>, in addition to the macros provided in
> <asm-generic/kpkeys.h>:
I don't quite understand the reason for using levels. Levels sounds like
it would all be in some ordered fashion, where higher levels have access
to lower levels.
Think of that as a key that can unlock all "lower" locks, not just a
single lock.
Then, the question is about the ordering once we introduce new
keys/locks. With two, it obviously doesn't matter :)
So naturally I wonder whether levels is really the right abstraction
here, and why we are not simply using "distinct" keys, like
KPKEY_DEFAULT
KPKEY_PGTABLE
KPKEY_SUPER_SECRET1
KPKEY_SUPER_SECRET2
Is it because you want KPKEY_PGTABLE also be able to write to KPKEY_DEFAULT?
But how would you handle KPKEY_SUPER_SECRET1 and KPKEY_SUPER_SECRET2 then?
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH net-next 5/6] net: stmmac: move PHY handling out of __stmmac_open()/release()
From: Russell King (Oracle) @ 2026-04-15 12:59 UTC (permalink / raw)
To: Alexander Stein
Cc: Andrew Lunn, Heiner Kallweit, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, linux-arm-kernel,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
In-Reply-To: <8409022.LvFx2qVVIh@steina-w>
On Wed, Apr 15, 2026 at 08:08:40AM +0200, Alexander Stein wrote:
> Hi,
>
> Am Dienstag, 23. September 2025, 13:26:19 CEST schrieb Russell King (Oracle):
> > Move the PHY attachment/detachment from the network driver out of
> > __stmmac_open() and __stmmac_release() into stmmac_open() and
> > stmmac_release() where these actions will only happen when the
> > interface is administratively brought up or down. It does not make
> > sense to detach and re-attach the PHY during a change of MTU.
>
> Sorry for coming up now. But I recently noticed this commit breaks changing
> the MTU on i.MX8MP. Once I simply change the MTU I run into some DMA error:
> $ ip link set dev end1 mtu 1400
> imx-dwmac 30bf0000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-0
> imx-dwmac 30bf0000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-1
> imx-dwmac 30bf0000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-2
> imx-dwmac 30bf0000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-3
> imx-dwmac 30bf0000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-4
> imx-dwmac 30bf0000.ethernet end1: Link is Down
> imx-dwmac 30bf0000.ethernet end1: Failed to reset the dma
> imx-dwmac 30bf0000.ethernet end1: stmmac_hw_setup: DMA engine initialization failed
This basically means that a clock is missing. Please provide more
information:
- what kernel version are you using?
- has EEE been negotiated?
- does the problem persist when EEE is disabled?
- which PHY is attached to stmmac?
- which PHY interface mode is being used to connect the PHY to stmmac?
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH net v5] net: stmmac: Prevent NULL deref when RX memory exhausted
From: Russell King (Oracle) @ 2026-04-15 12:56 UTC (permalink / raw)
To: Sam Edwards
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Maxime Chevallier,
Ovidiu Panait, Vladimir Oltean, Baruch Siach, Serge Semin,
Giuseppe Cavallaro, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, stable
In-Reply-To: <20260415023947.7627-1-CFSworks@gmail.com>
On Tue, Apr 14, 2026 at 07:39:47PM -0700, Sam Edwards wrote:
> The CPU receives frames from the MAC through conventional DMA: the CPU
> allocates buffers for the MAC, then the MAC fills them and returns
> ownership to the CPU. For each hardware RX queue, the CPU and MAC
> coordinate through a shared ring array of DMA descriptors: one
> descriptor per DMA buffer. Each descriptor includes the buffer's
> physical address and a status flag ("OWN") indicating which side owns
> the buffer: OWN=0 for CPU, OWN=1 for MAC. The CPU is only allowed to set
> the flag and the MAC is only allowed to clear it, and both must move
> through the ring in sequence: thus the ring is used for both
> "submissions" and "completions."
>
> In the stmmac driver, stmmac_rx() bookmarks its position in the ring
> with the `cur_rx` index. The main receive loop in that function checks
> for rx_descs[cur_rx].own=0, gives the corresponding buffer to the
> network stack (NULLing the pointer), and increments `cur_rx` modulo the
> ring size. After the loop exits, stmmac_rx_refill(), which bookmarks its
> position with `dirty_rx`, allocates fresh buffers and rearms the
> descriptors (setting OWN=1). If it fails any allocation, it simply stops
> early (leaving OWN=0) and will retry where it left off when next called.
>
> This means descriptors have a three-stage lifecycle (terms my own):
> - `empty` (OWN=1, buffer valid)
> - `full` (OWN=0, buffer valid and populated)
> - `dirty` (OWN=0, buffer NULL)
>
> But because stmmac_rx() only checks OWN, it confuses `full`/`dirty`. In
> the past (see 'Fixes:'), there was a bug where the loop could cycle
> `cur_rx` all the way back to the first descriptor it dirtied, resulting
> in a NULL dereference when mistaken for `full`. The aforementioned
> commit resolved that *specific* failure by capping the loop's iteration
> limit at `dma_rx_size - 1`, but this is only a partial fix: if the
> previous stmmac_rx_refill() didn't complete, then there are leftover
> `dirty` descriptors that the loop might encounter without needing to
> cycle fully around. The current code therefore panics (see 'Closes:')
> when stmmac_rx_refill() is memory-starved long enough for `cur_rx` to
> catch up to `dirty_rx`.
>
> Fix this by further tightening the clamp from `dma_rx_size - 1` to
> `dma_rx_size - stmmac_rx_dirty() - 1`, subtracting any remnant dirty
> entries and limiting the loop so that `cur_rx` cannot catch back up to
> `dirty_rx`. This carries no risk of arithmetic underflow: since the
> maximum possible return value of stmmac_rx_dirty() is `dma_rx_size - 1`,
> the worst the clamp can do is prevent the loop from running at all.
>
> Fixes: b6cb4541853c7 ("net: stmmac: avoid rx queue overrun")
> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221010
> Cc: stable@vger.kernel.org
> Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Locally, while debugging my issues, I used this to prevent cur_rx
catching up with dirty_rx:
status = stmmac_rx_status(priv, &priv->xstats, p);
/* check if managed by the DMA otherwise go ahead */
if (unlikely(status & dma_own))
break;
next_entry = STMMAC_NEXT_ENTRY(rx_q->cur_rx,
priv->dma_conf.dma_rx_size);
if (unlikely(next_entry == rx_q->dirty_rx))
break;
rx_q->cur_rx = next_entry;
If we care about the cost of reloading rx_q->dirty_rx on every
iteration, then I'd suggest that the cost we already incur reading and
writing rx_q->cur_rx is something that should be addressed, and
eliminating that would counter the cost of reading rx_q->dirty_rx. I
suspect, however, that the cost is minimal, as cur_tx and dirty_rx are
likely in the same cache line.
It looks like any fix to stmmac_rx() will also need a corresponding
fix for stmmac_rx_zc().
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH v6 00/30] pkeys-based page table hardening
From: David Hildenbrand (Arm) @ 2026-04-15 12:48 UTC (permalink / raw)
To: Kevin Brodsky, linux-hardening
Cc: linux-kernel, Andrew Morton, Andy Lutomirski, Catalin Marinas,
Dave Hansen, Ira Weiny, Jann Horn, Jeff Xu, Joey Gouly, Kees Cook,
Linus Walleij, Lorenzo Stoakes, Marc Zyngier, Mark Brown,
Matthew Wilcox, Maxwell Bland, Mike Rapoport (IBM),
Peter Zijlstra, Pierre Langlois, Quentin Perret, Rick Edgecombe,
Ryan Roberts, Thomas Gleixner, Vlastimil Babka, Will Deacon,
Yang Shi, Yeoreum Yun, linux-arm-kernel, linux-mm, x86
In-Reply-To: <20260227175518.3728055-1-kevin.brodsky@arm.com>
On 2/27/26 18:54, Kevin Brodsky wrote:
> NEW in v6: support for large block mappings through a dedicated page table
> allocator (patch 14-17)
Heh, I had to read till the very end to realize that this is an RFC, and
then saw your other mail.
I can recommend using b4 for patch management, where you can configure a
sticky prefix through
b4 prep --set-prefixes RFC
And using "b4 send" to automate all the rest.
>
> Threat model
> ============
>
> The proposed scheme aims at mitigating data-only attacks (e.g.
> use-after-free/cross-cache attacks). In other words, it is assumed that
> control flow is not corrupted, and that the attacker does not achieve
> arbitrary code execution. Nothing prevents the pkey register from being
> set to its most permissive state - the assumption is that the register
> is only modified on legitimate code paths.
>
> A few related notes:
>
> - Functions that set the pkey register are all implemented inline.
> Besides performance considerations, this is meant to avoid creating
> a function that can be used as a straightforward gadget to set the
> pkey register to an arbitrary value.
>
> - kpkeys_set_level() only accepts a compile-time constant as argument,
> as a variable could be manipulated by an attacker. This could be
> relaxed but it seems unlikely that a variable kpkeys level would be
> needed in practice.
>
I see a lot of value for that also as a debugging mechanism. I hear that
other people had private patches that would attempt to only map leaf
pages in the direct map in pte_offset_map_lock() and friends. I assume
there are some tricky bits to that (concurrent access to page tables).
What's the general take regarding the thread model you describe vs. MTE?
Regarding use-after-free, I'd assume KASAN would achieve something
similar. And with MTE "reasonably" fast. Or what is the biggest
difference you see, there?
I'd assume that one difference would be, that not even match-all
pointers could accidentally modify page tables.
In the future, would you think that both mechanisms (pkey PT table
protection + KASAN) would be active at the same time, or wouldn't there
really be a lot of value in having both enabled?
[...]
>
>
> Open questions
> ==============
>
> A few aspects in this RFC that are debatable and/or worth discussing:
>
> - Can the pkeys block allocator be abstracted into something more
> generic? This seems desirable considering other use-cases for changing
> attributes of regions of the linear map, but the handling of page
> tables while splitting may be difficult to integrate in a generic
> allocator.
>
> - There is currently no restriction on how kpkeys levels map to pkeys
> permissions. A typical approach is to allocate one pkey per level and
> make it writable at that level only. As the number of levels
> increases, we may however run out of pkeys, especially on arm64 (just
> 8 pkeys with POE). Depending on the use-cases, it may be acceptable to
> use the same pkey for the data associated to multiple levels.
>
>
> Any comment or feedback is highly appreciated, be it on the high-level
> approach or implementation choices!
How crucial would the dedicated page table allocator be for a first up
streamed version?
Assuming we introduce this as a debugging feature first, it would be
perfectly reasonable to just disallow large block mappings in the direct
map when enabled.
That means, we could merge basic support first and think about how to
deal with page tables in a different way with most of the pkey details
out of the picture.
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH net-next] net: stmmac: enable RPS and RBU interrupts
From: Russell King (Oracle) @ 2026-04-15 12:43 UTC (permalink / raw)
To: Sam Edwards
Cc: Jakub Kicinski, Andrew Lunn, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
linux-stm32, Linux Network Development Mailing List, Paolo Abeni
In-Reply-To: <CAH5Ym4jA8w9=UxMT4vKJpnXkuDHtkFtMcg4u2sy_0S+8wgy-9w@mail.gmail.com>
On Tue, Apr 14, 2026 at 07:12:34PM -0700, Sam Edwards wrote:
> On Tue, Apr 14, 2026 at 6:19 PM Russell King (Oracle)
> <linux@armlinux.org.uk> wrote:
> > Okay, just a quick note to say that nvidia's 5.10.216-tegra kernel
> > survives iperf3 -c -R to the imx6.
>
> Hi Russell,
>
> Aw, you beat me to it! I was about to report that 5.10.104-tegra is
> unaffected. And my iperf3 server is a multi-GbE amd64 machine.
>
> > Dumping the registers and comparing, and then forcing the RQS and TQS
> > values to 0x23 (+1 = 36, *256 = 9216 bytes) and 0x8f (+1 = 144,
> > *256 = 36864 ytes) respectively seems to solve the problem. Under
> > net-next, these both end up being 0xff (+1 = 256, *256 = 65536 bytes.)
> > Suspiciously, 36 * 4 = 144, and I also see that this kernel programs
> > all four of the MTL receive operation mode registers, but only the
> > first MTL transmit operation mode register. However, DMA channels 1-3
> > aren't initialised.
>
> Wow, great! I wonder if the problem is that the MTL FIFOs are smaller
> than that, so when the DMA suffers a momentary hiccup, the FIFOs are
> allowed to overflow, putting the hardware in a bad state.
>
> Though I suspect this is only half of the problem: do you still see
> RBUs? Everything you've shared so far suggests the DMA failures are
> _not_ because the rx ring is drying up.
Yes. Note that RBUs will happen not because of DMA failures, but if
the kernel fails to keep up with the packet rate. RBU means "we read
the next descriptor, and it wasn't owned by hardware".
> > Looking back at 5.10, I don't see any code that would account for these
> > values being programmed for TQS and RQS, it looks like the calculations
> > are basically the same as we have today.
>
> Note that Nvidia have their own "nvethernet" driver for their vendor
> kernel, which appears to pick the FIFO sizes from hardcoded tables in
> its eqos_configure_mtl_queue() [1] function.
That has:
const nveu32_t rx_fifo_sz[2U][OSI_EQOS_MAX_NUM_QUEUES] = {
{ FIFO_SZ(9U), FIFO_SZ(9U), FIFO_SZ(9U), FIFO_SZ(9U),
FIFO_SZ(1U), FIFO_SZ(1U), FIFO_SZ(1U), FIFO_SZ(1U) },
{ FIFO_SZ(36U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U),
FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(16U) },
};
const nveu32_t tx_fifo_sz[2U][OSI_EQOS_MAX_NUM_QUEUES] = {
{ FIFO_SZ(9U), FIFO_SZ(9U), FIFO_SZ(9U), FIFO_SZ(9U),
FIFO_SZ(1U), FIFO_SZ(1U), FIFO_SZ(1U), FIFO_SZ(1U) },
{ FIFO_SZ(8U), FIFO_SZ(8U), FIFO_SZ(8U), FIFO_SZ(8U),
FIFO_SZ(8U), FIFO_SZ(8U), FIFO_SZ(8U), FIFO_SZ(8U) },
};
where each of those values is the RQS/TQS value to use in KiB:
#define FIFO_SZ(x) ((((x) * 1024U) / 256U) - 1U)
This doesn't correspond with the values I'm seeing programmed into
the hardware under the 5.10.216-tegra kernel. I'm seeing TQS = 143
(36KiB), and RQS = 35 (9KiB). Yes, these values exist in the tables
above from a quick look, but they're not in the right place!
For example, tx_fifo_sz[] doesn't contain an entry for 36KiB.
rx_fifo_sz[0][0..3] looks plausible.
It's certainly not a case of misreading the register values, this is
what devmem2 said:
Value at address 0x02490d00: 0x008f000a
Value at address 0x02490d30: 0x02379eb0
where TQS is bits 24:16 of the register at offset 0xd00 - which is
0x8f, and RQS is bits 29:20 of the register at 0xd30, which is
0x23.
Now, as for FIFO sizes, if we sum up all the entries, then we
get:
SUM(rx_fifo_size[0][]) = 60KiB
SUM(rx_fifo_size[1][]) = 64KiB
SUM(tx_fifo_size[0][]) = 60KiB
SUM(tx_fifo_size[1][]) = 64KiB
From what I gather in core_local.h, l_mac_ver contains one of three
values - 0 = Legacy EQOS, 1 = Orin EQOS, 2 = Orin MGBE, and which
set of values is selected by bit 0 of that. Decoding this further,
Legacy EQOS is IP version v5.0, Orin EQOS is v5.3, and Orin MGBE
is v3.1 and v4.0.
So, I wonder whether there's something in "Legacy EQOS" that consumes
4KiB of FIFO that isn't documented in iMX8M (IP v5.1).
Is anyone aware of public SoC documentation that covers the v5.0 IP
version?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [Question mpam mpam/snapshot+extras/v6.18-rc1] Question with Configuring iommu_group in 'task'
From: Ben Horgan @ 2026-04-15 12:42 UTC (permalink / raw)
To: Zeng Heng, James Morse
Cc: Qinxin Xia, amitsinght, baisheng.gao, baolin.wang, carl,
dave.martin, david, dfustini, fenghuay, gshan, jonathan.cameron,
kobak, lcherian, linux-arm-kernel, linux-kernel, peternewman,
punit.agrawal, quic_jiles, reinette.chatre, rohit.mathew, scott,
sdonthineni, xhao, Linuxarm
In-Reply-To: <d5918112-0c9f-ecf3-226c-8c3cdd5cd508@huawei.com>
Hi Zeng,
On 4/15/26 02:27, Zeng Heng wrote:
> Hi Ben,
>
> On 2026/4/13 23:02, Ben Horgan wrote:
>> Hi Qinxin,
>>
>> On 4/3/26 03:44, Qinxin Xia wrote:
>>>
>>>
>>> On 2026/3/27 18:47:49, Ben Horgan <ben.horgan@arm.com> wrote:
>>>> Hi Qinxin,
>>>>
>>>> On 3/27/26 10:21, Qinxin Xia wrote:
>>>>>
>>>>> Hello everyone!
>>>>>
>>>>> In earlier versions, mpam supports the configuration of iommu_groups.
>>>>>
>>>>> 823 static ssize_t rdtgroup_tasks_write(struct kernfs_open_file *of,
>>>>> 824 char *buf, size_t nbytes,
>>>>> loff_t off)
>>>>> 825 {
>>>>> 826 struct rdtgroup *rdtgrp;
>>>>> 827 int iommu_group_id;
>>>>> 828 bool is_iommu;
>>>>> 829 char *pid_str;
>>>>> 830 int ret = 0;
>>>>> 831 pid_t pid;
>>>>> 832
>>>>> 833 rdtgrp = rdtgroup_kn_lock_live(of->kn);
>>>>> 834 if (!rdtgrp) {
>>>>> 835 rdtgroup_kn_unlock(of->kn);
>>>>> 836 return -ENOENT;
>>>>> 837 }
>>>>> 838 rdt_last_cmd_clear();
>>>>> 839
>>>>> 840 if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKED ||
>>>>> 841 rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP) {
>>>>> 842 ret = -EINVAL;
>>>>> 843 rdt_last_cmd_puts("Pseudo-locking in progress\n");
>>>>> 844 goto unlock;
>>>>> 845 }
>>>>> 846
>>>>> 847 while (buf && buf[0] != '\0' && buf[0] != '\n') {
>>>>> 848 pid_str = strim(strsep(&buf, ","));
>>>>> 849
>>>>> 850 is_iommu = string_is_iommu_group(pid_str, &iommu_group_id);
>>>>>
>>>>> What puzzles me is why we would put it under 'task'—this seems a little
>>>>> strange to users.It seems they are not related.Why don't we add a new
>>>>> interface like 'iommu'?
>>>>
>>>> I think it is likely that this interface would change if upstream support is added.
>>>>
>>>
>>> I have done some work in this direction before, and I will release an
>>> RFC later for further discussion.:-)
>>
>> Looking forward to seeing it.
>>
>> Ben
>>
>
> Following the current SMMU approach, I've submitted several bugfix
> patches for the MPAM driver, but haven't received any review feedback
> yet.
>
> To avoid these being overlooked, I'd like to kindly remind to take a
> look:
> v2: https://lore.kernel.org/all/20260414032610.1523958-1-zengheng4@huawei.com/
> v1: https://lore.kernel.org/all/20251107063300.1580046-1-zengheng4@huawei.com/
>
> Additionally, I'd like to check on the status of this branch — is it
> still actively maintained? It would be helpful to understand the future
> plans for MPAM development.
The MPAM snapshot and extras branches are no longer maintained. Work on these has stopped so that we can focus on
upstream. Apologies for not making this clear earlier.
Thanks,
Ben
>
>
> Thanks for your time,
> Zeng Heng
^ permalink raw reply
* Re: [PATCH bpf-next v2 1/2] bpf, arm64: Remove redundant bpf_flush_icache() after pack allocator finalize
From: Breno Leitao @ 2026-04-15 12:38 UTC (permalink / raw)
To: Puranjay Mohan
Cc: bpf, Alexei Starovoitov, Daniel Borkmann, Andrii Nakryiko,
Martin KaFai Lau, Eduard Zingerman, Kumar Kartikeya Dwivedi,
Song Liu, Yonghong Song, Jiri Olsa, Xu Kuohai, Catalin Marinas,
Will Deacon, Luke Nelson, Xi Wang, Björn Töpel,
Pu Lehui, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, linux-arm-kernel, linux-riscv, linux-kernel
In-Reply-To: <20260413191111.3426023-2-puranjay@kernel.org>
On Mon, Apr 13, 2026 at 12:11:08PM -0700, Puranjay Mohan wrote:
> bpf_flush_icache() calls flush_icache_range() to clean the data cache
> and invalidate the instruction cache for the JITed code region. However,
> since commit 1dad391daef1 ("bpf, arm64: use bpf_prog_pack for memory
> management"), this flush is redundant.
>
> bpf_jit_binary_pack_finalize() copies the JITed instructions to the ROX
> region via bpf_arch_text_copy() -> aarch64_insn_copy() -> __text_poke(),
> and __text_poke() already calls flush_icache_range() on the written
> range. The subsequent bpf_flush_icache() repeats the same cache
> maintenance on an overlapping range, including an unnecessary second
> synchronous IPI to all CPUs via kick_all_cpus_sync().
>
> Remove the redundant bpf_flush_icache() call and its now-unused
> definition.
>
> Fixes: 1dad391daef1 ("bpf, arm64: use bpf_prog_pack for memory management")
> Acked-by: Song Liu <song@kernel.org>
> Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
Acked-by: Breno Leitao <leitao@debian.org>
^ permalink raw reply
* Re: [PATCH v2] Bluetooth: Add Broadcom channel priority commands
From: Sasha Finkelstein @ 2026-04-15 12:33 UTC (permalink / raw)
To: Luiz Augusto von Dentz
Cc: Sven Peter, Janne Grunau, Neal Gompa, Marcel Holtmann,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, linux-kernel, asahi, linux-arm-kernel,
linux-bluetooth, netdev
In-Reply-To: <CABBYNZJAEqwfTuVqbFAnx97HBSjcwn3Hb+y+r4r2C=MMPxFoDg@mail.gmail.com>
On Tue, 14 Apr 2026 at 16:00, Luiz Augusto von Dentz
<luiz.dentz@gmail.com> wrote:
> > + if (sock)
> > + set_bit(SOCK_CUSTOM_SOCKOPT, &sock->flags);
>
> This is more complicated than it needs to be. I'd just add a new
> callback, `hdev->set_priority(handle, skb->priority)`, so the driver
> is called whenever it needs to elevate a connection's priority, that
> said there could be cases where a connection needs its priority set
> momentarily to transmit A2DP, followed by OBEX packets that are best
> effort. Therefore, `hci_conn` will probably need to track the priority
> so it can detect when it needs changing on a per skb basis.
I have tested per-skb priorities, and unfortunately, this does not work.
If something tries to send a low-priority packet (for example - a volume
adjustment), a priority drop causes the same kind of dropout that is
caused by scans. It appears that the only way to make this hardware work
is to set the entire hci connection as high priority for as long as it
is being used to transmit audio.
^ permalink raw reply
* Re: [PATCH v4 7/9] coresight: etm3x: introduce struct etm_caps
From: Jie Gan @ 2026-04-15 12:17 UTC (permalink / raw)
To: Yeoreum Yun, coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan
In-Reply-To: <20260413142003.3549310-8-yeoreum.yun@arm.com>
On 4/13/2026 10:20 PM, Yeoreum Yun wrote:
> Introduce struct etm_caps to describe ETMv3 capabilities
> and move capabilities information into it.
>
> Since drvdata->etmccr and drvdata->etmccer are used to check
> whether it supports fifofull logic and timestamping,
> remove etmccr and etmccer field from drvdata and add relevant fields
> in etm_caps structure.
>
> Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm.h | 42 ++++++++++++-------
> .../coresight/coresight-etm3x-core.c | 39 ++++++++++-------
> .../coresight/coresight-etm3x-sysfs.c | 29 ++++++++-----
> 3 files changed, 67 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> index 40f20daded4f..8d1a1079b008 100644
> --- a/drivers/hwtracing/coresight/coresight-etm.h
> +++ b/drivers/hwtracing/coresight/coresight-etm.h
> @@ -140,6 +140,30 @@
> ETM_ADD_COMP_0 | \
> ETM_EVENT_NOT_A)
>
> +/**
> + * struct etmv_caps - specifics ETM capabilities
s/etmv_caps/etm_caps
Thanks,
Jie
> + * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> + * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> + * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> + * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> + * @fifofull: FIFOFULL logic is present.
> + * @timestamp: Timestamping is implemented.
> + * @retstack: Return stack is implemented.
> + */
> +struct etm_caps {
> + int port_size;
> + u8 nr_addr_cmp;
> + u8 nr_cntr;
> + u8 nr_ext_inp;
> + u8 nr_ext_out;
> + u8 nr_ctxid_cmp;
> + bool fifofull : 1;
> + bool timestamp : 1;
> + bool retstack : 1;
> +};
> +
> /**
> * struct etm_config - configuration information related to an ETM
> * @mode: controls various modes supported by this ETM/PTM.
> @@ -212,19 +236,12 @@ struct etm_config {
> * @csdev: component vitals needed by the framework.
> * @spinlock: only one at a time pls.
> * @cpu: the cpu this component is affined to.
> - * @port_size: port size as reported by ETMCR bit 4-6 and 21.
> * @arch: ETM/PTM version number.
> + * @caps: ETM capabilities.
> * @use_cpu14: true if management registers need to be accessed via CP14.
> * @sticky_enable: true if ETM base configuration has been done.
> * @boot_enable:true if we should start tracing at boot time.
> * @os_unlock: true if access to management registers is allowed.
> - * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
> - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15.
> - * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
> - * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
> - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
> - * @etmccr: value of register ETMCCR.
> - * @etmccer: value of register ETMCCER.
> * @traceid: value of the current ID for this component.
> * @config: structure holding configuration parameters.
> */
> @@ -234,19 +251,12 @@ struct etm_drvdata {
> struct coresight_device *csdev;
> raw_spinlock_t spinlock;
> int cpu;
> - int port_size;
> u8 arch;
> + struct etm_caps caps;
> bool use_cp14;
> bool sticky_enable;
> bool boot_enable;
> bool os_unlock;
> - u8 nr_addr_cmp;
> - u8 nr_cntr;
> - u8 nr_ext_inp;
> - u8 nr_ext_out;
> - u8 nr_ctxid_cmp;
> - u32 etmccr;
> - u32 etmccer;
> u32 traceid;
> struct etm_config config;
> };
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index 4a702b515733..e42ca346da91 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -308,6 +308,7 @@ void etm_config_trace_mode(struct etm_config *config)
> static int etm_parse_event_config(struct etm_drvdata *drvdata,
> struct perf_event *event)
> {
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
> struct perf_event_attr *attr = &event->attr;
> u8 ts_level;
> @@ -356,8 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata,
> * has ret stack) on the same SoC. So only enable when it can be honored
> * - trace will still continue normally otherwise.
> */
> - if (ATTR_CFG_GET_FLD(attr, retstack) &&
> - (drvdata->etmccer & ETMCCER_RETSTACK))
> + if (ATTR_CFG_GET_FLD(attr, retstack) && (caps->retstack))
> config->ctrl |= ETMCR_RETURN_STACK;
>
> return 0;
> @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> {
> int i, rc;
> u32 etmcr;
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
>
> @@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etmcr = etm_readl(drvdata, ETMCR);
> /* Clear setting from a previous run if need be */
> etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
> - etmcr |= drvdata->port_size;
> + etmcr |= caps->port_size;
> etmcr |= ETMCR_ETM_EN;
> etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
> etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
> @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_writel(drvdata, config->enable_event, ETMTEEVR);
> etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
> etm_writel(drvdata, config->fifofull_level, ETMFFLR);
> - for (i = 0; i < drvdata->nr_addr_cmp; i++) {
> + for (i = 0; i < caps->nr_addr_cmp; i++) {
> etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
> etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
> }
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
> etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
> etm_writel(drvdata, config->cntr_rld_event[i],
> @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
> etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
> etm_writel(drvdata, config->seq_curr_state, ETMSQR);
> - for (i = 0; i < drvdata->nr_ext_out; i++)
> + for (i = 0; i < caps->nr_ext_out; i++)
> etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
> - for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
> + for (i = 0; i < caps->nr_ctxid_cmp; i++)
> etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
> etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
> etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
> @@ -563,6 +564,7 @@ static int etm_enable(struct coresight_device *csdev, struct perf_event *event,
> static void etm_disable_hw(struct etm_drvdata *drvdata)
> {
> int i;
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
>
> @@ -572,7 +574,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata)
> /* Read back sequencer and counters for post trace analysis */
> config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
>
> - for (i = 0; i < drvdata->nr_cntr; i++)
> + for (i = 0; i < caps->nr_cntr; i++)
> config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
>
> etm_set_pwrdwn(drvdata);
> @@ -754,7 +756,9 @@ static void etm_init_arch_data(void *info)
> {
> u32 etmidr;
> u32 etmccr;
> + u32 etmccer;
> struct etm_drvdata *drvdata = info;
> + struct etm_caps *caps = &drvdata->caps;
>
> /* Make sure all registers are accessible */
> etm_os_unlock(drvdata);
> @@ -779,16 +783,19 @@ static void etm_init_arch_data(void *info)
> /* Find all capabilities */
> etmidr = etm_readl(drvdata, ETMIDR);
> drvdata->arch = BMVAL(etmidr, 4, 11);
> - drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> + caps->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
> +
> + etmccer = etm_readl(drvdata, ETMCCER);
> + caps->timestamp = !!(etmccer & ETMCCER_TIMESTAMP);
> + caps->retstack = !!(etmccer & ETMCCER_RETSTACK);
>
> - drvdata->etmccer = etm_readl(drvdata, ETMCCER);
> etmccr = etm_readl(drvdata, ETMCCR);
> - drvdata->etmccr = etmccr;
> - drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> - drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
> - drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
> - drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
> - drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
> + caps->fifofull = !!(etmccr & ETMCCR_FIFOFULL);
> + caps->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
> + caps->nr_cntr = BMVAL(etmccr, 13, 15);
> + caps->nr_ext_inp = BMVAL(etmccr, 17, 19);
> + caps->nr_ext_out = BMVAL(etmccr, 20, 22);
> + caps->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
>
> coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
> etm_set_pwrdwn(drvdata);
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> index 42b12c33516b..f7330d830e21 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> @@ -15,8 +15,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev,
> {
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_addr_cmp;
> + val = caps->nr_addr_cmp;
> return sprintf(buf, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_addr_cmp);
> @@ -25,8 +26,9 @@ static ssize_t nr_cntr_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> { unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
>
> - val = drvdata->nr_cntr;
> + val = caps->nr_cntr;
> return sprintf(buf, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_cntr);
> @@ -37,7 +39,7 @@ static ssize_t nr_ctxid_cmp_show(struct device *dev,
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>
> - val = drvdata->nr_ctxid_cmp;
> + val = drvdata->caps.nr_ctxid_cmp;
> return sprintf(buf, "%#lx\n", val);
> }
> static DEVICE_ATTR_RO(nr_ctxid_cmp);
> @@ -80,7 +82,7 @@ static ssize_t reset_store(struct device *dev,
> memset(config, 0, sizeof(struct etm_config));
> config->mode = ETM_MODE_EXCLUDE;
> config->trigger_event = ETM_DEFAULT_EVENT_VAL;
> - for (i = 0; i < drvdata->nr_addr_cmp; i++) {
> + for (i = 0; i < drvdata->caps.nr_addr_cmp; i++) {
> config->addr_type[i] = ETM_ADDR_TYPE_NONE;
> }
>
> @@ -111,6 +113,7 @@ static ssize_t mode_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> @@ -131,7 +134,7 @@ static ssize_t mode_store(struct device *dev,
> config->ctrl &= ~ETMCR_CYC_ACC;
>
> if (config->mode & ETM_MODE_STALL) {
> - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
> + if (!caps->fifofull) {
> dev_warn(dev, "stall mode not supported\n");
> ret = -EINVAL;
> goto err_unlock;
> @@ -141,7 +144,7 @@ static ssize_t mode_store(struct device *dev,
> config->ctrl &= ~ETMCR_STALL_MODE;
>
> if (config->mode & ETM_MODE_TIMESTAMP) {
> - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
> + if (!caps->timestamp) {
> dev_warn(dev, "timestamp not supported\n");
> ret = -EINVAL;
> goto err_unlock;
> @@ -286,13 +289,14 @@ static ssize_t addr_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_addr_cmp)
> + if (val >= caps->nr_addr_cmp)
> return -EINVAL;
>
> /*
> @@ -589,13 +593,14 @@ static ssize_t cntr_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_cntr)
> + if (val >= caps->nr_cntr)
> return -EINVAL;
> /*
> * Use spinlock to ensure index doesn't change while it gets
> @@ -720,18 +725,19 @@ static ssize_t cntr_val_show(struct device *dev,
> int i, ret = 0;
> u32 val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> if (!coresight_get_mode(drvdata->csdev)) {
> raw_spin_lock(&drvdata->spinlock);
> - for (i = 0; i < drvdata->nr_cntr; i++)
> + for (i = 0; i < caps->nr_cntr; i++)
> ret += sprintf(buf, "counter %d: %x\n",
> i, config->cntr_val[i]);
> raw_spin_unlock(&drvdata->spinlock);
> return ret;
> }
>
> - for (i = 0; i < drvdata->nr_cntr; i++) {
> + for (i = 0; i < caps->nr_cntr; i++) {
> val = etm_readl(drvdata, ETMCNTVRn(i));
> ret += sprintf(buf, "counter %d: %x\n", i, val);
> }
> @@ -999,13 +1005,14 @@ static ssize_t ctxid_idx_store(struct device *dev,
> int ret;
> unsigned long val;
> struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + const struct etm_caps *caps = &drvdata->caps;
> struct etm_config *config = &drvdata->config;
>
> ret = kstrtoul(buf, 16, &val);
> if (ret)
> return ret;
>
> - if (val >= drvdata->nr_ctxid_cmp)
> + if (val >= caps->nr_ctxid_cmp)
> return -EINVAL;
>
> /*
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