* Re: [PATCH] gpio: rockchip: Fix GPIO after convert to dynamic base allocation
From: Bartosz Golaszewski @ 2026-04-20 8:46 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Heiko Stuebner, Shawn Lin,
Jonas Karlman
Cc: Bartosz Golaszewski, linux-gpio, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260416154928.2103388-1-jonas@kwiboo.se>
On Thu, 16 Apr 2026 15:49:28 +0000, Jonas Karlman wrote:
> The commit c8079f83e0bf ("gpio: rockchip: convert to dynamic GPIO base
> allocation") broke GPIO on devices using device trees which don't set
> the gpio-ranges property, something only Rockchip RK35xx SoC DTs do.
>
> On a Rockchip RK3399 device something like following is now observed:
>
> [ 0.082771] rockchip-gpio ff720000.gpio: probed /pinctrl/gpio@ff720000
> [ 0.083531] rockchip-gpio ff730000.gpio: probed /pinctrl/gpio@ff730000
> [ 0.084110] rockchip-gpio ff780000.gpio: probed /pinctrl/gpio@ff780000
> [ 0.084746] rockchip-gpio ff788000.gpio: probed /pinctrl/gpio@ff788000
> [ 0.085389] rockchip-gpio ff790000.gpio: probed /pinctrl/gpio@ff790000
> --
> [ 0.212208] rockchip-pinctrl pinctrl: pin 637 is not registered so it cannot be requested
> [ 0.212271] rockchip-pinctrl pinctrl: error -EINVAL: pin-637 (gpio3:637)
> [ 0.212344] leds-gpio leds: error -EINVAL: Failed to get GPIO '/leds/led-0'
> [ 0.212389] leds-gpio leds: probe with driver leds-gpio failed with error -22
> --
> [ 0.607545] rockchip-pinctrl pinctrl: pin 519 is not registered so it cannot be requested
> [ 0.608775] rockchip-pinctrl pinctrl: error -EINVAL: pin-519 (gpio0:519)
> [ 0.610003] dwmmc_rockchip fe320000.mmc: probe with driver dwmmc_rockchip failed with error -22
> --
> [ 0.805882] rockchip-pinctrl pinctrl: pin 547 is not registered so it cannot be requested
> [ 0.806672] rockchip-pinctrl pinctrl: error -EINVAL: pin-547 (gpio1:547)
> [ 0.807301] reg-fixed-voltage regulator-vbus-typec: error -EINVAL: can't get GPIO
> [ 0.807307] rockchip-pinctrl pinctrl: pin 602 is not registered so it cannot be requested
> [ 0.807970] reg-fixed-voltage regulator-vbus-typec: probe with driver reg-fixed-voltage failed with error -22
> [ 0.808692] rockchip-pinctrl pinctrl: error -EINVAL: pin-602 (gpio2:602)
> [ 0.810279] reg-fixed-voltage regulator-vcc3v3-pcie: error -EINVAL: can't get GPIO
> [ 0.810284] rockchip-pinctrl pinctrl: pin 665 is not registered so it cannot be requested
> [ 0.810299] rockchip-pinctrl pinctrl: error -EINVAL: pin-665 (gpio4:665)
> [ 0.810960] reg-fixed-voltage regulator-vcc3v3-pcie: probe with driver reg-fixed-voltage failed with error -22
> [ 0.811679] reg-fixed-voltage regulator-vcc5v0-host: error -EINVAL: can't get GPIO
> [ 0.813943] reg-fixed-voltage regulator-vcc5v0-host: probe with driver reg-fixed-voltage failed with error -22
> --
> [ 0.867788] rockchip-pinctrl pinctrl: pin 522 is not registered so it cannot be requested
> [ 0.868537] rockchip-pinctrl pinctrl: error -EINVAL: pin-522 (gpio0:522)
> [ 0.869166] pwrseq_simple sdio-pwrseq: error -EINVAL: reset GPIOs not ready
> [ 0.869798] pwrseq_simple sdio-pwrseq: probe with driver pwrseq_simple failed with error -22
> --
> [ 0.940365] rockchip-pinctrl pinctrl: pin 623 is not registered so it cannot be requested
> [ 0.941084] rockchip-pinctrl pinctrl: error -EINVAL: pin-623 (gpio3:623)
> [ 0.941823] rk_gmac-dwmac fe300000.ethernet: error -EINVAL: Cannot register the MDIO bus
> [ 0.942542] rk_gmac-dwmac fe300000.ethernet: error -EINVAL: MDIO bus (id: 0) registration failed
> [ 0.943772] rk_gmac-dwmac fe300000.ethernet: probe with driver rk_gmac-dwmac failed with error -22
>
> [...]
Applied, thanks!
[1/1] gpio: rockchip: Fix GPIO after convert to dynamic base allocation
https://git.kernel.org/brgl/c/5cd9c6d332f46d1de8b68117fe2a3f1b08ee80ff
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: amlogic: t7: khadas-vim4: Enable Bluetooth
From: Neil Armstrong @ 2026-04-20 8:47 UTC (permalink / raw)
To: Ronald Claveau, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20260416-add-bluetooth-t7-vim4-v2-3-9a57098fd055@aliel.fr>
On 4/16/26 10:54, Ronald Claveau wrote:
> Enable UART C on the Khadas VIM4 board and attach the BCM43438
> compatible Bluetooth controller to it. The node configures the RTS/CTS
> hardware flow control, the associated pinmux, the power supplies (vddao_3v3
> and vddao_1v8), the 32 kHz LPO clock shared with the wifi32k fixed
> clock, and the GPIO lines used for host wakeup, device wakeup and
> shutdown.
>
> Remove clocks and clock-names for UART A, as they are defined in DTSI.
This should be a separate patch.
Neil
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
> ---
> .../dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
> index 69d6118ba57e7..8ea7ae609fbd5 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
> @@ -250,6 +250,23 @@ &sd_emmc_c {
>
> &uart_a {
> status = "okay";
> - clocks = <&xtal>, <&xtal>, <&xtal>;
> - clock-names = "xtal", "pclk", "baud";
> +};
> +
> +&uart_c {
> + status = "okay";
> + pinctrl-0 = <&uart_c_pins>;
> + pinctrl-names = "default";
> + uart-has-rtscts;
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
> + host-wakeup-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
> + device-wakeup-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
> + max-speed = <3000000>;
> + clocks = <&wifi32k>;
> + clock-names = "lpo";
> + vbat-supply = <&vddao_3v3>;
> + vddio-supply = <&vddao_1v8>;
> + };
> };
>
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: amlogic: t7: Add UART controllers nodes
From: Neil Armstrong @ 2026-04-20 8:47 UTC (permalink / raw)
To: Ronald Claveau, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20260416-add-bluetooth-t7-vim4-v2-2-9a57098fd055@aliel.fr>
On 4/16/26 10:54, Ronald Claveau wrote:
> Add device tree nodes for UART B through F (serial@7a000 to
> serial@82000), completing the UART controller description for the T7
> SoC. Each node includes the peripheral clock.
>
> While at it, move the uart_a node to its correct position in the
> bus address order (0x78000) to comply with the DT requirement that
> nodes be sorted by their reg address. Complete the
> uart_a node with its peripheral clock (CLKID_SYS_UART_A) and the
> associated clock-names, matching the vendor default clock assignment,
> consistent with the other UART nodes.
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 61 +++++++++++++++++++++++++----
> 1 file changed, 54 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 4a55d9641bc9b..81c26b1e3e7a4 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -577,13 +577,6 @@ gpio_intc: interrupt-controller@4080 {
> <10 11 12 13 14 15 16 17 18 19 20 21>;
> };
>
> - uart_a: serial@78000 {
> - compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> - reg = <0x0 0x78000 0x0 0x18>;
> - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> - status = "disabled";
> - };
> -
> gp0: clock-controller@8080 {
> compatible = "amlogic,t7-gp0-pll";
> reg = <0x0 0x8080 0x0 0x20>;
> @@ -713,6 +706,60 @@ pwm_ao_cd: pwm@60000 {
> status = "disabled";
> };
>
> + uart_a: serial@78000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x78000 0x0 0x18>;
> + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_A>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_b: serial@7a000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x7a000 0x0 0x18>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_c: serial@7c000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x7c000 0x0 0x18>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_C>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_d: serial@7e000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x7e000 0x0 0x18>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_D>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_e: serial@80000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x80000 0x0 0x18>;
> + interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_E>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> + uart_f: serial@82000 {
> + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
> + reg = <0x0 0x82000 0x0 0x18>;
> + interrupts = <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_F>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + status = "disabled";
> + };
> +
> sd_emmc_a: mmc@88000 {
> compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
> reg = <0x0 0x88000 0x0 0x800>;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: dts: amlogic: t7: Add uart_c pinctrl pins group
From: Neil Armstrong @ 2026-04-20 8:47 UTC (permalink / raw)
To: Ronald Claveau, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20260416-add-bluetooth-t7-vim4-v2-1-9a57098fd055@aliel.fr>
On 4/16/26 10:54, Ronald Claveau wrote:
> Add the pin multiplexing configuration for UART C (TX, RX, CTS, RTS)
> in the T7 SoC pinctrl node, required to route the UART C signals
> through the correct pads before enabling the controller.
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 7fe72c94ed623..4a55d9641bc9b 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -553,6 +553,18 @@ mux {
> bias-pull-up;
> };
> };
> +
> + uart_c_pins: uart-c {
> + mux {
> + groups = "uart_c_tx",
> + "uart_c_rx",
> + "uart_c_cts",
> + "uart_c_rts";
> + bias-pull-up;
> + output-high;
> + function = "uart_c";
> + };
> + };
> };
>
> gpio_intc: interrupt-controller@4080 {
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH RFC v3 2/4] mm/pgtable: Make pfn_pte() filter out huge page attributes
From: Will Deacon @ 2026-04-20 8:48 UTC (permalink / raw)
To: Yin Tirui
Cc: linux-kernel, linux-mm, x86, linux-arm-kernel, willy, david,
catalin.marinas, tglx, mingo, bp, dave.hansen, hpa, luto, peterz,
akpm, lorenzo.stoakes, ziy, baolin.wang, Liam.Howlett, npache,
ryan.roberts, dev.jain, baohua, lance.yang, vbabka, rppt, surenb,
mhocko, anshuman.khandual, rmclure, kevin.brodsky, apopple, ajd,
pasha.tatashin, bhe, thuth, coxu, dan.j.williams, yu-cheng.yu,
yangyicong, baolu.lu, jgross, conor.dooley, Jonathan.Cameron,
riel, wangkefeng.wang, chenjun102
In-Reply-To: <20260228070906.1418911-3-yintirui@huawei.com>
On Sat, Feb 28, 2026 at 03:09:04PM +0800, Yin Tirui wrote:
> A fundamental principle of page table type safety is that `pte_t` represents
> the lowest level page table entry and should never carry huge page attributes.
>
> Currently, passing a pgprot with huge page bits (e.g., extracted via
> pmd_pgprot()) into pfn_pte() creates a malformed PTE that retains the huge
> attribute, leading to the necessity of the ugly `pte_clrhuge()` anti-pattern.
>
> Enforce type safety by making `pfn_pte()` inherently filter out huge page
> attributes:
> - On x86: Strip the `_PAGE_PSE` bit.
> - On ARM64: Mask out the block descriptor bits in `PTE_TYPE_MASK` and
> enforce the `PTE_TYPE_PAGE` format.
> - On RISC-V: No changes required, as RISC-V leaf PMDs and PTEs share the
> exact same hardware format and do not use a distinct huge bit.
>
> Signed-off-by: Yin Tirui <yintirui@huawei.com>
> ---
> arch/arm64/include/asm/pgtable.h | 4 +++-
> arch/x86/include/asm/pgtable.h | 4 ++++
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b3e58735c49b..f2a7a40106d2 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -141,7 +141,9 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
>
> #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
> #define pfn_pte(pfn,prot) \
> - __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
> + __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | \
> + ((pgprot_val(prot) & ~(PTE_TYPE_MASK & ~PTE_VALID)) | \
> + (PTE_TYPE_PAGE & ~PTE_VALID)))
Why are you touching arch/arm64? We don't implement pte_clrhuge() afaict.
What does this actually fix?
Will
^ permalink raw reply
* Re: [PATCH v2 2/4] soc: amlogic: clk-measure: Add A1 and T7 support
From: Neil Armstrong @ 2026-04-20 8:49 UTC (permalink / raw)
To: jian.hu, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <20260415-clkmsr_a1_t7-v2-2-02b6314427e6@amlogic.com>
On 4/15/26 10:33, Jian Hu via B4 Relay wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add support for the A1 and T7 SoC family in amlogic clk measure.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> drivers/soc/amlogic/meson-clk-measure.c | 272 ++++++++++++++++++++++++++++++++
> 1 file changed, 272 insertions(+)
>
> diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
> index d862e30a244e..8c4f3cc8c8ab 100644
> --- a/drivers/soc/amlogic/meson-clk-measure.c
> +++ b/drivers/soc/amlogic/meson-clk-measure.c
> @@ -787,6 +787,258 @@ static const struct meson_msr_id clk_msr_s4[] = {
>
> };
>
> +static const struct meson_msr_id clk_msr_a1[] = {
> + CLK_MSR_ID(0, "tdmout_b_sclk"),
> + CLK_MSR_ID(1, "tdmout_a_sclk"),
> + CLK_MSR_ID(2, "tdmin_lb_sclk"),
> + CLK_MSR_ID(3, "tdmin_b_sclk"),
> + CLK_MSR_ID(4, "tdmin_a_sclk"),
> + CLK_MSR_ID(5, "vad"),
> + CLK_MSR_ID(6, "resamplea"),
> + CLK_MSR_ID(7, "pdm_sysclk"),
> + CLK_MSR_ID(8, "pdm_dclk"),
> + CLK_MSR_ID(9, "locker_out"),
> + CLK_MSR_ID(10, "locker_in"),
> + CLK_MSR_ID(11, "spdifin"),
> + CLK_MSR_ID(12, "tdmin_vad"),
> + CLK_MSR_ID(13, "au_adc"),
> + CLK_MSR_ID(14, "au_dac"),
> + CLK_MSR_ID(16, "spicc_a"),
> + CLK_MSR_ID(17, "spifc"),
> + CLK_MSR_ID(18, "sd_emmc_a"),
> + CLK_MSR_ID(19, "dmcx4"),
> + CLK_MSR_ID(20, "dmc"),
> + CLK_MSR_ID(21, "psram"),
> + CLK_MSR_ID(22, "cecb"),
> + CLK_MSR_ID(23, "ceca"),
> + CLK_MSR_ID(24, "ts"),
> + CLK_MSR_ID(25, "pwm_f"),
> + CLK_MSR_ID(26, "pwm_e"),
> + CLK_MSR_ID(27, "pwm_d"),
> + CLK_MSR_ID(28, "pwm_c"),
> + CLK_MSR_ID(29, "pwm_b"),
> + CLK_MSR_ID(30, "pwm_a"),
> + CLK_MSR_ID(31, "saradc"),
> + CLK_MSR_ID(32, "usb_bus"),
> + CLK_MSR_ID(33, "dsp_b"),
> + CLK_MSR_ID(34, "dsp_a"),
> + CLK_MSR_ID(35, "axi"),
> + CLK_MSR_ID(36, "sys"),
> + CLK_MSR_ID(40, "rng_ring_osc0"),
> + CLK_MSR_ID(41, "rng_ring_osc1"),
> + CLK_MSR_ID(42, "rng_ring_osc2"),
> + CLK_MSR_ID(43, "rng_ring_osc3"),
> + CLK_MSR_ID(44, "dds_out"),
> + CLK_MSR_ID(45, "cpu_clk_div16"),
> + CLK_MSR_ID(46, "gpio_msr"),
> + CLK_MSR_ID(50, "osc_ring_cpu0"),
> + CLK_MSR_ID(51, "osc_ring_cpu1"),
> + CLK_MSR_ID(54, "osc_ring_top0"),
> + CLK_MSR_ID(55, "osc_ring_top1"),
> + CLK_MSR_ID(56, "osc_ring_ddr"),
> + CLK_MSR_ID(57, "osc_ring_dmc"),
> + CLK_MSR_ID(58, "osc_ring_dspa"),
> + CLK_MSR_ID(59, "osc_ring_dspb"),
> + CLK_MSR_ID(60, "osc_ring_rama"),
> + CLK_MSR_ID(61, "osc_ring_ramb"),
> +};
> +
> +static const struct meson_msr_id clk_msr_t7[] = {
> + CLK_MSR_ID(0, "sys"),
> + CLK_MSR_ID(1, "axi"),
> + CLK_MSR_ID(2, "rtc"),
> + CLK_MSR_ID(3, "dspa"),
> + CLK_MSR_ID(4, "dspb"),
> + CLK_MSR_ID(5, "mali"),
> + CLK_MSR_ID(6, "sys_cpu_clk_div16"),
> + CLK_MSR_ID(7, "ceca"),
> + CLK_MSR_ID(8, "cecb"),
> + CLK_MSR_ID(10, "fclk_div5"),
> + CLK_MSR_ID(11, "mpll0"),
> + CLK_MSR_ID(12, "mpll1"),
> + CLK_MSR_ID(13, "mpll2"),
> + CLK_MSR_ID(14, "mpll3"),
> + CLK_MSR_ID(15, "mpll_50m"),
> + CLK_MSR_ID(16, "pcie_inp"),
> + CLK_MSR_ID(17, "pcie_inn"),
> + CLK_MSR_ID(18, "mpll_test_out"),
> + CLK_MSR_ID(19, "hifi_pll"),
> + CLK_MSR_ID(20, "gp0_pll"),
> + CLK_MSR_ID(21, "gp1_pll"),
> + CLK_MSR_ID(22, "eth_mppll_50m"),
> + CLK_MSR_ID(23, "sys_pll_div16"),
> + CLK_MSR_ID(24, "ddr_dpll_pt"),
> + CLK_MSR_ID(25, "earcrx_pll"),
> + CLK_MSR_ID(26, "paie1_clk_inp"),
> + CLK_MSR_ID(27, "paie1_clk_inn"),
> + CLK_MSR_ID(28, "amlgdc"),
> + CLK_MSR_ID(29, "gdc"),
> + CLK_MSR_ID(30, "mod_eth_phy_ref"),
> + CLK_MSR_ID(31, "mod_eth_tx"),
> + CLK_MSR_ID(32, "eth_clk125Mhz"),
> + CLK_MSR_ID(33, "eth_clk_rmii"),
> + CLK_MSR_ID(34, "co_clkin_to_mac"),
> + CLK_MSR_ID(35, "mod_eth_rx_clk_rmii"),
> + CLK_MSR_ID(36, "co_rx"),
> + CLK_MSR_ID(37, "co_tx"),
> + CLK_MSR_ID(38, "eth_phy_rxclk"),
> + CLK_MSR_ID(39, "eth_phy_plltxclk"),
> + CLK_MSR_ID(40, "ephy_test"),
> + CLK_MSR_ID(41, "dsi_b_meas"),
> + CLK_MSR_ID(42, "hdmirx_apl"),
> + CLK_MSR_ID(43, "hdmirx_tmds"),
> + CLK_MSR_ID(44, "hdmirx_cable"),
> + CLK_MSR_ID(45, "hdmirx_apll_clk_audio"),
> + CLK_MSR_ID(46, "hdmirx_5m"),
> + CLK_MSR_ID(47, "hdmirx_2m"),
> + CLK_MSR_ID(48, "hdmirx_cfg"),
> + CLK_MSR_ID(49, "hdmirx_hdcp2x_eclk"),
> + CLK_MSR_ID(50, "vid_pll0_div"),
> + CLK_MSR_ID(51, "hdmi_vid_pll"),
> + CLK_MSR_ID(54, "vdac_clk"),
> + CLK_MSR_ID(55, "vpu_clk_buf"),
> + CLK_MSR_ID(56, "mod_tcon_clko"),
> + CLK_MSR_ID(57, "lcd_an_clk_ph2"),
> + CLK_MSR_ID(58, "lcd_an_clk_ph3"),
> + CLK_MSR_ID(59, "hdmi_tx_pixel"),
> + CLK_MSR_ID(60, "vdin_meas"),
> + CLK_MSR_ID(61, "vpu_clk"),
> + CLK_MSR_ID(62, "vpu_clkb"),
> + CLK_MSR_ID(63, "vpu_clkb_tmp"),
> + CLK_MSR_ID(64, "vpu_clkc"),
> + CLK_MSR_ID(65, "vid_lock"),
> + CLK_MSR_ID(66, "vapbclk"),
> + CLK_MSR_ID(67, "ge2d"),
> + CLK_MSR_ID(68, "aud_pll"),
> + CLK_MSR_ID(69, "aud_sck"),
> + CLK_MSR_ID(70, "dsi_a_meas"),
> + CLK_MSR_ID(72, "mipi_csi_phy"),
> + CLK_MSR_ID(73, "mipi_isp"),
> + CLK_MSR_ID(76, "hdmitx_tmds"),
> + CLK_MSR_ID(77, "hdmitx_sys"),
> + CLK_MSR_ID(78, "hdmitx_fe"),
> + CLK_MSR_ID(80, "hdmitx_prif"),
> + CLK_MSR_ID(81, "hdmitx_200m"),
> + CLK_MSR_ID(82, "hdmitx_aud"),
> + CLK_MSR_ID(83, "hdmitx_pnx"),
> + CLK_MSR_ID(84, "spicc5"),
> + CLK_MSR_ID(85, "spicc4"),
> + CLK_MSR_ID(86, "spicc3"),
> + CLK_MSR_ID(87, "spicc2"),
> + CLK_MSR_ID(93, "vdec"),
> + CLK_MSR_ID(94, "wave521_aclk"),
> + CLK_MSR_ID(95, "wave521_cclk"),
> + CLK_MSR_ID(96, "wave521_bclk"),
> + CLK_MSR_ID(97, "hcodec"),
> + CLK_MSR_ID(98, "hevcb"),
> + CLK_MSR_ID(99, "hevcf"),
> + CLK_MSR_ID(100, "hdmi_aud_pll"),
> + CLK_MSR_ID(101, "hdmi_acr_ref"),
> + CLK_MSR_ID(102, "hdmi_meter"),
> + CLK_MSR_ID(103, "hdmi_vid"),
> + CLK_MSR_ID(104, "hdmi_aud"),
> + CLK_MSR_ID(105, "hdmi_dsd"),
> + CLK_MSR_ID(108, "dsi1_phy"),
> + CLK_MSR_ID(109, "dsi0_phy"),
> + CLK_MSR_ID(110, "smartcard"),
> + CLK_MSR_ID(111, "sar_adc"),
> + CLK_MSR_ID(113, "sd_emmc_c"),
> + CLK_MSR_ID(114, "sd_emmc_b"),
> + CLK_MSR_ID(115, "sd_emmc_a"),
> + CLK_MSR_ID(116, "gpio_msr"),
> + CLK_MSR_ID(117, "spicc1"),
> + CLK_MSR_ID(118, "spicc0"),
> + CLK_MSR_ID(119, "anakin"),
> + CLK_MSR_ID(121, "ts_clk(temp sensor)"),
> + CLK_MSR_ID(122, "ts_a73"),
> + CLK_MSR_ID(123, "ts_a53"),
> + CLK_MSR_ID(124, "ts_nna"),
> + CLK_MSR_ID(130, "audio_vad"),
> + CLK_MSR_ID(131, "acodec_dac_clk_x128"),
> + CLK_MSR_ID(132, "audio_locker_in"),
> + CLK_MSR_ID(133, "audio_locker_out"),
> + CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
> + CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
> + CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
> + CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
> + CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
> + CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
> + CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
> + CLK_MSR_ID(141, "audio_resamplea"),
> + CLK_MSR_ID(142, "audio_pdm_sysclk"),
> + CLK_MSR_ID(143, "audio_spdifoutb_mst"),
> + CLK_MSR_ID(144, "audio_spdifout_mst"),
> + CLK_MSR_ID(145, "audio_spdifin_mst"),
> + CLK_MSR_ID(146, "audio_pdm_dclk"),
> + CLK_MSR_ID(147, "audio_resampleb"),
> + CLK_MSR_ID(148, "earcrx_pll_dmac"),
> + CLK_MSR_ID(156, "pwm_ao_h"),
> + CLK_MSR_ID(157, "pwm_ao_g"),
> + CLK_MSR_ID(158, "pwm_ao_f"),
> + CLK_MSR_ID(159, "pwm_ao_e"),
> + CLK_MSR_ID(160, "pwm_ao_d"),
> + CLK_MSR_ID(161, "pwm_ao_c"),
> + CLK_MSR_ID(162, "pwm_ao_b"),
> + CLK_MSR_ID(163, "pwm_ao_a"),
> + CLK_MSR_ID(164, "pwm_f"),
> + CLK_MSR_ID(165, "pwm_e"),
> + CLK_MSR_ID(166, "pwm_d"),
> + CLK_MSR_ID(167, "pwm_c"),
> + CLK_MSR_ID(168, "pwm_b"),
> + CLK_MSR_ID(169, "pwm_a"),
> + CLK_MSR_ID(170, "aclkm"),
> + CLK_MSR_ID(171, "mclk_pll"),
> + CLK_MSR_ID(172, "a73_sys_pll_div16"),
> + CLK_MSR_ID(173, "a73_cpu_clk_div16"),
> + CLK_MSR_ID(176, "rng_ring_0"),
> + CLK_MSR_ID(177, "rng_ring_1"),
> + CLK_MSR_ID(178, "rng_ring_2"),
> + CLK_MSR_ID(179, "rng_ring_3"),
> + CLK_MSR_ID(180, "am_ring_out0"),
> + CLK_MSR_ID(181, "am_ring_out1"),
> + CLK_MSR_ID(182, "am_ring_out2"),
> + CLK_MSR_ID(183, "am_ring_out3"),
> + CLK_MSR_ID(184, "am_ring_out4"),
> + CLK_MSR_ID(185, "am_ring_out5"),
> + CLK_MSR_ID(186, "am_ring_out6"),
> + CLK_MSR_ID(187, "am_ring_out7"),
> + CLK_MSR_ID(188, "am_ring_out8"),
> + CLK_MSR_ID(189, "am_ring_out9"),
> + CLK_MSR_ID(190, "am_ring_out10"),
> + CLK_MSR_ID(191, "am_ring_out11"),
> + CLK_MSR_ID(192, "am_ring_out12"),
> + CLK_MSR_ID(193, "am_ring_out13"),
> + CLK_MSR_ID(194, "am_ring_out14"),
> + CLK_MSR_ID(195, "am_ring_out15"),
> + CLK_MSR_ID(196, "am_ring_out16"),
> + CLK_MSR_ID(197, "am_ring_out17"),
> + CLK_MSR_ID(198, "am_ring_out18"),
> + CLK_MSR_ID(199, "am_ring_out19"),
> + CLK_MSR_ID(200, "mipi_csi_phy0"),
> + CLK_MSR_ID(201, "mipi_csi_phy1"),
> + CLK_MSR_ID(202, "mipi_csi_phy2"),
> + CLK_MSR_ID(203, "mipi_csi_phy3"),
> + CLK_MSR_ID(204, "vid_pll1_div"),
> + CLK_MSR_ID(205, "vid_pll2_div"),
> + CLK_MSR_ID(206, "am_ring_out20"),
> + CLK_MSR_ID(207, "am_ring_out21"),
> + CLK_MSR_ID(208, "am_ring_out22"),
> + CLK_MSR_ID(209, "am_ring_out23"),
> + CLK_MSR_ID(210, "am_ring_out24"),
> + CLK_MSR_ID(211, "am_ring_out25"),
> + CLK_MSR_ID(212, "am_ring_out26"),
> + CLK_MSR_ID(213, "am_ring_out27"),
> + CLK_MSR_ID(214, "am_ring_out28"),
> + CLK_MSR_ID(215, "am_ring_out29"),
> + CLK_MSR_ID(216, "am_ring_out30"),
> + CLK_MSR_ID(217, "am_ring_out31"),
> + CLK_MSR_ID(218, "am_ring_out32"),
> + CLK_MSR_ID(219, "enc0_if"),
> + CLK_MSR_ID(220, "enc2"),
> + CLK_MSR_ID(221, "enc1"),
> + CLK_MSR_ID(222, "enc0")
> +};
> +
> static int meson_measure_id(struct meson_msr_id *clk_msr_id,
> unsigned int duration)
> {
> @@ -1026,6 +1278,18 @@ static const struct meson_msr_data clk_msr_s4_data = {
> .reg = &msr_reg_offset_v2,
> };
>
> +static const struct meson_msr_data clk_msr_a1_data = {
> + .msr_table = (void *)clk_msr_a1,
> + .msr_count = ARRAY_SIZE(clk_msr_a1),
> + .reg = &msr_reg_offset_v2,
> +};
> +
> +static const struct meson_msr_data clk_msr_t7_data = {
> + .msr_table = (void *)clk_msr_t7,
> + .msr_count = ARRAY_SIZE(clk_msr_t7),
> + .reg = &msr_reg_offset_v2,
> +};
> +
> static const struct of_device_id meson_msr_match_table[] = {
> {
> .compatible = "amlogic,meson-gx-clk-measure",
> @@ -1059,6 +1323,14 @@ static const struct of_device_id meson_msr_match_table[] = {
> .compatible = "amlogic,s4-clk-measure",
> .data = &clk_msr_s4_data,
> },
> + {
> + .compatible = "amlogic,a1-clk-measure",
> + .data = &clk_msr_a1_data,
> + },
> + {
> + .compatible = "amlogic,t7-clk-measure",
> + .data = &clk_msr_t7_data,
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, meson_msr_match_table);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH v2 4/9] pmdomain: core: Add initial fine grained sync_state support
From: Geert Uytterhoeven @ 2026-04-20 8:49 UTC (permalink / raw)
To: Ulf Hansson
Cc: Saravana Kannan, Rafael J . Wysocki, Greg Kroah-Hartman, linux-pm,
Sudeep Holla, Cristian Marussi, Kevin Hilman, Stephen Boyd,
Marek Szyprowski, Bjorn Andersson, Abel Vesa, Peng Fan,
Tomi Valkeinen, Maulik Shah, Konrad Dybcio, Thierry Reding,
Jonathan Hunter, Dmitry Baryshkov, linux-arm-kernel, linux-kernel,
Geert Uytterhoeven
In-Reply-To: <20260410104058.83748-5-ulf.hansson@linaro.org>
Hi Ulf,
On Fri, 10 Apr 2026 at 12:41, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> A onecell (#power-domain-cells = <1 or 2>; in DT) power domain provider
> typically provides multiple independent power domains, each with their own
> corresponding consumers. In these cases we have to wait for all consumers
> for all the provided power domains before the ->sync_state() callback gets
> called for the supplier.
>
> In a first step to improve this, let's implement support for fine grained
> sync_state support a per genpd basis by using the ->queue_sync_state()
> callback. To take step by step, let's initially limit the improvement to
> the internal genpd provider driver and to its corresponding genpd devices
> for onecell providers.
>
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Thanks for your patch!
> --- a/drivers/pmdomain/core.c
> +++ b/drivers/pmdomain/core.c
> +static void genpd_parse_for_consumer(struct device_node *sup,
> + struct device_node *con)
> +{
> + struct generic_pm_domain *genpd;
> + int i;
unsigned int?
> +
> + for (i = 0; ; i++) {
... and you could move it inside the for-statement.
> + struct of_phandle_args pd_args;
> +
> + if (of_parse_phandle_with_args(con, "power-domains",
> + "#power-domain-cells",
> + i, &pd_args))
Checkpatch reports a superfluous space before the "i".
> + break;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 4/4] arm64: dts: amlogic: t7: Add clk measure support
From: Neil Armstrong @ 2026-04-20 8:52 UTC (permalink / raw)
To: Jian Hu, Ronald Claveau
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
In-Reply-To: <64cde9f6-4f28-4ba7-8362-aac28887ff22@amlogic.com>
On 4/20/26 05:25, Jian Hu wrote:
> Hi Ronald,
>
>
> Thanks for your review.
>
> On 4/17/2026 5:48 PM, Ronald Claveau wrote:
>> [ EXTERNAL EMAIL ]
>>
>> Hello Jian,
>>
>> On 4/15/26 10:33 AM, Jian Hu via B4 Relay wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the clock measure device to the T7 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> index 7fe72c94ed62..cec2ea74850d 100644
>>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> @@ -701,6 +701,11 @@ pwm_ao_cd: pwm@60000 {
>>> status = "disabled";
>>> };
>>>
>>> + clock-measurer@48000 {
>>> + compatible = "amlogic,t7-clk-measure";
>>> + reg = <0x0 0x48000 0x0 0x1c>;
>>> + };
>>> +
>> Can you please order by reg, it should be between pwm_ao_gh and pwm_ab.
>> Thank you.
>
>
> According to the "Order of Nodes" chapter in Documentation/devicetree/bindings/dts-coding-style.rst,
>
> nodes of the same type should be grouped together, and this takes higher priority.
>
> So I have placed the clock-measure node after all PWM nodes to avoid splitting the PWM group.
This is not something we ever followed in the past, and I don't think it makes sens here.
"""
Alternatively for some subarchitectures, nodes of the same type can be
grouped together, e.g. all I2C controllers one after another even if this
breaks unit address ordering.
"""
This doesn't apply here, so order strictly by address.
Neil
>
>
> Best regards,
>
> Jian
>
^ permalink raw reply
* Re: [RFC PATCH 4/4] firmware: arm_ffa: check pkvm initailised when initailise ffa driver
From: Will Deacon @ 2026-04-20 8:55 UTC (permalink / raw)
To: Yeoreum Yun
Cc: Marc Zyngier, linux-security-module, linux-kernel,
linux-integrity, linux-arm-kernel, kvmarm, paul, jmorris, serge,
zohar, roberto.sassu, dmitry.kasatkin, eric.snowberg, peterhuewe,
jarkko, jgg, sudeep.holla, oupton, joey.gouly, suzuki.poulose,
yuzenghui, catalin.marinas
In-Reply-To: <aeS4rAeVQ0yJIPYw@e129823.arm.com>
On Sun, Apr 19, 2026 at 12:12:44PM +0100, Yeoreum Yun wrote:
> Hi Marc,
>
> > On Sat, 18 Apr 2026 11:34:30 +0100,
> > Yeoreum Yun <yeoreum.yun@arm.com> wrote:
> > >
> > > > > @@ -2035,6 +2037,16 @@ static int __init ffa_init(void)
> > > > > u32 buf_sz;
> > > > > size_t rxtx_bufsz = SZ_4K;
> > > > >
> > > > > + /*
> > > > > + * When pKVM is enabled, the FF-A driver must be initialized
> > > > > + * after pKVM initialization. Otherwise, pKVM cannot negotiate
> > > > > + * the FF-A version or obtain RX/TX buffer information,
> > > > > + * which leads to failures in FF-A calls.
> > > > > + */
> > > > > + if (IS_ENABLED(CONFIG_KVM) && is_protected_kvm_enabled() &&
> > > > > + !is_kvm_arm_initialised())
> > > > > + return -EPROBE_DEFER;
> > > > > +
> > > >
> > > > That's still fundamentally wrong: pkvm is not ready until
> > > > finalize_pkvm() has finished, and that's not indicated by
> > > > is_kvm_arm_initialised().
> > >
> > > Thanks. I miss the TSC bit set in here.
> >
> > That's the least of the problems. None of the infrastructure is in
> > place at this stage...
> >
> > > IMHO, I'd like to make an new state check function --
> > > is_pkvm_arm_initialised() so that ff-a driver to know whether
> > > pkvm is initialised.
> >
> > Doesn't sound great, TBH.
> >
> > > or any other suggestion?
> >
> > Instead of adding more esoteric predicates, I'd rather you build on an
> > existing infrastructure. You have a dependency on KVM, use something
> > that is designed to enforce dependencies. Device links spring to mind
> > as something designed for that.
> >
> > Can you look into enabling this for KVM? If that's possible, then it
> > should be easy enough to delay the actual KVM registration after pKVM
> > is finalised.
>
> or what about some event notifier? Just like:
This seems a bit over-engineered to me. Why don't you just split the
FF-A initialisation into two steps: an early part which does the version
negotiation and then a later part which can fit in with whatever
dependencies you have on the TPM?
Will
^ permalink raw reply
* Re: [PATCH] gpio: aspeed: fix AST2700 debounce selector bit definitions
From: Bartosz Golaszewski @ 2026-04-20 9:15 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Joel Stanley, Andrew Jeffery,
Billy Tsai
Cc: Bartosz Golaszewski, linux-gpio, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20260415-gpio-fix-v1-1-b08a89b31e6f@aspeedtech.com>
On Wed, 15 Apr 2026 18:24:42 +0800, Billy Tsai wrote:
> The AST2700 datasheet defines reg_debounce_sel1 as the low bit and
> reg_debounce_sel2 as the high bit. The current driver uses the AST2600
> mapping instead, where sel1 is the high bit and sel2 is the low bit.
>
> As a result, the debounce selector bits are programmed in reverse on
> AST2700. Swap the G7 sel1/sel2 bit definitions so the driver matches the
> hardware definition.
>
> [...]
Applied, thanks!
[1/1] gpio: aspeed: fix AST2700 debounce selector bit definitions
https://git.kernel.org/brgl/c/e31eee4a961077d60ef2362507240c6743c1c2ae
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 4/4] arm64: dts: amlogic: t7: Add clk measure support
From: Ronald Claveau @ 2026-04-20 9:16 UTC (permalink / raw)
To: Jian Hu
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
In-Reply-To: <64cde9f6-4f28-4ba7-8362-aac28887ff22@amlogic.com>
Hi Jian,
On 4/20/26 5:25 AM, Jian Hu wrote:
> Hi Ronald,
>
>
> Thanks for your review.
>
> On 4/17/2026 5:48 PM, Ronald Claveau wrote:
>> [ EXTERNAL EMAIL ]
>>
>> Hello Jian,
>>
>> On 4/15/26 10:33 AM, Jian Hu via B4 Relay wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the clock measure device to the T7 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/
>>> arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> index 7fe72c94ed62..cec2ea74850d 100644
>>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> @@ -701,6 +701,11 @@ pwm_ao_cd: pwm@60000 {
>>> status = "disabled";
>>> };
>>>
>>> + clock-measurer@48000 {
>>> + compatible = "amlogic,t7-clk-measure";
>>> + reg = <0x0 0x48000 0x0 0x1c>;
>>> + };
>>> +
>> Can you please order by reg, it should be between pwm_ao_gh and pwm_ab.
>> Thank you.
>
>
> According to the "Order of Nodes" chapter in Documentation/devicetree/
> bindings/dts-coding-style.rst,
>
> nodes of the same type should be grouped together, and this takes higher
> priority.
>
> So I have placed the clock-measure node after all PWM nodes to avoid
> splitting the PWM group.
>
Thanks for your answer.
The documentation says nodes "shall be ordered by unit address" as the
primary rule.
The grouping by type is described as an alternative ("Alternatively"),
applicable to some subarchitectures, not as a rule that takes higher
priority.
So to me, I understand it as, unless your subarchitecture has an
established convention of grouping PWM nodes together, ordering by reg
remains the correct default here. And, in my opinion, sticking to a
single sorting method improves readability.
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH 2/3] gpio: axiado: add SGPIO controller support
From: Bartosz Golaszewski @ 2026-04-20 9:25 UTC (permalink / raw)
To: Petar Stepanovic
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Tzu-Hao Wei, Swark Yang, Prasad Bolisetty, Linus Walleij,
Bartosz Golaszewski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Harshit Shah, SriNavmani A
In-Reply-To: <20260414-axiado-ax3000-sgpio-controller-v1-2-b5c7e4c2e69b@axiado.com>
On Tue, 14 Apr 2026 15:48:33 +0200, Petar Stepanovic
<pstepanovic@axiado.com> said:
> Add support for the Axiado SGPIO controller.
>
> The controller provides a serialized interface for GPIOs with
> configurable direction and interrupt support.
>
> The driver registers the controller as a gpio_chip and uses
> regmap for register access.
>
> Signed-off-by: Petar Stepanovic <pstepanovic@axiado.com>
> ---
> drivers/gpio/Kconfig | 18 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-axiado-sgpio.c | 780 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 799 insertions(+)
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index bd185482a7fd..42c56d157092 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -198,6 +198,24 @@ config GPIO_ATH79
> Select this option to enable GPIO driver for
> Atheros AR71XX/AR724X/AR913X SoC devices.
>
> +config GPIO_AXIADO_SGPIO
> + bool "Axiado SGPIO support"
> + depends on OF_GPIO
You don't need this.
> + depends on ARCH_AXIADO || COMPILE_TEST
> + select GPIO_GENERIC
You don't seem to be using this.
> + select GPIOLIB_IRQCHIP
> + select REGMAP
> + help
> + Enable support for the Axiado Serial GPIO (SGPIO) controller.
> +
> + The SGPIO controller provides a serialized interface for
> + controlling multiple GPIO signals over a limited number of
> + physical lines. It supports configurable data direction and
> + interrupt handling.
> +
> + This driver integrates with the Linux GPIO subsystem and
> + exposes the controller as a standard GPIO provider.
> +
> config GPIO_RASPBERRYPI_EXP
> tristate "Raspberry Pi 3 GPIO Expander"
> default RASPBERRYPI_FIRMWARE
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 2421a8fd3733..909a97551807 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
> obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
> obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o
> obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
> +obj-$(CONFIG_GPIO_AXIADO_SGPIO) += gpio-axiado-sgpio.o
> obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
> obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
> obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
> diff --git a/drivers/gpio/gpio-axiado-sgpio.c b/drivers/gpio/gpio-axiado-sgpio.c
> new file mode 100644
> index 000000000000..8cd349ec6f53
> --- /dev/null
> +++ b/drivers/gpio/gpio-axiado-sgpio.c
> @@ -0,0 +1,780 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (c) 2022-2026 Axiado Corporation
> + */
Please add a blank line here...
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +
> +#include <linux/gpio/driver.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <linux/regmap.h>
> +
... and keep the includes together as well as ordered alphabetically.
> +struct sgpio_reg_offsets {
> + u32 mux_0;
> + u32 preset_0;
> + u32 count_0;
> + u32 pos_0;
> +
> + u32 mux_1;
> + u32 ld;
> + u32 ld_ss;
> +
> + u32 preset_1;
> + u32 count_1;
> + u32 pos_1;
> +
> + u32 mux_2;
> + u32 dout;
> + u32 dout_ss;
> +
> + u32 preset_2;
> + u32 count_2;
> + u32 pos_2;
> +
> + u32 mux_3;
> + u32 preset_3;
> + u32 count_3;
> + u32 pos_3;
> +
> + u32 mux_4;
> + u32 oe;
> + u32 oe_ss;
> +
> + u32 preset_4;
> + u32 count_4;
> + u32 pos_4;
> +
> + u32 mask;
> + u32 ctrl_en;
> + u32 ctrl_en_pos;
> +
> + u32 din_ss;
> + u32 status;
> +};
> +
> +static const struct sgpio_reg_offsets sgpio_offsets_512 = {
> + .mux_0 = 0x000,
> + .preset_0 = 0x1dc,
> + .count_0 = 0x1f0,
> + .pos_0 = 0x204,
> +
> + .mux_1 = 0x004,
> + .ld = 0x014,
> + .ld_ss = 0x0d8,
> +
> + .preset_1 = 0x1e0,
> + .count_1 = 0x1f4,
> + .pos_1 = 0x208,
> +
> + .mux_2 = 0x008,
> + .dout = 0x054,
> + .dout_ss = 0x158,
> +
> + .preset_2 = 0x1e4,
> + .count_2 = 0x1f8,
> + .pos_2 = 0x20c,
> +
> + .mux_3 = 0x00c,
> + .preset_3 = 0x1e8,
> + .count_3 = 0x1fc,
> + .pos_3 = 0x210,
> +
> + .mux_4 = 0x010,
> + .oe = 0x0d4,
> + .oe_ss = 0x1d8,
> +
> + .preset_4 = 0x1ec,
> + .count_4 = 0x200,
> + .pos_4 = 0x214,
> +
> + .mask = 0x224,
> + .ctrl_en = 0x218,
> + .ctrl_en_pos = 0x21c,
> +
> + .din_ss = 0x198,
> + .status = 0x228,
> +};
> +
> +static const struct sgpio_reg_offsets sgpio_offsets_128 = {
> + .mux_0 = 0x000,
> + .preset_0 = 0x08c,
> + .count_0 = 0x0a0,
> + .pos_0 = 0x0b4,
> +
> + .mux_1 = 0x004,
> + .ld = 0x014,
> + .ld_ss = 0x048,
> +
> + .preset_1 = 0x090,
> + .count_1 = 0x0a4,
> + .pos_1 = 0x0b8,
> +
> + .mux_2 = 0x008,
> + .dout = 0x024,
> + .dout_ss = 0x068,
> +
> + .preset_2 = 0x094,
> + .count_2 = 0x0a8,
> + .pos_2 = 0x0bc,
> +
> + .mux_3 = 0x00c,
> + .preset_3 = 0x098,
> + .count_3 = 0x0ac,
> + .pos_3 = 0x0c0,
> +
> + .mux_4 = 0x010,
> + .oe = 0x044,
> + .oe_ss = 0x088,
> +
> + .preset_4 = 0x09c,
> + .count_4 = 0x0b0,
> + .pos_4 = 0x0c4,
> +
> + .mask = 0x0d4,
> + .ctrl_en = 0x0c8,
> + .ctrl_en_pos = 0x0cc,
> +
> + .din_ss = 0x078,
> + .status = 0x0d8,
> +};
> +
> +#define MAX_SGPIO_PINS 512
> +#define MAX_OFFSET_REG 16
> +#define MAX_SLICE_COUNT 5
> +
> +struct ax3000_slice_info {
> + u32 out_mux;
> + u32 sgpio_mux;
> + u32 slice_mux;
> + u32 reg[MAX_OFFSET_REG];
> + u32 reg_ss[MAX_OFFSET_REG];
> + u32 preset;
> + u32 count;
> + u32 pos;
> +};
> +
> +struct ax3000_sgpio {
> + u32 preset_value;
> + u32 count_value;
> + u32 pos_reg;
> + struct ax3000_slice_info
> + slices[MAX_SLICE_COUNT]; /* 0=clk,1=load,2=out,3=in,4=oe */
> + spinlock_t lock;
> + int ngpios;
> + int max_sgpio_pins;
> + int max_offset_regs;
> + struct gpio_chip chip;
> + u32 irq_unmasked[MAX_SGPIO_PINS];
> + int parent_irq;
> + struct regmap *regmap;
> + u32 regmap_base_offset;
> + struct sgpio_reg_offsets *regs;
> +};
> +
> +static int sgpio_set_irq_type(struct irq_data *d, unsigned int type);
> +static void sgpio_mask_irq(struct irq_data *d);
> +static void sgpio_unmask_irq(struct irq_data *d);
> +static void sgpio_irq_shutdown(struct irq_data *d);
> +
> +static const struct irq_chip axiado_sgpio_irqchip = {
> + .name = "axiado-sgpio",
> + .irq_mask = sgpio_mask_irq,
> + .irq_unmask = sgpio_unmask_irq,
> + .irq_set_type = sgpio_set_irq_type,
> + .irq_shutdown = sgpio_irq_shutdown,
> + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
> +};
> +
> +static void ax3000_sgpio_set(struct gpio_chip *chip, unsigned int offset,
> + int value)
> +{
> + struct ax3000_sgpio *sgpio = gpiochip_get_data(chip);
> + unsigned long flags;
> + u32 bank = (offset / 2) / 32;
> + u32 position = (offset / 2) % 32;
> +
> + spin_lock_irqsave(&sgpio->lock, flags);
Please use guards for locks.
> + if (value)
> + sgpio->slices[2].reg_ss[bank] |= BIT(position);
> + else
> + sgpio->slices[2].reg_ss[bank] &= ~BIT(position);
> +
> + spin_unlock_irqrestore(&sgpio->lock, flags);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (bank * 4),
> + sgpio->slices[2].reg_ss[bank]);
> +}
> +
> +static int ax3000_sgpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct ax3000_sgpio *sgpio = gpiochip_get_data(chip);
> + u32 bank = (offset / 2) / 32;
> + u32 position = (offset / 2) % 32;
> +
> + if (offset % 2 == 0)
> + return !!(sgpio->slices[3].reg_ss[bank] & BIT(position));
> + else
> + return !!(sgpio->slices[2].reg_ss[bank] & BIT(position));
> +}
> +
> +static int ax3000_sgpio_dir_in(struct gpio_chip *chip, unsigned int offset)
> +{
> + if (!(offset % 2))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int ax3000_sgpio_dir_out(struct gpio_chip *chip, unsigned int offset,
> + int value)
> +{
> + if (offset % 2) {
> + if (chip->set)
> + chip->set(chip, offset, value);
> + return 0;
> + } else {
> + return -EINVAL;
> + }
> +}
> +
> +static irqreturn_t sgpio_irq_handler(int irq, void *arg)
> +{
> + struct ax3000_sgpio *sgpio = (struct ax3000_sgpio *)arg;
> + unsigned long flags;
> + u32 status, new_value;
> + u32 changed_value;
> + int i, bit, reg_ptr;
> +
> + /* Read-on-clear (ACK) parent cause */
> + regmap_read(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->status, &status);
> + status >>= 16;
> +
> + bool has_shifted_layout = (sgpio->max_offset_regs == MAX_OFFSET_REG);
> +
> + reg_ptr = has_shifted_layout ? 16 - DIV_ROUND_UP(sgpio->ngpios, 32) : 0;
> +
> + for (i = 0; i < DIV_ROUND_UP(sgpio->ngpios, 32); i++, reg_ptr++) {
> + if (status & BIT(reg_ptr)) {
> + regmap_read(sgpio->regmap,
> + sgpio->regmap_base_offset +
> + sgpio->regs->din_ss + (reg_ptr * 4),
> + &new_value);
> + spin_lock_irqsave(&sgpio->lock, flags);
> + changed_value = sgpio->slices[3].reg_ss[i] ^ new_value;
> + sgpio->slices[3].reg_ss[i] = new_value;
> + spin_unlock_irqrestore(&sgpio->lock, flags);
> +
> + while (changed_value) {
> + bit = __ffs(changed_value);
> + changed_value &= ~BIT(bit);
> +
> + irq_hw_number_t hwirq = i * 32 + bit;
> +
> + if (sgpio->irq_unmasked[hwirq]) {
> + unsigned int child_irq;
> +
> + child_irq = irq_find_mapping(sgpio->chip.irq.domain,
> + hwirq);
> +
> + if (child_irq)
> + handle_nested_irq(child_irq);
> + }
> + }
> + }
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void sgpio_hw_init(struct ax3000_sgpio *sgpio)
> +{
> + u32 bank;
> + u32 position;
> + int i = 0;
> + bool has_shifted_layout = (sgpio->max_offset_regs == MAX_OFFSET_REG);
> +
> + /* slice A0, Clock Pin - 0 */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_0, 0x306);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_0,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_0,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_0, 0x1f001f);
> +
> + /* Slice B1, Data Load Pin - 1 */
> + bank = (sgpio->ngpios - 1) / 32;
> + position = (sgpio->ngpios - 1) % 32;
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_1,
> + has_shifted_layout ? 0x30c : 0x304);
> +
> + for (i = 0; i < bank; i++) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld +
> + (i * 4),
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld_ss +
> + (i * 4),
> + 0xffffffff);
> + }
> +
> + if (position) {
> + u32 val;
> +
> + val = sgpio->slices[1].reg_ss[i];
> + val |= GENMASK(position - 1, 0);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld +
> + (i * 4),
> + val);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld_ss +
> + (i * 4),
> + val);
> + }
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_1,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_1,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_1,
> + sgpio->pos_reg);
> +
> + /* Slice C2, Data Out Pin - 2 */
> + bank = sgpio->ngpios / 32;
> + position = sgpio->ngpios % 32;
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_2,
> + has_shifted_layout ? 0x30c : 0x304);
> +
> + for (i = 0; i < bank; i++) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + }
> +
> + if (position) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + }
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_2,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_2,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_2,
> + sgpio->pos_reg);
> +
> + /* Slice D3, Data In Pin - 3 */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_3, 0x14C);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_3,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_3,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_3,
> + sgpio->pos_reg);
> +
> + /* Slice E4, Output Enable for respective pins */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_4,
> + has_shifted_layout ? 0x10c : 0x104);
> + regmap_write(sgpio->regmap, sgpio->regmap_base_offset + sgpio->regs->oe,
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->oe_ss,
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_4,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_4,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_4, 0x1f001f);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mask, 0xdfff);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en, 0xffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en_pos,
> + 0xffff);
> +}
> +
> +static int sgpio_set_irq_type(struct irq_data *d, unsigned int type)
> +{
> + switch (type) {
> + case IRQ_TYPE_EDGE_BOTH:
> + case IRQ_TYPE_EDGE_RISING:
> + case IRQ_TYPE_EDGE_FALLING:
> + irq_set_handler_locked(d, handle_edge_irq);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void sgpio_mask_irq(struct irq_data *d)
> +{
> + struct gpio_chip *chip;
> + struct ax3000_sgpio *sgpio;
> + u32 irq_num;
> +
> + chip = irq_data_get_irq_chip_data(d);
> + if (!chip) {
> + pr_err("Unable to get gpio_chip for IRQ\n");
> + return;
> + }
> +
> + sgpio = gpiochip_get_data(chip);
> + if (!sgpio) {
> + pr_err("Unable to get chip data\n");
> + return;
> + }
> +
> + irq_num = irqd_to_hwirq(d);
> + sgpio->irq_unmasked[irq_num / 2] = 0;
> +}
> +
> +static void sgpio_unmask_irq(struct irq_data *d)
> +{
> + struct gpio_chip *chip;
> + struct ax3000_sgpio *sgpio;
> + u32 irq_num;
> +
> + chip = irq_data_get_irq_chip_data(d);
> + if (!chip) {
> + pr_err("Unable to get gpio_chip for IRQ\n");
> + return;
> + }
> +
> + sgpio = gpiochip_get_data(chip);
> + if (!sgpio) {
> + pr_err("Unable to get chip data\n");
> + return;
> + }
> +
> + irq_num = irqd_to_hwirq(d);
> + sgpio->irq_unmasked[irq_num / 2] = 1;
> +}
> +
> +static void sgpio_irq_shutdown(struct irq_data *d)
> +{
> + sgpio_mask_irq(d);
> +}
> +
> +static int sgpio_probe(struct platform_device *pdev)
> +{
> + int rc;
> + int irq;
> + int i;
> + const __be32 *prop;
> + struct gpio_irq_chip *girq;
> + struct ax3000_sgpio *sgpio;
> + u32 variant;
> + u32 dout_value;
> + u32 bus_frequency;
> + u32 apb_frequency;
> + int dout_reverse;
> +
> + void __iomem *base;
> +
> + const struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + };
> +
> + sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
> + if (!sgpio)
> + return -ENOMEM;
> +
> + spin_lock_init(&sgpio->lock);
> +
> + sgpio->regmap = dev_get_regmap(pdev->dev.parent, NULL);
> +
> + if (sgpio->regmap) {
> + rc = of_property_read_u32(pdev->dev.of_node, "reg",
> + &sgpio->regmap_base_offset);
Why are you mixing of_property_*() with device_property_*()?
> + if (rc) {
> + dev_err(&pdev->dev, "Failed to read reg property: %d\n",
> + rc);
> + return rc;
> + }
> + dev_info(&pdev->dev, "Using regmap with base offset: 0x%x\n",
> + sgpio->regmap_base_offset);
> + } else {
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + sgpio->regmap =
> + devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
> +
> + if (IS_ERR(sgpio->regmap))
> + return PTR_ERR(sgpio->regmap);
> +
> + sgpio->regmap_base_offset = 0;
> +
> + dev_info(&pdev->dev, "Using MMIO regmap\n");
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "ngpios", &sgpio->ngpios);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read ngpios property\n");
> + return -EINVAL;
> + }
> +
> + if (device_property_read_u32(&pdev->dev, "design-variant", &variant)) {
> + dev_err(&pdev->dev, "design-variant not specified in DT\n");
> + return -EINVAL;
> + }
> +
> + if (variant == 128) {
> + sgpio->regs = &sgpio_offsets_128;
> + sgpio->max_sgpio_pins = 128;
> + sgpio->max_offset_regs = 4;
> + } else if (variant == 512) {
> + sgpio->regs = &sgpio_offsets_512;
> + sgpio->max_sgpio_pins = 512;
> + sgpio->max_offset_regs = 16;
> + } else {
> + return -EINVAL;
> + }
> +
> + if (sgpio->ngpios > sgpio->max_sgpio_pins) {
> + dev_err(&pdev->dev, "ngpio is greater than 512 pins\n");
> + return -EINVAL;
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "bus-frequency",
> + &bus_frequency);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read bus-frequency property\n");
> + return -EINVAL;
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "apb-frequency",
> + &apb_frequency);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read apb-frequency property\n");
> + return -EINVAL;
> + }
> +
> + sgpio->preset_value = (apb_frequency / bus_frequency) - 1;
> + sgpio->count_value = sgpio->preset_value;
> +
> + u32 pos;
> +
> + pos = sgpio->ngpios - 1;
> + sgpio->pos_reg = (pos << 16) | pos;
> +
> + prop = of_get_property(pdev->dev.of_node, "dout-init", NULL);
> + if (!prop) {
> + dev_err(&pdev->dev, "Failed to get dout-init\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < sgpio->max_offset_regs; i++) {
> + sgpio->slices[2].reg_ss[i] = 0;
> + dout_value = be32_to_cpu(prop[i]);
> +
> + for (dout_reverse = 0; dout_reverse < 32; ++dout_reverse) {
> + sgpio->slices[2].reg_ss[i] <<= 1;
> + sgpio->slices[2].reg_ss[i] |= (dout_value & 1);
> + dout_value >>= 1;
> + }
> + }
> +
> + sgpio_hw_init(sgpio);
> +
> + irq = platform_get_irq(pdev, 0);
> +
Unnecessary newline.
> + if (irq < 0) {
> + dev_err(&pdev->dev, "Failed to get parent IRQ: %d\n", irq);
> + return irq;
> + }
> + /* Store parent IRQ for cleanup */
> + sgpio->parent_irq = irq;
> +
> + rc = devm_request_threaded_irq(&pdev->dev, irq, NULL, sgpio_irq_handler,
> + IRQF_ONESHOT, "axiado-sgpio", sgpio);
> +
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Failed to request threaded IRQ %d: %d\n",
> + irq, rc);
> + return rc;
> + }
> +
> + sgpio->chip.parent = &pdev->dev;
> + sgpio->chip.ngpio = sgpio->ngpios * 2;
> + sgpio->chip.owner = THIS_MODULE;
> + sgpio->chip.direction_input = ax3000_sgpio_dir_in;
> + sgpio->chip.direction_output = ax3000_sgpio_dir_out;
> + sgpio->chip.get = ax3000_sgpio_get;
> + sgpio->chip.set = ax3000_sgpio_set;
> + sgpio->chip.label = dev_name(&pdev->dev);
> + sgpio->chip.base = -1;
> +
> + girq = &sgpio->chip.irq;
> +
> + girq->chip = &axiado_sgpio_irqchip;
> + girq->handler = handle_edge_irq;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->num_parents = 1;
> + girq->parents =
> + devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
> + if (!girq->parents) {
> + dev_err(&pdev->dev, "Failed to allocate parents array\n");
Drop this message, returning -ENOMEM is enough.
> + return -ENOMEM;
> + }
> + girq->parents[0] = irq;
> +
> + rc = devm_gpiochip_add_data(&pdev->dev, &sgpio->chip, sgpio);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", rc);
> + return rc;
Use return dev_err_probe() here and elsewhere.
> + }
> +
> + /* Store driver data for remove() */
> + platform_set_drvdata(pdev, sgpio);
> + dev_info(&pdev->dev, "SGPIO registered with %d GPIOs\n",
> + sgpio->chip.ngpio);
No need for this info message, please drop it.
> +
> + return 0;
> +}
> +
> +static int sgpio_remove(struct platform_device *pdev)
> +{
> + struct ax3000_sgpio *sgpio = platform_get_drvdata(pdev);
> + int i;
> +
> + if (!sgpio)
> + return 0;
> +
> + /* Disable interrupts in hardware */
> + if (sgpio->regs) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mask,
> + 0x0);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en,
> + 0x0);
> + }
> +
> + /* Disable and synchronize parent IRQ to avoid races with handlers */
> + if (sgpio->parent_irq >= 0) {
> + disable_irq(sgpio->parent_irq);
> + synchronize_irq(sgpio->parent_irq);
> + }
> +
> + /* Ensure all GPIO IRQ handlers complete before removal */
> + if (sgpio->chip.irq.domain) {
> + struct irq_domain *domain = sgpio->chip.irq.domain;
> + unsigned int irq;
> + int hwirq;
> +
> + for (hwirq = 0; hwirq < sgpio->chip.ngpio; hwirq++) {
> + irq = irq_find_mapping(domain, hwirq);
> + if (irq) {
> + disable_irq(irq);
> + synchronize_irq(irq);
> + }
> + }
> + }
> +
> + /* Clear internal IRQ state */
> + for (i = 0; i < sgpio->max_sgpio_pins; i++)
> + sgpio->irq_unmasked[i] = 0;
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ax_sgpio_match[] = {
> + { .compatible = "axiado,sgpio" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, ax_sgpio_match);
> +
> +static struct platform_driver sgpio_driver = {
> + .driver = {
> + .name = "sgpio",
> + .owner = THIS_MODULE,
> + .of_match_table = ax_sgpio_match,
> + },
> + .probe = sgpio_probe,
> + .remove = sgpio_remove,
> +};
> +
> +static int __init ax_sgpio_init(void)
> +{
> + int ret;
> +
> + ret = platform_driver_register(&sgpio_driver);
> + if (ret < 0) {
> + pr_err("Failed to register SGPIO driver\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void __exit ax_sgpio_exit(void)
> +{
> + platform_driver_unregister(&sgpio_driver);
> +}
> +
> +module_init(ax_sgpio_init);
> +module_exit(ax_sgpio_exit);
Just use module_platform_driver().
> +
> +MODULE_DESCRIPTION("Axiado Serial GPIO Driver");
> +MODULE_AUTHOR("Axiado Corporation");
> +MODULE_LICENSE("GPL");
>
> --
> 2.34.1
>
>
Bart
^ permalink raw reply
* Re: [RFC PATCH 4/4] firmware: arm_ffa: check pkvm initailised when initailise ffa driver
From: Yeoreum Yun @ 2026-04-20 9:25 UTC (permalink / raw)
To: Will Deacon
Cc: Marc Zyngier, linux-security-module, linux-kernel,
linux-integrity, linux-arm-kernel, kvmarm, paul, jmorris, serge,
zohar, roberto.sassu, dmitry.kasatkin, eric.snowberg, peterhuewe,
jarkko, jgg, sudeep.holla, oupton, joey.gouly, suzuki.poulose,
yuzenghui, catalin.marinas
In-Reply-To: <aeXp7WSqpXNytNPG@willie-the-truck>
Hi Will,
> On Sun, Apr 19, 2026 at 12:12:44PM +0100, Yeoreum Yun wrote:
> > Hi Marc,
> >
> > > On Sat, 18 Apr 2026 11:34:30 +0100,
> > > Yeoreum Yun <yeoreum.yun@arm.com> wrote:
> > > >
> > > > > > @@ -2035,6 +2037,16 @@ static int __init ffa_init(void)
> > > > > > u32 buf_sz;
> > > > > > size_t rxtx_bufsz = SZ_4K;
> > > > > >
> > > > > > + /*
> > > > > > + * When pKVM is enabled, the FF-A driver must be initialized
> > > > > > + * after pKVM initialization. Otherwise, pKVM cannot negotiate
> > > > > > + * the FF-A version or obtain RX/TX buffer information,
> > > > > > + * which leads to failures in FF-A calls.
> > > > > > + */
> > > > > > + if (IS_ENABLED(CONFIG_KVM) && is_protected_kvm_enabled() &&
> > > > > > + !is_kvm_arm_initialised())
> > > > > > + return -EPROBE_DEFER;
> > > > > > +
> > > > >
> > > > > That's still fundamentally wrong: pkvm is not ready until
> > > > > finalize_pkvm() has finished, and that's not indicated by
> > > > > is_kvm_arm_initialised().
> > > >
> > > > Thanks. I miss the TSC bit set in here.
> > >
> > > That's the least of the problems. None of the infrastructure is in
> > > place at this stage...
> > >
> > > > IMHO, I'd like to make an new state check function --
> > > > is_pkvm_arm_initialised() so that ff-a driver to know whether
> > > > pkvm is initialised.
> > >
> > > Doesn't sound great, TBH.
> > >
> > > > or any other suggestion?
> > >
> > > Instead of adding more esoteric predicates, I'd rather you build on an
> > > existing infrastructure. You have a dependency on KVM, use something
> > > that is designed to enforce dependencies. Device links spring to mind
> > > as something designed for that.
> > >
> > > Can you look into enabling this for KVM? If that's possible, then it
> > > should be easy enough to delay the actual KVM registration after pKVM
> > > is finalised.
> >
> > or what about some event notifier? Just like:
>
> This seems a bit over-engineered to me. Why don't you just split the
> FF-A initialisation into two steps: an early part which does the version
> negotiation and then a later part which can fit in with whatever
> dependencies you have on the TPM?
Sorry, I may have misunderstood your suggestion and
I might be in missing your point.
But, The issue here is that FFA_VERSION, FFA_RXTX_MAP, and
FFA_PARTITION_INFO_GET, which are invoked from ffa_init()
as part of early initialisation, must be trapped by pKVM.
In other words, even the early part of the initialization,
including version negotiation, needs to happen after pKVM
is initialized.
Because of this dependency, simply splitting the FF-A
initialization into two phases within the driver does not
seem sufficient, as it still requires knowing when pKVM
has been initialized.
Am I missing something?
--
Sincerely,
Yeoreum Yun
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: amlogic: t7: khadas-vim4: Enable Bluetooth
From: Ronald Claveau @ 2026-04-20 9:26 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <c9c3227f-2a46-47b5-963f-e784184f7f31@linaro.org>
On 4/20/26 10:47 AM, Neil Armstrong wrote:
>> Enable UART C on the Khadas VIM4 board and attach the BCM43438
>> compatible Bluetooth controller to it. The node configures the RTS/CTS
>> hardware flow control, the associated pinmux, the power supplies
>> (vddao_3v3
>> and vddao_1v8), the 32 kHz LPO clock shared with the wifi32k fixed
>> clock, and the GPIO lines used for host wakeup, device wakeup and
>> shutdown.
>>
>> Remove clocks and clock-names for UART A, as they are defined in DTSI.
>
> This should be a separate patch.
Thanks for your feedback.
I will then add the remove redundant clocks before that one.
--
Best regards,
Ronald
^ permalink raw reply
* [PATCH] ACPI: arm64: cpuidle: Tolerate platforms with no deep PSCI idle states
From: Breno Leitao @ 2026-04-20 9:27 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Len Brown, Huisong Li
Cc: Rafael J. Wysocki, linux-acpi, linux-arm-kernel, linux-kernel,
pjaroszynski, rmikey, kernel-team, stable, Breno Leitao
Commit cac173bea57d ("ACPI: processor: idle: Rework the handling of
acpi_processor_ffh_lpi_probe()") moved the acpi_processor_ffh_lpi_probe()
call from acpi_processor_setup_cpuidle_dev(), where its return value was
ignored, to acpi_processor_get_power_info(), where it is now treated as
a hard failure. As a result, platforms where psci_acpi_cpu_init_idle()
returned -ENODEV stopped registering any cpuidle states, forcing CPUs to
busy-poll when idle.
On NVIDIA Grace (aarch64) systems with PSCIv1.1, pr->power.count is 1
(only WFI, no deep PSCI states beyond it), so the previous
"count = pr->power.count - 1; if (count <= 0) return -ENODEV;" check
returned -ENODEV for all 72 CPUs and disabled cpuidle entirely.
The lpi_states count is already validated in acpi_processor_get_lpi_info(),
so the check here is redundant. Simplify the loop to iterate over
lpi_states[1..power.count). When only WFI is present, the loop body
simply does not execute and the function returns 0, which is the correct
outcome: there is nothing to validate for FFH and no error to report.
Suggested-by: Huisong Li <lihuisong@huawei.com>
Cc: stable@vger.kernel.org
Fixes: cac173bea57d ("ACPI: processor: idle: Rework the handling of acpi_processor_ffh_lpi_probe()")
Signed-off-by: Breno Leitao <leitao@debian.org>
---
drivers/acpi/arm64/cpuidle.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/acpi/arm64/cpuidle.c b/drivers/acpi/arm64/cpuidle.c
index 801f9c4501425..c68a5db8ebba8 100644
--- a/drivers/acpi/arm64/cpuidle.c
+++ b/drivers/acpi/arm64/cpuidle.c
@@ -16,7 +16,7 @@
static int psci_acpi_cpu_init_idle(unsigned int cpu)
{
- int i, count;
+ int i;
struct acpi_lpi_state *lpi;
struct acpi_processor *pr = per_cpu(processors, cpu);
@@ -30,14 +30,10 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu)
if (!psci_ops.cpu_suspend)
return -EOPNOTSUPP;
- count = pr->power.count - 1;
- if (count <= 0)
- return -ENODEV;
-
- for (i = 0; i < count; i++) {
+ for (i = 1; i < pr->power.count; i++) {
u32 state;
- lpi = &pr->power.lpi_states[i + 1];
+ lpi = &pr->power.lpi_states[i];
/*
* Only bits[31:0] represent a PSCI power_state while
* bits[63:32] must be 0x0 as per ARM ACPI FFH Specification
---
base-commit: 1c7cc4904160c6fc6377564140062d68a3dc93a0
change-id: 20260413-ffh-93f68b2f46a3
Best regards,
--
Breno Leitao <leitao@debian.org>
^ permalink raw reply related
* Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for parsing Root Port properties
From: mani @ 2026-04-20 9:35 UTC (permalink / raw)
To: Sherry Sun
Cc: Bjorn Helgaas, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Frank Li, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, bhelgaas@google.com, Hongxing Zhu,
l.stach@pengutronix.de, imx@lists.linux.dev,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <VI0PR04MB12114304913B6AACF6A206E10922F2@VI0PR04MB12114.eurprd04.prod.outlook.com>
On Mon, Apr 20, 2026 at 08:24:57AM +0000, Sherry Sun wrote:
[...]
> > Even if there are PERST# GPIOs from the host, connected to downstream
> > ports of a PCIe switch, they could be stored in the Root Port's (pci_host_port)
> > struct as a list of PERST#. This is what pcie-qcom driver does.
> >
> > It is too clumsy to handle PERST# individually for each device. We tried it
> > before with pwrctrl, but it always ended up biting us on who gets to control
> > the PERST#. We can't let pwrctrl handle PERST# for a switch port and host
> > controller driver handle it for RP. And we cannot let pwrctrl handle PERST# for
> > all ports, because, host controller drivers also need to control them for RC
> > initialization.
> >
> > That's why it was decided to handle PERST# for all ports in the host controller
> > drivers. So following that pattern, this helper could also be extended to parse
> > the PERST# from all ports defined in DT and store them in the same Root Port
> > struct.
> >
> > It should be trivial to implement this logic in the current helper. @Sherry:
> > Could you please implement this logic?
>
> Hi Mani, do you mean the similar logic in this patch?
> https://lore.kernel.org/all/20251216-pci-pwrctrl-rework-v2-1-745a563b9be6@oss.qualcomm.com/
> If yes, of cause I can do this for current helper functions in pci-host-common.c.
>
Yes!
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH 1/6] drm/connector: report IRQ_HPD events to drm_connector_oob_hotplug_event()
From: Dmitry Baryshkov @ 2026-04-20 9:50 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: dri-devel, linux-kernel, linux-usb, intel-gfx, intel-xe,
linux-amlogic, linux-arm-kernel, linux-arm-msm, freedreno,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Heikki Krogerus, Greg Kroah-Hartman, Andrzej Hajda,
Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Adrien Grassein, Jani Nikula, Rodrigo Vivi,
Joonas Lahtinen, Tvrtko Ursulin, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Rob Clark, Dmitry Baryshkov, Abhinav Kumar,
Jessica Zhang, Sean Paul, Marijn Suijten, Bjorn Andersson,
Konrad Dybcio, Pengyu Luo, Nikita Travkin, Yongxing Mou
In-Reply-To: <a2e60e74-a1be-469d-8f4d-ecce1f30b517@ideasonboard.com>
On Mon, Apr 20, 2026 at 07:50:46AM +0300, Tomi Valkeinen wrote:
> Hi,
>
> On 18/04/2026 01:32, Dmitry Baryshkov wrote:
> > On Thu, Apr 16, 2026 at 11:10:03AM +0300, Tomi Valkeinen wrote:
> > > Hi,
> > >
> > > On 16/04/2026 02:22, Dmitry Baryshkov wrote:
> > > > The DisplayPort standard defines a special kind of events called IRQ.
> > > > These events are used to notify DP Source about the events on the Sink
> > > > side. It is extremely important for DP MST handling, where the MST
> > > > events are reported through this IRQ.
> > > >
> > > > In case of the USB-C DP AltMode there is no actual HPD pulse, but the
> > > > events are ported through the bits in the AltMode VDOs.
> > > >
> > > > Extend the drm_connector_oob_hotplug_event() interface and report IRQ
> > > > events to the DisplayPort Sink drivers.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > > > ---
> > > > drivers/gpu/drm/drm_connector.c | 4 +++-
> > > > drivers/usb/typec/altmodes/displayport.c | 12 ++++++++----
> > > > include/drm/drm_connector.h | 3 ++-
> > > > 3 files changed, 13 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> > > > index 47dc53c4a738..5fdacbd84bd7 100644
> > > > --- a/drivers/gpu/drm/drm_connector.c
> > > > +++ b/drivers/gpu/drm/drm_connector.c
> > > > @@ -3510,6 +3510,7 @@ struct drm_connector *drm_connector_find_by_fwnode(struct fwnode_handle *fwnode)
> > > > * drm_connector_oob_hotplug_event - Report out-of-band hotplug event to connector
> > > > * @connector_fwnode: fwnode_handle to report the event on
> > > > * @status: hot plug detect logical state
> > > > + * @irq_hpd: HPD pulse detected
> > > > *
> > > > * On some hardware a hotplug event notification may come from outside the display
> > > > * driver / device. An example of this is some USB Type-C setups where the hardware
> > > > @@ -3520,7 +3521,8 @@ struct drm_connector *drm_connector_find_by_fwnode(struct fwnode_handle *fwnode)
> > > > * a drm_connector reference through calling drm_connector_find_by_fwnode().
> > > > */
> > > > void drm_connector_oob_hotplug_event(struct fwnode_handle *connector_fwnode,
> > > > - enum drm_connector_status status)
> > > > + enum drm_connector_status status,
> > > > + bool irq_hpd)
> > > I find the "IRQ HPD" naming always confusing, even if I'm somewhat familiar
> > > with DP, but if someone has mainly worked on HDMI, I'm sure it's even worse.
> > >
> > > Can we define this a bit more precisely? Is 'irq_hpd' only for displayport?
> > > If so, perhaps 'dp_irq_hpd' or 'displayport_irq_hpd'. I might even call it
> > > 'dp_hpd_pulse', but maybe that's not good as the spec talks about HPD pulse
> > > for both short and long ones (although in the kernel doc you just write "HPD
> > > pulse")... The kernel doc could be expanded a bit to make it clear what this
> > > flag indicates.
> >
> > I attempted to stay away from defining a DP-specific flag, keeping it
> > generic enough. HDMI is pretty close (IMO) to requiring separate flag in
>
> If it's not specifically the DP IRQ HPD, then we need to define what it
> means. I tried to think what it would mean with HDMI, but I didn't come up
> with anything.
I might be mistaken, but I had someting like HEAC HPD / EDID status
changes in mind (or HDCP-triggered HPD status changes). But here I
admit, I hadn't checked if it is actually applicable or not.
Anyway, for e.g. DVI or VGA that means nothing. But, my point really is
to abstain from defining someting as DP-only in the top-level API.
>
> > Linux. Likewise I'd rather not use "pulse". The DP AltMode defines a bit
> > in the VDO rather than a pulse.
> >
> > Anyway, if irq_hpd doesn't sound precise enough, what about "bool
> > extra_irq"? This would convey that this is the extra hpd-related IRQ,
> > but it would also be obvious that it's not related to the HPD pin
> > itself.
> We'd still need to define what exactly it means. I think it might be better
> to just define it as the DP IRQ HPD, as then the meaning is clear.
>
> Also, would an enum flags parameter be better than a bool parameter?
Maybe not enum, but u32 param. Then it can become:
@extra_status: additional type-specific information provided by the sink
without changing the HPD state
void drm_connector_oob_hotplug_event(..., u32 extra_status);
/* DP short HPD pulse or corresponding AltMode flag */
#define DRM_CONNECTOR_OOB_DP_IRQ_HPD BIT(0)
/* DP long HPD pulse, debounced XXX: do we need this? */
#define DRM_CONNECTOR_OOB_DP_REPLUG BIT(1)
For HDMI we might want to define:
/* HDMI 1.4b 8.5, HPD pulse */
#define DRM_CONNECTOR_OOB_HDMI_REPLUG BIT(0)
Or might not, 100ms is long enough for all debouncers.
For HDMI we potentially have another source of OOB events, CDC-messages
from CEC controller. I have not looked in the details of the HEAC 3.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v7 3/4] KVM: arm64: PMU: Introduce FIXED_COUNTERS_ONLY
From: Marc Zyngier @ 2026-04-20 9:51 UTC (permalink / raw)
To: Akihiko Odaki
Cc: Oliver Upton, Joey Gouly, Suzuki K Poulose, Zenghui Yu,
Catalin Marinas, Will Deacon, Kees Cook, Gustavo A. R. Silva,
Paolo Bonzini, Jonathan Corbet, Shuah Khan, linux-arm-kernel,
kvmarm, linux-kernel, linux-hardening, devel, kvm, linux-doc,
linux-kselftest
In-Reply-To: <06c6664c-7f0c-47b2-babf-ba2a541fd9f2@rsg.ci.i.u-tokyo.ac.jp>
On Mon, 20 Apr 2026 09:36:16 +0100,
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
>
> On 2026/04/20 2:19, Marc Zyngier wrote:
> > On Sat, 18 Apr 2026 09:14:25 +0100,
> > Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> wrote:
> >>
> >> On a heterogeneous arm64 system, KVM's PMU emulation is based on the
> >> features of a single host PMU instance. When a vCPU is migrated to a
> >> pCPU with an incompatible PMU, counters such as PMCCNTR_EL0 stop
> >> incrementing.
> >>
> >> Although this behavior is permitted by the architecture, Windows does
> >> not handle it gracefully and may crash with a division-by-zero error.
> >>
> >> The current workaround requires VMMs to pin vCPUs to a set of pCPUs
> >> that share a compatible PMU. This is difficult to implement correctly in
> >> QEMU/libvirt, where pinning occurs after vCPU initialization, and it
> >> also restricts the guest to a subset of available pCPUs.
> >>
> >> Introduce the KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY attribute to
> >> create a "fixed-counters-only" PMU. When set, KVM exposes a PMU that is
> >> compatible with all pCPUs but that does not support programmable
> >> event counters which may have different feature sets on different PMUs.
> >>
> >> This allows Windows guests to run reliably on heterogeneous systems
> >> without crashing, even without vCPU pinning, and enables VMMs to
> >> schedule vCPUs across all available pCPUs, making full use of the host
> >> hardware.
> >>
> >> Much like KVM_ARM_VCPU_PMU_V3_IRQ and other read-write attributes, this
> >> attribute provides a getter that facilitates kernel and userspace
> >> debugging/testing.
> >
> > OK, so that's the sales pitch. But how is it implemented? I would like
> > to be able to read a high-level description of the implementation
> > trade-offs.
>
> Implementation-wise it is very trivial. Essentially the following
> addition in kvm_arm_pmu_v3_get_attr() is the entire implementation:
> + case KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY:
> + if (test_bit(KVM_ARCH_FLAG_PMU_V3_FIXED_COUNTERS_ONLY,
> &vcpu->kvm->arch.flags))
> + return 0;
>
> Both its functionality and code complexity is trivial. So we can argue that:
> - the functionality is too trivial to be useful or
> - the interface/implementation complexity is so trivial that it does not
> incur maintenance burden
>
> In this case the selftest uses the getter so I was more inclined to
> have it, but adding one just for the selftest sounds too ad-hoc, so
> here I looked into other attributes to ensure that it was not
> introducing inconsistency with existing interfaces.
>
> As the result, I found there are other read-write attributes; in fact
> there are more read-write attributes than write-only ones.
You're completely missing the point. I'm referring to the whole of the
commit message, which is more of a marketing slide than a technical
description.
I really don't care about the getter at this stage, which while
pointless, does not make things more awful than they already are.
>
> >
> >>
> >> Signed-off-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
> >> ---
> >> Documentation/virt/kvm/devices/vcpu.rst | 29 ++++++
> >> arch/arm64/include/asm/kvm_host.h | 2 +
> >> arch/arm64/include/uapi/asm/kvm.h | 1 +
> >> arch/arm64/kvm/arm.c | 1 +
> >> arch/arm64/kvm/pmu-emul.c | 155 +++++++++++++++++++++++---------
> >> include/kvm/arm_pmu.h | 2 +
> >> 6 files changed, 147 insertions(+), 43 deletions(-)
> >>
> >> diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst
> >> index 60bf205cb373..e0aeb1897d77 100644
> >> --- a/Documentation/virt/kvm/devices/vcpu.rst
> >> +++ b/Documentation/virt/kvm/devices/vcpu.rst
> >> @@ -161,6 +161,35 @@ explicitly selected, or the number of counters is out of range for the
> >> selected PMU. Selecting a new PMU cancels the effect of setting this
> >> attribute.
> >> +1.6 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY
> >> +------------------------------------------------------
> >> +
> >> +:Parameters: no additional parameter in kvm_device_attr.addr
> >> +
> >> +:Returns:
> >> +
> >> + ======= =====================================================
> >> + -EBUSY Attempted to set after initializing PMUv3 or running
> >> + VCPU, or attempted to set for the first time after
> >> + setting an event filter
> >> + -ENXIO Attempted to get before setting
> >> + -ENODEV Attempted to set while PMUv3 not supported
> >> + ======= =====================================================
> >> +
> >> +If set, PMUv3 will be emulated without programmable event counters. The VCPU
> >> +will use any compatible hardware PMU. This attribute is particularly useful on
> >
> > Not quite "any PMU". It will use *the* PMU of the physical CPU,
> > irrespective of the implementation.
>
> I think:
>
> - this comment
> - one on the KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED note
> - one on kvm_pmu_create_perf_event()
> - and one on kvm_arm_pmu_v3_set_pmu_fixed_counters_only()
>
> All boil down into one question: will it support all possible CPUs, or
> will it support a subset? Let me answer here:
>
> This patch is written to support a subset instead of all possible
> CPUs. If a pCPU does not have a compatible PMU, the pCPU will not be
> supported and cause KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED.
This is not a thing. Either *all* the CPUs have a PMU that can be used
for KVM, or PMU support is not offered to guests. That's a hard line
in the sand. And the code already upholds this by checking the
sanitised PMUVer field.
>
> This patch does not enforce all possible CPUs are covered by the
> compatible PMUs. Theoretically speaking,
> kvm_arm_pmu_get_pmuver_limit() enables the PMU emulation when real
> PMUv3 hardware covers all possible CPUs *or* the relevant registers
> can be trapped with IMPDEF, so some pCPU may not have a compatible PMU
> and only provide the IMPDEF trapping.
How is that possible? Please describe the case where that can happen,
and I will make sure that such a system stops booting. The intent is
definitely that that:
- for early CPUs, we take the minimal capability of all CPUs
- for late CPUs, either they match at least the capability recorded by
early CPUs, or they don't boot.
> Practically, I don't think any sane configuration will ever have such
> a subset support, so we can explicitly enforce all possible CPUs are
> covered by the compatible PMUs if desired.
That's not just desired. This is a requirement. And it is already
enforced AFAICS.
>
> >
> >> +heterogeneous systems where different hardware PMUs cover different physical
> >> +CPUs. The compatibility of hardware PMUs can be checked with
> >> +KVM_ARM_VCPU_PMU_V3_SET_PMU. All VCPUs in a VM share this attribute. It isn't
> >> +possible to set it for the first time if a PMU event filter is already present.
> >
> > "for the first time" gives the impression that it will work if you try
> > again. I'd rather we say that "This feature is incompatible with the
> > existence of a PMU event filter".
>
> The following sequence will work:
> 1. Set KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY
> 2. Set KVM_ARM_VCPU_PMU_V3_FILTER
> 3. Set KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY
>
> This is to make the behavior conistent with KVM_ARM_VCPU_PMU_V3_SET_PMU.
I don't think this is correct. Filtering is completely at odds with
this patch, and I don't want to have to reason about the combination.
[...]
> >> + int i;
> >> +
> >> + for_each_set_bit(i, &mask, 32) {
> >> + pmc = kvm_vcpu_idx_to_pmc(vcpu, i);
> >> + if (!pmc->perf_event)
> >> + continue;
> >> +
> >> + cpu_pmu = to_arm_pmu(pmc->perf_event->pmu);
> >> + if (!cpumask_test_cpu(vcpu->cpu, &cpu_pmu->supported_cpus)) {
> >> + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu);
> >> + break;
> >> + }
> >> + }
> >> +}
> >> +
> >
> > Why do we need to inflict this on VMs that do not have the fixed
> > counter restriction?
>
> This function is to re-create the perf_event in case the current
> perf_event does not support the pCPU because e.g., the pCPU is a
> E-core while the perf_event only covers the P-cores.
That's not what I meant. This code is only here to support the
fixed-function feature. It makes no sense outside of it, because *we
don't support counter migration across implementations*.
So what's the purpose of this stuff for the normal KVM setup?
>
> >
> > And even then, all you have to reconfigure is the cycle counter. So
> > why the loop? All we want to find out is whether the cycle counter is
> > instantiated on the PMU that matches the current CPU.
>
> I just wanted to avoid hardcoding assumptions on the fixed
> counter(s). FEAT_PMUv3_ICNTR will be naturaly handled with a loop, for
> example.
Well, not that loop, since ICNTR is counter 32. So please let's stop
the nonsense and only add what is required?
[...]
> >> +
> >> clear_bit(KVM_ARCH_FLAG_PMU_V3_FIXED_COUNTERS_ONLY,
> >> &kvm->arch.flags);
> >
> > Why does this need to be cleared? I'd rather we make sure it is never
> > set the first place.
>
> KVM_ARM_VCPU_PMU_V3_SET_PMU and
> KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY can be set on the same
> VCPU. The last KVM_ARM_VCPU_PMU_V3_SET_PMU or
> KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY setting will be effective.
>
> A VMM may try set these attributes to check if the setting is
> supported. For example, the RFC QEMU patch first uses
> KVM_ARM_VCPU_PMU_V3_SET_PMU to find a compatible PMU that covers all
> pCPUs, and then falls back to
> KVM_ARM_VCPU_PMU_V3_FIXED_COUNTERS_ONLY. The order of such probing is
> up to the VMM.
KVM_ARM_VCPU_PMU_V3_SET_PMU is not a probing mechanism. You must probe
the PMUs by looking in /sys/bus/event_source/devices/, like kvmtool
does.
So there is no reason to support this stuff, and the two flags should
be made mutually exclusive.
[...]
> >>
> >
> > In conclusion, I find this patch to be rather messy. For a start, it
> > needs to be split in at least 5 patches:
> >
> > - at least two for the refactoring
> > - one for the PMU core changes
> > - one for the UAPI
> > - one for documentation
>
> That clarifies the expected granurarity of patches. The next version
> will be in that layout, perhaps with more patches if an additional
> change. Thanks for the guidance.
>
> >
> > I'd also like some clarification on how this is intended to work if we
> > enable FEAT_PMUv3_ICNTR, because the definition seems to be designed
> > to encompass all fixed-function counters, and I expect this to grow
> > over time.
>
> Indeed the UAPI was designed to encompass all fixed-function counters
> as suggested by Oliver.
>
> To support the UAPI, the implementation avoids hardcoding the
> assumption on the fixed counter(s). FEAT_PMUv3_INCTR will be naturaly
> supported once the common code is properly updated (i.e., the size of
> the event counter bitmask is grown the corresponding registers are
> wired up with a proper check of the feature.)
>
> I expect migration will be handled with the conventional register
> getters and setters, but please share if you have a concern.
At the very least I want to see some documentation explaining that.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH v3 6/8] arm64/module, sframe: Add sframe support for modules.
From: Jens Remus @ 2026-04-20 9:54 UTC (permalink / raw)
To: Dylan Hatch, Roman Gushchin, Weinan Liu, Will Deacon,
Josh Poimboeuf, Indu Bhagat, Peter Zijlstra, Steven Rostedt,
Catalin Marinas, Jiri Kosina, Indu Bhagat
Cc: Mark Rutland, Prasanna Kumar T S M, Puranjay Mohan, Song Liu,
joe.lawrence, linux-toolchains, linux-kernel, live-patching,
linux-arm-kernel, Heiko Carstens
In-Reply-To: <20260406185000.1378082-7-dylanbhatch@google.com>
On 4/6/2026 8:49 PM, Dylan Hatch wrote:
> Add sframe table to mod_arch_specific and support sframe PC lookups when
> an .sframe section can be found on incoming modules.
>
> Signed-off-by: Dylan Hatch <dylanbhatch@google.com>
> Signed-off-by: Weinan Liu <wnliu@google.com>
> diff --git a/kernel/unwind/sframe.c b/kernel/unwind/sframe.c
> +void sframe_module_init(struct module *mod, void *sframe, size_t sframe_size,
> + void *text, size_t text_size)
> +{
> + struct sframe_section sec;
> +
I think sec should better be explicitly zero-initialized, as it is done
in sframe_add_section() for user space. IIUC likewise is not needed in
init_sframe_table() for the kernel vmlinux, as static variables are
zero-initialized.
memset(&sec, 0, sizeof(sec));
> + sec.sec_type = SFRAME_KERNEL;
> + sec.sframe_start = (unsigned long)sframe;
> + sec.sframe_end = (unsigned long)sframe + sframe_size;
> + sec.text_start = (unsigned long)text;
> + sec.text_end = (unsigned long)text + text_size;
> +
> + if (WARN_ON(sframe_read_header(&sec)))
> + return;
> +
> + mod->arch.sframe_sec = sec;
> + mod->arch.sframe_init = true;
> +}
Regards,
Jens
--
Jens Remus
Linux on Z Development (D3303)
jremus@de.ibm.com / jremus@linux.ibm.com
IBM Deutschland Research & Development GmbH; Vorsitzender des Aufsichtsrats: Wolfgang Wendt; Geschäftsführung: David Faller; Sitz der Gesellschaft: Ehningen; Registergericht: Amtsgericht Stuttgart, HRB 243294
IBM Data Privacy Statement: https://www.ibm.com/privacy/
^ permalink raw reply
* Re: [PATCH v2 0/2] Add support for Amediatech X98Q (Amlogic S905W2)
From: Ferass El Hafidi @ 2026-04-20 9:56 UTC (permalink / raw)
To: linux-amlogic, christian.koever-draxl, robh, krzk+dt, conor+dt,
neil.armstrong, khilman
Cc: jbrunet, martin.blumenstingl, funderscore, devicetree,
linux-kernel, linux-arm-kernel, linux-amlogic,
christian.koever-draxl
In-Reply-To: <20260420061854.5421-1-christian.koever-draxl@student.uibk.ac.at>
Hi,
On Mon, 20 Apr 2026 06:18, christian.koever-draxl@student.uibk.ac.at wrote:
>From: Christian Stefan Kövér-Draxl <christian.koever-draxl@student.uibk.ac.at>
>
>Supported features:
>- 1GB/2GB RAM (via U-Boot memory fixup)
>- 10/100 Ethernet (Internal PHY)
>- eMMC and SD card storage
>- PWM-based CPU voltage regulation
>- UART (Serial console)
>
>Changes in v2:
>- Split dt-bindings and dts changes into separate patches.
>- Updated model string to match documented vendor prefix.
>- Put vddio_sd states array in a single line.
>- Added a clarifying comment for the unsupported Amlogic W150S1 Wi-Fi module.
>
>Notes:
>- The console uses uart_b at 921600 baud.
>- Verified memory via /proc/device-tree; U-Boot patches the node to around 2GB.
>- Tested on the 2GB RAM plus 16GB eMMC variant.
>
Sorry I was not clear, but the patches need to have a description.
checkpatch.pl should complain about this. Please use it to check that
your patches are in the correct format.
See the kernel docs about sending patches here:
https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
>Christian Stefan Kövér-Draxl (2):
> dt-bindings: arm: amlogic: add X98Q compatible
> arm64: dts: amlogic: add support for X98Q
>
> .../devicetree/bindings/arm/amlogic.yaml | 7 +
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../boot/dts/amlogic/meson-s4-s905w2-x98q.dts | 250 ++++++++++++++++++
> 3 files changed, 258 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4-s905w2-x98q.dts
>
>--
>2.53.0
--
Best regards,
Ferass
^ permalink raw reply
* Re: [PATCH 00/30] KVM: arm64: Add support for protected guest memory with pKVM
From: Will Deacon @ 2026-04-20 10:00 UTC (permalink / raw)
To: Pavan Kondeti
Cc: kvmarm, linux-arm-kernel, Marc Zyngier, Oliver Upton, Joey Gouly,
Suzuki K Poulose, Zenghui Yu, Catalin Marinas, Quentin Perret,
Fuad Tabba, Vincent Donnefort, Mostafa Saleh
In-Reply-To: <3f52367b-f927-4d4d-9df3-bcd8cd954d47@quicinc.com>
On Mon, Apr 20, 2026 at 01:32:03PM +0530, Pavan Kondeti wrote:
> Hi Will,
>
> On Mon, Jan 05, 2026 at 03:49:08PM +0000, Will Deacon wrote:
> > Hi folks,
> >
> > Although pKVM has been shipping in Android kernels for a while now,
> > protected guest (pVM) support has been somewhat languishing upstream.
> > This has partly been because we've been waiting for guest_memfd() but
> > also because it hasn't been clear how to expose pVMs to userspace (which
> > is necessary for testing) without getting everything in place beforehand.
> > This has led to frustration on both sides of the fence [1] and so this
> > patch series attempts to get things moving again by exposing pVM
> > features in an incremental fashion based on top of anonymous memory,
> > which is what we have been using in Android. The big difference between
> > this series and the Android implementation is the graceful handling of
> > host stage-2 faults arising from accesses made using kernel mappings.
> > The hope is that this will unblock pKVM upstreaming efforts while the
> > guest_memfd() work continues to evolve.
> >
> > Specifically, this patch series implements support for protected guest
> > memory with pKVM, where pages are unmapped from the host as they are
> > faulted into the guest and can be shared back from the guest using pKVM
> > hypercalls. Protected guests are created using a new machine type
> > identifier and can be booted to a shell using the kvmtool patches
> > available at [2], which finally means that we are able to test the pVM
> > logic in pKVM. Since this is an incremental step towards full isolation
> > from the host (for example, the CPU register state and DMA accesses are
> > not yet isolated), creating a pVM requires a developer Kconfig option to
> > be enabled in addition to booting with 'kvm-arm.mode=protected' and
> > results in a kernel taint.
> >
>
> Good to see Protected VM support in upstream w/ pKVM.
>
> We (Qualcomm) have been trying to resume Gunyah upstreaming [1] efforts
> for some time but the path to re-use guest_memfd is not straight forward as
> guest_memfd is tightly coupled with KVM. While the efforts to use it for
> pKVM is pending and refactoring to make it use outside KVM is not
> happening anytime soon, we plan to send Gunyah series similar to how
> this series is dealt with pages lent/donated to the Guest. Please let us
> know if you have any suggestions/comments for us.
The major problem I see with this is that the host/hyp interface for
handling stage-2 faults is internal to pKVM. The exception is injected
back into the host using a funky ESR encoding and the hypercall used
to forcefully reclaim the page is not ABI. I have no appetite for
standardising these mechanisms (the flexibility is one of pKVM's big
advantages) but I also do not want to complicate EL1 fault handling path
with hypervisor-specific crap that we have to maintain forever.
Will
^ permalink raw reply
* [PATCH V3] dmaengine: imx-sdma: Fix SPBA bus detection on multi-SPBA platforms
From: Shengjiu Wang @ 2026-04-20 10:08 UTC (permalink / raw)
To: vkoul, Frank.Li, s.hauer, kernel, festevam, dmaengine, imx,
linux-arm-kernel, linux-kernel
i.MX8M platforms have multiple SPBA buses under different AIPS buses.
The current code searches the entire device tree and returns the first
SPBA bus found, which may not be under the same AIPS bus as the SDMA
controller.
This breaks SDMA P2P transfers because the SDMA script needs to know
if peripherals are on SPBA or AIPS to configure watermark levels
correctly. Using the wrong SPBA bus causes DMA timeouts and transfer
failures.
Fix by searching for the SPBA bus under the SDMA's parent node (AIPS)
first, then falling back to a global search for backward compatibility.
Example device tree showing the issue:
aips1 {
spba1 { sai@...; }; /* Correct SPBA for sdma1 */
sdma1@...;
};
aips2 {
spba2 { uart@...; }; /* Wrong SPBA - found first by old code */
};
Fixes: 8391ecf465ec ("dmaengine: imx-sdma: Add device to device support")
Cc: stable@vger.kernel.org
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
changs in v3:
- add fallback to a global search for backward compatibility, which is
to address comments from sashiko.dev
- update commit subject and commit message
- add comments in code.
- add Cc stable tag
- Don't add Frank's RB on v2 as there are several other changes.
changes in v2:
- add fixes tag
- use __free(device_node) for auto release.
drivers/dma/imx-sdma.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 3d527883776b..592705af2319 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -2364,7 +2364,18 @@ static int sdma_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, ret,
"failed to register controller\n");
- spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
+ /*
+ * On i.MX8M platforms with multiple SPBA buses, we need to find
+ * the SPBA bus that's under the same AIPS bus as this SDMA controller.
+ * First check the SDMA's parent (AIPS bus) for a child SPBA bus.
+ * If not found, fall back to searching the entire device tree for
+ * backward compatibility with older platforms.
+ */
+ struct device_node *sdma_parent_np __free(device_node) = of_get_parent(np);
+
+ spba_bus = of_get_compatible_child(sdma_parent_np, "fsl,spba-bus");
+ if (!spba_bus)
+ spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
ret = of_address_to_resource(spba_bus, 0, &spba_res);
if (!ret) {
sdma->spba_start_addr = spba_res.start;
--
2.34.1
^ permalink raw reply related
* tpm: spi: do not call blocking ops when !TASK_RUNNING; during shutdown
From: Stefan Wahren @ 2026-04-20 10:25 UTC (permalink / raw)
To: Peter Huewe, Jarkko Sakkinen, Jason Gunthorpe
Cc: linux-arm-kernel, linux-integrity, kernel, Frank Li, Sascha Hauer,
imx@lists.linux.dev
Hi,
we use a custom i.MX93 board, which based on Phytec Phycore i.MX93 with
a TPM connected via SPI. If I enable CONFIG_DEBUG_ATOMIC_SLEEP=y in our
kernel config with mainline kernel 6.18.23 and reboot our board, I will
get the following warning:
[ 43.287416] do not call blocking ops when !TASK_RUNNING; state=1 set
at [<000000005a2107f3>] prepare_to_wait_event+0x54/0x14c
[ 43.299009] WARNING: CPU: 0 PID: 1 at kernel/sched/core.c:8857
__might_sleep+0x74/0x7c
[ 43.306920] Modules linked in: polyval_ce flexcan rtc_rv3028 can_dev
mse102x phy_can_transceiver fuse autofs4
[ 43.316838] CPU: 0 UID: 0 PID: 1 Comm: systemd-shutdow Not tainted
6.18.23-00002-g626a194342f0 #2 PREEMPT
[ 43.326471] Hardware name: chargebyte Charge SOM Evaluation Kit (DT)
[ 43.332807] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS
BTYPE=--)
[ 43.339757] pc : __might_sleep+0x74/0x7c
[ 43.343675] lr : __might_sleep+0x74/0x7c
[ 43.347592] sp : ffff800081aab720
[ 43.350894] x29: ffff800081aab720 x28: 0000000000000080 x27:
ffff000000235880
[ 43.358018] x26: ffff800081897000 x25: 0000000000000018 x24:
0000000000000000
[ 43.365142] x23: ffff800081aab907 x22: 0000000000000000 x21:
0000000000000080
[ 43.372266] x20: 000000000000010f x19: ffff80008131cd00 x18:
0000000000000001
[ 43.379390] x17: 0000000000000000 x16: 000000000017d600 x15:
ffff00003fda4680
[ 43.386514] x14: 0000000000017e01 x13: 0000000000000209 x12:
0000000000000000
[ 43.393638] x11: 00000000000000c0 x10: 0000000000000950 x9 :
ffff800081aab5a0
[ 43.400762] x8 : ffff0000000d89b0 x7 : ffff00003fda3f00 x6 :
000000013417d29a
[ 43.407886] x5 : 0000000000000000 x4 : 0000000000000002 x3 :
0000000000000010
[ 43.415010] x2 : 0000000000000000 x1 : 0000000000000000 x0 :
ffff0000000d8000
[ 43.422135] Call trace:
[ 43.424570] __might_sleep+0x74/0x7c (P)
[ 43.428487] mutex_lock+0x24/0x80
[ 43.431797] spi_bus_lock+0x20/0x50
[ 43.435281] tpm_tis_spi_transfer_full+0x70/0x2c4
[ 43.439979] tpm_tis_spi_read_bytes+0x3c/0x48
[ 43.444321] tpm_tis_status+0x58/0xf8
[ 43.447978] wait_for_tpm_stat_cond+0x30/0x90
[ 43.452329] wait_for_tpm_stat+0x1cc/0x2e0
[ 43.456419] tpm_tis_send_data+0xdc/0x334
[ 43.460423] tpm_tis_send_main+0x74/0x160
[ 43.464427] tpm_tis_send+0xd4/0x13c
[ 43.467998] tpm_transmit+0xc4/0x3c4
[ 43.471569] tpm_transmit_cmd+0x38/0xd4
[ 43.475399] tpm2_shutdown+0x6c/0xa4
[ 43.478970] tpm_class_shutdown+0x60/0x88
[ 43.482974] device_shutdown+0x130/0x25c
[ 43.486891] kernel_restart+0x44/0xa4
[ 43.490549] __do_sys_reboot+0x114/0x254
[ 43.494466] __arm64_sys_reboot+0x24/0x30
[ 43.498470] invoke_syscall+0x48/0x10c
[ 43.502214] el0_svc_common.constprop.0+0x40/0xe0
[ 43.506911] do_el0_svc+0x1c/0x28
[ 43.510222] el0_svc+0x34/0xec
[ 43.513273] el0t_64_sync_handler+0xa0/0xe4
[ 43.517441] el0t_64_sync+0x198/0x19c
Best regards
^ permalink raw reply
* Re: [RFC PATCH 1/4] security: ima: move ima_init into late_initcall_sync
From: Jonathan McDowell @ 2026-04-20 10:32 UTC (permalink / raw)
To: Yeoreum Yun
Cc: linux-security-module, linux-kernel, linux-integrity,
linux-arm-kernel, kvmarm, paul, jmorris, serge, zohar,
roberto.sassu, dmitry.kasatkin, eric.snowberg, peterhuewe, jarkko,
jgg, sudeep.holla, maz, oupton, joey.gouly, suzuki.poulose,
yuzenghui, catalin.marinas, will
In-Reply-To: <20260417175759.3191279-2-yeoreum.yun@arm.com>
On Fri, Apr 17, 2026 at 06:57:56PM +0100, Yeoreum Yun wrote:
>To generate the boot_aggregate log in the IMA subsystem with TPM PCR values,
>the TPM driver must be built as built-in and
>must be probed before the IMA subsystem is initialized.
>
>However, when the TPM device operates over the FF-A protocol using
>the CRB interface, probing fails and returns -EPROBE_DEFER if
>the tpm_crb_ffa device — an FF-A device that provides the communication
>interface to the tpm_crb driver — has not yet been probed.
>
>To ensure the TPM device operating over the FF-A protocol with
>the CRB interface is probed before IMA initialization,
>the following conditions must be met:
>
> 1. The corresponding ffa_device must be registered,
> which is done via ffa_init().
>
> 2. The tpm_crb_driver must successfully probe this device via
> tpm_crb_ffa_init().
>
> 3. The tpm_crb driver using CRB over FF-A can then
> be probed successfully. (See crb_acpi_add() and
> tpm_crb_ffa_init() for reference.)
>
>Unfortunately, ffa_init(), tpm_crb_ffa_init(), and crb_acpi_driver_init() are
>all registered with device_initcall, which means crb_acpi_driver_init() may
>be invoked before ffa_init() and tpm_crb_ffa_init() are completed.
>
>When this occurs, probing the TPM device is deferred.
>However, the deferred probe can happen after the IMA subsystem
>has already been initialized, since IMA initialization is performed
>during late_initcall, and deferred_probe_initcall() is performed
>at the same level.
>
>To resolve this, move ima_init() into late_inicall_sync level
>so that let IMA not miss TPM PCR value when generating boot_aggregate
>log though TPM device presents in the system.
>
>Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Awesome. This fixes the problems I saw with an SPI TPM on an NVIDIA
GB200 system and reported in
https://lore.kernel.org/linux-integrity/aYXEepLhUouN5f99@earth.li/
Reviewed-by: Jonathan McDowell <noodles@meta.com>
Tested-by: Jonathan McDowell <noodles@meta.com>
>---
> include/linux/lsm_hooks.h | 2 ++
> security/integrity/ima/ima_main.c | 2 +-
> security/lsm_init.c | 13 +++++++++++--
> 3 files changed, 14 insertions(+), 3 deletions(-)
>
>diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h
>index d48bf0ad26f4..88fe105b7f00 100644
>--- a/include/linux/lsm_hooks.h
>+++ b/include/linux/lsm_hooks.h
>@@ -166,6 +166,7 @@ enum lsm_order {
> * @initcall_fs: LSM callback for fs_initcall setup, optional
> * @initcall_device: LSM callback for device_initcall() setup, optional
> * @initcall_late: LSM callback for late_initcall() setup, optional
>+ * @initcall_late_sync: LSM callback for late_initcall_sync() setup, optional
> */
> struct lsm_info {
> const struct lsm_id *id;
>@@ -181,6 +182,7 @@ struct lsm_info {
> int (*initcall_fs)(void);
> int (*initcall_device)(void);
> int (*initcall_late)(void);
>+ int (*initcall_late_sync)(void);
> };
>
> #define DEFINE_LSM(lsm) \
>diff --git a/security/integrity/ima/ima_main.c b/security/integrity/ima/ima_main.c
>index 1d6229b156fb..ace280fa3212 100644
>--- a/security/integrity/ima/ima_main.c
>+++ b/security/integrity/ima/ima_main.c
>@@ -1320,5 +1320,5 @@ DEFINE_LSM(ima) = {
> .order = LSM_ORDER_LAST,
> .blobs = &ima_blob_sizes,
> /* Start IMA after the TPM is available */
>- .initcall_late = init_ima,
>+ .initcall_late_sync = init_ima,
> };
>diff --git a/security/lsm_init.c b/security/lsm_init.c
>index 573e2a7250c4..4e5c59beb82a 100644
>--- a/security/lsm_init.c
>+++ b/security/lsm_init.c
>@@ -547,13 +547,22 @@ device_initcall(security_initcall_device);
> * security_initcall_late - Run the LSM late initcalls
> */
> static int __init security_initcall_late(void)
>+{
>+ return lsm_initcall(late);
>+}
>+late_initcall(security_initcall_late);
>+
>+/**
>+ * security_initcall_late_sync - Run the LSM late initcalls sync
>+ */
>+static int __init security_initcall_late_sync(void)
> {
> int rc;
>
>- rc = lsm_initcall(late);
>+ rc = lsm_initcall(late_sync);
> lsm_pr_dbg("all enabled LSMs fully activated\n");
> call_blocking_lsm_notifier(LSM_STARTED_ALL, NULL);
>
> return rc;
> }
>-late_initcall(security_initcall_late);
>+late_initcall_sync(security_initcall_late_sync);
>--
>LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
>
>
J.
--
] https://www.earth.li/~noodles/ [] "Do I scare you?" "No." "Do you [
] PGP/GPG Key @ the.earth.li [] want me to?" -- Wayne's World. [
] via keyserver, web or email. [] [
] RSA: 4096/0x94FA372B2DA8B985 [] [
^ permalink raw reply
* Re: [RFC PATCH 4/4] firmware: arm_ffa: check pkvm initailised when initailise ffa driver
From: Will Deacon @ 2026-04-20 10:42 UTC (permalink / raw)
To: Yeoreum Yun
Cc: Marc Zyngier, linux-security-module, linux-kernel,
linux-integrity, linux-arm-kernel, kvmarm, paul, jmorris, serge,
zohar, roberto.sassu, dmitry.kasatkin, eric.snowberg, peterhuewe,
jarkko, jgg, sudeep.holla, oupton, joey.gouly, suzuki.poulose,
yuzenghui, catalin.marinas, sebastianene
In-Reply-To: <aeXxCe4hdizdQbFD@e129823.arm.com>
[+Seb for the pKVM FFA bits]
On Mon, Apr 20, 2026 at 10:25:29AM +0100, Yeoreum Yun wrote:
> > On Sun, Apr 19, 2026 at 12:12:44PM +0100, Yeoreum Yun wrote:
> > > > On Sat, 18 Apr 2026 11:34:30 +0100,
> > > > Yeoreum Yun <yeoreum.yun@arm.com> wrote:
> > > > >
> > > > > > > @@ -2035,6 +2037,16 @@ static int __init ffa_init(void)
> > > > > > > u32 buf_sz;
> > > > > > > size_t rxtx_bufsz = SZ_4K;
> > > > > > >
> > > > > > > + /*
> > > > > > > + * When pKVM is enabled, the FF-A driver must be initialized
> > > > > > > + * after pKVM initialization. Otherwise, pKVM cannot negotiate
> > > > > > > + * the FF-A version or obtain RX/TX buffer information,
> > > > > > > + * which leads to failures in FF-A calls.
> > > > > > > + */
> > > > > > > + if (IS_ENABLED(CONFIG_KVM) && is_protected_kvm_enabled() &&
> > > > > > > + !is_kvm_arm_initialised())
> > > > > > > + return -EPROBE_DEFER;
> > > > > > > +
> > > > > >
> > > > > > That's still fundamentally wrong: pkvm is not ready until
> > > > > > finalize_pkvm() has finished, and that's not indicated by
> > > > > > is_kvm_arm_initialised().
> > > > >
> > > > > Thanks. I miss the TSC bit set in here.
> > > >
> > > > That's the least of the problems. None of the infrastructure is in
> > > > place at this stage...
> > > >
> > > > > IMHO, I'd like to make an new state check function --
> > > > > is_pkvm_arm_initialised() so that ff-a driver to know whether
> > > > > pkvm is initialised.
> > > >
> > > > Doesn't sound great, TBH.
> > > >
> > > > > or any other suggestion?
> > > >
> > > > Instead of adding more esoteric predicates, I'd rather you build on an
> > > > existing infrastructure. You have a dependency on KVM, use something
> > > > that is designed to enforce dependencies. Device links spring to mind
> > > > as something designed for that.
> > > >
> > > > Can you look into enabling this for KVM? If that's possible, then it
> > > > should be easy enough to delay the actual KVM registration after pKVM
> > > > is finalised.
> > >
> > > or what about some event notifier? Just like:
> >
> > This seems a bit over-engineered to me. Why don't you just split the
> > FF-A initialisation into two steps: an early part which does the version
> > negotiation and then a later part which can fit in with whatever
> > dependencies you have on the TPM?
>
> Sorry, I may have misunderstood your suggestion and
> I might be in missing your point.
>
> But, The issue here is that FFA_VERSION, FFA_RXTX_MAP, and
> FFA_PARTITION_INFO_GET, which are invoked from ffa_init()
> as part of early initialisation, must be trapped by pKVM.
>
> In other words, even the early part of the initialization,
> including version negotiation, needs to happen after pKVM
> is initialized.
>
> Because of this dependency, simply splitting the FF-A
> initialization into two phases within the driver does not
> seem sufficient, as it still requires knowing when pKVM
> has been initialized.
>
> Am I missing something?
Ah sorry, I mixed up the ordering of 'module_init' vs 'rootfs_initcall'
and thought you wanted to probe the version earlier. But then I'm still
confused because, prior to 0e0546eabcd6 ("firmware: arm_ffa: Change
initcall level of ffa_init() to rootfs_initcall"), ffa_init() was a
'device_initcall' which is still called earlier than finalize_pkvm().
Will
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox