* Re: [PATCHv2 0/2] phy: miphy28lp: build and simplify allocation
From: Vinod Koul @ 2026-05-10 12:32 UTC (permalink / raw)
To: linux-phy, Rosen Penev
Cc: Neil Armstrong, Patrice Chotard, Kees Cook, Gustavo A. R. Silva,
linux-kernel, linux-arm-kernel, linux-hardening
In-Reply-To: <20260306222457.8400-1-rosenp@gmail.com>
On Fri, 06 Mar 2026 14:24:55 -0800, Rosen Penev wrote:
> First patch allows compilation on at least x86.
>
> Second uses a flexible array member to simplify allocation.
>
> v2: add first patch and fix second.
>
> Rosen Penev (2):
> phy: miphy28lp: add COMPILE_TEST
> phy: miphy28lp: kzalloc + kcalloc to single kzalloc
>
> [...]
Applied, thanks!
[1/2] phy: miphy28lp: add COMPILE_TEST
commit: cc68a1728abfcbde12d36015f244046ae74ddd44
[2/2] phy: miphy28lp: kzalloc + kcalloc to single kzalloc
commit: f3508a61c892c592e4e893a3681e568a5c671027
Best regards,
--
~Vinod
^ permalink raw reply
* Re: (subset) [PATCH RESEND v3 0/4] Add eMMC PHY support for Axiado AX3000 SoC
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: SriNavmani A, Prasad Bolisetty, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tzu-Hao Wei
Cc: linux-phy, devicetree, linux-arm-kernel, linux-kernel, openbmc
In-Reply-To: <20260504-axiado-ax3000-add-emmc-phy-driver-support-v3-0-3ab7eb45b0c5@axiado.com>
On Mon, 04 May 2026 09:38:31 +0800, Tzu-Hao Wei wrote:
> Axiado AX3000 SoC contains Arasan PHY which provides the interface to the
> HS200 eMMC controller.
>
> This series includes:
> 1. Add bindings for Axiado AX3000 eMMC PHY
> 2. Add Axiado AX3000 eMMC phy driver
> 3. Update MAINTAINERS for the new driver
> 4. Update Axiado AX3000 device tree
>
> [...]
Applied, thanks!
[1/4] dt-bindings: phy: axiado,ax3000-emmc-phy: add Axiado eMMC PHY
commit: 1a75ecefa4fbedefc1600e43445de4e1e7f03b55
[2/4] phy: axiado: add Axiado eMMC PHY driver
commit: 9e7dfa4bcd4e2c3541c4ee954ea5e66edab94d3f
[3/4] MAINTAINERS: Add Axiado AX3000 eMMC PHY driver
commit: 13ee293a904b7b7b0507aaa8c71f7be7e683800e
Best regards,
--
~Vinod
^ permalink raw reply
* Re: (subset) [PATCH v4 0/5] J722S SGMII support
From: Vinod Koul @ 2026-05-10 12:31 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Neil Armstrong,
Nora Schiffer
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Siddharth Vadapalli, Roger Quadros, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux
In-Reply-To: <cover.1775559102.git.nora.schiffer@ew.tq-group.com>
On Tue, 07 Apr 2026 13:42:32 +0200, Nora Schiffer wrote:
> The J722S CPSW and SERDES are very similar to the variants found on the
> AM64, but they additionally support SGMII. Introduce new compatible
> strings for the J722S to add this support to the drivers.
>
> This is a prerequisite for the Single-Pair Ethernet interface of the
> TQ-Systems MBa67xx baseboard for the TQMa67xx SoM, which will be
> submitted separately.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatible
commit: 059f1a4c9e3aa44d888c0e7cf4559403eece0438
[2/5] dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel compatible
commit: 567b3c62a7eb51db4cb562b416ec220132d524c9
[3/5] phy: ti: phy-j721e-wiz: add support for J722S SoC family
commit: 61849b7afb579630fc45dbeaf5449b42b33cc70e
[4/5] phy: ti: gmii-sel: add support for J722S SoC family
commit: d39cf00e7daea64889dda9abb0b7e6da04a69d04
Best regards,
--
~Vinod
^ permalink raw reply
* Re: [PATCH v2] phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870
From: Vinod Koul @ 2026-05-10 12:23 UTC (permalink / raw)
To: Łukasz Lebiedziński
Cc: neil.armstrong, krzk, alim.akhtar, andre.draszik, pritam.sutar,
kauschluss, johan, ivo.ivanov.ivanov1, linux-phy,
linux-arm-kernel, linux-samsung-soc, linux-kernel, stable,
Krzysztof Kozlowski
In-Reply-To: <20260406135627.234835-1-kernel@lvkasz.us>
On Mon, 06 Apr 2026 15:56:27 +0200, Łukasz Lebiedziński wrote:
> The existing PHYPARAM0 tuning values for Exynos7870 are incorrect,
> causing the USB 2.0 PHY to fail high-speed negotiation and fall back
> to full-speed (12Mbps) operation.
>
> Fix TXVREFTUNE (transmitter voltage reference) from 14 to 3,
> TXRESTUNE (transmitter impedance) from 3 to 2, and SQRXTUNE
> (squelch threshold) from 6 to 5. Also explicitly set
> TXPREEMPPULSETUNE to 0, which was previously missing from the
> tuning table despite being included in the register mask.
>
> [...]
Applied, thanks!
[1/1] phy: exynos5-usbdrd: fix USB 2.0 HS PHY tuning values for Exynos7870
commit: 5a759b120e31aa3ed914d98b51eb1755235250f2
Best regards,
--
~Vinod
^ permalink raw reply
* [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
From: Pramod Maurya @ 2026-05-10 12:01 UTC (permalink / raw)
To: jic23
Cc: pramod.nexgen, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michal Simek,
Lars-Peter Clausen, linux-iio, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260510083219.70224-1-pramod.nexgen@gmail.com>
Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.
The new binding covers the same hardware and compatible strings:
- xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
- xlnx,axi-xadc-1.00.a (AXI softmacro)
- xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
vendor-props.yaml meta-schema, which requires vendor-prefixed entries
in properties: to be type: boolean; xlnx,channels is a subnode (object)
so it belongs in patternProperties:
Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
(channel@a through channel@f) instead of decimal; correct range
is now "^channel@([0-9a-f]|10)$"
- Add allOf/if/then conditional to enforce xlnx,external-mux-channel
is required when xlnx,external-mux is "single" or "dual"
.../bindings/iio/adc/xilinx-xadc.txt | 141 ------------
.../bindings/iio/adc/xlnx,xadc.yaml | 205 ++++++++++++++++++
MAINTAINERS | 7 +
3 files changed, 212 insertions(+), 141 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
- - compatible: Should be one of
- * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
- configuration interface to interface to the XADC hardmacro.
- * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
- interface to the XADC hardmacro.
- * "xlnx,system-management-wiz-1.3": When using the
- Xilinx System Management Wizard fabric IP core to access the
- UltraScale and UltraScale+ System Monitor.
- - reg: Address and length of the register set for the device
- - interrupts: Interrupt for the XADC control interface.
- - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
- when using the axi-xadc or the axi-system-management-wizard this must be
- the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
- - xlnx,external-mux:
- * "none": No external multiplexer is used, this is the default
- if the property is omitted.
- * "single": External multiplexer mode is used with one
- multiplexer.
- * "dual": External multiplexer mode is used with two
- multiplexers for simultaneous sampling.
- - xlnx,external-mux-channel: Configures which pair of pins is used to
- sample data in external mux mode.
- Valid values for single external multiplexer mode are:
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Valid values for dual external multiplexer mode are:
- 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
- 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
- ...
- 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
- This property needs to be present if the device is configured for
- external multiplexer mode (either single or dual). If the device is
- not using external multiplexer mode the property is ignored.
- - xnlx,channels: List of external channels that are connected to the ADC
- Required properties:
- * #address-cells: Should be 1.
- * #size-cells: Should be 0.
-
- The child nodes of this node represent the external channels which are
- connected to the ADC. If the property is no present no external
- channels will be assumed to be connected.
-
- Each child node represents one channel and has the following
- properties:
- Required properties:
- * reg: Pair of pins the channel is connected to.
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Note each channel number should only be used at most
- once.
- Optional properties:
- * xlnx,bipolar: If set the channel is used in bipolar
- mode.
-
-
-Examples:
- xadc@f8007100 {
- compatible = "xlnx,zynq-xadc-1.00.a";
- reg = <0xf8007100 0x20>;
- interrupts = <0 7 4>;
- interrupt-parent = <&gic>;
- clocks = <&pcap_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- };
- channel@1 {
- reg = <1>;
- };
- channel@8 {
- reg = <8>;
- };
- };
- };
-
- xadc@43200000 {
- compatible = "xlnx,axi-xadc-1.00.a";
- reg = <0x43200000 0x1000>;
- interrupts = <0 53 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
-
- adc@80000000 {
- compatible = "xlnx,system-management-wiz-1.3";
- reg = <0x80000000 0x1000>;
- interrupts = <0 81 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..ab6f16109aeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+ The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+ (Dynamic Reconfiguration Port) interface for communication. Two different
+ frontends for the DRP interface are supported:
+
+ - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in
+ the SoC portion of the ZYNQ device.
+ - AXI softmacro: available on all Series 7 platforms as a softmacro
+ with an AXI interface (PG019).
+
+ The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+ FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+ via an AXI interface in the FPGA fabric.
+
+properties:
+ compatible:
+ enum:
+ - xlnx,zynq-xadc-1.00.a
+ - xlnx,axi-xadc-1.00.a
+ - xlnx,system-management-wiz-1.3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: |
+ When using the ZYNQ this must be the ZYNQ PCAP clock.
+ When using the axi-xadc or system-management-wiz this must be
+ the clock that provides the clock to the AXI bus interface.
+ maxItems: 1
+
+ xlnx,external-mux:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ Selects the external multiplexer mode.
+ enum:
+ - none
+ - single
+ - dual
+
+ xlnx,external-mux-channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Configures which pair of pins is used to sample data in external
+ multiplexer mode. This property is required when the device is
+ configured for external multiplexer mode.
+
+ Valid values for single external multiplexer mode:
+ 0: VP/VN
+ 1-16: VAUXP[0]/VAUXN[0] through VAUXP[15]/VAUXN[15]
+
+ Valid values for dual external multiplexer mode:
+ 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+ 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+ ...
+ 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+ minimum: 0
+ maximum: 16
+
+patternProperties:
+ "^xlnx,channels$":
+ type: object
+ description:
+ List of external channels connected to the ADC. If this property is
+ absent, no external channels are assumed to be connected.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^channel@([0-9a-f]|10)$":
+ type: object
+ description:
+ Represents an external channel connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ Pair of pins the channel is connected to.
+ 0: VP/VN
+ 1: VAUXP[0]/VAUXN[0]
+ 2: VAUXP[1]/VAUXN[1]
+ ...
+ 16: VAUXP[15]/VAUXN[15]
+ minimum: 0
+ maximum: 16
+
+ xlnx,bipolar:
+ $ref: /schemas/types.yaml#/definitions/flag
+ type: boolean
+ description:
+ If set, the channel is used in bipolar mode.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ required:
+ - '#address-cells'
+ - '#size-cells'
+
+ additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ xlnx,external-mux:
+ enum:
+ - single
+ - dual
+ required:
+ - xlnx,external-mux
+ then:
+ required:
+ - xlnx,external-mux-channel
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ /* ZYNQ hardmacro example */
+ adc@f8007100 {
+ compatible = "xlnx,zynq-xadc-1.00.a";
+ reg = <0xf8007100 0x20>;
+ interrupts = <0 7 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&pcap_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@8 {
+ reg = <8>;
+ };
+ };
+ };
+
+ - |
+ /* AXI softmacro example */
+ adc@43200000 {
+ compatible = "xlnx,axi-xadc-1.00.a";
+ reg = <0x43200000 0x1000>;
+ interrupts = <0 53 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
+
+ - |
+ /* UltraScale System Management Wizard example */
+ adc@80000000 {
+ compatible = "xlnx,system-management-wiz-1.3";
+ reg = <0x80000000 0x1000>;
+ interrupts = <0 81 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..9b107057ad8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29226,6 +29226,13 @@ F: Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
F: drivers/watchdog/of_xilinx_wdt.c
F: drivers/watchdog/xilinx_wwdt.c
+XILINX XADC DRIVER
+M: Lars-Peter Clausen <lars@metafoo.de>
+L: linux-iio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F: drivers/iio/adc/xilinx-xadc*
+
XILINX XDMA DRIVER
M: Lizhi Hou <lizhi.hou@amd.com>
M: Brian Xu <brian.xu@amd.com>
--
2.52.0
^ permalink raw reply related
* Re: [PATCH V2 RESEND 2/2] phy: mediatek: xsphy: add support to set disconnect threshold
From: Vinod Koul @ 2026-05-10 11:50 UTC (permalink / raw)
To: Chunfeng Yun
Cc: AngeloGioacchino Del Regno, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel
In-Reply-To: <20260413122836.4848-2-chunfeng.yun@mediatek.com>
On 13-04-26, 20:28, Chunfeng Yun wrote:
> Add a property to tune usb2 phy's disconnect threshold.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: change property name
> ---
> drivers/phy/mediatek/phy-mtk-xsphy.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c
> index c0ddb9273cc3..46345e4f4189 100644
> --- a/drivers/phy/mediatek/phy-mtk-xsphy.c
> +++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
> @@ -61,6 +61,7 @@
> #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
> #define P2A6_RG_BC11_SW_EN BIT(23)
> #define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
> +#define PA6_RG_U2_DISCTH GENMASK(7, 4)
>
> #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
> #define P2D_FORCE_IDDIG BIT(9)
> @@ -107,6 +108,7 @@ struct xsphy_instance {
> int eye_src;
> int eye_vrt;
> int eye_term;
> + int discth;
Please see
https://sashiko.dev/#/patchset/20260413122836.4848-1-chunfeng.yun%40mediatek.com
> };
>
> struct mtk_xsphy {
> @@ -256,9 +258,12 @@ static void phy_parse_property(struct mtk_xsphy *xsphy,
> &inst->eye_vrt);
> device_property_read_u32(dev, "mediatek,eye-term",
> &inst->eye_term);
> - dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
> + device_property_read_u32(dev, "mediatek,discth",
> + &inst->discth);
> + dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d, discth:%d\n",
> inst->efuse_intr, inst->eye_src,
> - inst->eye_vrt, inst->eye_term);
> + inst->eye_vrt, inst->eye_term,
> + inst->discth);
> break;
> case PHY_TYPE_USB3:
> device_property_read_u32(dev, "mediatek,efuse-intr",
> @@ -301,6 +306,9 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy,
> if (inst->eye_term)
> mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
> inst->eye_term);
> + if (inst->discth)
> + mtk_phy_update_field(pbase + XSP_USBPHYACR6, PA6_RG_U2_DISCTH,
> + inst->discth);
> }
>
> static void u3_phy_props_set(struct mtk_xsphy *xsphy,
> --
> 2.45.2
--
~Vinod
^ permalink raw reply
* Re: [PATCH v3 13/15] phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop()
From: Vinod Koul @ 2026-05-10 10:17 UTC (permalink / raw)
To: Brian Masney
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-kernel,
Chun-Kuang Hu, Philipp Zabel, Chunfeng Yun, Matthias Brugger,
AngeloGioacchino Del Regno, Neil Armstrong, dri-devel,
linux-mediatek, linux-arm-kernel, linux-phy
In-Reply-To: <20260505-clk-determine-rate-noop-v3-13-f3f829fbacdf@redhat.com>
On 05-05-26, 20:49, Brian Masney wrote:
> Drop the driver-specific empty determine_rate() function and use the new
> shared clk_determine_rate_noop() helper.
Acked-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* [PATCH v2 2/2] phy: rockchip: inno-hdmi: Remove deprecated way to configure TMDS rate
From: Jonas Karlman @ 2026-05-10 9:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: linux-phy, linux-rockchip, linux-arm-kernel, linux-kernel,
Jonas Karlman
In-Reply-To: <20260510095731.1222705-1-jonas@kwiboo.se>
The TMDS character rate of this PHY is configured using PHY bus width
in downstream vendor kernel and out-of-tree patches, however no in-tree
consumer of this PHY has ever called phy_set_bus_width() to change the
TMDS character rate as currently only 8-bit RGB output is supported by
the HDMI display driver.
The series "Split Generic PHY consumer and provider" clarifies that
phy_set_bus_width() is intended as a provider-only function.
Remove the deprecated unused fallback way to configure TMDS character
rate now that this HDMI PHY support using phy_configure() to configure
the TMDS character rate.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch, split from original patch
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 9cfe956fefe7..5e76a1ea9d9f 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -555,24 +555,10 @@ static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
unsigned long rate)
{
- int bus_width;
-
if (inno->hdmi_cfg.tmds_char_rate)
return inno->hdmi_cfg.tmds_char_rate;
- bus_width = phy_get_bus_width(inno->phy);
-
- switch (bus_width) {
- case 4:
- case 5:
- case 6:
- case 10:
- case 12:
- case 16:
- return (u64)rate * bus_width / 8;
- default:
- return rate;
- }
+ return rate;
}
static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id)
@@ -1437,7 +1423,6 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev)
phy_set_drvdata(inno->phy, inno);
phy_set_mode_ext(inno->phy, PHY_MODE_HDMI, PHY_HDMI_MODE_TMDS);
- phy_set_bus_width(inno->phy, 8);
if (inno->plat_data->ops->init) {
ret = inno->plat_data->ops->init(inno);
--
2.54.0
^ permalink raw reply related
* [PATCH v2 1/2] phy: rockchip: inno-hdmi: Add configure() and validate() ops
From: Jonas Karlman @ 2026-05-10 9:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: linux-phy, linux-rockchip, linux-arm-kernel, linux-kernel,
Jonas Karlman
In-Reply-To: <20260510095731.1222705-1-jonas@kwiboo.se>
The commit 10ed34d6eaaf ("phy: Add HDMI configuration options")
introduced a way for HDMI PHYs to be configured through the generic
phy_configure() function.
This driver derives the TMDS character rate from the pixel clock and the
PHY bus width setting. However, no in-tree consumer of this PHY has ever
called phy_set_bus_width() to change the TMDS character rate as only
8-bit RGB output is supported by the HDMI display driver.
Add configure() and validate() ops to allow consumers to configure the
TMDS character rate using phy_configure(). Fallback to the deprecated
way of using the PHY bus width to configure the TMDS character rate.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Add validate() ops to validate that the TMDS rate is supported
- Split out parts that remove the old workaround into a separate patch
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 47 ++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 1483907413fa..9cfe956fefe7 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
struct clk *phyclk;
unsigned long pixclock;
unsigned long tmdsclock;
+ struct phy_configure_opts_hdmi hdmi_cfg;
};
struct pre_pll_config {
@@ -554,7 +555,12 @@ static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
unsigned long rate)
{
- int bus_width = phy_get_bus_width(inno->phy);
+ int bus_width;
+
+ if (inno->hdmi_cfg.tmds_char_rate)
+ return inno->hdmi_cfg.tmds_char_rate;
+
+ bus_width = phy_get_bus_width(inno->phy);
switch (bus_width) {
case 4:
@@ -602,6 +608,42 @@ static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static int inno_hdmi_phy_validate(struct phy *phy, enum phy_mode mode,
+ int submode, union phy_configure_opts *opts)
+{
+ const struct pre_pll_config *cfg = pre_pll_cfg_table;
+ unsigned long tmdsclock;
+
+ if (!(mode == PHY_MODE_HDMI && submode == PHY_HDMI_MODE_TMDS))
+ return -EINVAL;
+
+ if (!opts->hdmi.tmds_char_rate || opts->hdmi.tmds_char_rate > 594000000)
+ return -EINVAL;
+
+ tmdsclock = opts->hdmi.tmds_char_rate;
+ for (; cfg->pixclock != 0; cfg++)
+ if (cfg->pixclock == tmdsclock && cfg->tmdsclock == tmdsclock)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int inno_hdmi_phy_configure(struct phy *phy,
+ union phy_configure_opts *opts)
+{
+ struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
+ int ret;
+
+ ret = inno_hdmi_phy_validate(phy, phy_get_mode(phy),
+ PHY_HDMI_MODE_TMDS, opts);
+ if (ret)
+ return ret;
+
+ inno->hdmi_cfg = opts->hdmi;
+
+ return 0;
+}
+
static int inno_hdmi_phy_power_on(struct phy *phy)
{
struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
@@ -670,6 +712,8 @@ static const struct phy_ops inno_hdmi_phy_ops = {
.owner = THIS_MODULE,
.power_on = inno_hdmi_phy_power_on,
.power_off = inno_hdmi_phy_power_off,
+ .configure = inno_hdmi_phy_configure,
+ .validate = inno_hdmi_phy_validate,
};
static const
@@ -1392,6 +1436,7 @@ static int inno_hdmi_phy_probe(struct platform_device *pdev)
}
phy_set_drvdata(inno->phy, inno);
+ phy_set_mode_ext(inno->phy, PHY_MODE_HDMI, PHY_HDMI_MODE_TMDS);
phy_set_bus_width(inno->phy, 8);
if (inno->plat_data->ops->init) {
--
2.54.0
^ permalink raw reply related
* [PATCH v2 0/2] phy: rockchip: inno-hdmi: Change TMDS rate handling to configure() ops
From: Jonas Karlman @ 2026-05-10 9:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner
Cc: linux-phy, linux-rockchip, linux-arm-kernel, linux-kernel,
Jonas Karlman
This series adds support for using phy_validate() and phy_configure()
with this HDMI PHY as an alternative to current in-tree unused way of
using PHY bus width to configure the TMDS character rate.
The only known users that calls phy_set_bus_width() on this PHY are my
out-of-tree HDMI 2.0 patches for Rockchip RK3228/RK3328, i.e. those
originating from LibreELEC (also carried by other distros), the
downstream vendor kernel uses a different implementation that also calls
phy_set_bus_width() on this PHY.
Patches that calls phy_validate() and phy_configure() on this PHY should
land on mailing lists any day now.
This series is part of a larger multi series effort to:
- phy: rockchip: inno-hdmi: Change TMDS rate handling to configure() ops
- drm/rockchip: dw_hdmi: Misc cleanup and propagate bus format
- drm: bridge: dw_hdmi: Misc enable/disable, CEC and EDID cleanup
- drm/bridge: dw-hdmi: Improve input/output bus format handling
- drm/bridge: dw-hdmi: Convert to a HDMI bridge and use of bridge connector
- drm/bridge: dw-hdmi: Add and use tmds_char_rate_valid() plat data ops
- drm/meson: hdmi: Misc cleanup and use CEC notifier helpers
- drm/rockchip: dw_hdmi: Enable YCbCr and Deep Color modes
Link to snapshot: https://github.com/Kwiboo/linux-rockchip/commits/next-20260508-rk-hdmi-v3/
Changes in v2:
- Split into two patches, one that adds new ops and a second that remove
the old and unused workaround
- Add validate() ops to validate that the TMDS rate is supported
Link to v1: https://lore.kernel.org/linux-phy/20260503172936.194003-1-jonas@kwiboo.se/
Jonas Karlman (2):
phy: rockchip: inno-hdmi: Add configure() and validate() ops
phy: rockchip: inno-hdmi: Remove deprecated way to configure TMDS rate
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 58 ++++++++++++++-----
1 file changed, 44 insertions(+), 14 deletions(-)
--
2.54.0
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
From: Rob Herring (Arm) @ 2026-05-10 9:43 UTC (permalink / raw)
To: Pramod Maurya
Cc: Krzysztof Kozlowski, linux-arm-kernel, jic23, linux-kernel,
David Lechner, Michal Simek, Andy Shevchenko, Conor Dooley,
Lars-Peter Clausen, devicetree, Nuno Sá, linux-iio
In-Reply-To: <20260510083219.70224-1-pramod.nexgen@gmail.com>
On Sun, 10 May 2026 04:32:13 -0400, Pramod Maurya wrote:
> Convert the Xilinx XADC and UltraScale System Monitor device tree binding
> from the legacy plain-text format to a YAML schema, enabling automated
> validation with dt-schema.
>
> The new binding covers the same hardware and compatible strings:
> - xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
> - xlnx,axi-xadc-1.00.a (AXI softmacro)
> - xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
>
> Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
> ---
> Changes in v3:
> - Move xlnx,channels from properties: to patternProperties: to satisfy
> vendor-props.yaml meta-schema, which requires vendor-prefixed entries
> in properties: to be type: boolean; xlnx,channels is a subnode (object)
> so it belongs in patternProperties:
>
> Changes in v2:
> - Fix patternProperties regex to use lowercase hex unit addresses
> (channel@a through channel@f) instead of decimal; correct range
> is now "^channel@([0-9a-f]|10)$"
> - Add allOf/if/then conditional to enforce xlnx,external-mux-channel
> is required when xlnx,external-mux is "single" or "dual"
>
> .../bindings/iio/adc/xilinx-xadc.txt | 141 ------------
> .../bindings/iio/adc/xlnx,xadc.yaml | 205 ++++++++++++++++++
> MAINTAINERS | 7 +
> 3 files changed, 212 insertions(+), 141 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
> create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml: patternProperties: '^xlnx,channels$' should not be valid under {'pattern': '^\\^[a-zA-Z0-9,\\-._#@]+\\$$'}
hint: Fixed strings belong in 'properties', not 'patternProperties'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260510083219.70224-1-pramod.nexgen@gmail.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH v4 2/5] nvmem: Add the Raspberry Pi OTP driver
From: Stefan Wahren @ 2026-05-10 9:37 UTC (permalink / raw)
To: Gregor Herburger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Eric Anholt,
Srinivas Kandagatla, Kees Cook, Gustavo A. R. Silva
Cc: devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
linux-hardening
In-Reply-To: <20260508-rpi-otp-driver-v4-2-cf8d725d8821@linutronix.de>
Am 08.05.26 um 16:42 schrieb Gregor Herburger:
> Raspberry Pis have OTP registers which can be accessed through the
> videocore firmware. Add a nvmem driver to support these OTP registers.
>
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
^ permalink raw reply
* Re: [PATCH v4 4/5] arm64: dts: broadcom: bcm2712: add raspberrypi,bcm2712-firmware compatible
From: Stefan Wahren @ 2026-05-10 9:29 UTC (permalink / raw)
To: Gregor Herburger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Eric Anholt,
Srinivas Kandagatla, Kees Cook, Gustavo A. R. Silva
Cc: devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
linux-hardening
In-Reply-To: <20260508-rpi-otp-driver-v4-4-cf8d725d8821@linutronix.de>
Am 08.05.26 um 16:42 schrieb Gregor Herburger:
> The Raspberry Pi 5 (BCM2712) firmware exposes additional features such
> as the additional OTP register region called 'private OTP'.
>
> Add the raspberrypi,bcm2712-firmware compatible to allow drivers to
> distinguish this hardware variant while keeping
> raspberrypi,bcm2835-firmware as a fallback for backward compatibility
> with existing drivers.
>
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
> ---
> arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> index b7a6bc34ae1a..4aa8ec7601b8 100644
> --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
> @@ -46,7 +46,9 @@ power_button: power-button {
>
> firmware {
> firmware: rpi-firmware {
> - compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
> + compatible = "raspberrypi,bcm2712-firmware",
> + "raspberrypi,bcm2835-firmware",
> + "simple-mfd";
>
> mboxes = <&mailbox>;
>
>
^ permalink raw reply
* Re: [PATCH v2] iio: adc: xilinx-ams: Replace spin_lock() and unlock() calls with guard(spinlock*)()
From: Andy Shevchenko @ 2026-05-10 9:24 UTC (permalink / raw)
To: Maxwell Doose
Cc: salih.erim, conall.ogriofa, jic23, michal.simek, David Lechner,
Nuno Sá, Andy Shevchenko, open list:XILINX AMS DRIVER,
moderated list:ARM/ZYNQ ARCHITECTURE, open list
In-Reply-To: <20260508124513.17752-1-m32285159@gmail.com>
On Fri, May 08, 2026 at 07:45:13AM -0500, Maxwell Doose wrote:
> Include linux/cleanup.h to take advantage of RAII macros.
>
> Replace spin_lock() and unlock() calls with their RAII macro
> counterparts, which modernizes the code and increases readability.
> Remove "flags" variables where spin_lock_irqsave() has been replaced
> with guard(spinlock_irqsave)().
Unneeded detail, everyone can see that in the guard()() implementation
for the spin locks. Otherwise, LGTM.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups
From: Cristian Ciocaltea @ 2026-05-10 8:55 UTC (permalink / raw)
To: Vinod Koul
Cc: Neil Armstrong, Heiko Stuebner, Algea Cao, Dmitry Baryshkov,
kernel, linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <agA1dFpheTaBfyUt@vaman>
Hi Vinod,
On 5/10/26 10:36 AM, Vinod Koul wrote:
> On 27-02-26, 22:48, Cristian Ciocaltea wrote:
>> This series provides a set of bug fixes and cleanups for the Rockchip
>> Samsung HDPTX PHY driver.
>>
>> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
>> calculation and synchronization issues. Specifically, it fixes edge
>> cases where the PHY PLL is pre-programmed by an external component (like
>> a bootloader) or when changing the color depth (bpc) while keeping the
>> modeline constant. Because the Common Clock Framework .set_rate()
>> callback might not be invoked if the pixel clock remains unchanged, this
>> previously led to out-of-sync states between CCF and the actual HDMI PHY
>> configuration.
>>
>> The second part focuses on code cleanups and modernizing the register
>> access. Now that dw_hdmi_qp driver has fully switched to using
>> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
>> and the restrict_rate_change flag logic. Finally, it refactors the
>> driver to consistently use standard bitfield macros.
>
> Sorry looks like I have missed to review this one.
> Can you please rebase on phy/fixes and send...
I've just verified and it applies cleanly on top of phy/fixes.
Do you still need a resend?
Regards,
Cristian
^ permalink raw reply
* [PATCH v3] dt-bindings: iio: adc: Convert xilinx-xadc bindings to YAML schema
From: Pramod Maurya @ 2026-05-10 8:32 UTC (permalink / raw)
To: jic23
Cc: pramod.nexgen, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Michal Simek,
Lars-Peter Clausen, linux-iio, devicetree, linux-arm-kernel,
linux-kernel
Convert the Xilinx XADC and UltraScale System Monitor device tree binding
from the legacy plain-text format to a YAML schema, enabling automated
validation with dt-schema.
The new binding covers the same hardware and compatible strings:
- xlnx,zynq-xadc-1.00.a (ZYNQ hardmacro)
- xlnx,axi-xadc-1.00.a (AXI softmacro)
- xlnx,system-management-wiz-1.3 (UltraScale System Management Wizard)
Signed-off-by: Pramod Maurya <pramod.nexgen@gmail.com>
---
Changes in v3:
- Move xlnx,channels from properties: to patternProperties: to satisfy
vendor-props.yaml meta-schema, which requires vendor-prefixed entries
in properties: to be type: boolean; xlnx,channels is a subnode (object)
so it belongs in patternProperties:
Changes in v2:
- Fix patternProperties regex to use lowercase hex unit addresses
(channel@a through channel@f) instead of decimal; correct range
is now "^channel@([0-9a-f]|10)$"
- Add allOf/if/then conditional to enforce xlnx,external-mux-channel
is required when xlnx,external-mux is "single" or "dual"
.../bindings/iio/adc/xilinx-xadc.txt | 141 ------------
.../bindings/iio/adc/xlnx,xadc.yaml | 205 ++++++++++++++++++
MAINTAINERS | 7 +
3 files changed, 212 insertions(+), 141 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
deleted file mode 100644
index f42e18078376..000000000000
--- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Xilinx XADC device driver
-
-This binding document describes the bindings for the Xilinx 7 Series XADC as well
-as the UltraScale/UltraScale+ System Monitor.
-
-The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
-The XADC has a DRP interface for communication. Currently two different
-frontends for the DRP interface exist. One that is only available on the ZYNQ
-family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
-on all series 7 platforms and is a softmacro with a AXI interface. This binding
-document describes the bindings for both of them since the bindings are very
-similar.
-
-The Xilinx System Monitor is an ADC that is found in the UltraScale and
-UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
-communication. Xilinx provides a standard IP core that can be used to access the
-System Monitor through an AXI interface in the FPGA fabric. This IP core is
-called the Xilinx System Management Wizard. This document describes the bindings
-for this IP.
-
-Required properties:
- - compatible: Should be one of
- * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
- configuration interface to interface to the XADC hardmacro.
- * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
- interface to the XADC hardmacro.
- * "xlnx,system-management-wiz-1.3": When using the
- Xilinx System Management Wizard fabric IP core to access the
- UltraScale and UltraScale+ System Monitor.
- - reg: Address and length of the register set for the device
- - interrupts: Interrupt for the XADC control interface.
- - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
- when using the axi-xadc or the axi-system-management-wizard this must be
- the clock that provides the clock to the AXI bus interface of the core.
-
-Optional properties:
- - xlnx,external-mux:
- * "none": No external multiplexer is used, this is the default
- if the property is omitted.
- * "single": External multiplexer mode is used with one
- multiplexer.
- * "dual": External multiplexer mode is used with two
- multiplexers for simultaneous sampling.
- - xlnx,external-mux-channel: Configures which pair of pins is used to
- sample data in external mux mode.
- Valid values for single external multiplexer mode are:
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Valid values for dual external multiplexer mode are:
- 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
- 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
- ...
- 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
-
- This property needs to be present if the device is configured for
- external multiplexer mode (either single or dual). If the device is
- not using external multiplexer mode the property is ignored.
- - xnlx,channels: List of external channels that are connected to the ADC
- Required properties:
- * #address-cells: Should be 1.
- * #size-cells: Should be 0.
-
- The child nodes of this node represent the external channels which are
- connected to the ADC. If the property is no present no external
- channels will be assumed to be connected.
-
- Each child node represents one channel and has the following
- properties:
- Required properties:
- * reg: Pair of pins the channel is connected to.
- 0: VP/VN
- 1: VAUXP[0]/VAUXN[0]
- 2: VAUXP[1]/VAUXN[1]
- ...
- 16: VAUXP[15]/VAUXN[15]
- Note each channel number should only be used at most
- once.
- Optional properties:
- * xlnx,bipolar: If set the channel is used in bipolar
- mode.
-
-
-Examples:
- xadc@f8007100 {
- compatible = "xlnx,zynq-xadc-1.00.a";
- reg = <0xf8007100 0x20>;
- interrupts = <0 7 4>;
- interrupt-parent = <&gic>;
- clocks = <&pcap_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- };
- channel@1 {
- reg = <1>;
- };
- channel@8 {
- reg = <8>;
- };
- };
- };
-
- xadc@43200000 {
- compatible = "xlnx,axi-xadc-1.00.a";
- reg = <0x43200000 0x1000>;
- interrupts = <0 53 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
-
- adc@80000000 {
- compatible = "xlnx,system-management-wiz-1.3";
- reg = <0x80000000 0x1000>;
- interrupts = <0 81 4>;
- interrupt-parent = <&gic>;
- clocks = <&fpga1_clk>;
-
- xlnx,channels {
- #address-cells = <1>;
- #size-cells = <0>;
- channel@0 {
- reg = <0>;
- xlnx,bipolar;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
new file mode 100644
index 000000000000..ab6f16109aeb
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/xlnx,xadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XADC and UltraScale System Monitor
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+
+description: |
+ The Xilinx XADC is an ADC found in the Series 7 FPGAs. It has a DRP
+ (Dynamic Reconfiguration Port) interface for communication. Two different
+ frontends for the DRP interface are supported:
+
+ - ZYNQ hardmacro: available only on the ZYNQ family as a hardmacro in
+ the SoC portion of the ZYNQ device.
+ - AXI softmacro: available on all Series 7 platforms as a softmacro
+ with an AXI interface (PG019).
+
+ The Xilinx System Monitor is an ADC found in UltraScale and UltraScale+
+ FPGAs. It is accessed through the Xilinx System Management Wizard IP core
+ via an AXI interface in the FPGA fabric.
+
+properties:
+ compatible:
+ enum:
+ - xlnx,zynq-xadc-1.00.a
+ - xlnx,axi-xadc-1.00.a
+ - xlnx,system-management-wiz-1.3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: |
+ When using the ZYNQ this must be the ZYNQ PCAP clock.
+ When using the axi-xadc or system-management-wiz this must be
+ the clock that provides the clock to the AXI bus interface.
+ maxItems: 1
+
+ xlnx,external-mux:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ Selects the external multiplexer mode.
+ enum:
+ - none
+ - single
+ - dual
+
+ xlnx,external-mux-channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Configures which pair of pins is used to sample data in external
+ multiplexer mode. This property is required when the device is
+ configured for external multiplexer mode.
+
+ Valid values for single external multiplexer mode:
+ 0: VP/VN
+ 1-16: VAUXP[0]/VAUXN[0] through VAUXP[15]/VAUXN[15]
+
+ Valid values for dual external multiplexer mode:
+ 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+ 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+ ...
+ 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+ minimum: 0
+ maximum: 16
+
+patternProperties:
+ "^xlnx,channels$":
+ type: object
+ description:
+ List of external channels connected to the ADC. If this property is
+ absent, no external channels are assumed to be connected.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^channel@([0-9a-f]|10)$":
+ type: object
+ description:
+ Represents an external channel connected to the ADC.
+
+ properties:
+ reg:
+ description: |
+ Pair of pins the channel is connected to.
+ 0: VP/VN
+ 1: VAUXP[0]/VAUXN[0]
+ 2: VAUXP[1]/VAUXN[1]
+ ...
+ 16: VAUXP[15]/VAUXN[15]
+ minimum: 0
+ maximum: 16
+
+ xlnx,bipolar:
+ $ref: /schemas/types.yaml#/definitions/flag
+ type: boolean
+ description:
+ If set, the channel is used in bipolar mode.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ required:
+ - '#address-cells'
+ - '#size-cells'
+
+ additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ xlnx,external-mux:
+ enum:
+ - single
+ - dual
+ required:
+ - xlnx,external-mux
+ then:
+ required:
+ - xlnx,external-mux-channel
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ /* ZYNQ hardmacro example */
+ adc@f8007100 {
+ compatible = "xlnx,zynq-xadc-1.00.a";
+ reg = <0xf8007100 0x20>;
+ interrupts = <0 7 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&pcap_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
+ channel@8 {
+ reg = <8>;
+ };
+ };
+ };
+
+ - |
+ /* AXI softmacro example */
+ adc@43200000 {
+ compatible = "xlnx,axi-xadc-1.00.a";
+ reg = <0x43200000 0x1000>;
+ interrupts = <0 53 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
+
+ - |
+ /* UltraScale System Management Wizard example */
+ adc@80000000 {
+ compatible = "xlnx,system-management-wiz-1.3";
+ reg = <0x80000000 0x1000>;
+ interrupts = <0 81 4>;
+ interrupt-parent = <&gic>;
+ clocks = <&fpga1_clk>;
+
+ xlnx,channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ xlnx,bipolar;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..9b107057ad8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -29226,6 +29226,13 @@ F: Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
F: drivers/watchdog/of_xilinx_wdt.c
F: drivers/watchdog/xilinx_wwdt.c
+XILINX XADC DRIVER
+M: Lars-Peter Clausen <lars@metafoo.de>
+L: linux-iio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/iio/adc/xlnx,xadc.yaml
+F: drivers/iio/adc/xilinx-xadc*
+
XILINX XDMA DRIVER
M: Lizhi Hou <lizhi.hou@amd.com>
M: Brian Xu <brian.xu@amd.com>
--
2.52.0
^ permalink raw reply related
* Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups
From: Vinod Koul @ 2026-05-10 7:36 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Neil Armstrong, Heiko Stuebner, Algea Cao, Dmitry Baryshkov,
kernel, linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com>
On 27-02-26, 22:48, Cristian Ciocaltea wrote:
> This series provides a set of bug fixes and cleanups for the Rockchip
> Samsung HDPTX PHY driver.
>
> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> calculation and synchronization issues. Specifically, it fixes edge
> cases where the PHY PLL is pre-programmed by an external component (like
> a bootloader) or when changing the color depth (bpc) while keeping the
> modeline constant. Because the Common Clock Framework .set_rate()
> callback might not be invoked if the pixel clock remains unchanged, this
> previously led to out-of-sync states between CCF and the actual HDMI PHY
> configuration.
>
> The second part focuses on code cleanups and modernizing the register
> access. Now that dw_hdmi_qp driver has fully switched to using
> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> and the restrict_rate_change flag logic. Finally, it refactors the
> driver to consistently use standard bitfield macros.
Sorry looks like I have missed to review this one.
Can you please rebase on phy/fixes and send...
Thanks
--
~Vinod
^ permalink raw reply
* Re: [PATCH v4 00/16] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups
From: Vinod Koul @ 2026-05-10 7:32 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Sebastian Reichel, Neil Armstrong, Frank Wang, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Andy Yan, Dmitry Baryshkov,
Yubing Zhang, Alexey Charkov, linux-phy, linux-arm-kernel,
linux-rockchip, linux-kernel, kernel, devicetree, William Wu
In-Reply-To: <6960660.0VBMTVartN@phil>
Hi Heiko,
On 03-05-26, 21:12, Heiko Stuebner wrote:
> Hi Vinod,
>
> Am Sonntag, 3. Mai 2026, 18:50:12 Mitteleuropäische Sommerzeit schrieb Vinod Koul:
> > Hi Sebastian,
> >
> > On 28-04-26, 18:13, Sebastian Reichel wrote:
> > > This series overhauls the Rockchip USBDP driver; apart from a
> > > a bunch of cleanups and small improvements the main goal is to
> > > get the driver ready for proper USB-C DP AltMode support.
> > >
> > > Once this series has landed, it unblocks enabling proper USB-C
> > > DP AltMode on the RK3588 and RK3576 platforms incl. runtime PM
> > > for the Synopsys DesignWare DisplayPort controller.
> > >
> > > Apart from this series, further changes are required on the
> > > DRM side. There are no compile-time dependencies between the
> > > DRM side and the PHY side, but the PHY side must be applied
> > > to avoid SErrors once runtime PM is added to the DisplayPort
> > > controller driver. Thus it would be really good to land this
> > > series in the next merge window.
> >
> > Looks like sasiko has flagged 8 high warning, can you please check them
>
> (1) as mentioned in a different patch thread, review should be happening
> on the lists. Tools regularly dump old results, so anyone looking at the
> mailinglist thread might now be able to follow along with what happened
> in 2 months or so.
>
> Also other robot tools can reply on the lists just fine.
It was not available in past, have enabled email reply as that is best
way for us. It should happen going forward
> (2) if 1. is so hugely impossible, please at least provide some reference
> to what you mean. Not everybody knows all the hype-tools-of-the-week and
> simply searching for that mysterious "sasiko" [0] did not provide any
> meaningful results for me, despite some amazon or youtube links for some
> non-kernel uses of that term ;-)
I am surprised that the hype of the week seems to missing for you or
Sebastian as Sashiko has been, IMO covered quite well. Instead of a random
web search I would have looked at lwn [1], [2].
> So a link should be present at least please.
Agree, I have sent to people who I thought might not be aware. I guess
better to not assume. In any case here are the comments, which maybe
valid or maybe not. As usual with tools we should use our discretion
https://sashiko.dev/#/patchset/20260428-rockchip-usbdp-cleanup-v4-0-7775671ece22%40collabora.com
[1]: https://lwn.net/Articles/1063292/
[2]: https://lwn.net/Articles/1063303/
--
~Vinod
^ permalink raw reply
* [PATCH] ARM: remove code to support non-sparse IRQs
From: Ethan Nelson-Moore @ 2026-05-10 5:31 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel; +Cc: Russell King, Ethan Nelson-Moore
Now that footbridge and riscpc have been converted to sparse IRQs, this
code is unused. Remove it.
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
---
This commit depends on my previous submissions "ARM: riscpc: convert to
sparse IRQs" and "ARM: footbridge: convert to sparse IRQs".
arch/arm/include/asm/irq.h | 5 -----
arch/arm/kernel/irq.c | 2 --
2 files changed, 7 deletions(-)
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 08589b88c3b9..449094a5044e 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -3,12 +3,7 @@
#define __ASM_ARM_IRQ_H
#define NR_IRQS_LEGACY 16
-
-#ifndef CONFIG_SPARSE_IRQ
-#include <mach/irqs.h>
-#else
#define NR_IRQS NR_IRQS_LEGACY
-#endif
#ifdef CONFIG_ARCH_FOOTBRIDGE
#define irq_canonicalize(i) (((i) == 2) ? 9 : i)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index e1993e28a9ec..7458c529a489 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -148,9 +148,7 @@ void __init init_IRQ(void)
uniphier_cache_init();
}
-#ifdef CONFIG_SPARSE_IRQ
int __init arch_probe_nr_irqs(void)
{
return irq_set_nr_irqs(machine_desc->nr_irqs ? : NR_IRQS);
}
-#endif
--
2.43.0
^ permalink raw reply related
* [PATCH] pmdomain: sunxi: support power domain flags for pck600
From: Yuanshen Cao @ 2026-05-10 5:25 UTC (permalink / raw)
To: Ulf Hansson, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland
Cc: linux-pm, linux-arm-kernel, linux-sunxi, linux-kernel,
Icenowy Zheng, Mikhail Kalashnikov, Yuanshen Cao
Hi everyone,
This patch refactors the sunxi pck600 power domain implementation to
support individual power domain flags.
While bringing up the PowerVR GPU on the A733 (Radxa Cubie A7Z), we
found that one of the GPU power domains must be configured as "always
on." While the Radxa BSP device tree leaves the GPU power domain nodes
commented out, the GPU driver code contains traces indicating an "always
on" requirement [1].
Currently, sunxi_pck600_desc only supports specifying pd_names. This
patch introduces sunxi_pck600_pd_desc, which stores both the name and
its associated flags. This also (more or less) aligns the implementation
with the existing sun50i PPU handling of always-on domains.
With this change, individual power domains can now be configured more
granularly. In particular, the GPU_CORE domain in sun60i_a733_pck600_pds
can now be explicitly marked with GENPD_FLAG_ALWAYS_ON.
The patch was tested on the Radxa Cubie A7Z, where the GPU now functions
as expected.
Thanks to Icenowy for her support and expertise on sunxi and PowerVR,
and thanks to Mikhail for identifying this exact cause of the GPU
bring-up issue.
[1] https://github.com/radxa/allwinner-bsp/blob/cubie-aiot-v1.4.6/modules/gpu/img-bxm/linux/rogue_km/services/system/rogue/rgx_sunxi/sunxi_platform.c#L62
Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com>
---
drivers/pmdomain/sunxi/sun55i-pck600.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/pmdomain/sunxi/sun55i-pck600.c b/drivers/pmdomain/sunxi/sun55i-pck600.c
index 1d47bbd35ced..8a37d11b65a2 100644
--- a/drivers/pmdomain/sunxi/sun55i-pck600.c
+++ b/drivers/pmdomain/sunxi/sun55i-pck600.c
@@ -41,8 +41,13 @@
#define PPU_REG_SIZE 0x1000
+struct sunxi_pck600_pd_desc {
+ const char *name;
+ unsigned int flags;
+};
+
struct sunxi_pck600_desc {
- const char * const *pd_names;
+ const struct sunxi_pck600_pd_desc *pd_descs;
unsigned int num_domains;
u32 logic_power_switch0_delay_offset;
u32 logic_power_switch1_delay_offset;
@@ -164,10 +169,12 @@ static int sunxi_pck600_probe(struct platform_device *pdev)
for (i = 0; i < desc->num_domains; i++) {
struct sunxi_pck600_pd *pd = &pck->pds[i];
+ const struct sunxi_pck600_pd_desc *pd_desc = &desc->pd_descs[i];
- pd->genpd.name = desc->pd_names[i];
+ pd->genpd.name = pd_desc->name;
pd->genpd.power_off = sunxi_pck600_power_off;
pd->genpd.power_on = sunxi_pck600_power_on;
+ pd->genpd.flags = pd_desc->flags;
pd->base = base + PPU_REG_SIZE * i;
sunxi_pck600_pd_setup(pd, desc);
@@ -195,13 +202,14 @@ static int sunxi_pck600_probe(struct platform_device *pdev)
return ret;
}
-static const char * const sun55i_a523_pck600_pd_names[] = {
- "VE", "GPU", "VI", "VO0", "VO1", "DE", "NAND", "PCIE"
+static const struct sunxi_pck600_pd_desc sun55i_a523_pck600_pds[] = {
+ { "VE", }, { "GPU", }, { "VI", }, { "VO0", }, { "VO1", },
+ { "DE", }, { "NAND", }, { "PCIE", },
};
static const struct sunxi_pck600_desc sun55i_a523_pck600_desc = {
- .pd_names = sun55i_a523_pck600_pd_names,
- .num_domains = ARRAY_SIZE(sun55i_a523_pck600_pd_names),
+ .pd_descs = sun55i_a523_pck600_pds,
+ .num_domains = ARRAY_SIZE(sun55i_a523_pck600_pds),
.logic_power_switch0_delay_offset = 0xc00,
.logic_power_switch1_delay_offset = 0xc04,
.off2on_delay_offset = 0xc10,
@@ -213,14 +221,15 @@ static const struct sunxi_pck600_desc sun55i_a523_pck600_desc = {
.has_rst_clk = true,
};
-static const char * const sun60i_a733_pck600_pd_names[] = {
- "VI", "DE_SYS", "VE_DEC", "VE_ENC", "NPU",
- "GPU_TOP", "GPU_CORE", "PCIE", "USB2", "VO", "VO1"
+static const struct sunxi_pck600_pd_desc sun60i_a733_pck600_pds[] = {
+ { "VI", }, { "DE_SYS", }, { "VE_DEC", }, { "VE_ENC", }, { "NPU", },
+ { "GPU_TOP", }, { "GPU_CORE", GENPD_FLAG_ALWAYS_ON },
+ { "PCIE", }, { "USB2", }, { "VO", }, { "VO1", },
};
static const struct sunxi_pck600_desc sun60i_a733_pck600_desc = {
- .pd_names = sun60i_a733_pck600_pd_names,
- .num_domains = ARRAY_SIZE(sun60i_a733_pck600_pd_names),
+ .pd_descs = sun60i_a733_pck600_pds,
+ .num_domains = ARRAY_SIZE(sun60i_a733_pck600_pds),
.logic_power_switch0_delay_offset = 0xc00,
.logic_power_switch1_delay_offset = 0xc04,
.off2on_delay_offset = 0xc10,
---
base-commit: 1bfaee9d3351b9b32a99766bbfb1f5baed60ddef
change-id: 20260510-pck600-a733-gpu-dcbfc0c7ce99
Best regards,
--
Yuanshen Cao <alex.caoys@gmail.com>
^ permalink raw reply related
* [PATCH] ARM: footbridge: convert to sparse IRQs
From: Ethan Nelson-Moore @ 2026-05-10 5:20 UTC (permalink / raw)
To: linux-arm-kernel, linux-input, linux-serial
Cc: Ethan Nelson-Moore, Russell King, Arnd Bergmann,
Greg Kroah-Hartman, Dmitry Torokhov, Jiri Slaby,
Russell King (Oracle), Linus Walleij, Kees Cook,
Nathan Chancellor, Sebastian Andrzej Siewior, Steven Rostedt,
Thomas Weissschuh, Peter Zijlstra
To improve future maintainability, change the interrupt handling for
mach-footbridge to use sparse IRQs.
Since the number of possible interrupts is already fixed and relatively
small, just make it use all legacy interrupts preallocated using the
.nr_irqs field in the machine descriptor, rather than actually
allocating domains on the fly.
Many files had to be adjusted to include <mach/irqs.h>
explicitly because it is no longer implicitly included with sparse
IRQs.
Description adapted from commit c78a41fc04f0 ("ARM: s3c24xx: convert
to sparse-irq").
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
---
This commit depends on my previous submission "ARM: <asm/floppy.h>: fix
build with sparse IRQs".
arch/arm/Kconfig | 2 +-
arch/arm/include/asm/irq.h | 4 +++-
| 2 +-
| 2 +-
| 2 +-
| 2 ++
| 4 +---
| 2 +-
| 2 +-
| 2 +-
| 2 ++
| 2 +-
drivers/char/nwbutton.c | 2 +-
drivers/input/serio/i8042-io.h | 6 +++---
drivers/tty/serial/21285.c | 2 +-
15 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 09b2767fee0f..1155c78bb6aa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -153,7 +153,7 @@ config ARM
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
- select SPARSE_IRQ if !ARCH_FOOTBRIDGE
+ select SPARSE_IRQ
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
select TIMER_OF if OF
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 26c1d2ced4ce..08589b88c3b9 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -10,7 +10,9 @@
#define NR_IRQS NR_IRQS_LEGACY
#endif
-#ifndef irq_canonicalize
+#ifdef CONFIG_ARCH_FOOTBRIDGE
+#define irq_canonicalize(i) (((i) == 2) ? 9 : i)
+#else
#define irq_canonicalize(i) (i)
#endif
--git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 2908c9ef3c9b..7d7ad1c1ef3f 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -12,7 +12,7 @@
#include <linux/irq.h>
#include <linux/sched_clock.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach/time.h>
--git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index e1b336624883..ffdecfadc9e2 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -17,7 +17,7 @@
#include <linux/io.h>
#include <linux/spinlock.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/mach/pci.h>
#include <asm/hardware/dec21285.h>
--git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c
index c3f280d08fa7..d2168660dd01 100644
--- a/arch/arm/mach-footbridge/ebsa285-pci.c
+++ b/arch/arm/mach-footbridge/ebsa285-pci.c
@@ -10,7 +10,7 @@
#include <linux/pci.h>
#include <linux/init.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
--git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 1cb7d674bc81..a820f7467468 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -10,6 +10,7 @@
#include <linux/slab.h>
#include <linux/leds.h>
+#include <mach/irqs.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>
@@ -117,6 +118,7 @@ MACHINE_START(EBSA285, "EBSA285")
.video_end = 0x000bffff,
.map_io = footbridge_map_io,
.init_early = footbridge_sched_clock,
+ .nr_irqs = FOOTBRIDGE_NR_IRQS,
.init_irq = footbridge_init_irq,
.init_time = footbridge_timer_init,
.restart = footbridge_restart,
--git a/arch/arm/mach-footbridge/include/mach/irqs.h b/arch/arm/mach-footbridge/include/mach/irqs.h
index a5f41846ab9c..10f1fbc24012 100644
--- a/arch/arm/mach-footbridge/include/mach/irqs.h
+++ b/arch/arm/mach-footbridge/include/mach/irqs.h
@@ -11,7 +11,7 @@
*/
#include <asm/mach-types.h>
-#define NR_IRQS 36
+#define FOOTBRIDGE_NR_IRQS 36
#define NR_DC21285_IRQS 16
#define _ISA_IRQ(x) (0 + (x))
@@ -93,5 +93,3 @@
#define I8042_KBD_IRQ IRQ_ISA_KEYBOARD
#define I8042_AUX_IRQ (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
#define IRQ_FLOPPYDISK IRQ_ISA_FLOPPY
-
-#define irq_canonicalize(_i) (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i)
--git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 842ddb4121ef..e4e71bdf1dc7 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -21,8 +21,8 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include <asm/hardware/dec21285.h>
-#include <asm/irq.h>
#include <asm/mach-types.h>
#include "common.h"
--git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index 723e3eae995d..07dee61b0b03 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -13,7 +13,7 @@
#include <linux/spinlock.h>
#include <linux/timex.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/mach/time.h>
#include "common.h"
--git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c
index 84caccddce44..1e7b0f5fb111 100644
--- a/arch/arm/mach-footbridge/isa.c
+++ b/arch/arm/mach-footbridge/isa.c
@@ -7,7 +7,7 @@
#include <linux/init.h>
#include <linux/serial_8250.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/hardware/dec21285.h>
#include "common.h"
--git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index c024eefd4978..ab17ba916d47 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -16,6 +16,7 @@
#include <linux/slab.h>
#include <linux/leds.h>
+#include <mach/irqs.h>
#include <asm/hardware/dec21285.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
@@ -766,6 +767,7 @@ MACHINE_START(NETWINDER, "Rebel-NetWinder")
.reserve_lp2 = 1,
.fixup = fixup_netwinder,
.map_io = footbridge_map_io,
+ .nr_irqs = FOOTBRIDGE_NR_IRQS,
.init_irq = footbridge_init_irq,
.init_time = isa_timer_init,
.restart = netwinder_restart,
--git a/arch/arm/mach-footbridge/netwinder-pci.c b/arch/arm/mach-footbridge/netwinder-pci.c
index e8304392074b..bfd5c0606c71 100644
--- a/arch/arm/mach-footbridge/netwinder-pci.c
+++ b/arch/arm/mach-footbridge/netwinder-pci.c
@@ -10,7 +10,7 @@
#include <linux/pci.h>
#include <linux/init.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
diff --git a/drivers/char/nwbutton.c b/drivers/char/nwbutton.c
index 92cee5717237..99819b184aac 100644
--- a/drivers/char/nwbutton.c
+++ b/drivers/char/nwbutton.c
@@ -18,7 +18,7 @@
#include <linux/init.h>
#include <linux/uaccess.h>
-#include <asm/irq.h>
+#include <mach/irqs.h>
#include <asm/mach-types.h>
#define __NWBUTTON_C /* Tell the header file who we are */
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index a8f4b2d70e59..cea72bd888af 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -15,9 +15,9 @@
* IRQs.
*/
-#if defined(__arm__)
-/* defined in include/asm-arm/arch-xxx/irqs.h */
-#include <asm/irq.h>
+#ifdef CONFIG_ARCH_FOOTBRIDGE
+/* defined in arch/arm/mach-footbridge/include/mach/irqs.h */
+#include <mach/irqs.h>
#elif defined(CONFIG_PPC)
extern int of_i8042_kbd_irq;
extern int of_i8042_aux_irq;
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index 4de0c975ebdc..f0c63875912e 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -15,11 +15,11 @@
#include <linux/serial.h>
#include <linux/io.h>
-#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/system_info.h>
#include <asm/hardware/dec21285.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#define BAUD_BASE (mem_fclk_21285/64)
--
2.43.0
^ permalink raw reply related
* Re: [PATCH] ARM: riscpc: convert to sparse IRQs
From: Ethan Nelson-Moore @ 2026-05-10 3:55 UTC (permalink / raw)
To: linux-arm-kernel, linux-input
Cc: Russell King, Dmitry Torokhov, Russell King (Oracle),
Arnd Bergmann, Linus Walleij, Kees Cook, Nathan Chancellor,
Steven Rostedt, Thomas Weissschuh, Sebastian Andrzej Siewior,
Peter Zijlstra
In-Reply-To: <20260510034652.349166-1-enelsonmoore@gmail.com>
On Sat, May 9, 2026 at 8:47 PM Ethan Nelson-Moore
<enelsonmoore@gmail.com> wrote:
> This commit depends on my previous submission "ARM: <asm/floppy.h>: fix
> build with sparse IRQs".
It also depends on these commits, which I neglected to mention,
because it modifies the same sections of code:
ARM: riscpc: use iomd.h everywhere and remove redundant ioc.h header
ARM: move Risc PC-specific <asm/hardware/iomd.h> header into mach-rpc
^ permalink raw reply
* [PATCH] ARM: riscpc: convert to sparse IRQs
From: Ethan Nelson-Moore @ 2026-05-10 3:46 UTC (permalink / raw)
To: linux-arm-kernel, linux-input
Cc: Ethan Nelson-Moore, Russell King, Dmitry Torokhov,
Russell King (Oracle), Arnd Bergmann, Linus Walleij, Kees Cook,
Nathan Chancellor, Steven Rostedt, Thomas Weissschuh,
Sebastian Andrzej Siewior, Peter Zijlstra
To improve future maintainability, change the interrupt handling for
mach-rpc to use sparse IRQs.
Since the number of possible interrupts is already fixed and relatively
small, just make it use all legacy interrupts preallocated using the
.nr_irqs field in the machine descriptor, rather than actually
allocating domains on the fly.
Several files had to be adjusted to include <mach/irqs.h>
explicitly because it is no longer implicitly included with sparse
IRQs.
Description adapted from commit c78a41fc04f0 ("ARM: s3c24xx: convert
to sparse-irq").
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
---
This commit depends on my previous submission "ARM: <asm/floppy.h>: fix
build with sparse IRQs".
arch/arm/Kconfig | 2 +-
arch/arm/mach-rpc/dma.c | 1 +
arch/arm/mach-rpc/ecard.c | 2 +-
arch/arm/mach-rpc/include/mach/irqs.h | 2 +-
arch/arm/mach-rpc/irq.c | 3 ++-
arch/arm/mach-rpc/riscpc.c | 2 ++
arch/arm/mach-rpc/time.c | 1 +
drivers/input/mouse/rpcmouse.c | 2 +-
drivers/input/serio/rpckbd.c | 1 +
9 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 71fc5dd4123f..09b2767fee0f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -153,7 +153,7 @@ config ARM
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
- select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
+ select SPARSE_IRQ if !ARCH_FOOTBRIDGE
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
select TIMER_OF if OF
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 717a81475670..238aa59612a8 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -17,6 +17,7 @@
#include <asm/fiq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include <linux/uaccess.h>
#include <asm/mach/dma.h>
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index 972465840548..27af35bd6a79 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -46,9 +46,9 @@
#include <asm/dma.h>
#include <asm/ecard.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/mmu_context.h>
-#include <asm/mach/irq.h>
#include <asm/tlbflush.h>
#include "ecard.h"
diff --git a/arch/arm/mach-rpc/include/mach/irqs.h b/arch/arm/mach-rpc/include/mach/irqs.h
index 0c3428fd9729..738a9457c473 100644
--- a/arch/arm/mach-rpc/include/mach/irqs.h
+++ b/arch/arm/mach-rpc/include/mach/irqs.h
@@ -39,4 +39,4 @@
*/
#define FIQ_START 64
-#define NR_IRQS 128
+#define RPC_NR_IRQS 128
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 649d81874c86..5e3414fc3657 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -5,6 +5,7 @@
#include <asm/mach/irq.h>
#include <mach/iomd.h>
+#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/fiq.h>
@@ -177,7 +178,7 @@ void __init rpc_init_irq(void)
set_handle_irq(iomd_handle_irq);
- for (irq = 0; irq < NR_IRQS; irq++) {
+ for (irq = 0; irq < RPC_NR_IRQS; irq++) {
clr = IRQ_NOREQUEST;
set = 0;
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index d068f5e4873d..bdad13226c6d 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -23,6 +23,7 @@
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <mach/iomd.h>
+#include <mach/irqs.h>
#include <asm/page.h>
#include <asm/domain.h>
#include <asm/setup.h>
@@ -219,6 +220,7 @@ MACHINE_START(RISCPC, "Acorn-RiscPC")
.reserve_lp0 = 1,
.reserve_lp1 = 1,
.map_io = rpc_map_io,
+ .nr_irqs = RPC_NR_IRQS,
.init_irq = rpc_init_irq,
.init_time = ioc_timer_init,
.restart = rpc_restart,
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index 566113f9774f..02f0fd58c7da 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -18,6 +18,7 @@
#include <mach/hardware.h>
#include <mach/iomd.h>
+#include <mach/irqs.h>
#include <asm/mach/time.h>
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 475c3ca22fd4..cead12069319 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -22,8 +22,8 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/irq.h>
#include <mach/iomd.h>
+#include <mach/irqs.h>
MODULE_AUTHOR("Vojtech Pavlik, Russell King");
MODULE_DESCRIPTION("Acorn RiscPC mouse driver");
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index e452ad07e2fa..7bcaed28c7a4 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -18,6 +18,7 @@
#include <mach/hardware.h>
#include <mach/iomd.h>
+#include <mach/irqs.h>
MODULE_AUTHOR("Vojtech Pavlik, Russell King");
MODULE_DESCRIPTION("Acorn RiscPC PS/2 keyboard controller driver");
--
2.43.0
^ permalink raw reply related
* [PATCH] ARM: <asm/floppy.h>: fix build with sparse IRQs
From: Ethan Nelson-Moore @ 2026-05-10 3:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: Russell King, Ethan Nelson-Moore, Ian Molton
If sparse IRQs are enabled, <mach/irqs.h> is no longer implicitly
included when building the floppy driver. This causes the build to fail
because IRQ_FLOPPYDISK, which is used by <asm/floppy.h>, is no longer
defined. Fix this issue by including <mach/irqs.h> from <asm/floppy.h>.
The only machines that select ARCH_MAY_HAVE_PC_FDC (and thus use
<asm/floppy.h>) are footbridge and rpc, both of which have
<mach/irqs.h>.
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
---
arch/arm/include/asm/floppy.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h
index e579f77162e9..4fdc3f633b1e 100644
--- a/arch/arm/include/asm/floppy.h
+++ b/arch/arm/include/asm/floppy.h
@@ -6,6 +6,9 @@
*
* Note that we don't touch FLOPPY_DMA nor FLOPPY_IRQ here
*/
+
+#include <mach/irqs.h> /* for IRQ_FLOPPYDISK */
+
#ifndef __ASM_ARM_FLOPPY_H
#define __ASM_ARM_FLOPPY_H
--
2.43.0
^ permalink raw reply related
* [PATCH] ARM: move Risc PC-specific <asm/hardware/iomd.h> header into mach-rpc
From: Ethan Nelson-Moore @ 2026-05-10 3:10 UTC (permalink / raw)
To: linux-arm-kernel, linux-i2c, linux-input, linux-fbdev
Cc: Russell King, Ethan Nelson-Moore, Andi Shyti, Dmitry Torokhov,
Helge Deller, Kees Cook
The <asm/hardware/iomd.h> header is specific to the IOMD chip used on
the Risc PC. Move it into mach-rpc to avoid polluting asm/hardware/
with machine-specific headers.
Also take the opportunity to remove a comment with the file path from
the header, which is bad style.
Signed-off-by: Ethan Nelson-Moore <enelsonmoore@gmail.com>
---
MAINTAINERS | 1 -
arch/arm/mach-rpc/dma.c | 2 +-
arch/arm/{include/asm/hardware => mach-rpc/include/mach}/iomd.h | 2 --
arch/arm/mach-rpc/irq.c | 2 +-
arch/arm/mach-rpc/riscpc.c | 2 +-
arch/arm/mach-rpc/time.c | 2 +-
drivers/i2c/busses/i2c-acorn.c | 2 +-
drivers/input/mouse/rpcmouse.c | 2 +-
drivers/input/serio/rpckbd.c | 2 +-
drivers/video/fbdev/acornfb.h | 2 +-
10 files changed, 8 insertions(+), 11 deletions(-)
rename arch/arm/{include/asm/hardware => mach-rpc/include/mach}/iomd.h (98%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 211cc683e25b..6a1da8903c04 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3398,7 +3398,6 @@ M: Russell King <linux@armlinux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
W: http://www.armlinux.org.uk/
-F: arch/arm/include/asm/hardware/iomd.h
F: arch/arm/mach-rpc/
F: drivers/net/ethernet/8390/etherh.c
F: drivers/net/ethernet/i825xx/ether1*
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c
index 50e0f97afd75..717a81475670 100644
--- a/arch/arm/mach-rpc/dma.c
+++ b/arch/arm/mach-rpc/dma.c
@@ -20,7 +20,7 @@
#include <linux/uaccess.h>
#include <asm/mach/dma.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
struct iomd_dma {
struct dma_struct dma;
diff --git a/arch/arm/include/asm/hardware/iomd.h b/arch/arm/mach-rpc/include/mach/iomd.h
similarity index 98%
rename from arch/arm/include/asm/hardware/iomd.h
rename to arch/arm/mach-rpc/include/mach/iomd.h
index e3f130345ebc..2a3f4a5f3fd9 100644
--- a/arch/arm/include/asm/hardware/iomd.h
+++ b/arch/arm/mach-rpc/include/mach/iomd.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * arch/arm/include/asm/hardware/iomd.h
- *
* Copyright (C) 1999 Russell King
*
* This file contains information out the IOMD ASIC used in the
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index e924c9b813ab..649d81874c86 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -4,7 +4,7 @@
#include <linux/io.h>
#include <asm/mach/irq.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
#include <asm/irq.h>
#include <asm/fiq.h>
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index f70fb9c4b0cb..d068f5e4873d 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -22,7 +22,7 @@
#include <asm/elf.h>
#include <asm/mach-types.h>
#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
#include <asm/page.h>
#include <asm/domain.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index ad93c4dfafcd..566113f9774f 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -17,7 +17,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
#include <asm/mach/time.h>
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index 99b6b1c3fd9e..703b4a42f466 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -13,7 +13,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
#define FORCE_ONES 0xdc
#define SCL 0x02
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 6774029e0a1a..475c3ca22fd4 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -23,7 +23,7 @@
#include <mach/hardware.h>
#include <asm/irq.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
MODULE_AUTHOR("Vojtech Pavlik, Russell King");
MODULE_DESCRIPTION("Acorn RiscPC mouse driver");
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c
index 4d817850ba3b..e452ad07e2fa 100644
--- a/drivers/input/serio/rpckbd.c
+++ b/drivers/input/serio/rpckbd.c
@@ -17,7 +17,7 @@
#include <linux/slab.h>
#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
MODULE_AUTHOR("Vojtech Pavlik, Russell King");
MODULE_DESCRIPTION("Acorn RiscPC PS/2 keyboard controller driver");
diff --git a/drivers/video/fbdev/acornfb.h b/drivers/video/fbdev/acornfb.h
index f8df4ecb4fd7..e65388587f80 100644
--- a/drivers/video/fbdev/acornfb.h
+++ b/drivers/video/fbdev/acornfb.h
@@ -7,7 +7,7 @@
* Frame buffer code for Acorn platforms
*/
#if defined(HAS_VIDC20)
-#include <asm/hardware/iomd.h>
+#include <mach/iomd.h>
#define VIDC_PALETTE_SIZE 256
#define VIDC_NAME "VIDC20"
#endif
--
2.43.0
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