* [PATCH net-next v3 2/6] net: phy: Add Airoha phy library for shared code
From: Louis-Alexis Eyraud @ 2026-05-12 4:33 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com>
In preparation of Airoha AN8801R PHY support, split out the interface
functions that will be common between the already present air_en8811h
driver and the new one, and put them into a new library named
air_phy_lib.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_en8811h.c | 13 ++-----------
drivers/net/phy/air_phy_lib.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 16 ++++++++++++++++
5 files changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index b5ee338b620d..b6b1cde7e51f 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,10 +92,16 @@ config AS21XXX_PHY
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ select AIR_NET_PHYLIB
select PHY_COMMON_PROPS
help
Currently supports the Airoha EN8811H PHY.
+config AIR_NET_PHYLIB
+ tristate
+ help
+ Airoha Ethernet PHY common library
+
config AMD_PHY
tristate "AMD and Altima PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 05e4878af27a..7cf1fa9e12cb 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,6 +30,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o
obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 29ae73e65caa..be7c3426182a 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -21,6 +21,8 @@
#include <linux/wordpart.h>
#include <linux/unaligned.h>
+#include "air_phy_lib.h"
+
#define EN8811H_PHY_ID 0x03a2a411
#define AN8811HB_PHY_ID 0xc0ff04a0
@@ -40,7 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_EXT_PAGE_ACCESS 0x1f
#define AIR_PHY_PAGE_STANDARD 0x0000
#define AIR_PHY_PAGE_EXTENDED_4 0x0004
@@ -244,16 +245,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int air_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-}
-
-static int air_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-}
-
static int __air_buckpbus_reg_write(struct phy_device *phydev,
u32 pbus_address, u32 pbus_data)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
new file mode 100644
index 000000000000..8ef5af4becf0
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Airoha Ethernet PHY common library
+ *
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#include "air_phy_lib.h"
+
+#define AIR_EXT_PAGE_ACCESS 0x1f
+
+int air_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(air_phy_read_page);
+
+int air_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(air_phy_write_page);
+
+MODULE_DESCRIPTION("Airoha PHY Library");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Louis-Alexis Eyraud");
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
new file mode 100644
index 000000000000..79367e8e5907
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef __AIR_PHY_LIB_H
+#define __AIR_PHY_LIB_H
+
+#include <linux/phy.h>
+
+int air_phy_read_page(struct phy_device *phydev);
+int air_phy_write_page(struct phy_device *phydev, int page);
+
+#endif /* __AIR_PHY_LIB_H */
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v3 4/6] net: phy: Rename Airoha common BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-12 4:33 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com>
Rename the BuckPBus register accessors functions present in air_phy_lib
and their calls in air_en8811h driver, so all exported functions start
with the same prefix.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 110 +++++++++++++++++++++---------------------
drivers/net/phy/air_phy_lib.c | 18 +++----
drivers/net/phy/air_phy_lib.h | 12 ++---
3 files changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 2498bd3f7993..a42898ae4135 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -287,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
@@ -313,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
@@ -346,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
@@ -372,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -414,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -433,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -460,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -755,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
@@ -767,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
@@ -777,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
@@ -788,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
@@ -854,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
@@ -866,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
@@ -876,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
@@ -887,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
@@ -998,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1039,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1061,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
@@ -1074,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
@@ -1110,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
@@ -1264,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index 687c59197b16..1212dd0a37b7 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -136,8 +136,8 @@ static int __air_buckpbus_reg_modify(struct phy_device *phydev,
return 0;
}
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data)
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
{
int saved_page;
int ret = 0;
@@ -153,10 +153,10 @@ int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data)
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
{
int saved_page;
int ret = 0;
@@ -173,10 +173,10 @@ int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set)
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
{
int saved_page;
int ret = 0;
@@ -193,7 +193,7 @@ int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
int air_phy_read_page(struct phy_device *phydev)
{
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index b637f3e0f2d5..a2f8b3725761 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -27,12 +27,12 @@
#define AIR_BPBUS_RD_DATA_HIGH 0x17
#define AIR_BPBUS_RD_DATA_LOW 0x18
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set);
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data);
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v3 6/6] net: phy: air_an8801: ensure maximum available speed link use
From: Louis-Alexis Eyraud @ 2026-05-12 4:33 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com>
To ensure that the Airoha AN8801R PHY uses the maximum available link
speed, an additional register write is needed to configure the function
mode for either 1G or 100M/10M operation after link detection.
So, in air_an8801 driver, implement a custom read_status callback, that
after genphy_read_status determines the link speed, sets the bit 0 of
the link mode register (REG_LINK_MODE) if the detected speed is 1Gbps,
or unsets it otherwise.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_an8801.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
index a0f164cbf92b..af46951b1a33 100644
--- a/drivers/net/phy/air_an8801.c
+++ b/drivers/net/phy/air_an8801.c
@@ -964,6 +964,36 @@ static int an8801r_config_init(struct phy_device *phydev)
return 0;
}
+static int an8801r_read_status(struct phy_device *phydev)
+{
+ int prev_speed, ret;
+ u32 val;
+
+ prev_speed = phydev->speed;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (phydev->link && prev_speed != phydev->speed) {
+ /* Ensure that PHY switches to 1G speed when available,
+ * by configuring the function mode for either 1G or 100M/10M
+ * operation.
+ * Therefore, set the link mode register, after read_status
+ * determines the link speed.
+ */
+ val = phydev->speed == SPEED_1000 ?
+ AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+ return an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LINK_MODE,
+ AN8801_BPBUS_LINK_MODE_1000,
+ val);
+ }
+
+ return 0;
+}
+
static int an8801r_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -1061,6 +1091,7 @@ static struct phy_driver airoha_driver[] = {
.suspend = an8801r_suspend,
.resume = an8801r_resume,
.config_aneg = genphy_config_aneg,
+ .read_status = an8801r_read_status,
.config_intr = an8801r_config_intr,
.handle_interrupt = an8801r_handle_interrupt,
.set_wol = an8801r_set_wol,
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v3 0/6] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-12 4:33 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.
The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
- Energy Efficient Ethernet (802.3az)
- Full Duplex Control Flow (802.3x)
- auto-negotiation
- crossover detect and autocorrection,
- Wake-on-LAN with Magic Packet
- Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.
The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.
Since v2, the series also adds the air_phy_lib library, which goal is to
share common code between air_en8811h and air_an8801 drivers, and its use
in them. The first shared functions are the existing BuckPbus register
accessors and air_phy_read/write_page functions coming from air_en8811h
driver.
The series is based on net-next kernel tree (sha1: 63751099502d) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.
[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Changes in v3:
- Rebased on net-next (7e0cccae6b45)
- Updated patch 1 to describe the function-enumator property for the
LEDs and its possible values
- Modified patch 2 to add missing includes in air_phy_lib source and
header files
- Split patch 3 in two so that the api call renames in air_en8811h
driver is done in a separate patch
- Simplified return code handling in several functions
- Fixed return code handling in several functions detected by AI
peer-reviews (netdev-ai or sashiko)
- Added additional interrupt enabled check before enabling/disabling
link changed interrupt in an8801r_suspend/resume callbacks
- Fixed register mask for GPIO LED selection register in
an8801r_led_init function
- Fixed potential uninitialized variable in an8801r_led_polarity_set
function
- Fixed LED blink register settings in an8801r_led_blink_set function
- Split an8801r_read_status function implementation in a separate patch
as requested and add comment to describe why the link mode register
needed to be modified after reading the link speed.
- Link to v2: https://lore.kernel.org/r/20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com
Changes in v2:
- Rebased on net-next (d1e59a4697371)
- Fixed dt-bindings to remove the leds property from the required ones and
add wakeup-source as valid property
- Added new reviewed-by trailer for dt_bindings
- Added new patches (2 and 3) to create air_phy_lib, to share common code
between air_en8811h and air_an8801 drivers and use it in air_en8811h.
- Remove custom BuckPBus register accessor functions and definitions from
air_an8801 and use the ones from air_phy_lib. It also fixes a build
issue on v1 due to an uninitialized variable used in
__air_buckpbus_reg_read, that is now removed from driver code
- Added air_an8801_probe function to allocate the newly added private
data structure and detect if the PHY is wakeup capable and the interrupt
can be registered as a wakeup IRQ, and perform the needed actions
- Added an8801r_suspend and an8801r_resume functions to perform specific
actions when WoL is enabled (reset its status, enable/disable the Link
Changed interrupt) and call the genphy_suspend/resume functions if
needed
- Modified an8801r_get_wol to return WoL is not supported if the PHY
device is not wakeup capable
- Modified an8801r_set_wol to return EOPNOTSUPP error code if the PHY
device is not wakeup capable, and to update the wakeup flag according
to WoL mode
- Modified an8801r_config_init to remove EEE disabling and replace
__phy_write use by phy_write_paged
- Reworked an8801r_rgmii_delay_config and its subfunctions to fix a
double return use in PHY_INTERFACE_MODE_RGMII_ID case, replace the
magic value use for default TX and RX delay and handle better the
enable/disable the inserted delays for all RGMII modes
- Merged an8801r_did_interrupt function in an8801r_handle_interrupt
- Modified the an8801r_handle_interrupt processing to process differently
the Magic Packet (to notify system wakeup) and the Link Changed
interrupt (to notify PHY state machine)
- Splitted the reset WoL status part from an8801r_ack_interrupt and fix
an issue that in some random cases made WAKEUP_CTL1 register lose the
Magic Packet WoL settings
- Modified an8801r_of_init_leds function so it does not return an error
if the leds configuration is not present in devicetree
- Removed feature field and add PHY_ALWAYS_CALL_SUSPEND flag in
airoha_driver data structure
- Link to v1: https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-0-0ae4ee5a2f9d@collabora.com
---
AngeloGioacchino Del Regno (2):
dt-bindings: net: Add support for Airoha AN8801/R GbE PHY
net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver
Louis-Alexis Eyraud (4):
net: phy: Add Airoha phy library for shared code
net: phy: air_phy_lib: Factorize BuckPBus register accessors
net: phy: Rename Airoha common BuckPBus register accessors
net: phy: air_an8801: ensure maximum available speed link use
.../devicetree/bindings/net/airoha,an8801.yaml | 85 ++
drivers/net/phy/Kconfig | 12 +
drivers/net/phy/Makefile | 2 +
drivers/net/phy/air_an8801.c | 1119 ++++++++++++++++++++
drivers/net/phy/air_en8811h.c | 316 +-----
drivers/net/phy/air_phy_lib.c | 212 ++++
drivers/net/phy/air_phy_lib.h | 39 +
7 files changed, 1527 insertions(+), 258 deletions(-)
---
base-commit: 63751099502d10f0aa6bb35273e56c5800cc4e3a
change-id: 20260303-add-airoha-an8801-support-57d544a4afed
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* [PATCH v3 3/7] gpio: regmap: Add gpio_regmap_operation and write-enable support
From: Yu-Chun Lin @ 2026-05-12 3:33 UTC (permalink / raw)
To: linusw, brgl, robh, krzk+dt, conor+dt, afaerber, wbg,
mathieu.dubois-briand, mwalle, lars, Michael.Hennerich, jic23,
nuno.sa, andy, dlechner, tychang
Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel,
linux-realtek-soc, linux-iio, cy.huang, stanley_chang,
eleanor.lin, james.tai, Linus Walleij
In-Reply-To: <20260512033317.1602537-1-eleanor.lin@realtek.com>
Extend the reg_mask_xlate callback with an operation type parameter
(gpio_regmap_operation) to allow drivers to return different
register/mask combinations for different GPIO operations.
Also add write-enable mechanism for hardware that requires setting a
write-enable bit before modifying GPIO control registers.
Consequently, update all existing drivers utilizing the gpio-regmap
framework (across drivers/gpio, drivers/iio, and drivers/pinctrl)
to accommodate the new reg_mask_xlate function signature.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
drivers/gpio/gpio-104-idi-48.c | 18 +++++--
drivers/gpio/gpio-i8255.c | 13 ++++-
drivers/gpio/gpio-idio-16.c | 16 ++++--
drivers/gpio/gpio-max7360.c | 10 ++++
drivers/gpio/gpio-pcie-idio-24.c | 15 ++++--
drivers/gpio/gpio-regmap.c | 72 ++++++++++++++++++++-------
drivers/iio/adc/ad7173.c | 32 +++++++++---
drivers/iio/addac/stx104.c | 17 +++++--
drivers/pinctrl/bcm/pinctrl-bcm63xx.c | 12 ++++-
drivers/pinctrl/pinctrl-tps6594.c | 10 ++++
include/linux/gpio/regmap.h | 43 ++++++++++++++--
11 files changed, 214 insertions(+), 44 deletions(-)
diff --git a/drivers/gpio/gpio-104-idi-48.c b/drivers/gpio/gpio-104-idi-48.c
index ba73ee9c0c29..ebd0587f99c5 100644
--- a/drivers/gpio/gpio-104-idi-48.c
+++ b/drivers/gpio/gpio-104-idi-48.c
@@ -36,9 +36,10 @@ MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
#define IDI48_IRQ_STATUS 0x7
#define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS
-static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
- unsigned int *mask)
+static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
+ unsigned int base, unsigned int offset,
+ unsigned int *reg, unsigned int *mask)
{
const unsigned int line = offset % 8;
const unsigned int stride = offset / 8;
@@ -46,7 +47,16 @@ static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
const unsigned int port_stride = stride % 3;
*reg = base + port + port_stride;
- *mask = BIT(line);
+
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = BIT(line);
+ break;
+ }
return 0;
}
diff --git a/drivers/gpio/gpio-i8255.c b/drivers/gpio/gpio-i8255.c
index 953018bfa2b1..ec3c3186e2d1 100644
--- a/drivers/gpio/gpio-i8255.c
+++ b/drivers/gpio/gpio-i8255.c
@@ -67,8 +67,8 @@ static int i8255_ppi_init(struct regmap *const map, const unsigned int base)
return regmap_write(map, base + I8255_PORTC, 0x00);
}
-static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
+static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_operation op,
+ unsigned int base, unsigned int offset, unsigned int *reg,
unsigned int *mask)
{
const unsigned int ppi = offset / I8255_NGPIO;
@@ -76,6 +76,15 @@ static int i8255_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
const unsigned int stride = ppi_offset / I8255_NGPIO_PER_REG;
const unsigned int line = ppi_offset % I8255_NGPIO_PER_REG;
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ return 0;
+ default:
+ break;
+ }
+
switch (base) {
case I8255_REG_DAT_BASE:
*reg = base + stride + ppi * 4;
diff --git a/drivers/gpio/gpio-idio-16.c b/drivers/gpio/gpio-idio-16.c
index 4fbae6f6a497..d78a05c22531 100644
--- a/drivers/gpio/gpio-idio-16.c
+++ b/drivers/gpio/gpio-idio-16.c
@@ -66,9 +66,9 @@ static int idio_16_handle_mask_sync(const int index, const unsigned int mask_buf
return 0;
}
-static int idio_16_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned int base,
- const unsigned int offset, unsigned int *const reg,
- unsigned int *const mask)
+static int idio_16_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpio_regmap_operation op,
+ const unsigned int base, const unsigned int offset,
+ unsigned int *const reg, unsigned int *const mask)
{
unsigned int stride;
@@ -81,7 +81,15 @@ static int idio_16_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned
*reg = IDIO_16_IN_BASE + stride * IDIO_16_REG_STRIDE;
}
- *mask = BIT(offset % IDIO_16_NGPIO_PER_REG);
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = BIT(offset % IDIO_16_NGPIO_PER_REG);
+ break;
+ }
return 0;
}
diff --git a/drivers/gpio/gpio-max7360.c b/drivers/gpio/gpio-max7360.c
index db92a43776a9..2a26313d021d 100644
--- a/drivers/gpio/gpio-max7360.c
+++ b/drivers/gpio/gpio-max7360.c
@@ -94,9 +94,19 @@ static int max7360_set_gpos_count(struct device *dev, struct regmap *regmap)
}
static int max7360_gpio_reg_mask_xlate(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ return 0;
+ default:
+ break;
+ }
+
if (base == MAX7360_REG_PWMBASE) {
/*
* GPIO output is using PWM duty cycle registers: one register
diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c
index 80c0ba0afa67..dc80f96174c2 100644
--- a/drivers/gpio/gpio-pcie-idio-24.c
+++ b/drivers/gpio/gpio-pcie-idio-24.c
@@ -225,9 +225,9 @@ static int idio_24_set_type_config(unsigned int **const buf, const unsigned int
return ret;
}
-static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned int base,
- const unsigned int offset, unsigned int *const reg,
- unsigned int *const mask)
+static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpio_regmap_operation op,
+ const unsigned int base, const unsigned int offset,
+ unsigned int *const reg, unsigned int *const mask)
{
const unsigned int out_stride = offset / IDIO_24_NGPIO_PER_REG;
const unsigned int in_stride = (offset - 24) / IDIO_24_NGPIO_PER_REG;
@@ -235,6 +235,15 @@ static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned
int err;
unsigned int ctrl_reg;
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ return 0;
+ default:
+ break;
+ }
+
switch (base) {
case IDIO_24_OUT_BASE:
*mask = BIT(offset % IDIO_24_NGPIO_PER_REG);
diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
index deb9eebb58de..c76eef20e412 100644
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -38,9 +38,10 @@ struct gpio_regmap {
struct regmap_irq_chip_data *irq_chip_data;
#endif
- int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
- unsigned int *mask);
+ int (*reg_mask_xlate)(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
+ unsigned int base, unsigned int offset,
+ unsigned int *reg, unsigned int *mask);
void *driver_data;
};
@@ -54,6 +55,7 @@ static unsigned int gpio_regmap_addr(unsigned int addr)
}
static int gpio_regmap_simple_xlate(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
@@ -61,7 +63,16 @@ static int gpio_regmap_simple_xlate(struct gpio_regmap *gpio,
unsigned int stride = offset / gpio->ngpio_per_reg;
*reg = base + stride * gpio->reg_stride;
- *mask = BIT(line);
+
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = BIT(line);
+ break;
+ }
return 0;
}
@@ -69,7 +80,7 @@ static int gpio_regmap_simple_xlate(struct gpio_regmap *gpio,
static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset)
{
struct gpio_regmap *gpio = gpiochip_get_data(chip);
- unsigned int base, val, reg, mask;
+ unsigned int base, val, reg, mask, dir_mask;
int ret;
/* we might not have an output register if we are input only */
@@ -78,10 +89,24 @@ static int gpio_regmap_get(struct gpio_chip *chip, unsigned int offset)
else
base = gpio_regmap_addr(gpio->reg_set_base);
- ret = gpio->reg_mask_xlate(gpio, base, offset, ®, &mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_GET_OP, base, offset, ®, &dir_mask);
if (ret)
return ret;
+ ret = regmap_read(gpio->regmap, reg, &val);
+ if (ret)
+ return ret;
+
+ if (val & dir_mask) {
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_OUT, base, offset, ®, &mask);
+ if (ret)
+ return ret;
+ } else {
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_IN, base, offset, ®, &mask);
+ if (ret)
+ return ret;
+ }
+
/* ensure we don't spoil any register cache with pin input values */
if (gpio->reg_dat_base == gpio->reg_set_base)
ret = regmap_read_bypassed(gpio->regmap, reg, &val);
@@ -98,10 +123,14 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsigned int offset,
{
struct gpio_regmap *gpio = gpiochip_get_data(chip);
unsigned int base = gpio_regmap_addr(gpio->reg_set_base);
- unsigned int reg, mask, mask_val;
+ unsigned int reg, mask, mask_val, wren_mask;
int ret;
- ret = gpio->reg_mask_xlate(gpio, base, offset, ®, &mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WREN_OP, base, offset, ®, &wren_mask);
+ if (ret)
+ return ret;
+
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_OP, base, offset, ®, &mask);
if (ret)
return ret;
@@ -112,9 +141,9 @@ static int gpio_regmap_set(struct gpio_chip *chip, unsigned int offset,
/* ignore input values which shadow the old output value */
if (gpio->reg_dat_base == gpio->reg_set_base)
- ret = regmap_write_bits(gpio->regmap, reg, mask, mask_val);
+ ret = regmap_write_bits(gpio->regmap, reg, mask | wren_mask, mask_val | wren_mask);
else
- ret = regmap_update_bits(gpio->regmap, reg, mask, mask_val);
+ ret = regmap_update_bits(gpio->regmap, reg, mask | wren_mask, mask_val | wren_mask);
return ret;
}
@@ -123,7 +152,7 @@ static int gpio_regmap_set_with_clear(struct gpio_chip *chip,
unsigned int offset, int val)
{
struct gpio_regmap *gpio = gpiochip_get_data(chip);
- unsigned int base, reg, mask;
+ unsigned int base, reg, mask, wren_mask;
int ret;
if (val)
@@ -131,11 +160,15 @@ static int gpio_regmap_set_with_clear(struct gpio_chip *chip,
else
base = gpio_regmap_addr(gpio->reg_clr_base);
- ret = gpio->reg_mask_xlate(gpio, base, offset, ®, &mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WREN_OP, base, offset, ®, &wren_mask);
if (ret)
return ret;
- return regmap_write(gpio->regmap, reg, mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_WITH_CLEAR_OP, base, offset, ®, &mask);
+ if (ret)
+ return ret;
+
+ return regmap_write(gpio->regmap, reg, mask | wren_mask);
}
static int gpio_regmap_get_direction(struct gpio_chip *chip,
@@ -167,7 +200,7 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
return -ENOTSUPP;
}
- ret = gpio->reg_mask_xlate(gpio, base, offset, ®, &mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_GET_DIR_OP, base, offset, ®, &mask);
if (ret)
return ret;
@@ -185,7 +218,7 @@ static int gpio_regmap_set_direction(struct gpio_chip *chip,
unsigned int offset, bool output)
{
struct gpio_regmap *gpio = gpiochip_get_data(chip);
- unsigned int base, val, reg, mask;
+ unsigned int base, val, reg, mask, wren_mask;
int invert, ret;
if (gpio->reg_dir_out_base) {
@@ -198,7 +231,12 @@ static int gpio_regmap_set_direction(struct gpio_chip *chip,
return -ENOTSUPP;
}
- ret = gpio->reg_mask_xlate(gpio, base, offset, ®, &mask);
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_DIR_OP, base, offset, ®, &mask);
+ if (ret)
+ return ret;
+
+ ret = gpio->reg_mask_xlate(gpio, GPIO_REGMAP_SET_DIR_WREN_OP, base, offset, ®,
+ &wren_mask);
if (ret)
return ret;
@@ -207,7 +245,7 @@ static int gpio_regmap_set_direction(struct gpio_chip *chip,
else
val = output ? mask : 0;
- return regmap_update_bits(gpio->regmap, reg, mask, val);
+ return regmap_update_bits(gpio->regmap, reg, mask | wren_mask, val | wren_mask);
}
static int gpio_regmap_direction_input(struct gpio_chip *chip,
diff --git a/drivers/iio/adc/ad7173.c b/drivers/iio/adc/ad7173.c
index f76a9e08f39e..e8a6921bc443 100644
--- a/drivers/iio/adc/ad7173.c
+++ b/drivers/iio/adc/ad7173.c
@@ -561,21 +561,41 @@ static int ad4111_openwire_event(struct iio_dev *indio_dev,
return ret;
}
-static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
+static int ad7173_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_operation op,
+ unsigned int base, unsigned int offset, unsigned int *reg,
unsigned int *mask)
{
- *mask = AD7173_GPO_DATA(offset);
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ return 0;
+ default:
+ *mask = AD7173_GPO_DATA(offset);
+ break;
+ }
+
*reg = base;
+
return 0;
}
-static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
+static int ad4111_mask_xlate(struct gpio_regmap *gpio, enum gpio_regmap_operation op,
+ unsigned int base, unsigned int offset, unsigned int *reg,
unsigned int *mask)
{
- *mask = AD4111_GPO01_DATA(offset);
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = AD4111_GPO01_DATA(offset);
+ break;
+ }
+
*reg = base;
+
return 0;
}
diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c
index 7bdf2cb94176..a4e54ed102a2 100644
--- a/drivers/iio/addac/stx104.c
+++ b/drivers/iio/addac/stx104.c
@@ -349,16 +349,25 @@ static const struct iio_chan_spec stx104_channels_diff[] = {
STX104_IN_CHAN(6, 1), STX104_IN_CHAN(7, 1)
};
-static int stx104_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned int base,
- unsigned int offset, unsigned int *const reg,
- unsigned int *const mask)
+static int stx104_reg_mask_xlate(struct gpio_regmap *const gpio, enum gpio_regmap_operation op,
+ const unsigned int base, unsigned int offset,
+ unsigned int *const reg, unsigned int *const mask)
{
/* Output lines are located at same register bit offsets as input lines */
if (offset >= 4)
offset -= 4;
*reg = base;
- *mask = BIT(offset);
+
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = BIT(offset);
+ break;
+ }
return 0;
}
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c
index 59d2ce8462d8..3a868deb7793 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c
@@ -20,6 +20,7 @@
#define BCM63XX_DATA_REG 0x0c
static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
@@ -27,7 +28,16 @@ static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
unsigned int stride = offset / BCM63XX_BANK_GPIOS;
*reg = base - stride * BCM63XX_BANK_SIZE;
- *mask = BIT(line);
+
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ break;
+ default:
+ *mask = BIT(line);
+ break;
+ }
return 0;
}
diff --git a/drivers/pinctrl/pinctrl-tps6594.c b/drivers/pinctrl/pinctrl-tps6594.c
index 6726853110d1..e30a856712af 100644
--- a/drivers/pinctrl/pinctrl-tps6594.c
+++ b/drivers/pinctrl/pinctrl-tps6594.c
@@ -347,12 +347,22 @@ static struct tps6594_pinctrl tps6594_template_pinctrl = {
};
static int tps6594_gpio_regmap_xlate(struct gpio_regmap *gpio,
+ enum gpio_regmap_operation op,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
unsigned int line = offset % 8;
unsigned int stride = offset / 8;
+ switch (op) {
+ case GPIO_REGMAP_SET_WREN_OP:
+ case GPIO_REGMAP_SET_DIR_WREN_OP:
+ *mask = 0;
+ return 0;
+ default:
+ break;
+ }
+
switch (base) {
case TPS6594_REG_GPIOX_CONF(0):
*reg = TPS6594_REG_GPIOX_CONF(offset);
diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
index e4a95f805a81..519fc81add8a 100644
--- a/include/linux/gpio/regmap.h
+++ b/include/linux/gpio/regmap.h
@@ -13,6 +13,43 @@ struct regmap;
#define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1))
#define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO)
+/**
+ * enum gpio_regmap_operation - Operation type for reg_mask_xlate callback
+ *
+ * This enum is used to distinguish between different types of GPIO operations
+ * so that the reg_mask_xlate callback can return the appropriate mask for each
+ * operation type.
+ *
+ * Value operations:
+ * @GPIO_REGMAP_GET_OP: Mask for reading direction to detect if GPIO is input or output.
+ * Used in gpio_regmap_get() to determine the GPIO direction.
+ * @GPIO_REGMAP_IN: Mask for reading input value. Used when GPIO is configured as input.
+ * @GPIO_REGMAP_OUT: Mask for reading output value. Used when GPIO is configured as output.
+ *
+ * Output operations:
+ * @GPIO_REGMAP_SET_OP: Mask for setting GPIO output value.
+ * @GPIO_REGMAP_SET_WITH_CLEAR_OP: Mask for setting/clearing GPIO using separate registers.
+ * @GPIO_REGMAP_SET_WREN_OP: Write-enable mask for output operations. May be used to enable
+ * writes to protected registers.
+ *
+ * Direction operations:
+ * @GPIO_REGMAP_GET_DIR_OP: Mask for reading GPIO direction (input/output).
+ * @GPIO_REGMAP_SET_DIR_OP: Mask for setting GPIO direction (input/output).
+ * @GPIO_REGMAP_SET_DIR_WREN_OP: Write-enable mask for direction operations. May be used to
+ * enable writes to protected direction registers.
+ */
+enum gpio_regmap_operation {
+ GPIO_REGMAP_GET_OP,
+ GPIO_REGMAP_SET_OP,
+ GPIO_REGMAP_SET_WITH_CLEAR_OP,
+ GPIO_REGMAP_SET_WREN_OP,
+ GPIO_REGMAP_GET_DIR_OP,
+ GPIO_REGMAP_SET_DIR_OP,
+ GPIO_REGMAP_SET_DIR_WREN_OP,
+ GPIO_REGMAP_IN,
+ GPIO_REGMAP_OUT,
+};
+
/**
* struct gpio_regmap_config - Description of a generic regmap gpio_chip.
* @parent: The parent device
@@ -97,9 +134,9 @@ struct gpio_regmap_config {
unsigned long regmap_irq_flags;
#endif
- int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
- unsigned int offset, unsigned int *reg,
- unsigned int *mask);
+ int (*reg_mask_xlate)(struct gpio_regmap *gpio, enum gpio_regmap_operation,
+ unsigned int base, unsigned int offset,
+ unsigned int *reg, unsigned int *mask);
int (*init_valid_mask)(struct gpio_chip *gc,
unsigned long *valid_mask,
--
2.34.1
^ permalink raw reply related
* [PATCH v1 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence
From: Richard Zhu @ 2026-05-12 5:22 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel
This series addresses PHY initialization sequence issues for i.MX95 PCIe
that were identified through careful review of the i.MX95 PCIe PHY Databook.
The current implementation does not strictly follow the timing requirements
specified in the PHY documentation for reference clock configuration and
PHY reset sequencing. These violations can potentially lead to unreliable
PHY initialization.
Patch 1 ensures that the REF_USE_PAD configuration is applied before the
PHY reset is toggled, as required by the Common Block Signals specification.
Any change to ref_use_pad must be followed by a PHY reset assertion to take
effect properly.
Patch 2 corrects the ref_clk_en signal timing by moving its manipulation
into the reference clock enable function. This ensures the reference clock
is stable before ref_clk_en is asserted and before the PHY reset is
de-asserted, meeting the PHY's power sequencing requirements.
Together, these patches ensure proper PHY initialization sequence compliance
and improve the reliability of PCIe operation on i.MX95 platforms.
[PATCH v1 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for
[PATCH v1 2/2] PCI: imx6: Assert ref_clk_en after reference clock
drivers/pci/controller/dwc/pci-imx6.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++--------------
1 file changed, 51 insertions(+), 14 deletions(-)
^ permalink raw reply
* [PATCH v1 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95
From: Richard Zhu @ 2026-05-12 5:22 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel, Richard Zhu,
stable
In-Reply-To: <20260512052244.49414-1-hongxing.zhu@nxp.com>
According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
Common Block Signals section selects the reference clock source connected
to the PHY pads. Per the specification, any change to this input must be
followed by a PHY reset assertion to take effect.
Move the REF_USE_PAD configuration before the PHY reset toggle to comply
with the required initialization sequence.
Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
Cc: <stable@vger.kernel.org>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 1034ac5c5f5c1..c57f18d9e4ffa 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -137,6 +137,7 @@ struct imx_pcie_drvdata {
const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const struct pci_epc_features *epc_features;
+ int (*init_pre_reset)(struct imx_pcie *pcie);
int (*init_phy)(struct imx_pcie *pcie);
int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
int (*core_reset)(struct imx_pcie *pcie, bool assert);
@@ -247,6 +248,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
+static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
+{
+ bool ext = imx_pcie->enable_ext_refclk;
+
+ /*
+ * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
+ * used to select reference clock connected to a pair of pads.
+ *
+ * Any change in this input must be followed by phy_reset assertion.
+ */
+
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_REF_USE_PAD,
+ ext ? IMX95_PCIE_REF_USE_PAD : 0);
+
+ return 0;
+}
+
static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
bool ext = imx_pcie->enable_ext_refclk;
@@ -269,9 +288,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
IMX95_PCIE_PHY_CR_PARA_SEL,
IMX95_PCIE_PHY_CR_PARA_SEL);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
- IMX95_PCIE_REF_USE_PAD,
- ext ? IMX95_PCIE_REF_USE_PAD : 0);
regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
IMX95_PCIE_REF_CLKEN,
ext ? 0 : IMX95_PCIE_REF_CLKEN);
@@ -1251,6 +1267,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
pp->bridge->disable_device = imx_pcie_disable_device;
}
+ if (imx_pcie->drvdata->init_pre_reset)
+ imx_pcie->drvdata->init_pre_reset(imx_pcie);
+
imx_pcie_assert_core_reset(imx_pcie);
imx_pcie_assert_perst(imx_pcie, true);
@@ -1961,6 +1980,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
.core_reset = imx95_pcie_core_reset,
.init_phy = imx95_pcie_init_phy,
+ .init_pre_reset = imx95_pcie_init_pre_reset,
.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
.enable_ref_clk = imx95_pcie_enable_ref_clk,
.clr_clkreq_override = imx95_pcie_clr_clkreq_override,
@@ -2016,6 +2036,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.ltssm_mask = IMX95_PCIE_LTSSM_EN,
.mode_off[0] = IMX95_PE0_GEN_CTRL_1,
.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+ .init_pre_reset = imx95_pcie_init_pre_reset,
.init_phy = imx95_pcie_init_phy,
.core_reset = imx95_pcie_core_reset,
.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
--
2.37.1
^ permalink raw reply related
* [PATCH v1 2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95
From: Richard Zhu @ 2026-05-12 5:22 UTC (permalink / raw)
To: frank.li, l.stach, lpieralisi, kwilczynski, mani, robh, bhelgaas,
s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, imx, linux-kernel, Richard Zhu,
stable
In-Reply-To: <20260512052244.49414-1-hongxing.zhu@nxp.com>
According to the PHY Databook Common Block Signals section, the
ref_clk_en signal must remain de-asserted until the reference clock is
running at the appropriate frequency. Once the clock is stable,
ref_clk_en can be asserted. For lower power states where the reference
clock to the PHY is disabled, ref_clk_en should also be de-asserted.
Move the ref_clk_en bit manipulation into imx95_pcie_enable_ref_clk()
to ensure the reference clock stabilizes before ref_clk_en is asserted
and before the PHY reset is de-asserted. This aligns with the timing
requirements specified in the PHY documentation.
Fixes: d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 40 +++++++++++++++++++--------
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c57f18d9e4ffa..c3e623aa18bc2 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -268,8 +268,6 @@ static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
{
- bool ext = imx_pcie->enable_ext_refclk;
-
/*
* ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
* Through Beacon or PERST# De-assertion
@@ -288,10 +286,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
IMX95_PCIE_PHY_CR_PARA_SEL,
IMX95_PCIE_PHY_CR_PARA_SEL);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
- IMX95_PCIE_REF_CLKEN,
- ext ? 0 : IMX95_PCIE_REF_CLKEN);
-
return 0;
}
@@ -740,7 +734,29 @@ static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
{
+ bool ext = imx_pcie->enable_ext_refclk;
+
imx95_pcie_clkreq_override(imx_pcie, enable);
+ /*
+ * The ref_clk_en signal must remain de-asserted until the
+ * reference clock is running at appropriate frequency, at which
+ * point this bit can be asserted. For lower power states where
+ * the reference clock to the PHY is disabled, it may also be
+ * de-asserted.
+ * +------------------- -+--------+----------------+
+ * | External clock mode | Enable | PCIE_REF_CLKEN |
+ * +---------------------+--------+----------------+
+ * | TRUE | X | 1b'0 |
+ * +---------------------+--------+----------------+
+ * | FALSE | TRUE | 1b'1 |
+ * +---------------------+--------+----------------+
+ * | FALSE | FALSE | 1b'0 |
+ * +---------------------+--------+----------------+
+ */
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_REF_CLKEN,
+ ext || !enable ? 0 : IMX95_PCIE_REF_CLKEN);
+
return 0;
}
@@ -1262,6 +1278,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
}
}
+ ret = imx_pcie_clk_enable(imx_pcie);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
+ goto err_reg_disable;
+ }
+
if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {
pp->bridge->enable_device = imx_pcie_enable_device;
pp->bridge->disable_device = imx_pcie_disable_device;
@@ -1278,12 +1300,6 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
imx_pcie_configure_type(imx_pcie);
- ret = imx_pcie_clk_enable(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
- goto err_reg_disable;
- }
-
if (imx_pcie->phy) {
ret = phy_init(imx_pcie->phy);
if (ret) {
--
2.37.1
^ permalink raw reply related
* [PATCH v2 04/16] dt-bindings: mfd: mediatek: mt6397: add mt6323 PMIC thermal
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The MediaTek mt6323 PMIC temperature can be read using AUXADC channel.
Add the devicetree binding documentation for the MediaTek mt6323 thermal.
While mt6323 exposes only a single thermal sensor, newer PMICs like
mt6358 provide more than one sensor. Therefore define #thermal-sensor-cells
as 1 to avoid breaking devicetree ABI in the future.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
.../devicetree/bindings/mfd/mediatek,mt6397.yaml | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
index beaa67bf0df2..2c826737189e 100644
--- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
@@ -242,6 +242,31 @@ properties:
description:
Pin controller
+ thermal:
+ type: object
+ unevaluatedProperties: false
+ description:
+ PMIC thermal monitoring
+
+ properties:
+ compatible:
+ const: mediatek,mt6323-thermal
+
+ io-channels:
+ description:
+ IIO channel for the AUXADC to read raw data from.
+ maxItems: 1
+
+ nvmem-cells:
+ maxItems: 1
+
+ "#thermal-sensor-cells":
+ const: 1
+ required:
+ - compatible
+ - io-channels
+ - "#thermal-sensor-cells"
+
required:
- compatible
- regulators
@@ -250,6 +275,7 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/iio/adc/mediatek,mt6323-auxadc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
@@ -262,6 +288,16 @@ examples:
efuse {
compatible = "mediatek,mt6323-efuse";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mt6323_thermal_calibration_data: thermal-data@14 {
+ reg = <0x14 0x4>;
+ };
+ };
};
leds {
@@ -511,6 +547,14 @@ examples:
rtc {
compatible = "mediatek,mt6323-rtc";
};
+
+ thermal {
+ compatible = "mediatek,mt6323-thermal";
+ nvmem-cells = <&mt6323_thermal_calibration_data>;
+
+ io-channels = <&mt6323_adc MT6323_AUXADC_CHIP_TEMP>;
+ #thermal-sensor-cells = <1>;
+ };
};
- |
--
2.54.0
^ permalink raw reply related
* [PATCH v2 00/16] add AUXADC, EFUSE and thermal drivers for the MediaTek mt6323 PMIC
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
This series adds support for AUXADC, EFUSE and thermal drivers for the
MediaTek mt6323 PMIC
Usually vendor downstream kernels for devices with mt6323 include various
useful drivers like AUXADC, thermal, fuel gauge etc. Bring it to the
upstream kernel by rewriting some drivers from 3.18 vendor tree.
Currently dt-bindings limit some values like ADC channel count and names
to what mt6323 has, but the drivers were designed in a way to support
other PMICs like mt6358 (which has very similar thermal logic).
Tested on the MediaTek mt6572 and mt8163 SoCs, both paired with mt6323.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Changes in v2:
- dt-bindings:
- Drop Tested-by tags (Krzysztof)
- AUXADC: drop mt6323 standalone binding and merge into mt6359 (Krzysztof)
- EFUSE: drop mt6323 standalone binding and merge into mt6397 (Krzysztof)
- Thermal: drop iio-channel-names, nvmem-cells description, unused label (Rob)
- Thermal: Merge into mt6397 mfd
- AUXADC driver:
- Fix formatting for macro, OF table, etc (Andy, Jonathan)
- Drop dev field from the mt6323_auxadc struct (Andy)
- Use dt-bindings constants for channels instead of raw numbers
- Simplify mt6323_auxadc_check_if_stuck implemenetation with iopoll (Andy)
- Drop untested audio channel support (Andy, Jonathan)
- Replace check for chan->address with chan->channel to avoid confusion (Jonathan)
- Replace scoped_guard with guard in mt6323_auxadc_read_raw (Andy)
- Replace mutex_init with devm helper in probe (Andy)
- EFUSE driver:
- Add comments about read function (Andy)
- Use sizeof() (Andy)
- Thermal driver:
- Rename to mtk_pmic_thermal for proper module name
- Add module name to Kconfig
- Use bitfield.h APIs for efuse extraction (Andy)
- Drop nvmem cell name for consistency with devicetree bindings
- Replace raw numbers with constants (Andy)
- Add comments to read function, remove redundant parentheses (Andy)
- Add comments to precalc function, simplify it for readability (Andy)
- Reorder struct fields (Andy)
- Drop cali_val field, since per-PMIC functions are used
- Use __free for nvmem_cell_read cleanup (Andy)
- Maintainers:
- Split patch into 3 for different subsystems (Krzysztof)
- Downgrade to "Odd fixes"
- Note: Signing key has been changed since v1. Sorry for inconvenience
- Link to v1: https://patch.msgid.link/20260504-mt6323-v1-0-799b58b355ff@protonmail.com
---
Roman Vivchar (16):
dt-bindings: iio: adc: mt6359: generalize description for mt63xx series
dt-bindings: iio: adc: mt6359: add mt6323 PMIC AUXADC
dt-bindings: mfd: mediatek: mt6397: add mt6323 PMIC EFUSE
dt-bindings: mfd: mediatek: mt6397: add mt6323 PMIC thermal
iio: adc: mediatek: add mt6323 PMIC AUXADC driver
nvmem: add mt6323 PMIC EFUSE driver
thermal: mediatek: add PMIC thermal support
mfd: mt6397-core: add mt6323 AUXADC support
mfd: mt6397-core: add mt6323 EFUSE support
mfd: mt6397-core: add mt6323 thermal support
ARM: dts: mediatek: mt6323: add AUXADC support
ARM: dts: mediatek: mt6323: add EFUSE support
ARM: dts: mediatek: mt6323: add thermal support
MAINTAINERS: add MediaTek mt6323 PMIC AUXADC driver maintainer
MAINTAINERS: add MediaTek mt6323 PMIC EFUSE driver maintainer
MAINTAINERS: add MediaTek mt6323 PMIC thermal driver maintainer
.../bindings/iio/adc/mediatek,mt6359-auxadc.yaml | 3 +-
.../devicetree/bindings/mfd/mediatek,mt6397.yaml | 65 +++++
MAINTAINERS | 15 +
arch/arm/boot/dts/mediatek/mt6323.dtsi | 40 +++
drivers/iio/adc/Kconfig | 11 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/mt6323-auxadc.c | 319 +++++++++++++++++++++
drivers/mfd/mt6397-core.c | 9 +
drivers/nvmem/Kconfig | 11 +
drivers/nvmem/Makefile | 2 +
drivers/nvmem/mt6323-efuse.c | 86 ++++++
drivers/thermal/mediatek/Kconfig | 12 +
drivers/thermal/mediatek/Makefile | 1 +
drivers/thermal/mediatek/mtk_pmic_thermal.c | 316 ++++++++++++++++++++
.../dt-bindings/iio/adc/mediatek,mt6323-auxadc.h | 24 ++
15 files changed, 914 insertions(+), 1 deletion(-)
---
base-commit: 028ef9c96e96197026887c0f092424679298aae8
change-id: 20260502-mt6323-94e1f2d2abb3
Best regards,
--
Roman Vivchar <rva333@protonmail.com>
^ permalink raw reply
* [PATCH v2 03/16] dt-bindings: mfd: mediatek: mt6397: add mt6323 PMIC EFUSE
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The MediaTek mt6323 PMIC includes an EFUSE used for storing calibration
data.
Add the devicetree binding documentation for the MediaTek mt6323 EFUSE.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
.../devicetree/bindings/mfd/mediatek,mt6397.yaml | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
index 05c121b0cb3d..beaa67bf0df2 100644
--- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
@@ -145,6 +145,23 @@ properties:
required:
- compatible
+ efuse:
+ type: object
+ unevaluatedProperties: false
+ description:
+ The efuse is responsible for storing calibration data, such as thermal
+ sensor calibration.
+
+ properties:
+ compatible:
+ const: mediatek,mt6323-efuse
+
+ nvmem-layout:
+ $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
+
+ required:
+ - compatible
+
leds:
type: object
additionalProperties: false
@@ -243,6 +260,10 @@ examples:
interrupt-controller;
#interrupt-cells = <2>;
+ efuse {
+ compatible = "mediatek,mt6323-efuse";
+ };
+
leds {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 07/16] thermal: mediatek: add PMIC thermal support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add a new driver to support thermal monitoring on MediaTek PMICs.
The driver retrieves calibration data from EFUSE, calculates the
temperature using a linear interpolation, and registers the device with
the thermal framework.
Initial support is added for the mt6323 PMIC.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/thermal/mediatek/Kconfig | 12 ++
drivers/thermal/mediatek/Makefile | 1 +
drivers/thermal/mediatek/mtk_pmic_thermal.c | 316 ++++++++++++++++++++++++++++
3 files changed, 329 insertions(+)
diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig
index d82c86d9be56..8320d109fde6 100644
--- a/drivers/thermal/mediatek/Kconfig
+++ b/drivers/thermal/mediatek/Kconfig
@@ -34,4 +34,16 @@ config MTK_LVTS_THERMAL_DEBUGFS
help
Enable this option to debug the internals of the device driver.
+config MTK_PMIC_THERMAL
+ tristate "AUXADC temperature sensor driver for MediaTek PMICs"
+ depends on MFD_MT6397
+ help
+ Enable this option if you want to get PMIC temperature
+ information for MediaTek platforms.
+ This driver configures thermal controllers to collect
+ temperature via AUXADC interface.
+
+ This driver can also be built as a module. If so, the module will be
+ called mtk_pmic_thermal.
+
endif
diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile
index 1c6daa1e644b..bfb3b6f02539 100644
--- a/drivers/thermal/mediatek/Makefile
+++ b/drivers/thermal/mediatek/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o
obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o
+obj-$(CONFIG_MTK_PMIC_THERMAL) += mtk_pmic_thermal.o
diff --git a/drivers/thermal/mediatek/mtk_pmic_thermal.c b/drivers/thermal/mediatek/mtk_pmic_thermal.c
new file mode 100644
index 000000000000..f644dad15fc2
--- /dev/null
+++ b/drivers/thermal/mediatek/mtk_pmic_thermal.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 Roman Vivchar <rva333@protonmail.com>
+ *
+ * Based on drivers/thermal/mediatek/auxadc_thermal.c
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/err.h>
+#include <linux/iio/consumer.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+#include <linux/units.h>
+
+#include <linux/mfd/mt6323/registers.h>
+
+#define MAX_SENSORS 1
+
+#define MT6323_TEMP_MIN (-20 * MILLIDEGREE_PER_DEGREE)
+#define MT6323_TEMP_MAX (50 * MILLIDEGREE_PER_DEGREE)
+
+/* Layout of the fuses providing the calibration data */
+#define CALIB_BUF0_VTS_MASK GENMASK(15, 8)
+#define CALIB_BUF0_DEGC_CALI_MASK GENMASK(7, 2)
+#define CALIB_BUF0_ADC_CALI_EN_MASK BIT(1)
+
+#define CALIB_BUF1_ID_20_MASK BIT(14)
+#define CALIB_BUF1_ID_10_MASK BIT(12)
+#define CALIB_BUF1_O_SLOPE_20_HI GENMASK(13, 11)
+#define CALIB_BUF1_O_SLOPE_20_LO GENMASK(8, 6)
+#define CALIB_BUF1_O_SLOPE_10_MASK GENMASK(11, 6)
+#define CALIB_BUF1_O_SLOPE_SIGN_MASK BIT(5)
+#define CALIB_BUF1_VTS_MASK GENMASK(4, 0)
+
+#define MT6323_CALIBRATION 171
+#define MT6323_ADC_VOLTAGE_RANGE 1800
+#define MT6323_ADC_RESOLUTION 32768
+#define MT6323_ADC_VBE_OFFSET 9102
+
+#define MT6323_DEFAULT_VTS 3698
+#define MT6323_DEFAULT_DEGC_CALI 50
+#define MT6323_DEFAULT_SLOPE 0
+#define MT6323_DEFAULT_SLOPE_SIGN 0
+
+struct mtk_pmic_thermal;
+
+struct mtk_thermal_data {
+ const char *const *sensors;
+ s32 num_sensors;
+
+ int (*extract_efuse)(struct mtk_pmic_thermal *mt, u16 *buf);
+ void (*precalc)(struct mtk_pmic_thermal *mt, s32 vts, s32 degc_cali,
+ s32 o_slope, s32 o_slope_sign);
+};
+
+struct mtk_pmic_sensor {
+ struct mtk_pmic_thermal *mt;
+ struct iio_channel *adc_channel;
+ struct thermal_zone_device *tzdev;
+
+ int id;
+};
+
+struct mtk_pmic_thermal {
+ struct device *dev;
+ struct regmap *regmap;
+ const struct mtk_thermal_data *data;
+
+ struct mtk_pmic_sensor sensors[MAX_SENSORS];
+
+ s32 t_slope1;
+ s32 t_slope2;
+ s32 t_intercept;
+};
+
+static bool mtk_pmic_thermal_temp_is_valid(int temp)
+{
+ return (temp >= MT6323_TEMP_MIN) && (temp <= MT6323_TEMP_MAX);
+}
+
+static int mtk_pmic_read_temp(struct thermal_zone_device *tz, int *temperature)
+{
+ struct mtk_pmic_sensor *sensor = thermal_zone_device_priv(tz);
+ int ret, raw, temp;
+
+ ret = iio_read_channel_processed(sensor->adc_channel, &raw);
+ if (ret < 0) {
+ dev_err(sensor->mt->dev, "failed to read iio channel: %d\n",
+ ret);
+ return ret;
+ }
+
+ /*
+ * slope1 * V
+ * t = Intercept + ----------
+ * slope2
+ */
+ temp = sensor->mt->t_intercept +
+ (sensor->mt->t_slope1 * raw) / sensor->mt->t_slope2;
+
+ if (!mtk_pmic_thermal_temp_is_valid(temp))
+ return -EINVAL;
+
+ *temperature = temp;
+ return 0;
+}
+
+static const struct thermal_zone_device_ops mtk_pmic_thermal_ops = {
+ .get_temp = mtk_pmic_read_temp,
+};
+
+static void mtk_pmic_thermal_precalc_mt6323(struct mtk_pmic_thermal *mt,
+ s32 vts, s32 degc_cali, s32 o_slope,
+ s32 o_slope_sign)
+{
+ s32 vbe_t;
+
+ mt->t_slope1 = 100 * MILLIDEGREE_PER_DEGREE;
+
+ /*
+ * Temperature coefficient. The o_slope is a trim value applied to
+ * the base calibration
+ */
+ if (o_slope_sign == 0)
+ mt->t_slope2 = -(MT6323_CALIBRATION + o_slope);
+ else
+ mt->t_slope2 = -(MT6323_CALIBRATION - o_slope);
+
+ /*
+ * (Vraw + offset) * Vref
+ * Vbe (mV) = -1 * ---------------------- * 1000
+ * adc_resolution
+ */
+ vbe_t = (vts + MT6323_ADC_VBE_OFFSET) * MT6323_ADC_VOLTAGE_RANGE;
+ vbe_t = -1 * (vbe_t / MT6323_ADC_RESOLUTION) * MILLIDEGREE_PER_DEGREE;
+
+ /* Intercept adjusts minimal temperature margin with degc_cali offset */
+ mt->t_intercept = vbe_t * 100 / mt->t_slope2;
+ mt->t_intercept += degc_cali * MILLIDEGREE_PER_DEGREE / 2;
+}
+
+static int mtk_pmic_thermal_extract_efuse_mt6323(struct mtk_pmic_thermal *mt,
+ u16 *buf)
+{
+ u32 reg;
+ s32 vts, degc_cali, o_slope, o_slope_sign, id;
+ int ret;
+
+ if (!FIELD_GET(CALIB_BUF0_ADC_CALI_EN_MASK, buf[0]))
+ return -EINVAL;
+
+ /* Voltage offset */
+ vts = (FIELD_GET(CALIB_BUF1_VTS_MASK, buf[1]) << 8) |
+ FIELD_GET(CALIB_BUF0_VTS_MASK, buf[0]);
+
+ /* Reference temperature for the vts */
+ degc_cali = FIELD_GET(CALIB_BUF0_DEGC_CALI_MASK, buf[0]);
+
+ o_slope_sign = FIELD_GET(CALIB_BUF1_O_SLOPE_SIGN_MASK, buf[1]);
+
+ ret = regmap_read(mt->regmap, MT6323_CID, ®);
+ if (ret) {
+ dev_err(mt->dev, "failed to read chip id\n");
+ return ret;
+ }
+
+ if (reg == 0x1023) {
+ o_slope = FIELD_GET(CALIB_BUF1_O_SLOPE_10_MASK, buf[1]);
+ id = FIELD_GET(CALIB_BUF1_ID_10_MASK, buf[1]);
+ } else if (reg == 0x2023) {
+ o_slope = (FIELD_GET(CALIB_BUF1_O_SLOPE_20_HI, buf[1]) << 3) |
+ FIELD_GET(CALIB_BUF1_O_SLOPE_20_LO, buf[1]);
+ id = FIELD_GET(CALIB_BUF1_ID_20_MASK, buf[1]);
+ } else {
+ dev_err(mt->dev, "invalid chip id: 0x%x\n", reg);
+ return -EINVAL;
+ }
+
+ if (id == 0)
+ o_slope = 0;
+
+ mt->data->precalc(mt, vts, degc_cali, o_slope, o_slope_sign);
+
+ return 0;
+}
+
+static int mtk_pmic_thermal_get_calib_data(struct device *dev,
+ struct mtk_pmic_thermal *mt)
+{
+ void *buf __free(kfree) = NULL;
+ struct nvmem_cell *cell;
+ size_t len;
+ int ret;
+
+ cell = nvmem_cell_get(dev, NULL);
+ if (IS_ERR(cell))
+ return PTR_ERR(cell);
+
+ buf = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+
+ if (IS_ERR(buf)) {
+ ret = PTR_ERR(buf);
+ buf = NULL;
+ return ret;
+ }
+
+ if (len < 2 * sizeof(u16)) {
+ dev_err(dev, "invalid calibration data length\n");
+ return -EINVAL;
+ }
+
+ ret = mt->data->extract_efuse(mt, buf);
+ if (ret) {
+ dev_info(dev, "device not calibrated, using default values\n");
+ mt->data->precalc(mt, MT6323_DEFAULT_VTS,
+ MT6323_DEFAULT_DEGC_CALI,
+ MT6323_DEFAULT_SLOPE,
+ MT6323_DEFAULT_SLOPE_SIGN);
+ }
+
+ return 0;
+}
+
+static int mtk_pmic_thermal_init_sensor(struct mtk_pmic_thermal *mt, int id)
+{
+ struct mtk_pmic_sensor *sensor = &mt->sensors[id];
+ struct device *dev = mt->dev;
+
+ sensor->id = id;
+ sensor->mt = mt;
+
+ if (mt->data->num_sensors > 1)
+ sensor->adc_channel = devm_iio_channel_get(dev, mt->data->sensors[id]);
+ else
+ sensor->adc_channel = devm_iio_channel_get(dev, NULL);
+
+ if (IS_ERR(sensor->adc_channel))
+ return dev_err_probe(dev, PTR_ERR(sensor->adc_channel),
+ "failed to get channel %s\n",
+ mt->data->sensors[id]);
+
+ sensor->tzdev = devm_thermal_of_zone_register(dev, id, sensor,
+ &mtk_pmic_thermal_ops);
+ if (IS_ERR(sensor->tzdev))
+ return dev_err_probe(dev, PTR_ERR(sensor->tzdev),
+ "failed to register thermal zone %d\n", id);
+
+ return 0;
+}
+
+static int mtk_pmic_thermal_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_pmic_thermal *mt;
+ int ret;
+
+ mt = devm_kzalloc(dev, sizeof(*mt), GFP_KERNEL);
+ if (!mt)
+ return -ENOMEM;
+
+ mt->regmap = dev_get_regmap(dev->parent->parent, NULL);
+ if (!mt->regmap)
+ return dev_err_probe(dev, -ENODEV, "failed to get regmap");
+
+ mt->dev = dev;
+ mt->data = device_get_match_data(dev);
+
+ ret = mtk_pmic_thermal_get_calib_data(dev, mt);
+ if (ret)
+ return ret;
+
+ for (int i = 0; i < mt->data->num_sensors; i++) {
+ ret = mtk_pmic_thermal_init_sensor(mt, i);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const char *const mt6323_adc_channels[] = { "vts" };
+
+static const struct mtk_thermal_data mt6323_thermal_data = {
+ .sensors = mt6323_adc_channels,
+ .num_sensors = ARRAY_SIZE(mt6323_adc_channels),
+ .extract_efuse = mtk_pmic_thermal_extract_efuse_mt6323,
+ .precalc = mtk_pmic_thermal_precalc_mt6323,
+};
+
+static const struct of_device_id mtk_pmic_thermal_of_match[] = {
+ { .compatible = "mediatek,mt6323-thermal",
+ .data = &mt6323_thermal_data },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_pmic_thermal_of_match);
+
+static struct platform_driver mtk_pmic_thermal_driver = {
+ .probe = mtk_pmic_thermal_probe,
+ .driver = {
+ .name = "mtk-pmic-thermal",
+ .of_match_table = mtk_pmic_thermal_of_match,
+ },
+};
+module_platform_driver(mtk_pmic_thermal_driver);
+
+MODULE_DESCRIPTION("MediaTek PMIC thermal driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH v2 02/16] dt-bindings: iio: adc: mt6359: add mt6323 PMIC AUXADC
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The MediaTek mt6323 PMIC includes an AUXADC used for battery voltage,
temperature, and other internal measurements.
Add the devicetree binding documentation and the associated header file
defining the ADC channel constants.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
.../bindings/iio/adc/mediatek,mt6359-auxadc.yaml | 1 +
.../dt-bindings/iio/adc/mediatek,mt6323-auxadc.h | 24 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
index 2e8857e104f5..1cafc314b8ab 100644
--- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
@@ -19,6 +19,7 @@ description:
properties:
compatible:
enum:
+ - mediatek,mt6323-auxadc
- mediatek,mt6357-auxadc
- mediatek,mt6358-auxadc
- mediatek,mt6359-auxadc
diff --git a/include/dt-bindings/iio/adc/mediatek,mt6323-auxadc.h b/include/dt-bindings/iio/adc/mediatek,mt6323-auxadc.h
new file mode 100644
index 000000000000..6ee9a9ecffc1
--- /dev/null
+++ b/include/dt-bindings/iio/adc/mediatek,mt6323-auxadc.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6323_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6323_AUXADC_H
+
+#define MT6323_AUXADC_BATON2 0
+#define MT6323_AUXADC_CH6 1
+#define MT6323_AUXADC_BAT_TEMP 2
+#define MT6323_AUXADC_CHIP_TEMP 3
+#define MT6323_AUXADC_VCDT 4
+#define MT6323_AUXADC_BATON1 5
+#define MT6323_AUXADC_ISENSE 6
+#define MT6323_AUXADC_BATSNS 7
+#define MT6323_AUXADC_ACCDET 8
+#define MT6323_AUXADC_AUDIO0 9
+#define MT6323_AUXADC_AUDIO1 10
+#define MT6323_AUXADC_AUDIO2 11
+#define MT6323_AUXADC_AUDIO3 12
+#define MT6323_AUXADC_AUDIO4 13
+#define MT6323_AUXADC_AUDIO5 14
+#define MT6323_AUXADC_AUDIO6 15
+#define MT6323_AUXADC_AUDIO7 16
+
+#endif
--
2.54.0
^ permalink raw reply related
* [PATCH v2 08/16] mfd: mt6397-core: add mt6323 AUXADC support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC includes an AUXADC. Register the AUXADC in the mt6323
devices array to allow the corresponding driver to probe using compatible
string.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/mfd/mt6397-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 3e58d0764c7e..013b0857fb54 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -125,6 +125,9 @@ static const struct resource mt6323_pwrc_resources[] = {
static const struct mfd_cell mt6323_devs[] = {
{
+ .name = "mt6323-auxadc",
+ .of_compatible = "mediatek,mt6323-auxadc",
+ }, {
.name = "mt6323-rtc",
.num_resources = ARRAY_SIZE(mt6323_rtc_resources),
.resources = mt6323_rtc_resources,
--
2.54.0
^ permalink raw reply related
* [PATCH v2 01/16] dt-bindings: iio: adc: mt6359: generalize description for mt63xx series
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Update binding title to the MT63xx, since the list of compatibles already
includes mt6363 and mt6373 which don't belong to the mt6350 family.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
index 5d4ab701f51a..2e8857e104f5 100644
--- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/iio/adc/mediatek,mt6359-auxadc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: MediaTek MT6350 series PMIC AUXADC
+title: MediaTek MT63xx series PMIC AUXADC
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
--
2.54.0
^ permalink raw reply related
* [PATCH v2 10/16] mfd: mt6397-core: add mt6323 thermal support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC temperature can be measured using AUXADC channel.
Register the thermal in the mt6323 devices array to allow the
corresponding driver to probe using compatible string.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/mfd/mt6397-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 2d9419b80a5c..061ac242f1f8 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -151,6 +151,9 @@ static const struct mfd_cell mt6323_devs[] = {
.num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
.resources = mt6323_pwrc_resources,
.of_compatible = "mediatek,mt6323-pwrc"
+ }, {
+ .name = "mt6323-thermal",
+ .of_compatible = "mediatek,mt6323-thermal",
},
};
--
2.54.0
^ permalink raw reply related
* [PATCH v2 05/16] iio: adc: mediatek: add mt6323 PMIC AUXADC driver
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The mt6323 AUXADC is a 15-bit ADC used for system monitoring. This driver
provides support for reading various channels including battery and
charger voltages, battery and chip temperature, current sensing and
accessory detection.
Add a driver for the AUXADC found in the MediaTek mt6323 PMIC.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/iio/adc/Kconfig | 11 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/mt6323-auxadc.c | 319 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 331 insertions(+)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 60038ae8dfc4..a03614b46041 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -1137,6 +1137,17 @@ config MCP3911
This driver can also be built as a module. If so, the module will be
called mcp3911.
+config MEDIATEK_MT6323_AUXADC
+ tristate "MediaTek MT6323 PMIC AUXADC driver"
+ depends on MFD_MT6397
+ help
+ Say yes here to enable support for MediaTek MT6323 PMIC Auxiliary ADC.
+ This driver provides multiple channels for system monitoring,
+ such as battery voltage, PMIC temperature, and others.
+
+ This driver can also be built as a module. If so, the module will be
+ called mt6323-auxadc.
+
config MEDIATEK_MT6359_AUXADC
tristate "MediaTek MT6359 PMIC AUXADC driver"
depends on MFD_MT6397
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index c76550415ff1..58161750d6e3 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -99,6 +99,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MCP3564) += mcp3564.o
obj-$(CONFIG_MCP3911) += mcp3911.o
+obj-$(CONFIG_MEDIATEK_MT6323_AUXADC) += mt6323-auxadc.o
obj-$(CONFIG_MEDIATEK_MT6359_AUXADC) += mt6359-auxadc.o
obj-$(CONFIG_MEDIATEK_MT6360_ADC) += mt6360-adc.o
obj-$(CONFIG_MEDIATEK_MT6370_ADC) += mt6370-adc.o
diff --git a/drivers/iio/adc/mt6323-auxadc.c b/drivers/iio/adc/mt6323-auxadc.c
new file mode 100644
index 000000000000..2c2b495e3d38
--- /dev/null
+++ b/drivers/iio/adc/mt6323-auxadc.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 Roman Vivchar <rva333@protonmail.com>
+ *
+ * Based on drivers/iio/adc/mt6359-auxadc.c
+ */
+
+#include <linux/array_size.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/iio/iio.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/stringify.h>
+#include <linux/types.h>
+
+#include <linux/mfd/mt6397/core.h>
+#include <linux/mfd/mt6323/registers.h>
+
+#include <dt-bindings/iio/adc/mediatek,mt6323-auxadc.h>
+
+#define AUXADC_RSTB_SEL BIT(7)
+#define AUXADC_RSTB_SW BIT(5)
+
+#define AUXADC_CTL_CK BIT(5)
+
+#define AUXADC_TRIM_CH2 (3 << 10)
+#define AUXADC_TRIM_CH4 (3 << 8)
+#define AUXADC_TRIM_CH5 (3 << 4)
+#define AUXADC_TRIM_CH6 (3 << 2)
+
+#define AUXADC_VREF18_ENB_MD BIT(15)
+#define AUXADC_MD_STATUS BIT(0)
+
+#define AUXADC_GPS_STATUS BIT(1)
+
+#define AUXADC_VREF18_SELB BIT(1)
+#define AUXADC_DECI_GDLY_SEL BIT(0)
+
+#define AUXADC_VBUF_EN BIT(4)
+
+#define AUXADC_DECI_GDLY_MASK GENMASK(15, 14)
+#define AUXADC_ADC19_BUSY_MASK GENMASK(15, 1)
+#define AUXADC_RDY_MASK BIT(15)
+#define AUXADC_DATA_MASK GENMASK(14, 0)
+
+#define AUXADC_OSR_MASK GENMASK(12, 10)
+#define AUXADC_DEFAULT_OSR 3
+
+#define AUXADC_LOW_CHANNEL_MASK GENMASK(9, 0)
+#define AUXADC_AUDIO_CHANNEL_MASK GENMASK(8, 0)
+
+#define VOLTAGE_FULL_RANGE 1800
+#define AUXADC_PRECISE 32768
+
+#define MTK_PMIC_IIO_CHAN(_name, _idx, _ch_type) \
+{ \
+ .type = _ch_type, \
+ .indexed = 1, \
+ .channel = _idx, \
+ .address = _idx, \
+ .datasheet_name = __stringify(_name), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE) \
+}
+
+static const struct iio_chan_spec mt6323_auxadc_channels[] = {
+ MTK_PMIC_IIO_CHAN(baton2, MT6323_AUXADC_BATON2, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(ch6, MT6323_AUXADC_CH6, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(bat_temp, MT6323_AUXADC_BAT_TEMP, IIO_TEMP),
+ MTK_PMIC_IIO_CHAN(chip_temp, MT6323_AUXADC_CHIP_TEMP, IIO_TEMP),
+ MTK_PMIC_IIO_CHAN(vcdt, MT6323_AUXADC_VCDT, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(baton1, MT6323_AUXADC_BATON1, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(isense, MT6323_AUXADC_ISENSE, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(batsns, MT6323_AUXADC_BATSNS, IIO_VOLTAGE),
+ MTK_PMIC_IIO_CHAN(accdet, MT6323_AUXADC_ACCDET, IIO_VOLTAGE),
+};
+
+/**
+ * struct mt6323_auxadc - Main driver structure
+ * @regmap: Regmap from PWRAP
+ * @lock: Mutex to serialize AUXADC reading vs configuration
+ *
+ * The MediaTek MT6323 (as well as lot of other PMICs) have the following hierarchy:
+ * PMIC AUXADC <- PMIC MFD <- SoC PWRAP (wrapper for PWRAP FSM)
+ *
+ * Therefore, PWRAP regmap should be get using dev->parent->parent.
+ */
+struct mt6323_auxadc {
+ struct regmap *regmap;
+ struct mutex lock;
+};
+
+static u32 mt6323_auxadc_channel_to_reg(unsigned long channel)
+{
+ switch (channel) {
+ case MT6323_AUXADC_BATON2:
+ return MT6323_AUXADC_ADC6;
+ case MT6323_AUXADC_CH6:
+ return MT6323_AUXADC_ADC11;
+ case MT6323_AUXADC_BAT_TEMP:
+ return MT6323_AUXADC_ADC5;
+ case MT6323_AUXADC_CHIP_TEMP:
+ return MT6323_AUXADC_ADC4;
+ case MT6323_AUXADC_VCDT:
+ return MT6323_AUXADC_ADC2;
+ case MT6323_AUXADC_BATON1:
+ return MT6323_AUXADC_ADC3;
+ case MT6323_AUXADC_ISENSE:
+ return MT6323_AUXADC_ADC1;
+ case MT6323_AUXADC_BATSNS:
+ return MT6323_AUXADC_ADC0;
+ case MT6323_AUXADC_ACCDET:
+ return MT6323_AUXADC_ADC7;
+ default:
+ return MT6323_AUXADC_ADC17;
+ }
+}
+
+static int mt6323_auxadc_prepare_channel(struct mt6323_auxadc *auxadc)
+{
+ struct regmap *map = auxadc->regmap;
+ u32 val;
+ int ret;
+
+ ret = regmap_read(map, MT6323_AUXADC_CON19, &val);
+ if (ret)
+ return ret;
+
+ /* The ADC is idle */
+ if (!(val & AUXADC_DECI_GDLY_MASK))
+ return 0;
+
+ ret = regmap_read_poll_timeout(map, MT6323_AUXADC_ADC19, val,
+ !(val & AUXADC_ADC19_BUSY_MASK), 10, 500);
+ if (ret)
+ return ret;
+
+ return regmap_clear_bits(map, MT6323_AUXADC_CON19,
+ AUXADC_DECI_GDLY_MASK);
+}
+
+static int mt6323_auxadc_request(struct mt6323_auxadc *auxadc,
+ unsigned long channel)
+{
+ struct regmap *map = auxadc->regmap;
+ int ret;
+
+ ret = regmap_set_bits(map, MT6323_AUXADC_CON11, AUXADC_VBUF_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(map, MT6323_AUXADC_CON22, BIT(channel));
+ if (ret)
+ return ret;
+
+ return regmap_set_bits(map, MT6323_AUXADC_CON22, BIT(channel));
+}
+
+static int mt6323_auxadc_read(struct mt6323_auxadc *auxadc,
+ const struct iio_chan_spec *chan, int *out)
+{
+ struct regmap *map = auxadc->regmap;
+ u32 val, reg = mt6323_auxadc_channel_to_reg(chan->address);
+ int ret;
+
+ ret = regmap_read_poll_timeout(map, reg, val, (val & AUXADC_RDY_MASK),
+ 1 * USEC_PER_MSEC, 100 * USEC_PER_MSEC);
+ if (ret)
+ return ret;
+
+ *out = FIELD_GET(AUXADC_DATA_MASK, val);
+
+ return 0;
+}
+
+static int mt6323_auxadc_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, int *val,
+ int *val2, long mask)
+{
+ struct mt6323_auxadc *auxadc = iio_priv(indio_dev);
+ int ret, mult = 1;
+
+ if (mask == IIO_CHAN_INFO_RAW) {
+ guard(mutex)(&auxadc->lock);
+ ret = mt6323_auxadc_prepare_channel(auxadc);
+ if (ret)
+ return ret;
+
+ ret = mt6323_auxadc_request(auxadc, chan->address);
+ if (ret)
+ return ret;
+
+ fsleep(300);
+
+ ret = mt6323_auxadc_read(auxadc, chan, val);
+ if (ret)
+ return ret;
+ return IIO_VAL_INT;
+ } else if (mask == IIO_CHAN_INFO_SCALE) {
+ if (chan->channel == MT6323_AUXADC_ISENSE ||
+ chan->channel == MT6323_AUXADC_BATSNS)
+ mult = 4;
+
+ *val = mult * VOLTAGE_FULL_RANGE;
+ *val2 = AUXADC_PRECISE;
+
+ return IIO_VAL_FRACTIONAL;
+ } else
+ return -EINVAL;
+}
+
+static int mt6323_auxadc_init(struct mt6323_auxadc *auxadc)
+{
+ struct regmap *map = auxadc->regmap;
+ int ret;
+
+ ret = regmap_set_bits(map, MT6323_STRUP_CON10,
+ AUXADC_RSTB_SW | AUXADC_RSTB_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(map, MT6323_TOP_CKPDN2, AUXADC_CTL_CK);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(map, MT6323_AUXADC_CON10,
+ AUXADC_TRIM_CH2 | AUXADC_TRIM_CH4 |
+ AUXADC_TRIM_CH5 | AUXADC_TRIM_CH6);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(map, MT6323_AUXADC_CON27,
+ AUXADC_VREF18_ENB_MD | AUXADC_MD_STATUS);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(map, MT6323_AUXADC_CON19, AUXADC_GPS_STATUS);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(map, MT6323_AUXADC_CON26,
+ AUXADC_VREF18_SELB | AUXADC_DECI_GDLY_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(map, MT6323_AUXADC_CON9, AUXADC_OSR_MASK,
+ FIELD_PREP(AUXADC_OSR_MASK,
+ AUXADC_DEFAULT_OSR));
+ return ret;
+}
+
+static const struct iio_info mt6323_auxadc_iio_info = {
+ .read_raw = mt6323_auxadc_read_raw,
+};
+
+static int mt6323_auxadc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mt6323_auxadc *auxadc;
+ struct iio_dev *iio;
+ struct regmap *regmap;
+ int ret;
+
+ regmap = dev_get_regmap(dev->parent->parent, NULL);
+ if (!regmap)
+ return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
+
+ iio = devm_iio_device_alloc(dev, sizeof(*auxadc));
+ if (!iio)
+ return -ENOMEM;
+
+ auxadc = iio_priv(iio);
+ auxadc->regmap = regmap;
+
+ ret = devm_mutex_init(dev, &auxadc->lock);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to initialize mutex\n");
+
+ ret = mt6323_auxadc_init(auxadc);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to initialize auxadc\n");
+
+ iio->name = "mt6323-auxadc";
+ iio->info = &mt6323_auxadc_iio_info;
+ iio->modes = INDIO_DIRECT_MODE;
+ iio->channels = mt6323_auxadc_channels;
+ iio->num_channels = ARRAY_SIZE(mt6323_auxadc_channels);
+
+ ret = devm_iio_device_register(dev, iio);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register iio device\n");
+
+ return 0;
+}
+
+static const struct of_device_id mt6323_auxadc_of_match[] = {
+ { .compatible = "mediatek,mt6323-auxadc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6323_auxadc_of_match);
+
+static struct platform_driver mt6323_auxadc_driver = {
+ .driver = {
+ .name = "mt6323-auxadc",
+ .of_match_table = mt6323_auxadc_of_match,
+ },
+ .probe = mt6323_auxadc_probe,
+};
+module_platform_driver(mt6323_auxadc_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek MT6323 PMIC AUXADC Driver");
--
2.54.0
^ permalink raw reply related
* [PATCH v2 06/16] nvmem: add mt6323 PMIC EFUSE driver
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add support for the EFUSE controller found in the Mediatek MT6323 PMIC.
The MT6323 EFUSE stores 24 bytes of hardware-related data, such as
thermal sensor calibration values.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/nvmem/Kconfig | 11 ++++++
drivers/nvmem/Makefile | 2 ++
drivers/nvmem/mt6323-efuse.c | 86 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 99 insertions(+)
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 74ddbd0f79b0..db248a3c4e87 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -227,6 +227,17 @@ config NVMEM_MTK_EFUSE
This driver can also be built as a module. If so, the module
will be called efuse-mtk.
+config NVMEM_MT6323_EFUSE
+ tristate "Mediatek MT6323 PMIC EFUSE support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on MFD_MT6397
+ help
+ This is a driver to access hardware related data like sensor
+ calibration, etc.
+
+ This driver can also be built as a module. If so, the module
+ will be called efuse-mt6323.
+
config NVMEM_MXS_OCOTP
tristate "Freescale MXS On-Chip OTP Memory Support"
depends on ARCH_MXS || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 7252b8ec88d4..0e2b73f42b25 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -48,6 +48,8 @@ obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o
nvmem-microchip-otpc-y := microchip-otpc.o
obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o
nvmem_mtk-efuse-y := mtk-efuse.o
+obj-$(CONFIG_NVMEM_MT6323_EFUSE) += nvmem_mt6323-efuse.o
+nvmem_mt6323-efuse-y := mt6323-efuse.o
obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o
nvmem-mxs-ocotp-y := mxs-ocotp.o
obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o
diff --git a/drivers/nvmem/mt6323-efuse.c b/drivers/nvmem/mt6323-efuse.c
new file mode 100644
index 000000000000..52db62784add
--- /dev/null
+++ b/drivers/nvmem/mt6323-efuse.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2026 Roman Vivchar <rva333@protonmail.com>
+ */
+
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include <linux/mfd/mt6323/registers.h>
+
+#define MT6323_EFUSE_DOUT_BASE MT6323_EFUSE_DOUT_0_15
+#define MT6323_EFUSE_SIZE 24
+
+static int mt6323_efuse_read(void *context, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct regmap *map = context;
+ u32 tmp;
+ u16 *buf = val;
+ int ret;
+
+ /*
+ * Manual regmap_read with loop is needed, because PWRAP is not
+ * a continuous MMIO space, but rather FSM which doesn't implement
+ * necessary read callback for the regmap_read_raw and regmap_read_bulk
+ * functions.
+ */
+ for (size_t i = 0; i < bytes; i += sizeof(*buf)) {
+ ret = regmap_read(map, MT6323_EFUSE_DOUT_BASE + offset + i, &tmp);
+ if (ret)
+ return ret;
+
+ *buf++ = (u16)tmp;
+ }
+
+ return 0;
+}
+
+static int mt6323_efuse_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct nvmem_config config = {
+ .name = "mt6323-efuse",
+ .stride = 2,
+ .word_size = 2,
+ .size = MT6323_EFUSE_SIZE,
+ .reg_read = mt6323_efuse_read,
+ };
+ struct nvmem_device *nvmem;
+ struct regmap *regmap;
+
+ /* efuse -> mfd -> pwrap */
+ regmap = dev_get_regmap(dev->parent->parent, NULL);
+ if (!regmap)
+ return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
+
+ config.dev = dev;
+ config.priv = regmap;
+
+ nvmem = devm_nvmem_register(dev, &config);
+ return PTR_ERR_OR_ZERO(nvmem);
+}
+
+static const struct of_device_id mt6323_efuse_of_match[] = {
+ { .compatible = "mediatek,mt6323-efuse" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6323_efuse_of_match);
+
+static struct platform_driver mt6323_efuse_driver = {
+ .probe = mt6323_efuse_probe,
+ .driver = {
+ .name = "mt6323-efuse",
+ .of_match_table = mt6323_efuse_of_match,
+ },
+};
+module_platform_driver(mt6323_efuse_driver);
+
+MODULE_DESCRIPTION("Mediatek MT6323 PMIC EFUSE driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH v2 11/16] ARM: dts: mediatek: mt6323: add AUXADC support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add the devicetree node for the mt6323 AUXADC.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
arch/arm/boot/dts/mediatek/mt6323.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi
index c230c865116d..c070f4b0936c 100644
--- a/arch/arm/boot/dts/mediatek/mt6323.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi
@@ -14,6 +14,11 @@ pmic: mt6323 {
interrupt-controller;
#interrupt-cells = <2>;
+ mt6323_adc: adc {
+ compatible = "mediatek,mt6323-auxadc";
+ #io-channel-cells = <1>;
+ };
+
mt6323_leds: leds {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
--
2.54.0
^ permalink raw reply related
* [PATCH v2 09/16] mfd: mt6397-core: add mt6323 EFUSE support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC includes an EFUSE. Register the EFUSE in the mt6323
devices array to allow the corresponding driver to probe using compatible
string.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
drivers/mfd/mt6397-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 013b0857fb54..2d9419b80a5c 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -127,6 +127,9 @@ static const struct mfd_cell mt6323_devs[] = {
{
.name = "mt6323-auxadc",
.of_compatible = "mediatek,mt6323-auxadc",
+ }, {
+ .name = "mt6323-efuse",
+ .of_compatible = "mediatek,mt6323-efuse",
}, {
.name = "mt6323-rtc",
.num_resources = ARRAY_SIZE(mt6323_rtc_resources),
--
2.54.0
^ permalink raw reply related
* [PATCH v2 14/16] MAINTAINERS: add MediaTek mt6323 PMIC AUXADC driver maintainer
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add myself as MediaTek mt6323 AUXADC driver maintainer.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d1cc0e12fe1f..52249c301633 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16337,6 +16337,11 @@ S: Orphan
F: Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
F: drivers/mtd/nand/raw/mtk_*
+MEDIATEK PMIC AUXADC DRIVER
+M: Roman Vivchar <rva333@protonmail.com>
+S: Odd Fixes
+F: drivers/iio/adc/mt6323-auxadc.c
+
MEDIATEK PMIC LED DRIVER
M: Sen Chu <sen.chu@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
--
2.54.0
^ permalink raw reply related
* [PATCH v2 13/16] ARM: dts: mediatek: mt6323: add thermal support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add the devicetree node for the mt6323 thermal.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
arch/arm/boot/dts/mediatek/mt6323.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi
index 435936b477fa..9825e15ab4e4 100644
--- a/arch/arm/boot/dts/mediatek/mt6323.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi
@@ -6,6 +6,8 @@
*
*/
+#include <dt-bindings/iio/adc/mediatek,mt6323-auxadc.h>
+
&pwrap {
pmic: mt6323 {
compatible = "mediatek,mt6323";
@@ -21,6 +23,16 @@ mt6323_adc: adc {
mt6323_efuse: efuse {
compatible = "mediatek,mt6323-efuse";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mt6323_thermal_calibration_data: thermal-data@14 {
+ reg = <0x14 0x4>;
+ };
+ };
};
mt6323_leds: leds {
@@ -274,5 +286,24 @@ power-controller {
rtc {
compatible = "mediatek,mt6323-rtc";
};
+
+ mt6323_thermal: thermal {
+ compatible = "mediatek,mt6323-thermal";
+ nvmem-cells = <&mt6323_thermal_calibration_data>;
+
+ io-channels = <&mt6323_adc MT6323_AUXADC_CHIP_TEMP>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+};
+
+/ {
+ thermal-zones {
+ pmic_vts_thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&mt6323_thermal 0>;
+ };
};
};
--
2.54.0
^ permalink raw reply related
* [PATCH v2 15/16] MAINTAINERS: add MediaTek mt6323 PMIC EFUSE driver maintainer
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add myself as MediaTek mt6323 EFUSE driver maintainer.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 52249c301633..bf2e066f377d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16342,6 +16342,11 @@ M: Roman Vivchar <rva333@protonmail.com>
S: Odd Fixes
F: drivers/iio/adc/mt6323-auxadc.c
+MEDIATEK PMIC EFUSE DRIVER
+M: Roman Vivchar <rva333@protonmail.com>
+S: Odd Fixes
+F: drivers/nvmem/mt6323-efuse.c
+
MEDIATEK PMIC LED DRIVER
M: Sen Chu <sen.chu@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
--
2.54.0
^ permalink raw reply related
* [PATCH v2 16/16] MAINTAINERS: add MediaTek mt6323 PMIC thermal driver maintainer
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add myself as MediaTek mt6323 thermal driver maintainer.
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index bf2e066f377d..3001a713b083 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16355,6 +16355,11 @@ S: Maintained
F: Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml
F: drivers/leds/leds-mt6323.c
+MEDIATEK PMIC THERMAL DRIVER
+M: Roman Vivchar <rva333@protonmail.com>
+S: Odd Fixes
+F: drivers/thermal/mediatek/mtk_pmic_thermal.c
+
MEDIATEK RANDOM NUMBER GENERATOR SUPPORT
M: Sean Wang <sean.wang@mediatek.com>
S: Maintained
--
2.54.0
^ permalink raw reply related
* [PATCH v2 12/16] ARM: dts: mediatek: mt6323: add EFUSE support
From: Roman Vivchar via B4 Relay @ 2026-05-12 5:18 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Sen Chu, Sean Wang, Macpaul Lin,
Lee Jones, Roman Vivchar, Srinivas Kandagatla, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-pm, Ben Grisdale
In-Reply-To: <20260512-mt6323-v2-0-3efcba579e88@protonmail.com>
From: Roman Vivchar <rva333@protonmail.com>
Add the efuse node for the mt6323 efuse.
Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
Signed-off-by: Roman Vivchar <rva333@protonmail.com>
---
arch/arm/boot/dts/mediatek/mt6323.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi
index c070f4b0936c..435936b477fa 100644
--- a/arch/arm/boot/dts/mediatek/mt6323.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi
@@ -19,6 +19,10 @@ mt6323_adc: adc {
#io-channel-cells = <1>;
};
+ mt6323_efuse: efuse {
+ compatible = "mediatek,mt6323-efuse";
+ };
+
mt6323_leds: leds {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
--
2.54.0
^ permalink raw reply related
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