* Re: [PATCH v3 1/4] dt-bindings: remoteproc: add imx-rproc-psci
From: Krzysztof Kozlowski @ 2026-05-14 11:38 UTC (permalink / raw)
To: Jiafei Pan
Cc: andersson, mathieu.poirier, peng.fan, Frank.Li, s.hauer, kernel,
festevam, imx, linux-arm-kernel, linux-kernel, Zhiqiang.Hou,
mingkai.hu, linux-remoteproc, devicetree
In-Reply-To: <20260511023928.39640-2-Jiafei.Pan@nxp.com>
On Mon, May 11, 2026 at 10:39:25AM +0800, Jiafei Pan wrote:
> Add compatible string "fsl,imx-rproc-psci" for i.MX Cortex-A Core's
> remoteproc support.
>
> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
>
> ---
> Changes in v3:
> - Fixed dt_binding_check warnings
>
> ---
> .../remoteproc/fsl,imx-rproc-psci.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml
>
> diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml
> new file mode 100644
> index 000000000000..28d00dbf8bc7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc-psci.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc-psci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX Cortex-A Core Remote Processor via PSCI
> +
> +maintainers:
> + - Jiafei Pan <Jiafei.Pan@nxp.com>
> +
> +description:
> + This binding provides support for managing Cortex-A cores as remote
Describe the hardware, not the binding.
> + processors on i.MX platforms using the PSCI (Power State Coordination
> + Interface) for CPU power management operations. This allows single
> + Cortex-A core or multiple Cortex-A cores to be controlled by Linux as
> + a remote processor, enabling them to run RTOS or bare-metal applications.
> +
> +properties:
> + compatible:
> + const: fsl,imx-rproc-psci
Why isn't the compatible specific?
> +
> + fsl,cpus-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Bitmask indicating which CPU cores are assigned to this remote
> + processor instance. Each bit represents a CPU core, where bit N
> + corresponds to CPU N. For example, 0x2 (0b10) assigns CPU core 1,
> + while 0x6 (0b110) assigns CPU cores 1 and 2.
So you partition existing Cortex-A cores? Or how exactly? Why isn't this
deducible from the compatible (I assume you read carefully writing
bindings)?
> +
> + memory-region:
> + maxItems: 1
> + description:
> + Phandle to a reserved memory region to be used for the remote
> + processor's code and data.
> +
> +required:
> + - compatible
> + - fsl,cpus-mask
> + - memory-region
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + remoteproc-ca55-1 {
Implement previous comments.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v3] clocksource: move NXP timer selection to drivers/clocksource
From: Enric Balletbo i Serra @ 2026-05-14 11:14 UTC (permalink / raw)
To: Russell King, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Daniel Lezcano, Thomas Gleixner
Cc: linux-arm-kernel, imx, linux-kernel, Enric Balletbo i Serra
From: Enric Balletbo i Serra <eballetb@redhat.com>
The Kconfig logic for selecting the scheduler clocksource on
NXP Vybrid (VF610) uses a `choice` block restricted to 32-bit ARM. This
prevents 64-bit architectures, such as the NXP S32 family, from enabling
the NXP Periodic Interrupt Timer (PIT) driver (CONFIG_NXP_PIT_TIMER).
Relocate the NXP clocksource selection from arch/arm/mach-imx/Kconfig to
drivers/clocksource/Kconfig. This allows the configuration to be shared
across different architectures.
Update the selection to include support for ARCH_S32 and add a "None"
option restricted to ARCH_S32, since Vybrid lacks the ARM Architected
Timer. The Vybrid Global Timer option is restricted to ARCH_MULTI_V7
SOC_VF610 platforms to prevent it from being visible on Cortex-M4 builds,
which lack the ARM Global Timer hardware.
Fixes: bee33f22d7c3 ("clocksource/drivers/nxp-pit: Add NXP Automotive s32g2 / s32g3 support")
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Enric Balletbo i Serra <eballetb@redhat.com>
---
Changes in v3:
- Restrict VF_TIMER_NONE to ARCH_S32 to prevent selecting it on Vybrid
platforms which lack the ARM Architected Timer
- Link to v2: https://lore.kernel.org/r/20260513-fix-nxp-timer-v2-1-533b99c57b67@redhat.com
Changes in v2:
- Fix VF_USE_ARM_GLOBAL_TIMER dependency: use ARCH_MULTI_V7 instead of
ARM to prevent the option from being visible on Cortex-M4 builds
(Sashiko AI review)
- Link to v1: https://lore.kernel.org/r/20260302-fix-nxp-timer-v1-1-af4bc62d4ffa@redhat.com
---
arch/arm/mach-imx/Kconfig | 21 ---------------------
drivers/clocksource/Kconfig | 31 +++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 6ea1bd55acf8..a361840d7a04 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -227,27 +227,6 @@ config SOC_VF610
help
This enables support for Freescale Vybrid VF610 processor.
-choice
- prompt "Clocksource for scheduler clock"
- depends on SOC_VF610
- default VF_USE_ARM_GLOBAL_TIMER
-
- config VF_USE_ARM_GLOBAL_TIMER
- bool "Use ARM Global Timer"
- depends on ARCH_MULTI_V7
- select ARM_GLOBAL_TIMER
- select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
- help
- Use the ARM Global Timer as clocksource
-
- config VF_USE_PIT_TIMER
- bool "Use PIT timer"
- select NXP_PIT_TIMER
- help
- Use SoC Periodic Interrupt Timer (PIT) as clocksource
-
-endchoice
-
endif
endif
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index d1a33a231a44..d9c76dd443f8 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -793,4 +793,35 @@ config RTK_SYSTIMER
this option only when building for a Realtek platform or for compilation
testing.
+choice
+ prompt "NXP clocksource for scheduler clock"
+ depends on SOC_VF610 || ARCH_S32
+ # Default to Global Timer for Vybrid (32-bit)
+ default VF_USE_ARM_GLOBAL_TIMER if SOC_VF610
+ # Default to None for S32 (64-bit)
+ default VF_TIMER_NONE if ARCH_S32
+
+ config VF_USE_ARM_GLOBAL_TIMER
+ bool "Use NXP Vybrid Global Timer"
+ depends on ARCH_MULTI_V7 && SOC_VF610
+ select ARM_GLOBAL_TIMER
+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ help
+ Use the NXP Vybrid Global Timer as clocksource.
+
+ config VF_USE_PIT_TIMER
+ bool "Use NXP PIT timer"
+ select NXP_PIT_TIMER
+ help
+ Use NXP Periodic Interrupt Timer (PIT) as clocksource.
+
+ config VF_TIMER_NONE
+ bool "None (Use standard Arch Timer)"
+ depends on ARCH_S32
+ help
+ Do not use any specific NXP timer driver. Use the standard
+ ARM Architected Timer instead.
+
+endchoice
+
endmenu
---
base-commit: 7fd2df204f342fc17d1a0bfcd474b24232fb0f32
change-id: 20260302-fix-nxp-timer-9cb1fbd7afcd
Best regards,
--
Enric Balletbo i Serra <eballetb@redhat.com>
^ permalink raw reply related
* Re: [PATCH v5 1/3] firmware: smccc: coco: Manage arm-smccc platform device and CCA auxiliary drivers
From: Suzuki K Poulose @ 2026-05-14 11:04 UTC (permalink / raw)
To: Aneesh Kumar K.V (Arm), linux-coco, linux-arm-kernel,
linux-kernel
Cc: Catalin Marinas, Greg KH, Jeremy Linton, Jonathan Cameron,
Lorenzo Pieralisi, Mark Rutland, Sudeep Holla, Will Deacon,
Steven Price
In-Reply-To: <20260514094030.42495-2-aneesh.kumar@kernel.org>
Hi Aneesh
On 14/05/2026 10:40, Aneesh Kumar K.V (Arm) wrote:
> Make the SMCCC driver responsible for registering the arm-smccc platform
> device and after confirming the relevant SMCCC function IDs, create
> the arm_cca_guest auxiliary device.
>
There are a few changes squashed in to this patch. Please could we
split the patch in the following order ?
1. Add platform device for arm-smccc
2. Move TRNG to Auxilliary Device - (Even though it is a later patch,
move it before the RSI changes)
3. Move RSI dev as Auxilliary
4. Add the firmware sysfs ABI.
That way, first two could be merged while we figure out (3) and (4)
> Also update the arm-cca-guest driver to use the auxiliary device
> interface instead of the platform device (arm-cca-dev). The removal of
> the platform device registration will follow in a subsequent patch,
> allowing this change to be applied without immediately breaking existing
> userspace dependencies [1].
>
> [1] https://lore.kernel.org/all/4a7d84b2-2ec4-4773-a2d5-7b63d5c683cf@arm.com
>
> Signed-off-by: Aneesh Kumar K.V (Arm) <aneesh.kumar@kernel.org>
> ---
> arch/arm64/include/asm/rsi.h | 2 +-
> arch/arm64/kernel/rsi.c | 2 +-
> drivers/firmware/smccc/Kconfig | 1 +
> drivers/firmware/smccc/Makefile | 1 +
> drivers/firmware/smccc/rmm.c | 24 ++++++++
> drivers/firmware/smccc/rmm.h | 17 ++++++
> drivers/firmware/smccc/smccc.c | 17 ++++++
> drivers/virt/coco/arm-cca-guest/Kconfig | 1 +
> drivers/virt/coco/arm-cca-guest/Makefile | 2 +
> .../{arm-cca-guest.c => arm-cca.c} | 59 +++++++++----------
> 10 files changed, 94 insertions(+), 32 deletions(-)
> create mode 100644 drivers/firmware/smccc/rmm.c
> create mode 100644 drivers/firmware/smccc/rmm.h
> rename drivers/virt/coco/arm-cca-guest/{arm-cca-guest.c => arm-cca.c} (84%)
>
> diff --git a/arch/arm64/include/asm/rsi.h b/arch/arm64/include/asm/rsi.h
> index 88b50d660e85..2d2d363aaaee 100644
> --- a/arch/arm64/include/asm/rsi.h
> +++ b/arch/arm64/include/asm/rsi.h
> @@ -10,7 +10,7 @@
> #include <linux/jump_label.h>
> #include <asm/rsi_cmds.h>
>
> -#define RSI_PDEV_NAME "arm-cca-dev"
> +#define RSI_DEV_NAME "arm-rsi-dev"
>
> DECLARE_STATIC_KEY_FALSE(rsi_present);
>
> diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c
> index 9e846ce4ef9c..8380e5ba88d2 100644
> --- a/arch/arm64/kernel/rsi.c
> +++ b/arch/arm64/kernel/rsi.c
> @@ -161,7 +161,7 @@ void __init arm64_rsi_init(void)
> }
>
> static struct platform_device rsi_dev = {
> - .name = RSI_PDEV_NAME,
> + .name = "arm-cca-dev",
> .id = PLATFORM_DEVID_NONE
> };
>
> diff --git a/drivers/firmware/smccc/Kconfig b/drivers/firmware/smccc/Kconfig
> index 15e7466179a6..2b6984757241 100644
> --- a/drivers/firmware/smccc/Kconfig
> +++ b/drivers/firmware/smccc/Kconfig
> @@ -8,6 +8,7 @@ config HAVE_ARM_SMCCC
> config HAVE_ARM_SMCCC_DISCOVERY
> bool
> depends on ARM_PSCI_FW
> + select AUXILIARY_BUS
> default y
> help
> SMCCC v1.0 lacked discoverability and hence PSCI v1.0 was updated
> diff --git a/drivers/firmware/smccc/Makefile b/drivers/firmware/smccc/Makefile
> index 40d19144a860..146dc3c03c20 100644
> --- a/drivers/firmware/smccc/Makefile
> +++ b/drivers/firmware/smccc/Makefile
> @@ -2,3 +2,4 @@
> #
> obj-$(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) += smccc.o kvm_guest.o
> obj-$(CONFIG_ARM_SMCCC_SOC_ID) += soc_id.o
> +obj-$(CONFIG_ARM64) += rmm.o
> diff --git a/drivers/firmware/smccc/rmm.c b/drivers/firmware/smccc/rmm.c
> new file mode 100644
> index 000000000000..728338cb5a22
> --- /dev/null
> +++ b/drivers/firmware/smccc/rmm.c
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2026 Arm Limited
> + */
> +
> +#include <linux/auxiliary_bus.h>
> +
> +#include "rmm.h"
> +
> +void __init register_rsi_device(struct platform_device *pdev)
> +{
> + unsigned long ret;
> + unsigned long ver_lower, ver_higher;
> +
> + if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_SMC)
> + return;
> +
> + ret = rsi_request_version(RSI_ABI_VERSION, &ver_lower, &ver_higher);
> + if (ret != RSI_SUCCESS)
> + return;
> +
> + __devm_auxiliary_device_create(&pdev->dev,
> + "arm_cca_guest", RSI_DEV_NAME, NULL, 0);
> +}
> diff --git a/drivers/firmware/smccc/rmm.h b/drivers/firmware/smccc/rmm.h
> new file mode 100644
> index 000000000000..a47a650d4f51
> --- /dev/null
> +++ b/drivers/firmware/smccc/rmm.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _SMCCC_RMM_H
> +#define _SMCCC_RMM_H
> +
> +#include <linux/platform_device.h>
> +
> +#ifdef CONFIG_ARM64
> +#include <asm/rsi_cmds.h>
> +void __init register_rsi_device(struct platform_device *pdev);
> +#else
> +
> +static void __init register_rsi_device(struct platform_device *pdev)
> +{
> +
> +}
> +#endif
> +#endif
> diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
> index bdee057db2fd..eb077b9aa6da 100644
> --- a/drivers/firmware/smccc/smccc.c
> +++ b/drivers/firmware/smccc/smccc.c
> @@ -12,6 +12,8 @@
> #include <linux/platform_device.h>
> #include <asm/archrandom.h>
>
> +#include "rmm.h"
> +
> static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
> static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
>
> @@ -85,6 +87,21 @@ static int __init smccc_devices_init(void)
> {
> struct platform_device *pdev;
>
> + if (smccc_conduit == SMCCC_CONDUIT_NONE)
> + return 0;
> +
> + pdev = platform_device_register_simple("arm-smccc",
> + PLATFORM_DEVID_NONE, NULL, 0);
> + if (IS_ERR(pdev)) {
> + pr_err("arm-smccc: could not register device: %ld\n", PTR_ERR(pdev));
> + } else {
> + /*
> + * Register the RMI and RSI devices only when firmware exposes
> + * the required SMCCC function IDs at a supported revision.
> + */
> + register_rsi_device(pdev);
> + }
> +
> if (smccc_trng_available) {
> pdev = platform_device_register_simple("smccc_trng", -1,
> NULL, 0);
> diff --git a/drivers/virt/coco/arm-cca-guest/Kconfig b/drivers/virt/coco/arm-cca-guest/Kconfig
> index 3f0f013f03f1..a42359a90558 100644
> --- a/drivers/virt/coco/arm-cca-guest/Kconfig
> +++ b/drivers/virt/coco/arm-cca-guest/Kconfig
> @@ -2,6 +2,7 @@ config ARM_CCA_GUEST
> tristate "Arm CCA Guest driver"
> depends on ARM64
> select TSM_REPORTS
> + select AUXILIARY_BUS
> help
> The driver provides userspace interface to request and
> attestation report from the Realm Management Monitor(RMM).
> diff --git a/drivers/virt/coco/arm-cca-guest/Makefile b/drivers/virt/coco/arm-cca-guest/Makefile
> index 69eeba08e98a..75a120e24fda 100644
> --- a/drivers/virt/coco/arm-cca-guest/Makefile
> +++ b/drivers/virt/coco/arm-cca-guest/Makefile
> @@ -1,2 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_ARM_CCA_GUEST) += arm-cca-guest.o
> +
> +arm-cca-guest-y += arm-cca.o
> diff --git a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c b/drivers/virt/coco/arm-cca-guest/arm-cca.c
> similarity index 84%
> rename from drivers/virt/coco/arm-cca-guest/arm-cca-guest.c
> rename to drivers/virt/coco/arm-cca-guest/arm-cca.c
> index 0c9ea24a200c..7daada072cc0 100644
> --- a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c
> +++ b/drivers/virt/coco/arm-cca-guest/arm-cca.c
> @@ -3,6 +3,7 @@
> * Copyright (C) 2023 ARM Ltd.
> */
>
> +#include <linux/auxiliary_bus.h>
> #include <linux/arm-smccc.h>
> #include <linux/cc_platform.h>
> #include <linux/kernel.h>
> @@ -181,52 +182,50 @@ static int arm_cca_report_new(struct tsm_report *report, void *data)
> return ret;
> }
>
> -static const struct tsm_report_ops arm_cca_tsm_ops = {
> +static const struct tsm_report_ops arm_cca_tsm_report_ops = {
> .name = KBUILD_MODNAME,
> .report_new = arm_cca_report_new,
> };
>
> -/**
> - * arm_cca_guest_init - Register with the Trusted Security Module (TSM)
> - * interface.
> - *
> - * Return:
> - * * %0 - Registered successfully with the TSM interface.
> - * * %-ENODEV - The execution context is not an Arm Realm.
> - * * %-EBUSY - Already registered.
> - */
> -static int __init arm_cca_guest_init(void)
> +static void unregister_cca_tsm_report(void *data)
> +{
> + tsm_report_unregister(&arm_cca_tsm_report_ops);
> +}
> +
> +static int cca_devsec_tsm_probe(struct auxiliary_device *adev,
super minor nit: While I understand you plan to use this for DEV SEC TSM
in the future, could we retain the generic TSM name usage ?
> + const struct auxiliary_device_id *id)
> {
> int ret;
>
> if (!is_realm_world())
> return -ENODEV;
>
> - ret = tsm_report_register(&arm_cca_tsm_ops, NULL);
> - if (ret < 0)
> - pr_err("Error %d registering with TSM\n", ret);
> + ret = tsm_report_register(&arm_cca_tsm_report_ops, NULL);
> + if (ret < 0) {
> + dev_err_probe(&adev->dev, ret, "Error registering with TSM\n");
> + return ret;
> + }
>
> - return ret;
> -}
> -module_init(arm_cca_guest_init);
> + ret = devm_add_action_or_reset(&adev->dev, unregister_cca_tsm_report, NULL);
> + if (ret < 0) {
> + dev_err_probe(&adev->dev, ret, "Error registering devm action\n");
> + return ret;
> + }
>
> -/**
> - * arm_cca_guest_exit - unregister with the Trusted Security Module (TSM)
> - * interface.
> - */
> -static void __exit arm_cca_guest_exit(void)
> -{
> - tsm_report_unregister(&arm_cca_tsm_ops);
> + return 0;
> }
> -module_exit(arm_cca_guest_exit);
>
> -/* modalias, so userspace can autoload this module when RSI is available */
> -static const struct platform_device_id arm_cca_match[] __maybe_unused = {
> - { RSI_PDEV_NAME, 0},
> - { }
> +static const struct auxiliary_device_id cca_devsec_tsm_id_table[] = {
same as above, s/devsec_// ?
Suzuki
> + { .name = KBUILD_MODNAME "." RSI_DEV_NAME },
> + {}
> };
> +MODULE_DEVICE_TABLE(auxiliary, cca_devsec_tsm_id_table);
>
> -MODULE_DEVICE_TABLE(platform, arm_cca_match);
> +static struct auxiliary_driver cca_devsec_tsm_driver = {
> + .probe = cca_devsec_tsm_probe,
> + .id_table = cca_devsec_tsm_id_table,
> +};
> +module_auxiliary_driver(cca_devsec_tsm_driver);
> MODULE_AUTHOR("Sami Mujawar <sami.mujawar@arm.com>");
> MODULE_DESCRIPTION("Arm CCA Guest TSM Driver");
> MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: [PATCH 4/5] ARM: dts: qcom: msm8974-oneplus-bacon: Fix sn3193 shutdown GPIO polarity
From: Konrad Dybcio @ 2026-05-14 10:58 UTC (permalink / raw)
To: Jun Yan, Lee Jones, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Vincent Knecht, Grant Feng, Andre Przywara, Florian Fainelli,
Heiko Stuebner, Michal Simek, Wei Xu, Robert Marko
Cc: Pavel Machek, Krzysztof Kozlowski, Alexandre TORGUE,
Jisheng Zhang, Enric Balletbo i Serra, Romain Perier, linux-leds,
devicetree, linux-kernel, linux-arm-msm, linux-arm-kernel
In-Reply-To: <20260508152435.21389-5-jerrysteve1101@gmail.com>
On 5/8/26 5:24 PM, Jun Yan wrote:
> The sn3193 shutdown pin is active-low[1]. Correct the GPIO flags
> from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW to match the hardware.
>
> [1] https://lumissil.com/assets/pdf/core/IS31FL3193_DS.pdf
>
> Fixes: 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories")
> Signed-off-by: Jun Yan <jerrysteve1101@gmail.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 3/5] arm64: dts: qcom: msm8916-alcatel-idol347: Fix sn3190 shutdown GPIO polarity
From: Konrad Dybcio @ 2026-05-14 10:58 UTC (permalink / raw)
To: Jun Yan, Lee Jones, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Vincent Knecht, Grant Feng, Andre Przywara, Heiko Stuebner,
Romain Perier, Paul Barker, Patrice Chotard, Robert Marko
Cc: Pavel Machek, Krzysztof Kozlowski, Jesper Nilsson, Peter Rosin,
linux-leds, devicetree, linux-kernel, linux-arm-msm,
linux-arm-kernel
In-Reply-To: <20260508152435.21389-4-jerrysteve1101@gmail.com>
On 5/8/26 5:24 PM, Jun Yan wrote:
> The sn3190 shutdown pin is active-low [1]. Correct the GPIO flags
> from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW to match the hardware.
>
> [1] https://lumissil.com/assets/pdf/core/IS31FL3190_DS.pdf
>
> Fixes: 1c8cc183d070 ("arm64: dts: qcom: msm8916-alcatel-idol347: add LED indicator")
> Signed-off-by: Jun Yan <jerrysteve1101@gmail.com>
> ---
Assuming you get the other backwards compat pieces in:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v5 4/8] mfd: khadas-mcu: Add support for VIM4 MCU variant
From: Lee Jones @ 2026-05-14 10:54 UTC (permalink / raw)
To: Ronald Claveau via B4 Relay
Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andi Shyti, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Beniamino Galvani, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Liam Girdwood, Mark Brown, linux-amlogic, devicetree,
linux-kernel, linux-i2c, linux-arm-kernel, linux-pm,
Ronald Claveau
In-Reply-To: <20260424-add-mcu-fan-khadas-vim4-v5-4-afcfa7157b23@aliel.fr>
On Fri, 24 Apr 2026, Ronald Claveau via B4 Relay wrote:
> From: Ronald Claveau <linux-kernel-dev@aliel.fr>
>
> Refactor probe() to use per-variant khadas_mcu_data
> instead of hardcoded globals.
>
> Add dedicated regmap configuration and device data for the VIM4 MCU,
> with its own volatile/writeable registers.
>
> Add the fan control register
> (0–100 levels vs 0–3 for previous supported boards).
>
> Add a new compatible string "khadas,vim4-mcu".
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
> ---
> drivers/mfd/khadas-mcu.c | 106 ++++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 95 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mfd/khadas-mcu.c b/drivers/mfd/khadas-mcu.c
> index ba981a7886921..b36b3b3ab73c0 100644
> --- a/drivers/mfd/khadas-mcu.c
> +++ b/drivers/mfd/khadas-mcu.c
> @@ -75,15 +75,91 @@ static const struct regmap_config khadas_mcu_regmap_config = {
> .cache_type = REGCACHE_MAPLE,
> };
>
> +static const struct khadas_mcu_fan_pdata khadas_mcu_fan_pdata = {
> + .fan_reg = KHADAS_MCU_CMD_FAN_STATUS_CTRL_REG,
> + .max_level = 3,
> +};
What is 3?
> +
> static struct mfd_cell khadas_mcu_fan_cells[] = {
> /* VIM1/2 Rev13+ and VIM3 only */
> - { .name = "khadas-mcu-fan-ctrl", },
> + {
> + .name = "khadas-mcu-fan-ctrl",
> + .platform_data = &khadas_mcu_fan_pdata,
> + .pdata_size = sizeof(khadas_mcu_fan_pdata),
> + },
> };
Worth making this const at one point.
>
> static struct mfd_cell khadas_mcu_cells[] = {
> { .name = "khadas-mcu-user-mem", },
> };
>
> +static const struct khadas_mcu_data khadas_mcu_data = {
> + .regmap_config = &khadas_mcu_regmap_config,
> + .cells = khadas_mcu_cells,
> + .ncells = ARRAY_SIZE(khadas_mcu_cells),
> + .fan_cells = khadas_mcu_fan_cells,
> + .nfan_cells = ARRAY_SIZE(khadas_mcu_fan_cells),
> +};
This is a red flag!
> +static bool khadas_mcu_vim4_reg_volatile(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case KHADAS_MCU_PWR_OFF_CMD_REG:
> + case KHADAS_MCU_VIM4_REST_CONF_REG:
> + case KHADAS_MCU_WOL_INIT_START_REG:
> + case KHADAS_MCU_VIM4_LED_ON_RAM_REG:
> + case KHADAS_MCU_VIM4_FAN_CTRL_REG:
> + case KHADAS_MCU_VIM4_WDT_EN_REG:
> + case KHADAS_MCU_VIM4_SYS_RST_REG:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static bool khadas_mcu_vim4_reg_writeable(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case KHADAS_MCU_VERSION_0_REG:
> + case KHADAS_MCU_VERSION_1_REG:
> + case KHADAS_MCU_SHUTDOWN_NORMAL_STATUS_REG:
> + return false;
> + default:
> + return true;
> + }
> +}
> +
> +static const struct regmap_config khadas_mcu_vim4_regmap_config = {
> + .reg_bits = 8,
> + .reg_stride = 1,
> + .val_bits = 8,
> + .max_register = KHADAS_MCU_VIM4_SYS_RST_REG,
> + .volatile_reg = khadas_mcu_vim4_reg_volatile,
> + .writeable_reg = khadas_mcu_vim4_reg_writeable,
> + .cache_type = REGCACHE_MAPLE,
> +};
> +
> +static const struct khadas_mcu_fan_pdata khadas_vim4_fan_pdata = {
> + .fan_reg = KHADAS_MCU_VIM4_FAN_CTRL_REG,
> + .max_level = 0x64,
> +};
> +
> +static const struct mfd_cell khadas_mcu_vim4_cells[] = {
> + {
> + .name = "khadas-mcu-fan-ctrl",
> + .platform_data = &khadas_vim4_fan_pdata,
> + .pdata_size = sizeof(khadas_vim4_fan_pdata),
> + },
> +};
> +
> +static const struct khadas_mcu_data khadas_vim4_mcu_data = {
> + .regmap_config = &khadas_mcu_vim4_regmap_config,
> + .cells = NULL,
> + .ncells = 0,
> + .fan_cells = khadas_mcu_vim4_cells,
> + .nfan_cells = ARRAY_SIZE(khadas_mcu_vim4_cells),
> +};
> +
> static int khadas_mcu_probe(struct i2c_client *client)
> {
> struct device *dev = &client->dev;
> @@ -94,28 +170,35 @@ static int khadas_mcu_probe(struct i2c_client *client)
> if (!ddata)
> return -ENOMEM;
>
> + ddata->data = i2c_get_match_data(client);
> + if (!ddata->data)
> + return -EINVAL;
Shouldn't this be -ENODEV?
> i2c_set_clientdata(client, ddata);
>
> ddata->dev = dev;
>
> - ddata->regmap = devm_regmap_init_i2c(client, &khadas_mcu_regmap_config);
> + ddata->regmap = devm_regmap_init_i2c(client,
> + ddata->data->regmap_config);
Use up to 100-chars to prevent this kind of wrapping.
> if (IS_ERR(ddata->regmap)) {
> ret = PTR_ERR(ddata->regmap);
> dev_err(dev, "Failed to allocate register map: %d\n", ret);
> return ret;
> }
Maybe convert this to dev_err_probe() at one point.
> - ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
> - khadas_mcu_cells,
> - ARRAY_SIZE(khadas_mcu_cells),
> - NULL, 0, NULL);
> - if (ret)
> - return ret;
> + if (ddata->data->cells && ddata->data->ncells) {
> + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
> + ddata->data->cells,
> + ddata->data->ncells,
> + NULL, 0, NULL);
> + if (ret)
> + return ret;
> + }
>
> if (of_property_present(dev->of_node, "#cooling-cells"))
> return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
> - khadas_mcu_fan_cells,
> - ARRAY_SIZE(khadas_mcu_fan_cells),
> + ddata->data->fan_cells,
> + ddata->data->nfan_cells,
> NULL, 0, NULL);
>
> return 0;
> @@ -123,7 +206,8 @@ static int khadas_mcu_probe(struct i2c_client *client)
>
> #ifdef CONFIG_OF
> static const struct of_device_id khadas_mcu_of_match[] = {
> - { .compatible = "khadas,mcu", },
> + { .compatible = "khadas,mcu", .data = &khadas_mcu_data },
> + { .compatible = "khadas,vim4-mcu", .data = &khadas_vim4_mcu_data },
We don't allow data from one registration API (MFD) to be shoved through
another (DT). Pass a value to match on instead, then use a switch()
statement or similar to populate or register the devices.
> {},
> };
> MODULE_DEVICE_TABLE(of, khadas_mcu_of_match);
>
> --
> 2.49.0
>
>
^ permalink raw reply
* Re: [PATCH v5 0/3] Switch Arm CCA to use an auxiliary device instead of a platform device
From: Aneesh Kumar K.V @ 2026-05-14 10:51 UTC (permalink / raw)
To: Greg KH
Cc: linux-coco, linux-arm-kernel, linux-kernel, Catalin Marinas,
Jeremy Linton, Jonathan Cameron, Lorenzo Pieralisi, Mark Rutland,
Sudeep Holla, Will Deacon, Steven Price, Suzuki K Poulose
In-Reply-To: <2026051453-batting-delighted-0a57@gregkh>
Greg KH <gregkh@linuxfoundation.org> writes:
> On Thu, May 14, 2026 at 03:10:27PM +0530, Aneesh Kumar K.V (Arm) wrote:
>> As discussed here:
>> https://lore.kernel.org/all/20250728135216.48084-12-aneesh.kumar@kernel.org
>>
>> The general feedback was that a platform device should not be used when
>> there is no underlying platform resource to represent. The existing CCA
>> support uses a platform device solely to anchor the TSM interface in the
>> device hierarchy, which is not an appropriate use of a platform device.
>> Use an auxiliary device instead to track CCA support.
>
> Why an aux device? If this has no platform resources, please use the
> faux bus support instead, that is what it is there for. aux devices are
> used when you are sharing a real resource among different "child"
> drivers, and need some way to coordinate that sharing. If you have no
> resources, there's nothing to share, so no need for the complexity that
> aux gives you, just use faux instead.
>
We did discuss between faux an auxiliary devices early here
https://lore.kernel.org/all/20251010135922.GC3833649@ziepe.ca
To summarize auxiliary device was choosen so that we can do module
autoloading.
-aneesh
^ permalink raw reply
* Re: [PATCH 0/5] scmi: Log client subsystem entity counts
From: Sudeep Holla @ 2026-05-14 10:38 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Guenter Roeck, Andy Shevchenko, Alex Tran, Sudeep Holla,
Jyoti Bhayana, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Cristian Marussi, Linus Walleij,
Rafael J. Wysocki, Philipp Zabel, Viresh Kumar, linux-iio,
linux-kernel, arm-scmi, linux-arm-kernel, linux-gpio, linux-pm,
linux-hwmon
In-Reply-To: <2026051441-agreed-suffice-bbe1@gregkh>
On Thu, May 14, 2026 at 08:48:19AM +0200, Greg Kroah-Hartman wrote:
> On Wed, May 13, 2026 at 11:27:21AM -0700, Guenter Roeck wrote:
> > On 5/13/26 11:02, Andy Shevchenko wrote:
> > > +Greg (I believe the trend is to drop such messages and not add them [back]?)
> > >
> >
> > Is there some common guidance on this ? I'd be all for dropping messages
> > instead of adding them, but there seems to be a perpetual battle between
> > people who want to log everything and people concerned about logging noise.
> > As maintainer I always seem to be stuck between those two camps.
>
> When drivers work properly, they should be quiet. This patch series
> adds a bunch of dev_info() calls, which is not ok. If a developer wants
> to see extra messages, use the dev_dbg() infrastructure, or the tracing
> infrastructure, both of which are there for this very reason.
>
I completely agree and tend to follow that. But I always assumed it was
left to maintainers taste.
> So yes, I agree with Andy, this series is not ok, don't make more noise
> please.
>
I am now thinking if [1] was the one setting example for this series. I did
ack it as I left it to the subsystem maintainer's choice(in this case author
as well).
--
Regards,
Sudeep
[1] https://lore.kernel.org/all/20260304101457.7470-1-ulf.hansson@linaro.org/
^ permalink raw reply
* [PATCH] i2c: davinci: fix division by zero on missing clock-frequency
From: Chaitanya Sabnis @ 2026-05-14 10:37 UTC (permalink / raw)
To: brgl, andi.shyti
Cc: linux-arm-kernel, linux-i2c, linux-kernel, Chaitanya Sabnis,
Sashiko
When the 'clock-frequency' property is missing from the device tree,
the driver falls back to DAVINCI_I2C_DEFAULT_BUS_FREQ. However, this
macro is defined in kHz (100), whereas the device tree property is
expected in Hz.
The probe function blindly divided the fallback value by 1000, causing
integer truncation that resulted in dev->bus_freq = 0. This triggered
a deterministic division-by-zero kernel panic when calculating clock
dividers later in the probe sequence.
Fix this by isolating the division so it only applies to the Hz value
read from the device tree, cleanly assigning the kHz default otherwise.
Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/all/20260514044726.57297C2BCB7@smtp.kernel.org/
Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
---
drivers/i2c/busses/i2c-davinci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index a773ba082321..bd0754abdcb7 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -760,9 +760,9 @@ static int davinci_i2c_probe(struct platform_device *pdev)
r = device_property_read_u32(&pdev->dev, "clock-frequency", &prop);
if (r)
- prop = DAVINCI_I2C_DEFAULT_BUS_FREQ;
-
- dev->bus_freq = prop / 1000;
+ dev->bus_freq = DAVINCI_I2C_DEFAULT_BUS_FREQ;
+ else
+ dev->bus_freq = prop / 1000;
dev->has_pfunc = device_property_present(&pdev->dev, "ti,has-pfunc");
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 2/4] ASoC: stm: stm32_i2s: Use guard() for spin locks
From: Bui Duc Phuc @ 2026-05-14 10:33 UTC (permalink / raw)
To: Mark Brown
Cc: Olivier Moysan, Arnaud Pouliquen, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, Maxime Coquelin, Alexandre Torgue, linux-sound,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <agUknFcDIfwrOCld@sirena.co.uk>
Hi Mark,
On Thu, May 14, 2026 at 8:25 AM Mark Brown <broonie@kernel.org> wrote:
> How does scoped_guard interact with break statements - does this still
> apply to the switch? I've not looked at how they're implemented...
I checked the scoped_guard macro implementation...
and You're right the break statement inside scoped_guard only exits
the guard's implicit loop, which is not what I intended.
Since there are no further statements after the switch block in this
function, I will replace the break with return 0 to correctly exit
the function.
I'll send a v2 of the whole series with this fix.
Would that work for you?
Best regard,
Phuc
^ permalink raw reply
* Re: [RFC PATCH net-next 0/3] net: macb: candidate fixes for silent TX stall on BCM2712/RP1
From: Théo Lebrun @ 2026-05-14 10:31 UTC (permalink / raw)
To: Lukasz Raczylo, netdev
Cc: Nicolas Ferre, Claudiu Beznea, Andrew Lunn, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, linux-kernel,
linux-arm-kernel, linux-rpi-kernel
In-Reply-To: <cover.1777064117.git.lukasz@raczylo.com>
Hello Lukasz,
On Sat Apr 25, 2026 at 12:38 AM CEST, Lukasz Raczylo wrote:
> This series proposes three candidate fixes for the silent TX stall
> observed on Raspberry Pi 5 (BCM2712 SoC, Cadence GEM via RP1 PCIe
> south bridge). The bug has been reported, with reproducers, at:
I've taken over the MACB driver maintenance following Clandiu & Nicolas'
work. I have read with curiosity your series and links attached
(though I skimmed over parts because there's been a lot of discussion).
Have you moved forward since your initial post? I've seen your
still-working-on-it message from May 8th on the rpi kernel PR. I have a
few remarks and/or questions:
- You still think the two fix patches solve it? Any clearer picture of
which of the two patches inbetween [1/3] or[2/3] fixes it? Does
[3/3] ever trigger on your targets?
- Can you clarify the exact symptoms? I've seen a few contradictory
facts. Two I remember:
- You say here it is a Tx stall but I've seen messages in the linked
threads that say explicitely broken Tx & Rx.
https://github.com/cilium/cilium/issues/43198#issue-3706713821
- You say here link down/up fixes it, but there is a comment that
says they unload/reload the module (rtheobald). They don't say
explicitely that link down/up doesn't work for them though, but
someone before in the thread recommended link down/up. Another
one says "Only power cycle recovers the node" (lexfrei).
- Also, some messages point out disabling TSO / SG / EEE helped it.
Any comment on that? It would help point fingers.
- Some comments are about DT props missing. Is that lead dead now?
- I've seen no mention of the bug having been reproduced on upstream
kernel (?). What does the rpi kernel bring to the table that makes
everyone use it?
- Anything was found to increase the reproducibility of the bug? If it
was then a bisect could be made possible, as I've seen mentions that
it didn't appear on some older kernels.
Now about the patches:
> Reading the current driver we identified three plausible races
> between driver and hardware, each of which could independently
> produce the observed behaviour. We did not determine which is the
> actual root cause -- that likely requires either BCM2712/RP1
> documentation we do not have, or dynamic tracing of the driver
> during an in-situ stall. The series therefore attempts to close
> all three, with each commit message stating which specific race
> that patch is targeting.
>
> Patch 1/3 -- flush PCIe posted write after TSTART doorbell.
> Writes to NCR are posted PCIe writes and may not reach the MAC
> before the driver returns. If the TSTART doorbell is lost, no
> TX starts, no TCOMP arrives, and the ring goes quiescent. A
> read-back of NCR after the write is a standard read-after-write
> PCIe flush.
- Makes sense, but only on MACB mounted over PCI, which is not the
majority.
- IDK if we can do better than a readl(NCR) on all platforms.
- I am surprised it is the only writel() that needs to be flushed?
> Patch 2/3 -- re-check ISR after IER re-enable in macb_tx_poll().
> An existing comment in macb_tx_poll() notes that completions
> raised while TCOMP is masked do not re-fire when IER is
> re-enabled, and mitigates the window with macb_tx_complete_pending(),
> which inspects driver-visible ring state only (after rmb()). On
> PCIe-attached parts the descriptor DMA write that sets TX_USED
> can remain in flight when that check runs; the rmb() orders CPU
> writes but does not retire peripheral DMA. Reading ISR directly
> after IER re-enable addresses this in two ways: (a) the MMIO read
> is an architected PCIe read barrier for prior DMA writes, so a
> subsequent macb_tx_complete_pending() sees up-to-date TX_USED
> state; (b) it directly observes a pending TCOMP bit if the
> hardware has one set. Either signal reschedules NAPI.
This will not fly because ISR might be read-to-clear.
See macb_queue_isr_clear() and how it is used. So we cannot re-read ISR
safely on those platforms.
> Patch 3/3 -- TX stall watchdog. Defence-in-depth. If patches
> 1 and 2 close the races we identified, this patch performs a
> single spin_lock_irqsave/unlock and a branch per queue per
> second with no other effect. If a further race remains that we
> have not identified, it invokes the driver's own existing
> macb_tx_restart(), which already verifies that TBQP is behind
> tx_head before re-asserting TSTART. We include this patch
> because we have empirically observed multi-minute stalls on this
> hardware; we are willing to drop it if the preference is for
> 1 and 2 to stand alone.
Good idea, but that is what ndo_tx_timeout() is meant for no? It is a
mechanism that is not specific to our HW so that should be implemented
at the subsystem level, and it looks like it already is. :-)
We are aware of a few software scheduling races that we plan on fixing.
If your above patches ended up not fixing the issue, you could look
into those.
https://lore.kernel.org/netdev/DHIT9TPJQJ46.21A89R5UAFXVH@bootlin.com/
Thanks!
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v4 1/7] dt-bindings: clock: qcom: Add video clock controller on Qualcomm Eliza SoC
From: Taniya Das @ 2026-05-14 10:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Maxime Coquelin,
Alexandre Torgue, Luca Weiss, Ajit Pandey, Imran Shaik,
Jagadeesh Kona, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel
In-Reply-To: <20260514-obedient-crouching-bulldog-7d63a8@quoll>
On 5/14/2026 3:48 PM, Krzysztof Kozlowski wrote:
> On Wed, May 13, 2026 at 08:57:36PM +0530, Taniya Das wrote:
>> Eliza Video clock controller is on CX and MX rails similar to Milos.
>> Add compatible string for Eliza video clock controller to the existing
>> Milos videocc binding and add the dt-bindings header for Eliza.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> ---
>> .../bindings/clock/qcom,milos-videocc.yaml | 9 ++++--
>> include/dt-bindings/clock/qcom,eliza-videocc.h | 37 ++++++++++++++++++++++
>> 2 files changed, 44 insertions(+), 2 deletions(-)
>
> Please allow others to actually review your patchsets. You sent v4
> immediately without waiting for v3 review.... which did happen. So now
> please address somewhere comments for v3.
>
I have put a comment to ignore the v3 patch comment as I had missed
change in clock node, but for sure will address the v3 comments as well.
--
Thanks,
Taniya Das
^ permalink raw reply
* Re: [PATCH v5 0/3] Switch Arm CCA to use an auxiliary device instead of a platform device
From: Greg KH @ 2026-05-14 10:19 UTC (permalink / raw)
To: Aneesh Kumar K.V (Arm)
Cc: linux-coco, linux-arm-kernel, linux-kernel, Catalin Marinas,
Jeremy Linton, Jonathan Cameron, Lorenzo Pieralisi, Mark Rutland,
Sudeep Holla, Will Deacon, Steven Price, Suzuki K Poulose
In-Reply-To: <20260514094030.42495-1-aneesh.kumar@kernel.org>
On Thu, May 14, 2026 at 03:10:27PM +0530, Aneesh Kumar K.V (Arm) wrote:
> As discussed here:
> https://lore.kernel.org/all/20250728135216.48084-12-aneesh.kumar@kernel.org
>
> The general feedback was that a platform device should not be used when
> there is no underlying platform resource to represent. The existing CCA
> support uses a platform device solely to anchor the TSM interface in the
> device hierarchy, which is not an appropriate use of a platform device.
> Use an auxiliary device instead to track CCA support.
Why an aux device? If this has no platform resources, please use the
faux bus support instead, that is what it is there for. aux devices are
used when you are sharing a real resource among different "child"
drivers, and need some way to coordinate that sharing. If you have no
resources, there's nothing to share, so no need for the complexity that
aux gives you, just use faux instead.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v4 1/7] dt-bindings: clock: qcom: Add video clock controller on Qualcomm Eliza SoC
From: Krzysztof Kozlowski @ 2026-05-14 10:18 UTC (permalink / raw)
To: Taniya Das
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Maxime Coquelin,
Alexandre Torgue, Luca Weiss, Ajit Pandey, Imran Shaik,
Jagadeesh Kona, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel
In-Reply-To: <20260513-eliza_mm_cc_v2-v4-1-e61b5434e8d9@oss.qualcomm.com>
On Wed, May 13, 2026 at 08:57:36PM +0530, Taniya Das wrote:
> Eliza Video clock controller is on CX and MX rails similar to Milos.
> Add compatible string for Eliza video clock controller to the existing
> Milos videocc binding and add the dt-bindings header for Eliza.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,milos-videocc.yaml | 9 ++++--
> include/dt-bindings/clock/qcom,eliza-videocc.h | 37 ++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 2 deletions(-)
Please allow others to actually review your patchsets. You sent v4
immediately without waiting for v3 review.... which did happen. So now
please address somewhere comments for v3.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
From: Krzysztof Kozlowski @ 2026-05-14 10:16 UTC (permalink / raw)
To: Richard Zhu
Cc: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam, linux-pci,
linux-arm-kernel, devicetree, imx, linux-kernel
In-Reply-To: <20260513025101.1498104-2-hongxing.zhu@nxp.com>
On Wed, May 13, 2026 at 10:50:59AM +0800, Richard Zhu wrote:
> Add optional interrupt entries to the i.MX6Q PCIe binding to support
Describe hardware, not "binding".
> event-based interrupt handling:
Same questions as last time.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 3/6] dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU
From: Krzysztof Kozlowski @ 2026-05-14 10:14 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu
In-Reply-To: <20260513-glymur-gpu-dt-v4-3-f83832c3bc9a@oss.qualcomm.com>
On Wed, May 13, 2026 at 12:51:20AM +0530, Akhil P Oommen wrote:
> Add the interconnects property to the common SMMU properties and extend
> the sm8750 clock description section to also cover Glymur since it uses
> the same single "hlos" vote clock.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 2/6] dt-bindings: display/msm: gpu: Document Adreno X2-185
From: Krzysztof Kozlowski @ 2026-05-14 10:13 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel,
linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu
In-Reply-To: <20260513-glymur-gpu-dt-v4-2-f83832c3bc9a@oss.qualcomm.com>
On Wed, May 13, 2026 at 12:51:19AM +0530, Akhil P Oommen wrote:
> Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
> It features a new slice architecture with 4 slices, significantly higher
> bandwidth throughput compared to mobile counterparts, raytracing support,
> and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
> other improvements. Update the dt bindings documentation to describe this
> GPU.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/display/msm/gpu.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Someone needs to start applying Adreno GPU patches...
https://lore.kernel.org/all/20260301142033.88851-2-krzysztof.kozlowski@oss.qualcomm.com/
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 04b2328903ca..e67cd708dda2 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -411,6 +411,22 @@ allOf:
> - clocks
> - clock-names
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,adreno-44070001
> + then:
> + properties:
> + reg:
> + minItems: 2
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: kgsl_3d0_reg_memory
> + - const: cx_mem
Are you sure there is no cx_dbgc? If not, then just minItems+maxItems
like for 'reg:'.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 4/4] arm64: dts: mediatek: mt8195-cherry: Sort top level nodes correctly
From: Chen-Yu Tsai @ 2026-05-14 10:12 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-mediatek, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260514101254.2749300-1-wenst@chromium.org>
The thermistor device nodes were added before the vbus regulator and
reserved memory nodes, when they should be after them, based on
alphabetical order of the device node _name_.
Move them to the correct position. No functional changes intended.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 94 +++++++++----------
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 538c46ada32b..ef7afc436aef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -149,6 +149,53 @@ ppvar_sys: regulator-ppvar-sys {
regulator-boot-on;
};
+ usb_vbus: regulator-5v0-usb-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&pp5000_s5>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scp_mem: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+
+ adsp_mem: memory@60000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60000000 0 0xd80000>;
+ no-map;
+ };
+
+ afe_mem: memory@60d80000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60d80000 0 0x100000>;
+ no-map;
+ };
+
+ adsp_device_mem: memory@60e80000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x60e80000 0 0x280000>;
+ no-map;
+ };
+ };
+
+ spk_amplifier: rt1019p {
+ compatible = "realtek,rt1019p";
+ label = "rt1019p";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rt1019p_pins_default>;
+ sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
+ };
+
/* Murata NCP03WF104F05RL */
tboard_thermistor1: thermal-sensor-t1 {
compatible = "generic-adc-thermal";
@@ -219,53 +266,6 @@ tboard_thermistor2: thermal-sensor-t2 {
120000 51
125000 44>;
};
-
- usb_vbus: regulator-5v0-usb-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb-vbus";
- enable-active-high;
- regulator-always-on;
- vin-supply = <&pp5000_s5>;
- };
-
- reserved_memory: reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- scp_mem: memory@50000000 {
- compatible = "shared-dma-pool";
- reg = <0 0x50000000 0 0x2900000>;
- no-map;
- };
-
- adsp_mem: memory@60000000 {
- compatible = "shared-dma-pool";
- reg = <0 0x60000000 0 0xd80000>;
- no-map;
- };
-
- afe_mem: memory@60d80000 {
- compatible = "shared-dma-pool";
- reg = <0 0x60d80000 0 0x100000>;
- no-map;
- };
-
- adsp_device_mem: memory@60e80000 {
- compatible = "shared-dma-pool";
- reg = <0 0x60e80000 0 0x280000>;
- no-map;
- };
- };
-
- spk_amplifier: rt1019p {
- compatible = "realtek,rt1019p";
- label = "rt1019p";
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&rt1019p_pins_default>;
- sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
- };
};
&adsp {
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: mediatek: mt8195-cherry: Fix names for EC controlled regulators
From: Chen-Yu Tsai @ 2026-05-14 10:12 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-mediatek, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260514101254.2749300-1-wenst@chromium.org>
The names currently given to the EC controlled regulators do not match
what is used in the hardware design.
Fix the names and the labels.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index ca2bb367ee68..538c46ada32b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -717,8 +717,8 @@ &mmc1 {
pinctrl-1 = <&mmc1_pins_default>;
sd-uhs-sdr50;
sd-uhs-sdr104;
- vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
- vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
+ vmmc-supply = <&pp3000_sd>;
+ vqmmc-supply = <&pp3000_vmc_pmu>;
};
&mt6359codec {
@@ -1436,19 +1436,19 @@ i2c_tunnel: i2c-tunnel {
#size-cells = <0>;
};
- mt_pmic_vmc_ldo_reg: regulator@0 {
+ pp3000_vmc_pmu: regulator@0 {
compatible = "google,cros-ec-regulator";
reg = <0>;
- regulator-name = "mt_pmic_vmc_ldo";
+ regulator-name = "pp3000_vmc_pmu";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
vin-supply = <&pp4200_z2>;
};
- mt_pmic_vmch_ldo_reg: regulator@1 {
+ pp3000_sd: regulator@1 {
compatible = "google,cros-ec-regulator";
reg = <1>;
- regulator-name = "mt_pmic_vmch_ldo";
+ regulator-name = "pp3000_sd";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
vin-supply = <&pp4200_z2>;
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 2/4] arm64: dts: mediatek: mt8192-asurada: Add (BT|WIFI)_KILL_1V8_L GPIO line names
From: Chen-Yu Tsai @ 2026-05-14 10:12 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-mediatek, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260514101254.2749300-1-wenst@chromium.org>
GPIO lines 59 and 61 are named BT_KILL_1V8_L and WIFI_KILL_1V8_L in the
hardware design. Add them to the gpio-line-names property to make the
names available to users and developers.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 3c8b4c2f6f23..b7387075cb87 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -727,9 +727,9 @@ &pio {
"SD_DATA1",
"",
"",
+ "BT_KILL_1V8_L",
"",
- "",
- "",
+ "WIFI_KILL_1V8_L",
"",
"PCIE_WAKE_ODL",
"PCIE_RST_L",
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 1/4] arm64: dts: mediatek: mt8192-asurada: Fix SPI-NOR flash compatible
From: Chen-Yu Tsai @ 2026-05-14 10:12 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-mediatek, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260514101254.2749300-1-wenst@chromium.org>
For JEDEC compatible SPI NOR chips, there should be a single generic
"jedec,spi-nor" compatible.
Drop the model-specific compatible from the flash node.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 84b89b317890..3c8b4c2f6f23 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -631,7 +631,7 @@ &nor_flash {
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
flash@0 {
- compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+ compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <2>;
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 0/4] arm64: dts: mediatek: random Chromebook cleanups
From: Chen-Yu Tsai @ 2026-05-14 10:12 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno
Cc: Chen-Yu Tsai, linux-mediatek, devicetree, linux-arm-kernel,
linux-kernel
Hi,
Here are some random DT cleanups that are not directly related to other
topics I'm working on, but came up when checking for warnings.
The regulator related changes overlap with my other "Regulator cleanup
for Chromebooks" series [1].
Please have a look.
Thanks
ChenYu
[1] https://lore.kernel.org/all/20260505101408.1796563-1-wenst@chromium.org/
Chen-Yu Tsai (4):
arm64: dts: mediatek: mt8192-asurada: Fix SPI-NOR flash compatible
arm64: dts: mediatek: mt8192-asurada: Add (BT|WIFI)_KILL_1V8_L GPIO
line names
arm64: dts: mediatek: mt8195-cherry: Fix names for EC controlled
regulators
arm64: dts: mediatek: mt8195-cherry: Sort top level nodes correctly
.../boot/dts/mediatek/mt8192-asurada.dtsi | 6 +-
.../boot/dts/mediatek/mt8195-cherry.dtsi | 106 +++++++++---------
2 files changed, 56 insertions(+), 56 deletions(-)
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply
* Re: [PATCH v6 05/10] dt-bindings: arm: fsl: Add solidrun lx2160a twins board
From: Josua Mayer @ 2026-05-14 10:12 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Yazan Shhady, Jon Nettleton, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <20260514-macho-white-tapir-4f8cf2@quoll>
Hi Krzysztof,
Am 14.05.26 um 08:43 schrieb Krzysztof Kozlowski:
> On Tue, May 12, 2026 at 04:39:00PM +0200, Josua Mayer wrote:
>> The SolidRun LX2160A Twins board supports two configurations, one with
>> with a sinle CEX-7 module, and one with two (dual).
>>
>> The dual configuration was not yet tested.
> And how do see dual configuration? New compatible? For the same
> hardware (the same because from SoC point of view it will be exactly
> the same)?
From SoC point of view the sides are different, and the hardware looks different
when it is assembled for dual configuration. Most notably each cpu in dual
version only sees 12 SFP connectors each, while the single sees 20.
Further the port numbering might be different between left and right side cpu.
Finally there are some complications in the current pcb version with resource
distribution (i.e. fans, leds).
>
> You must post complete binding, otherwise this feels risky and when you
> actually try running dual configuration you will see that existing
> binding makes no sense.
I thought about this and decided against it.
The single version is simple to describe, the cpu always sits in the right side socket,
sees 20 SFP connectors and has full control over every peripheral.
The dual version will require different description even if only one cpu is installed.
Currently dual is hardware only without any software, and changes may or may not
be made to the PCB to simplify things. Therefore I avoided drafting any bindings.
sincerely
Josua Mayer
^ permalink raw reply
* Re: [PATCH v5 01/10] dt-bindings: display: rockchip: analogix-dp: Fix hclk as third clock for RK3588
From: Krzysztof Kozlowski @ 2026-05-14 10:03 UTC (permalink / raw)
To: Damon Ding
Cc: hjc, heiko, andy.yan, maarten.lankhorst, mripard, tzimmermann,
airlied, simona, robh, krzk+dt, conor+dt, andrzej.hajda,
neil.armstrong, rfoss, Laurent.pinchart, jonas, jernej.skrabec,
nicolas.frattaroli, cristian.ciocaltea, sebastian.reichel,
dmitry.baryshkov, luca.ceresoli, dianders, m.szyprowski,
dri-devel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260513074414.2053435-2-damon.ding@rock-chips.com>
On Wed, May 13, 2026 at 03:44:05PM +0800, Damon Ding wrote:
> RK3588 eDP controller requires HCLK_VO1 (video output bus clock)
> to access the VO1 GRF registers and enable the video datapath.
To access GRF? Then it is the same clock input.
AGAIN (reiterated soooo many times by me): you describe here clock
input, NOT OUTPUT.
>
> Previously, the clock was enabled implicitly via the 'rockchip,vo-grf'
> phandle reference, which allowed the eDP to work without explicitly
> managing the hclk_vo1 clock. However, this is not safe or explicit.
>
> Enforce the correct third clock name on a per-compatible basis to
> standardize clock requirements per SoC. This makes the clock
> dependency clear and removes reliance on implicit clock enablement
> from GRF phandle.
>
> Fixes: f855146263b1 ("dt-bindings: display: rockchip: analogix-dp: Add support for RK3588")
> Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
>
> ---
>
> Changes in v4:
> - Modify the commit msg.
>
> Changes in v5:
> - Enforce the correct third clock name on a per-compatible basis.
> - Modify the commit msg simultaneously.
> ---
> .../rockchip/rockchip,analogix-dp.yaml | 37 +++++++++++++++++--
> 1 file changed, 33 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> index d99b23b88cc5..8001c1facf98 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> @@ -23,10 +23,7 @@ properties:
>
> clock-names:
> minItems: 2
> - items:
> - - const: dp
> - - const: pclk
> - - const: grf
What is 'grf' clock in such case?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 6/7] mm/vmalloc: align vm_area so vmap() can batch mappings
From: Wen Jiang @ 2026-05-14 9:41 UTC (permalink / raw)
To: linux-mm, linux-arm-kernel, catalin.marinas, will, akpm, urezki
Cc: baohua, Xueyuan.chen21, dev.jain, rppt, david, ryan.roberts,
anshuman.khandual, ajd, linux-kernel, Wen Jiang, Xueyuan Chen
In-Reply-To: <20260514094108.2016201-1-jiangwen6@xiaomi.com>
From: "Barry Song (Xiaomi)" <baohua@kernel.org>
Try to align the vmap virtual address to PMD_SHIFT or a
larger PTE mapping size hinted by the architecture, so
contiguous pages can be batch-mapped when setting PMD or
PTE entries.
Signed-off-by: Barry Song (Xiaomi) <baohua@kernel.org>
Signed-off-by: Wen Jiang <jiangwen6@xiaomi.com>
Tested-by: Xueyuan Chen <xueyuan.chen21@gmail.com>
---
mm/vmalloc.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index c30a7673e..b3389c8f1 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -3591,6 +3591,35 @@ static int __vmap_huge(unsigned long addr, unsigned long end,
return err;
}
+static struct vm_struct *get_aligned_vm_area(unsigned long size, unsigned long flags)
+{
+ unsigned int shift = (size >= PMD_SIZE) ? PMD_SHIFT :
+ arch_vmap_pte_supported_shift(size);
+ struct vm_struct *vm_area = NULL;
+
+ /*
+ * Try to allocate an aligned vm_area so contiguous pages can be
+ * mapped in batches.
+ */
+ while (1) {
+ unsigned long align = 1UL << shift;
+
+ vm_area = __get_vm_area_node(size, align, PAGE_SHIFT, flags,
+ VMALLOC_START, VMALLOC_END,
+ NUMA_NO_NODE, GFP_KERNEL,
+ __builtin_return_address(0));
+ if (vm_area || shift <= PAGE_SHIFT)
+ goto out;
+ if (shift == PMD_SHIFT)
+ shift = arch_vmap_pte_supported_shift(size);
+ else if (shift > PAGE_SHIFT)
+ shift = PAGE_SHIFT;
+ }
+
+out:
+ return vm_area;
+}
+
/**
* vmap - map an array of pages into virtually contiguous space
* @pages: array of page pointers
@@ -3629,7 +3658,7 @@ void *vmap(struct page **pages, unsigned int count,
return NULL;
size = (unsigned long)count << PAGE_SHIFT;
- area = get_vm_area_caller(size, flags, __builtin_return_address(0));
+ area = get_aligned_vm_area(size, flags);
if (!area)
return NULL;
--
2.34.1
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