* [PATCH v3 0/3] arm64: dts: freescale: add Toradex Aquila iMX95
From: Franz Schnyder @ 2026-05-21 9:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, Conor Dooley,
João Paulo Gonçalves, Emanuele Ghidoli,
Francesco Dolcini, Antoine Gouby, Ernest Van Hoecke
This patch series adds support for the Toradex Aquila i.MX95 SoM and its
currently available carrier boards: the Aquila Development Board and the
Clover carrier board.
The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR5 RAM,
up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit
Ethernet PHY, a 10 Gigabit Ethernet interface, an I2C EEPROM and
Temperature Sensor, an RX8130 RTC, one Quad lane CSI interface, one Quad
lane DSI or CSI interface, one LVDS interface (one or two channels), and
some optional addons: DisplayPort (through a DSI-DP bridge), TPM 2.0,
and a WiFi/BT module.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Link: https://www.toradex.com/products/carrier-board/clover
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
Changes in v3:
- Changed QSPI_1 4bit iomux node name to 'flexspi14bitgrp'
- Deleted the cdns,* properties from flexspi1
- Link to v2: https://patch.msgid.link/20260520-add-aquila-imx95-v2-0-06424a51e33a@toradex.com
Changes in v2:
- Add 'acked-by' tag from Conor to the bindings patch
- Reordering iomux by node name
- Changed Francesco's tags to have the Toradex mail address
- Link to v1: https://lore.kernel.org/r/20260506-add-aquila-imx95-v1-0-69c8ee1c5413@toradex.com
---
Antoine Gouby (1):
arm64: dts: freescale: imx95-aquila: Add Clover carrier board
Franz Schnyder (1):
dt-bindings: arm: fsl: add Aquila iMX95
João Paulo Gonçalves (1):
arm64: dts: freescale: add Aquila iMX95 support
Documentation/devicetree/bindings/arm/fsl.yaml | 8 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../boot/dts/freescale/imx95-aquila-clover.dts | 289 +++++
arch/arm64/boot/dts/freescale/imx95-aquila-dev.dts | 393 +++++++
arch/arm64/boot/dts/freescale/imx95-aquila.dtsi | 1160 ++++++++++++++++++++
5 files changed, 1852 insertions(+)
---
base-commit: 596d0f9f4fefffbf783ab26cfa90cf50f5dd6bb0
change-id: 20260501-add-aquila-imx95-423256af3d21
Best regards,
--
Franz Schnyder <franz.schnyder@toradex.com>
^ permalink raw reply
* [PATCH v3 1/3] dt-bindings: arm: fsl: add Aquila iMX95
From: Franz Schnyder @ 2026-05-21 9:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel,
Francesco Dolcini, Franz Schnyder, Conor Dooley
In-Reply-To: <20260521-add-aquila-imx95-v3-0-621843807def@toradex.com>
From: Franz Schnyder <franz.schnyder@toradex.com>
Add DT compatible strings for the Aquila i.MX95 SoM and its supported
carrier boards: the Aquila Development Board and the Clover carrier
board.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Link: https://www.toradex.com/products/carrier-board/clover
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
---
v3: No changes
v2: Added Conor's acked-by
v1: https://lore.kernel.org/all/20260506-add-aquila-imx95-v1-1-69c8ee1c5413@toradex.com/
---
Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 59f7f168bf7c4..ea4cc98dadebc 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1507,6 +1507,14 @@ properties:
- const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC
- const: fsl,imx95
+ - description: Toradex Boards with Aquila iMX95 Modules
+ items:
+ - enum:
+ - toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board
+ - toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board
+ - const: toradex,aquila-imx95 # Aquila iMX95 Module
+ - const: fsl,imx95
+
- description: Toradex Boards with SMARC iMX95 Modules
items:
- const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board
--
2.43.0
^ permalink raw reply related
* [soc:for-next] BUILD SUCCESS 8dbb80525730a16c7b38b07c2400df36e11ed605
From: kernel test robot @ 2026-05-21 8:54 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linux-arm-kernel, arm
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
branch HEAD: 8dbb80525730a16c7b38b07c2400df36e11ed605 soc: document merges
elapsed time: 721m
configs tested: 185
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-15.2.0
alpha allyesconfig gcc-15.2.0
alpha defconfig gcc-15.2.0
arc allmodconfig clang-16
arc allnoconfig gcc-15.2.0
arc allyesconfig clang-23
arc allyesconfig gcc-15.2.0
arc defconfig gcc-15.2.0
arc randconfig-001-20260521 gcc-8.5.0
arc randconfig-002-20260521 gcc-8.5.0
arm allnoconfig gcc-15.2.0
arm allyesconfig clang-16
arm defconfig gcc-15.2.0
arm footbridge_defconfig clang-17
arm randconfig-001-20260521 gcc-8.5.0
arm randconfig-002-20260521 gcc-8.5.0
arm randconfig-003-20260521 gcc-8.5.0
arm randconfig-004-20260521 gcc-8.5.0
arm64 allmodconfig clang-19
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-15.2.0
arm64 defconfig gcc-15.2.0
arm64 randconfig-001-20260521 gcc-8.5.0
arm64 randconfig-002-20260521 gcc-8.5.0
arm64 randconfig-003-20260521 gcc-8.5.0
arm64 randconfig-004-20260521 gcc-8.5.0
csky allmodconfig gcc-15.2.0
csky allnoconfig gcc-15.2.0
csky defconfig gcc-15.2.0
csky randconfig-001-20260521 gcc-8.5.0
csky randconfig-002-20260521 gcc-8.5.0
hexagon allmodconfig gcc-15.2.0
hexagon allnoconfig gcc-15.2.0
hexagon defconfig gcc-15.2.0
hexagon randconfig-001-20260521 gcc-11.5.0
hexagon randconfig-002-20260521 gcc-11.5.0
i386 allmodconfig clang-20
i386 allnoconfig gcc-15.2.0
i386 allyesconfig clang-20
i386 buildonly-randconfig-001-20260521 clang-20
i386 buildonly-randconfig-002-20260521 clang-20
i386 buildonly-randconfig-003-20260521 clang-20
i386 buildonly-randconfig-004-20260521 clang-20
i386 buildonly-randconfig-005-20260521 clang-20
i386 buildonly-randconfig-006-20260521 clang-20
i386 defconfig gcc-15.2.0
i386 randconfig-001-20260521 clang-20
i386 randconfig-002-20260521 clang-20
i386 randconfig-003-20260521 clang-20
i386 randconfig-004-20260521 clang-20
i386 randconfig-005-20260521 clang-20
i386 randconfig-006-20260521 clang-20
i386 randconfig-007-20260521 clang-20
i386 randconfig-011-20260521 gcc-14
i386 randconfig-012-20260521 gcc-14
i386 randconfig-013-20260521 gcc-14
i386 randconfig-014-20260521 gcc-14
i386 randconfig-015-20260521 gcc-14
i386 randconfig-016-20260521 gcc-14
i386 randconfig-017-20260521 gcc-14
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig gcc-15.2.0
loongarch defconfig clang-19
loongarch randconfig-001-20260521 gcc-11.5.0
loongarch randconfig-002-20260521 gcc-11.5.0
m68k allmodconfig gcc-15.2.0
m68k allnoconfig gcc-15.2.0
m68k allyesconfig clang-16
m68k defconfig clang-19
microblaze allnoconfig gcc-15.2.0
microblaze allyesconfig gcc-15.2.0
microblaze defconfig clang-19
mips allmodconfig gcc-15.2.0
mips allnoconfig gcc-15.2.0
mips allyesconfig gcc-15.2.0
mips rt305x_defconfig clang-23
nios2 10m50_defconfig gcc-11.5.0
nios2 allmodconfig clang-23
nios2 allnoconfig clang-23
nios2 defconfig clang-19
nios2 randconfig-001-20260521 gcc-11.5.0
nios2 randconfig-002-20260521 gcc-11.5.0
openrisc allmodconfig clang-23
openrisc allnoconfig clang-23
openrisc defconfig gcc-15.2.0
parisc allmodconfig gcc-15.2.0
parisc allnoconfig clang-23
parisc allyesconfig clang-19
parisc allyesconfig gcc-15.2.0
parisc defconfig gcc-15.2.0
parisc randconfig-001-20260521 gcc-12.5.0
parisc randconfig-002-20260521 gcc-12.5.0
parisc64 defconfig clang-19
powerpc allmodconfig gcc-15.2.0
powerpc allnoconfig clang-23
powerpc mgcoge_defconfig clang-23
powerpc mpc837x_rdb_defconfig gcc-15.2.0
powerpc randconfig-001-20260521 gcc-12.5.0
powerpc randconfig-002-20260521 gcc-12.5.0
powerpc sam440ep_defconfig gcc-15.2.0
powerpc64 randconfig-001-20260521 gcc-12.5.0
powerpc64 randconfig-002-20260521 gcc-12.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allyesconfig clang-16
riscv defconfig gcc-15.2.0
riscv randconfig-001-20260521 gcc-15.2.0
riscv randconfig-002-20260521 gcc-15.2.0
s390 allmodconfig clang-18
s390 allmodconfig clang-19
s390 allnoconfig clang-23
s390 allyesconfig gcc-15.2.0
s390 defconfig gcc-15.2.0
s390 randconfig-001-20260521 gcc-15.2.0
s390 randconfig-002-20260521 gcc-15.2.0
sh allmodconfig gcc-15.2.0
sh allnoconfig clang-23
sh allyesconfig clang-19
sh allyesconfig gcc-15.2.0
sh defconfig gcc-14
sh randconfig-001-20260521 gcc-15.2.0
sh randconfig-002-20260521 gcc-15.2.0
sparc allnoconfig clang-23
sparc defconfig gcc-15.2.0
sparc randconfig-001-20260521 gcc-8.5.0
sparc randconfig-002-20260521 gcc-8.5.0
sparc64 allmodconfig clang-23
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260521 gcc-8.5.0
sparc64 randconfig-002-20260521 gcc-8.5.0
um allmodconfig clang-19
um allnoconfig clang-23
um allyesconfig gcc-15.2.0
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260521 gcc-8.5.0
um randconfig-002-20260521 gcc-8.5.0
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-20
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-20
x86_64 buildonly-randconfig-001-20260521 clang-20
x86_64 buildonly-randconfig-002-20260521 clang-20
x86_64 buildonly-randconfig-003-20260521 clang-20
x86_64 buildonly-randconfig-004-20260521 clang-20
x86_64 buildonly-randconfig-005-20260521 clang-20
x86_64 buildonly-randconfig-006-20260521 clang-20
x86_64 defconfig gcc-14
x86_64 kexec clang-20
x86_64 randconfig-001-20260521 clang-20
x86_64 randconfig-002-20260521 clang-20
x86_64 randconfig-003-20260521 clang-20
x86_64 randconfig-004-20260521 clang-20
x86_64 randconfig-005-20260521 clang-20
x86_64 randconfig-006-20260521 clang-20
x86_64 randconfig-011-20260521 gcc-14
x86_64 randconfig-012-20260521 gcc-14
x86_64 randconfig-013-20260521 gcc-14
x86_64 randconfig-014-20260521 gcc-14
x86_64 randconfig-015-20260521 gcc-14
x86_64 randconfig-016-20260521 gcc-14
x86_64 randconfig-071 clang-20
x86_64 randconfig-071-20260521 clang-20
x86_64 randconfig-072 clang-20
x86_64 randconfig-072-20260521 clang-20
x86_64 randconfig-073 clang-20
x86_64 randconfig-073-20260521 clang-20
x86_64 randconfig-074 clang-20
x86_64 randconfig-074-20260521 clang-20
x86_64 randconfig-075 clang-20
x86_64 randconfig-075-20260521 clang-20
x86_64 randconfig-076 clang-20
x86_64 randconfig-076-20260521 clang-20
x86_64 rhel-9.4 clang-20
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-20
x86_64 rhel-9.4-kselftests clang-20
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-20
xtensa allnoconfig clang-23
xtensa allyesconfig clang-23
xtensa randconfig-001-20260521 gcc-8.5.0
xtensa randconfig-002-20260521 gcc-8.5.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH] [RFC] arm64: mmu: use range based TLB flushing when hot unplugging memory
From: Ryan Roberts @ 2026-05-21 8:50 UTC (permalink / raw)
To: Alistair Popple, linux-arm-kernel
Cc: linux-kernel, linux-mm, catalin.marinas, will, david,
anshuman.khandual, dev.jain, balbirs, jhubbard
In-Reply-To: <20260521042426.2128731-1-apopple@nvidia.com>
On 21/05/2026 05:24, Alistair Popple wrote:
> Hot unplugging memory on ARM64 requires a TLB invalidate after unmapping
> the page to be hot unplugged from the direct map. Currently that happens
> one page at a time, meaning range based invalidates cannot be used. The
> result of this is that removing large amounts of memory takes a long
> time and in some cases can trigger an RCU stall warning.
>
> For example on one system hot unplugging 480GB of memory takes ~1
> minute. With this change the same operation took ~1 second, a 60x
> improvement.
>
> Signed-off-by: Alistair Popple <apopple@nvidia.com>
>
> ---
>
> This is an RFC, because I'm not sure the change is correct as it frees
> the PTE page before flushing the TLB. I'm not familiar enough with ARM64
> architecture to be sure this is safe, for example I don't know if HW
> can update PTE bits such as access/dirty in the page through a stale
> TLB entry.
>
> If so this would open a window during which the page is free but could
> still be written to. Likely the safe option would be to collect all the
> pages to be free on a list and free them after doing the range based TLB
> flush, but wanted to get feedback on the approach before implementing it
> which is the goal of this RFC.
Hi Alistair,
This patch doesn't apply on v7.1-rc4 because it conflicts with this patch:
Commit 48478b9f79137 ("arm64/mm: Enable batched TLB flush in unmap_hotplug_range()")
which has a very similar performance improvement, so hopefully it solves your
problem?
There are two paths which use this logic; unmapping the linear map and unmapping
the corresponding vmemmap. In the latter case, the memory is also freed, so we
can't safely do the range optimizaiton there since the TLB needs to be flushed
before freeing the memory. But the linear map is the big, slow bit so hopefully
it's sufficent for you?
Thanks,
Ryan
> ---
> arch/arm64/mm/mmu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index 0c24fe650e95..75c773232c14 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -1459,11 +1459,12 @@ static void unmap_hotplug_pte_range(pmd_t *pmdp, unsigned long addr,
>
> WARN_ON(!pte_present(pte));
> __pte_clear(&init_mm, addr, ptep);
> - flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
> if (free_mapped)
> free_hotplug_page_range(pte_page(pte),
> PAGE_SIZE, altmap);
> } while (addr += PAGE_SIZE, addr < end);
> +
> + flush_tlb_kernel_range(addr, end);
> }
>
> static void unmap_hotplug_pmd_range(pud_t *pudp, unsigned long addr,
^ permalink raw reply
* [PATCH v11 1/2] kunit: add tests for smp_cond_load_*_timeout()
From: Ankur Arora @ 2026-05-21 8:30 UTC (permalink / raw)
To: linux-kernel, linux-arch, linux-arm-kernel, linux-pm, linux-next,
bpf
Cc: arnd, catalin.marinas, will, peterz, akpm, mark.rutland, harisokn,
cl, ast, rafael, daniel.lezcano, memxor, zhenglifeng1, xueshuai,
rdunlap, david.laight.linux, joao.m.martins, boris.ostrovsky,
konrad.wilk, ashok.bhat, Ankur Arora, Boqun Feng, Boqun Feng,
Christoph Lameter, Ingo Molnar, Konrad Dybcio, Mark Brown
In-Reply-To: <20260408122538.3610871-15-ankur.a.arora@oracle.com>
Add success and failure case tests for smp_cond_load_*_timeout().
All of the test cases wait on some state in smp_cond_load_*_timeout().
In the success case we spawn a kthread that pokes the bit.
Success or failure cases depend on the expected bit being set (or not).
Additionally in failure cases smp_cond_load_*_timeout() cannot return
before timeout.
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Boqun Feng <boqun@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoph Lameter <cl@linux.com>
Cc: Haris Okanovic <harisokn@amazon.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
---
Note: This fixes an error in the test case reported by Mark Brown
in https://lore.kernel.org/lkml/agr_RxvNtfASfevg@sirena.org.uk/.
There are three changes over the old version:
- One of the test conditions used in the test was much too strict.
The test was treating success as implying that the
smp_cond_load_relaxed_timeout() call has to return before timeout.
(runtime <= timeout_ns).
However, all that we know is that on failure (!success), the
smp_cond_load_relaxed_timeout() *cannot* return before timeout.
(runtime >= timeout_ns).
- The test can run in a wide variety of environments including in
emulation. So to reduce the chance of failure due to timing,
remove the kthreaded case.
- Parametrize the test cases.
---
lib/Kconfig.debug | 10 +++
lib/tests/Makefile | 1 +
lib/tests/barrier-timeout-test.c | 128 +++++++++++++++++++++++++++++++
3 files changed, 139 insertions(+)
create mode 100644 lib/tests/barrier-timeout-test.c
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index ce25724be414..9d54c48d7d98 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -2413,6 +2413,16 @@ config FPROBE_SANITY_TEST
Say N if you are unsure.
+config BARRIER_TIMEOUT_TEST
+ tristate "KUnit tests for smp_cond_load_relaxed_timeout()"
+ depends on KUNIT
+ default KUNIT_ALL_TESTS
+ help
+ Builds KUnit tests that validate wake-up and timeout handling paths
+ in smp_cond_load_relaxed_timeout().
+
+ Say N if you are unsure.
+
config BACKTRACE_SELF_TEST
tristate "Self test for the backtrace code"
depends on DEBUG_KERNEL
diff --git a/lib/tests/Makefile b/lib/tests/Makefile
index 7e9c2fa52e35..19c1d6b17856 100644
--- a/lib/tests/Makefile
+++ b/lib/tests/Makefile
@@ -20,6 +20,7 @@ CFLAGS_fortify_kunit.o += $(DISABLE_STRUCTLEAK_PLUGIN)
obj-$(CONFIG_FORTIFY_KUNIT_TEST) += fortify_kunit.o
CFLAGS_test_fprobe.o += $(CC_FLAGS_FTRACE)
obj-$(CONFIG_FPROBE_SANITY_TEST) += test_fprobe.o
+obj-$(CONFIG_BARRIER_TIMEOUT_TEST) += barrier-timeout-test.o
obj-$(CONFIG_GLOB_KUNIT_TEST) += glob_kunit.o
obj-$(CONFIG_HASHTABLE_KUNIT_TEST) += hashtable_test.o
obj-$(CONFIG_HASH_KUNIT_TEST) += test_hash.o
diff --git a/lib/tests/barrier-timeout-test.c b/lib/tests/barrier-timeout-test.c
new file mode 100644
index 000000000000..2160844b27b8
--- /dev/null
+++ b/lib/tests/barrier-timeout-test.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * KUnit tests exercising smp_cond_load_relaxed_timeout().
+ *
+ * Copyright (c) 2026, Oracle Corp.
+ * Author: Ankur Arora <ankur.a.arora@oracle.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/sched/clock.h>
+#include <linux/delay.h>
+#include <asm/barrier.h>
+#include <kunit/test.h>
+#include <kunit/visibility.h>
+
+MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
+
+struct clock_state {
+ s64 start_time;
+ s64 end_time;
+};
+
+#define TIMEOUT_MSEC 2
+#define TEST_FLAG_VAL BIT(2)
+static unsigned int flag;
+
+static s64 basic_clock(struct clock_state *clk)
+{
+ clk->end_time = local_clock();
+ return clk->end_time;
+}
+
+static void update_flags(void)
+{
+ WRITE_ONCE(flag, TEST_FLAG_VAL);
+}
+
+static s64 mocked_clock(struct clock_state *clk)
+{
+ s64 clk_mid = clk->start_time + (TIMEOUT_MSEC * NSEC_PER_MSEC)/2;
+
+ clk->end_time = local_clock();
+ if (clk->end_time >= clk_mid)
+ update_flags();
+ return clk->end_time;
+}
+
+typedef s64 (*clkfn_t)(struct clock_state *);
+struct smp_cond_update_params {
+ clkfn_t clock;
+ bool acquire;
+ bool succeeds;
+};
+
+static const struct smp_cond_update_params update_params_list[] = {
+ /* mocked-clock updates flag inline. */
+ { .clock = &mocked_clock, .succeeds=true, .acquire=false, },
+ { .clock = &mocked_clock, .succeeds=true, .acquire=true, },
+
+ /* basic-clock doesn't update flag. */
+ { .clock = &basic_clock, .succeeds=false, .acquire=true, },
+ { .clock = &basic_clock, .succeeds=false, .acquire=false, },
+};
+
+static void param_to_desc(const struct smp_cond_update_params *p, char *desc)
+{
+ char *clk, *update;
+
+ if (p->clock == &mocked_clock) {
+ clk = "mocked";
+ update = "inline";
+ } else if (p->clock == &basic_clock) {
+ clk = "basic";
+ update = "none";
+ }
+
+
+ snprintf(desc, KUNIT_PARAM_DESC_SIZE, "smp_cond_%s_timeout: clock-%s, update=%s",
+ p->acquire ? "acquire": "relaxed", clk, update);
+}
+
+KUNIT_ARRAY_PARAM(smp_cond_update_params, update_params_list, param_to_desc);
+
+
+static void test_smp_cond_timeout(struct kunit *test)
+{
+ const struct smp_cond_update_params *p = test->param_value;
+ struct clock_state clk = {
+ .start_time = local_clock(),
+ .end_time = local_clock(),
+ };
+ s64 runtime, timeout_ns = TIMEOUT_MSEC * NSEC_PER_MSEC;
+ unsigned int result;
+
+ flag = 0;
+ if (p->acquire) {
+ result = smp_cond_load_acquire_timeout(&flag,
+ (VAL & TEST_FLAG_VAL),
+ p->clock(&clk),
+ timeout_ns);
+ } else {
+ result = smp_cond_load_relaxed_timeout(&flag,
+ (VAL & TEST_FLAG_VAL),
+ p->clock(&clk),
+ timeout_ns);
+ }
+
+ runtime = clk.end_time - clk.start_time;
+ KUNIT_EXPECT_EQ(test, (bool)(result & TEST_FLAG_VAL), p->succeeds);
+ if (!p->succeeds)
+ KUNIT_EXPECT_GE(test, runtime, timeout_ns);
+}
+
+static struct kunit_case barrier_timeout_test_cases[] = {
+ KUNIT_CASE_PARAM(test_smp_cond_timeout, smp_cond_update_params_gen_params),
+ {}
+};
+
+static struct kunit_suite barrier_timeout_test_suite = {
+ .name = "smp-cond-load-*-timeout",
+ .test_cases = barrier_timeout_test_cases,
+};
+
+kunit_test_suite(barrier_timeout_test_suite);
+
+MODULE_DESCRIPTION("KUnit tests for smp_cond_load_relaxed_timeout()");
+MODULE_LICENSE("GPL");
--
2.43.7
^ permalink raw reply related
* [PATCH v11 2/2] kunit: add clock tests for smp_cond_load_relaxed_timeout()
From: Ankur Arora @ 2026-05-21 8:30 UTC (permalink / raw)
To: linux-kernel, linux-arch, linux-arm-kernel, linux-pm, linux-next,
bpf
Cc: arnd, catalin.marinas, will, peterz, akpm, mark.rutland, harisokn,
cl, ast, rafael, daniel.lezcano, memxor, zhenglifeng1, xueshuai,
rdunlap, david.laight.linux, joao.m.martins, boris.ostrovsky,
konrad.wilk, ashok.bhat, Ankur Arora, Boqun Feng, Boqun Feng,
Christoph Lameter, Ingo Molnar, Konrad Dybcio, Mark Brown
In-Reply-To: <20260521083038.134260-1-ankur.a.arora@oracle.com>
Add a few clock tests for smp_cond_load_relaxed_timeout(). These
ensure that the implementation doesn't do any funny stuff with the
clock (like multiple accesses per iteration.)
Also ensure that edge cases are handled sanely. Note that two edge
cases fail: S64_MAX and U64_MAX. However, both of those are quite
far out and if needed, can be addressed in the implementation of
the interface.
Also, this tests only smp_cond_load_relaxed_timeout(). The acquire
variant uses an identical clock path and testing wouldn't add anything.
Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Boqun Feng <boqun@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoph Lameter <cl@linux.com>
Cc: Haris Okanovic <harisokn@amazon.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
---
lib/tests/barrier-timeout-test.c | 57 ++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/lib/tests/barrier-timeout-test.c b/lib/tests/barrier-timeout-test.c
index 2160844b27b8..6ce6c7b0fc44 100644
--- a/lib/tests/barrier-timeout-test.c
+++ b/lib/tests/barrier-timeout-test.c
@@ -19,6 +19,8 @@ MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
struct clock_state {
s64 start_time;
s64 end_time;
+ s64 extra;
+ u32 niters;
};
#define TIMEOUT_MSEC 2
@@ -112,8 +114,63 @@ static void test_smp_cond_timeout(struct kunit *test)
KUNIT_EXPECT_GE(test, runtime, timeout_ns);
}
+static s64 synthetic_clock(struct clock_state *clk) {
+ clk->end_time += clk->extra;
+ clk->niters++;
+
+ return clk->end_time;
+}
+
+
+struct smp_cond_expiry_params {
+ char *desc;
+ s64 timeout;
+ s64 clk_inc;
+ u32 niters;
+};
+
+static const struct smp_cond_expiry_params expiry_params_list[] = {
+ { .clk_inc = (0x1ULL << 28), .timeout = -1LL, .niters = 1, .desc = "-1LL", },
+ { .clk_inc = (0x1ULL << 28), .timeout = (0x1ULL << 30), .niters = 1 + (1 << (30-28)), .desc = "1<<30", },
+ { .clk_inc = (0x1ULL << 28), .timeout = S32_MAX, .niters = 1 + (1 << (31-28)), .desc = "S32_MAX", },
+ { .clk_inc = (0x1ULL << 28), .timeout = U32_MAX, .niters = 1 + (1 << (32-28)), .desc = "U32_MAX", },
+ { .clk_inc = (0x1ULL << 28), .timeout = (0x1ULL << 33), .niters = 1 + (1 << (33-28)), .desc = "1<<33", },
+};
+
+static void expiry_param_to_desc(const struct smp_cond_expiry_params *p, char *desc)
+{
+ snprintf(desc, KUNIT_PARAM_DESC_SIZE, "smp_cond_%s_timeout: clock-%s, timeout=%s, iterations=%u",
+ "relaxed", "synthetic", p->desc, p->niters);
+}
+
+static void test_smp_cond_expiry(struct kunit *test)
+{
+ const struct smp_cond_expiry_params *p = test->param_value;
+ struct clock_state clk = {
+ .start_time = 0,
+ .end_time = 0,
+ .extra = p->clk_inc,
+ .niters = 0,
+ };
+ unsigned int result;
+ s64 runtime;
+
+ flag = 0;
+ result = smp_cond_load_relaxed_timeout(&flag,
+ 0,
+ synthetic_clock(&clk),
+ p->timeout);
+
+ runtime = (u64)clk.end_time - (u64)clk.start_time;
+ KUNIT_EXPECT_EQ(test, clk.niters, p->niters);
+ KUNIT_EXPECT_GE(test, runtime, p->timeout);
+}
+
+
+KUNIT_ARRAY_PARAM(smp_cond_expiry_params, expiry_params_list, expiry_param_to_desc);
static struct kunit_case barrier_timeout_test_cases[] = {
KUNIT_CASE_PARAM(test_smp_cond_timeout, smp_cond_update_params_gen_params),
+ KUNIT_CASE_PARAM(test_smp_cond_expiry, smp_cond_expiry_params_gen_params),
{}
};
--
2.43.7
^ permalink raw reply related
* [PATCH v4] i2c: imx: mark I2C adapter when hardware is powered down
From: Carlos Song (OSS) @ 2026-05-21 8:32 UTC (permalink / raw)
To: o.rempel, kernel, andi.shyti, Frank.Li, s.hauer, festevam,
haibo.chen, carlos.song
Cc: linux-i2c, imx, linux-arm-kernel, linux-kernel, stable
From: Carlos Song <carlos.song@nxp.com>
Mark the I2C adapter as suspended during system suspend to block further
transfers, and resume it on system resume. This prevents potential hangs
when the hardware is powered down but clients still attempt I2C transfers.
Fixes: 358025ac091e ("i2c: imx: make controller available until system suspend_noirq() and from resume_noirq()")
Cc: stable@vger.kernel.org
Signed-off-by: Carlos Song <carlos.song@nxp.com>
---
Change for v4:
- Restore hrtimer when pm_runtime_force_suspend failed when slave mode
enabled.
Change for v3:
- Add hrtimer_cancel in i2c_imx_suspend_noirq to cancel slave_timer for
safe suspend in i2c slave mode.
Change for v2:
- Call i2c_mark_adapter_suspended() before pm_runtime_force_suspend()
to prevent potential deadlock if a transfer is active during suspend.
- Roll back with i2c_mark_adapter_resumed() if pm_runtime_force_suspend()
fails.
---
drivers/i2c/busses/i2c-imx.c | 45 ++++++++++++++++++++++++++++++++++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 28313d0fad37..73317ddd5f02 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -1922,6 +1922,47 @@ static int i2c_imx_runtime_resume(struct device *dev)
return 0;
}
+static int __maybe_unused i2c_imx_suspend_noirq(struct device *dev)
+{
+ struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
+ int ret;
+
+ i2c_mark_adapter_suspended(&i2c_imx->adapter);
+
+ /*
+ * Cancel the slave timer before powering down to prevent
+ * i2c_imx_slave_timeout() from accessing hardware registers
+ * while the clock is disabled.
+ */
+ hrtimer_cancel(&i2c_imx->slave_timer);
+
+ ret = pm_runtime_force_suspend(dev);
+ if (ret) {
+ i2c_mark_adapter_resumed(&i2c_imx->adapter);
+ if (i2c_imx->slave) {
+ hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
+ hrtimer_restart(&i2c_imx->slave_timer);
+ }
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __maybe_unused i2c_imx_resume_noirq(struct device *dev)
+{
+ struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pm_runtime_force_resume(dev);
+ if (ret)
+ return ret;
+
+ i2c_mark_adapter_resumed(&i2c_imx->adapter);
+
+ return 0;
+}
+
static int i2c_imx_suspend(struct device *dev)
{
/*
@@ -1955,8 +1996,8 @@ static int i2c_imx_resume(struct device *dev)
}
static const struct dev_pm_ops i2c_imx_pm_ops = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
- pm_runtime_force_resume)
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend_noirq,
+ i2c_imx_resume_noirq)
SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume)
RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL)
};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v4 4/5] KVM: arm64: Fix bounds checking in do_ffa_mem_reclaim()
From: Marc Zyngier @ 2026-05-21 8:28 UTC (permalink / raw)
To: Mostafa Saleh
Cc: op-tee, linux-kernel, kvmarm, linux-arm-kernel, oupton,
joey.gouly, suzuki.poulose, catalin.marinas, jens.wiklander,
sumit.garg, sebastianene, vdonnefort, sudeep.holla
In-Reply-To: <20260520204948.2440882-5-smostafa@google.com>
On Wed, 20 May 2026 21:49:47 +0100,
Mostafa Saleh <smostafa@google.com> wrote:
>
> Sashiko (locally) reports out of bound write possiblity if SPMD
> returns an invalid data.
>
> While SPMD is considered trusted, pKVM does some basic checks,
> for offset to be less than or equal len.
>
> However, that is incorrect as even if the offset is smaller than
> len pKVM can still access out of bound memory in the next
> ffa_host_unshare_ranges().
>
> Split this check into 2:
> 1- Check that the fixed portion of the descriptor fits.
> 2- After getting reg, check the variable array size addr_range_cnt
> fits.
>
> Signed-off-by: Mostafa Saleh <smostafa@google.com>
> ---
> arch/arm64/kvm/hyp/nvhe/ffa.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> index 1af722771178..e6aa2bfa63b1 100644
> --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> @@ -607,7 +607,7 @@ static void do_ffa_mem_reclaim(struct arm_smccc_1_2_regs *res,
> * check that we end up with something that doesn't look _completely_
> * bogus.
> */
> - if (WARN_ON(offset > len ||
> + if (WARN_ON(offset + CONSTITUENTS_OFFSET(0) > len ||
> fraglen > KVM_FFA_MBOX_NR_PAGES * PAGE_SIZE)) {
Do you really want to keep this a WARN_ON(), given that this results
in a panic in most pKVM configurations?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH/RFC 05/14] firmware: arm_scmi: Add scmi_get_base_info()
From: Geert Uytterhoeven @ 2026-05-21 8:27 UTC (permalink / raw)
To: Cristian Marussi
Cc: Sudeep Holla, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Magnus Damm, Saravana Kannan, Michael Turquette, Stephen Boyd,
Philipp Zabel, Ulf Hansson, Rafael J . Wysocki, Kevin Hilman,
Florian Fainelli, Wolfram Sang, Marek Vasut, Kuninori Morimoto,
arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel
In-Reply-To: <CAMuHMdU8VRCOZtLrM2EoHFmhd5XFs8cwXc2A1tPTTr01KvUx0g@mail.gmail.com>
On Thu, 21 May 2026 at 09:53, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sun, 17 May 2026 at 22:42, Cristian Marussi <cristian.marussi@arm.com> wrote:
> > On Fri, May 08, 2026 at 12:26:19PM +0200, Geert Uytterhoeven wrote:
> > > On Mon, 27 Apr 2026 at 01:03, Cristian Marussi <cristian.marussi@arm.com> wrote:
> > > > On Fri, Apr 24, 2026 at 02:08:55PM +0200, Geert Uytterhoeven wrote:
> > > > > On Wed, 22 Apr 2026 at 20:45, Cristian Marussi <cristian.marussi@arm.com> wrote:
> > > > > > Also because this should be one of the selling point of the SCMI stack
> > > > > > in a virtualized environment: you can ship the same kernel drivers with
> > > > > > the same DT and you know that ID=<N> will always identify the specific
> > > > > > resource that is needed by your driver without worrying about the fact
> > > > > > that in reality in the backstage the effectively managed physical resource
> > > > > > could be different across different platforms, because that does not matter
> > > > >
> > > > > This sounds strange to me, do I understand it correctly?
> > > > > So the ID should (1) be tied to the use-case, and not to the underlying
> > > > > hardware, and (2) be the same for different platforms?
> > > > >
> > > > > For (1): Then we must not put these IDs in DT at all, as DT is supposed
> > > > > to describe the hardware (and firmware IDs in DT were IMHO already
> > > > > a stretch before).
> > > > > For (2): How can there be a contiguous list of IDs, as not all platforms
> > > > > may have the same underlying hardware?
> > > >
> > > > I would NOT say that an SCMI FW must behave like this regarding IDs, but it
> > > > is a possible SCMI deployed setup that can be useful in virtualized setups
> > > >
> > > > I mean, the DT describes the hardware of course BUT when you refer to
> > > > some of this hardware DT bits from some other subsystem by referencing a
> > > > phandle, even in the non-SCMI world, you are in fact selecting a specific
> > > > resource that fit you use case, right ? Can we say this ?
> > > > I mean you needed that specific clock or regulator that you described
> > > > previously so as to be able to enable some other piece of HW...
> > > >
> > > > Now, the SCMI provides an abstraction on top of this, since you really
> > > > discover domain IDs of a specific class (clocks/regulators etc) you are
> > > > in fact describing an HW abstraction that you then refer with the usual
> > > > phandle...also because there is NOT so much SCMI hardware to describe,
> > > > given that the HW is handled transparently (opaquely really :P) by the
> > > > driver on the FW side...
> > > >
> > > > ...you basically obtain such domain ID, usable as phandles through dynamic
> > > > SCMI enumeration so that you can use it all over your DT to make use of such
> > > > resources...
> > > >
> > > > ...on top of this, consider that the SCMI server CAN provide to its agents
> > > > a per-agent-view of the world, IOW it can (and should) expose to a specific
> > > > agent ONLY the resources needed by that agent, i.e. it can expose the set
> > > > of resources 1-N to two distinct agents and that does NOT mean that the
> > > > underlying physical resource mapped by ID=3 in both agents has to be
> > > > effectively the same piece of hardware: it could be the case, and this
> > > > would be useful to exposed and managed properly a shared resource, or
> > > > it could also be that the same ID=3 could refer to completely distinct
> > > > pieces of the same class of hardware...(same protocol same class of
> > > > resource...)
> > >
> > > Exposing only the clocks/reset/power domains the agent can use,
> > > in a contiguous list of IDS, means that the number space changes,
> > > depending on which resources are exposed.
> >
> > Yes, potentially, it depedns on how the HW/FW stack was designed I
> > suppose...
> >
> > > Suppose you have a system where you want to assign a specific hardware
> > > block in the SoC to the realtime CPU core instead of the application
> > > CPU core running Linux.
> >
> > Ok, so this is definitely a considerable change.
> >
> > > That means all resources used by that block must no longer be exposed
> > > to the Linux agent, and the corresponding IDs must be removed from
> > > the ID space exposed to Linux. As the ID space must be sequential
> > > and contiguous, the IDs must be renumbered, impacting resources that
> > > are exposed to Linux. As these IDs are used in the SoC .dtsi, they
> > > must be changed there, too, However, these IDs have become part of
> > > the stable DT ABI, and thus cannot be changed.
> >
> > Well, you have to ship a final DTB blob that is crafted to describe the
> > actual HW at the end, right ?
> >
> > I mean, in your example, it seems to me that you have changed considerably
> > the HW surface by moving a clock (and its related resources) away from the
> > reach of Linux as a whole, so should not be expected to have an updated
> > DTB shipped ?
>
> It is not necessary to ship an updated DTB.
> The bootloader stack can just change the "status" properties of devices
> nodes that are be taken away from Linux from "okay" to "reserved":
>
> Devicetree Specification, Release v0.4, Table 2.4: Values for statu
> property states:
>
> Value: "reserved"
> Description:
> Indicates that the device is operational, but should not be
> used. Typically this is used for devices that are controlled
> by another software component, such as platform firmware.
>
> When all SCMI IDs change, too, much more work needs to be done.
It's a pity we cannot use strings in e.g. clock specifiers.
Then we could look them up by name (which would hopefully be more
stable) instead of by ID...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* RE: [PATCH v3] i2c: imx: mark I2C adapter when hardware is powered down
From: Carlos Song (OSS) @ 2026-05-21 8:27 UTC (permalink / raw)
To: Mukesh Savaliya, Carlos Song (OSS), o.rempel@pengutronix.de,
kernel@pengutronix.de, andi.shyti@kernel.org, Frank Li,
s.hauer@pengutronix.de, festevam@gmail.com, Carlos Song,
Bough Chen
Cc: linux-i2c@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
In-Reply-To: <4979e748-ce4e-4244-8906-e22a1e6472e7@oss.qualcomm.com>
> -----Original Message-----
> From: Mukesh Savaliya <mukesh.savaliya@oss.qualcomm.com>
> Sent: Thursday, May 21, 2026 3:40 PM
> To: Carlos Song (OSS) <carlos.song@oss.nxp.com>; o.rempel@pengutronix.de;
> kernel@pengutronix.de; andi.shyti@kernel.org; Frank Li <frank.li@nxp.com>;
> s.hauer@pengutronix.de; festevam@gmail.com; Carlos Song
> <carlos.song@nxp.com>; Bough Chen <haibo.chen@nxp.com>
> Cc: linux-i2c@vger.kernel.org; imx@lists.linux.dev;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> stable@vger.kernel.org
> Subject: Re: [PATCH v3] i2c: imx: mark I2C adapter when hardware is powered
> down
>
> [You don't often get email from mukesh.savaliya@oss.qualcomm.com. Learn
> why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> Hi Carlos,
>
> On 5/20/2026 3:45 PM, Carlos Song (OSS) wrote:
> > From: Carlos Song <carlos.song@nxp.com>
> >
> > Mark the I2C adapter as suspended during system suspend to block
> > further transfers, and resume it on system resume. This prevents
> > potential hangs when the hardware is powered down but clients still attempt
> I2C transfers.
> >
> Code changes looks fine to me but have comment on commit log.
>
> It seems, you are adding support of _noirq() callbacks to allow transfers during
> suspend/resume noirq phase of PM.
>
> Would it make sense if you can write "Replace system PM callbacks with noirq
> PM callbacks" OR "Allow transfers during _noirq phase of the PM ops" instead of
> "mark I2C adapter when hardware is powered down" ?
>
Hi,
Thank you for your comments!
But this patch is added is not for support noirq PM callback or transfer in noirq phase.
In fact, this fix is to mark the I2C adapter as suspended during system noirq suspend to block further
transfers, and resume it on system noirq resume. This is to prohibit I2C device calling the I2C controller
after the system noirq suspend and before noirq resume, because at this time the I2C instance is powered
off or the clock is disabled ... So I want to keep current commit. How do you think?
Carlos Song
> > Fixes: 358025ac091e ("i2c: imx: make controller available until system
> > suspend_noirq() and from resume_noirq()")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Carlos Song <carlos.song@nxp.com>
> > ---
> > Change for v3:
> > - Add hrtimer_cancel in i2c_imx_suspend_noirq to cancel slave_timer for
> > safe suspend in i2c slave mode.
> > Change for v2:
> > - Call i2c_mark_adapter_suspended() before
> pm_runtime_force_suspend()
> > to prevent potential deadlock if a transfer is active during suspend.
> > - Roll back with i2c_mark_adapter_resumed() if
> pm_runtime_force_suspend()
> > fails.
> > ---
>
> [...]
^ permalink raw reply
* [PATCH v3 0/2] Add PWM support Amlogic S7 S7D S6
From: Xianwei Zhao via B4 Relay @ 2026-05-21 8:26 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao, Junyi Zhao, Krzysztof Kozlowski
Add bindings and driver support Amlogic S7/S7D/S6 SoCs.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
Changes in v3:
- Use npwm instead of single_pwm in priv_data and format adjustments.
- Link to v2: https://lore.kernel.org/r/20260402-s6-s7-pwm-v2-0-657dce040956@amlogic.com
Changes in v2:
- Simpler s7 clock desc, and drop the example in bindings.
- Make minor changes to probe based on Martin's suggestion.
- Link to v1: https://lore.kernel.org/r/20260326-s6-s7-pwm-v1-0-67e2f72b98bc@amlogic.com
---
Junyi Zhao (1):
dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D
Xianwei Zhao (1):
pwm: meson: Add support for Amlogic S7
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 19 ++++++++++
drivers/pwm/pwm-meson.c | 41 ++++++++++++++++++++--
2 files changed, 57 insertions(+), 3 deletions(-)
---
base-commit: b1385d0c7b7c633e55adcf4a7c1ef46c43a84a4a
change-id: 20260325-s6-s7-pwm-281658b88736
Best regards,
--
Xianwei Zhao <xianwei.zhao@amlogic.com>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: pwm: amlogic: Add new bindings for S6 S7 S7D
From: Xianwei Zhao via B4 Relay @ 2026-05-21 8:26 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao, Junyi Zhao, Krzysztof Kozlowski
In-Reply-To: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com>
From: Junyi Zhao <junyi.zhao@amlogic.com>
Amlogic S7/S7D/S6 different from the previous SoCs, a controller
includes one pwm, at the same time, the controller has only one
input clock source.
Signed-off-by: Junyi Zhao <junyi.zhao@amlogic.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
index c337d85da40f..93fa97f4011b 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml
@@ -37,6 +37,7 @@ properties:
- enum:
- amlogic,meson8-pwm-v2
- amlogic,meson-s4-pwm
+ - amlogic,s7-pwm
- items:
- enum:
- amlogic,a4-pwm
@@ -45,6 +46,11 @@ properties:
- amlogic,t7-pwm
- amlogic,meson-a1-pwm
- const: amlogic,meson-s4-pwm
+ - items:
+ - enum:
+ - amlogic,s6-pwm
+ - amlogic,s7d-pwm
+ - const: amlogic,s7-pwm
- items:
- enum:
- amlogic,meson8b-pwm-v2
@@ -146,6 +152,19 @@ allOf:
clock-names: false
required:
- clocks
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,s7-pwm
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names: false
+ required:
+ - clocks
- if:
properties:
--
2.52.0
^ permalink raw reply related
* [PATCH v3 2/2] pwm: meson: Add support for Amlogic S7
From: Xianwei Zhao via B4 Relay @ 2026-05-21 8:26 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Xianwei Zhao
In-Reply-To: <20260521-s6-s7-pwm-v3-0-57b073fbafef@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add support for Amlogic S7 PWM. Amlogic S7 different from the
previous SoCs, a controller includes one pwm, at the same time,
the controller has only one input clock source.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/pwm/pwm-meson.c | 41 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 8c6bf3d49753..66c41bf036de 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -113,6 +113,7 @@ struct meson_pwm_data {
int (*channels_init)(struct pwm_chip *chip);
bool has_constant;
bool has_polarity;
+ u8 npwm;
};
struct meson_pwm {
@@ -503,6 +504,18 @@ static void meson_pwm_s4_put_clk(void *data)
clk_put(clk);
}
+static int meson_pwm_init_channels_s7(struct pwm_chip *chip)
+{
+ struct device *dev = pwmchip_parent(chip);
+ struct meson_pwm *meson = to_meson_pwm(chip);
+
+ meson->channels[0].clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(meson->channels[0].clk))
+ return dev_err_probe(dev, PTR_ERR(meson->channels[0].clk),
+ "Failed to get clk\n");
+ return 0;
+}
+
static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
{
struct device *dev = pwmchip_parent(chip);
@@ -530,6 +543,7 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *chip)
static const struct meson_pwm_data pwm_meson8b_data = {
.parent_names = { "xtal", NULL, "fclk_div4", "fclk_div3" },
.channels_init = meson_pwm_init_channels_meson8b_legacy,
+ .npwm = MESON_NUM_PWMS,
};
/*
@@ -539,6 +553,7 @@ static const struct meson_pwm_data pwm_meson8b_data = {
static const struct meson_pwm_data pwm_gxbb_ao_data = {
.parent_names = { "xtal", "clk81", NULL, NULL },
.channels_init = meson_pwm_init_channels_meson8b_legacy,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_axg_ee_data = {
@@ -546,6 +561,7 @@ static const struct meson_pwm_data pwm_axg_ee_data = {
.channels_init = meson_pwm_init_channels_meson8b_legacy,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_axg_ao_data = {
@@ -553,6 +569,7 @@ static const struct meson_pwm_data pwm_axg_ao_data = {
.channels_init = meson_pwm_init_channels_meson8b_legacy,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_g12a_ee_data = {
@@ -560,6 +577,7 @@ static const struct meson_pwm_data pwm_g12a_ee_data = {
.channels_init = meson_pwm_init_channels_meson8b_legacy,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
@@ -567,6 +585,7 @@ static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
.channels_init = meson_pwm_init_channels_meson8b_legacy,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
@@ -574,22 +593,33 @@ static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
.channels_init = meson_pwm_init_channels_meson8b_legacy,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_meson8_v2_data = {
.channels_init = meson_pwm_init_channels_meson8b_v2,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_meson_axg_v2_data = {
.channels_init = meson_pwm_init_channels_meson8b_v2,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
};
static const struct meson_pwm_data pwm_s4_data = {
.channels_init = meson_pwm_init_channels_s4,
.has_constant = true,
.has_polarity = true,
+ .npwm = MESON_NUM_PWMS,
+};
+
+static const struct meson_pwm_data pwm_s7_data = {
+ .channels_init = meson_pwm_init_channels_s7,
+ .has_constant = true,
+ .has_polarity = true,
+ .npwm = 1,
};
static const struct of_device_id meson_pwm_matches[] = {
@@ -642,7 +672,11 @@ static const struct of_device_id meson_pwm_matches[] = {
.compatible = "amlogic,meson-s4-pwm",
.data = &pwm_s4_data
},
- {},
+ {
+ .compatible = "amlogic,s7-pwm",
+ .data = &pwm_s7_data
+ },
+ { }
};
MODULE_DEVICE_TABLE(of, meson_pwm_matches);
@@ -650,9 +684,10 @@ static int meson_pwm_probe(struct platform_device *pdev)
{
struct pwm_chip *chip;
struct meson_pwm *meson;
+ const struct meson_pwm_data *pdata = of_device_get_match_data(&pdev->dev);
int err;
- chip = devm_pwmchip_alloc(&pdev->dev, MESON_NUM_PWMS, sizeof(*meson));
+ chip = devm_pwmchip_alloc(&pdev->dev, pdata->npwm, sizeof(*meson));
if (IS_ERR(chip))
return PTR_ERR(chip);
meson = to_meson_pwm(chip);
@@ -664,7 +699,7 @@ static int meson_pwm_probe(struct platform_device *pdev)
spin_lock_init(&meson->lock);
chip->ops = &meson_pwm_ops;
- meson->data = of_device_get_match_data(&pdev->dev);
+ meson->data = pdata;
err = meson->data->channels_init(chip);
if (err < 0)
--
2.52.0
^ permalink raw reply related
* Re: [PATCH 5/6] firmware: samsung: acpm: Add TMU protocol support
From: Peter Griffin @ 2026-05-21 8:25 UTC (permalink / raw)
To: Alexey Klimov
Cc: Tudor Ambarus, Krzysztof Kozlowski, Michael Turquette,
Stephen Boyd, Lee Jones, Alim Akhtar, Sylwester Nawrocki,
Chanwoo Choi, André Draszik, linux-kernel, linux-samsung-soc,
linux-arm-kernel, linux-clk, jyescas, kernel-team,
Krzysztof Kozlowski
In-Reply-To: <DINT2DFDVWFX.BGTG7LOC91RH@linaro.org>
Hi Alexey,
On Wed, 20 May 2026 at 22:01, Alexey Klimov <alexey.klimov@linaro.org> wrote:
>
> Hi Tudor,
>
> On Tue May 19, 2026 at 4:46 PM BST, Tudor Ambarus wrote:
> > Hi, Alexey,
> >
> > On 5/18/26 2:24 PM, Alexey Klimov wrote:
> >> Thinking further about this I'd humbly suggest that even
> >>
> >> if (fw_err >= 0)
> >> return 0;
> >>
> >> pr_debug_ratelimited("ACPM tmu call returned: %x\n", fw_err);
> >> or pr_debug(...);
> >>
> >> if (fw_err == -1)
> >> return -EACCES;
> >>
> >> some debug message would do.
> >> Perhaps we need some convertation, for instance as it is done in scmi
> >> code (scmi_to_linux_errno(), scmi_linux_errmap[]). But I don't have any
> >> data for mapping acpm errors to some human meanings.
> >
> > I did that for the pmic helpers. I don't need any debug prints for
> > gs101 TMU as I have clear instructions from firmware: 0 for success,
> > -1 for error.
>
> This doesn't look like a right approach for upstreaming a ACPM TMU
> framework.
>
> You are trying to submit a gs101-specific implementation masquerading
> it as a generic ACPM TMU framework, while explicitly pushing the
> refactoring work onto the next developer to add support for other
> SoCs in this generic ACPM code.
>
> The ACPM TMU protocol implementation on Exynos850 is different: it uses
> different error codes, and half of the calls in this 'generic' driver
> are not even implemented in the Exynos850 firmware. Relying on a
> hardcoded if (fw_err == -1) in a driver named generic ACPM is broken
> by design and may silently swallow critical firmware errors on other
> SoCs.
>
> What about such options below?
> - rename the driver to reflect reality: rename this specifically to
> gs101-acpm-tmu-something to reflect that it is tailored for gs101-s;
>
> or
> - abstract the firmware error handling paths through driver_data or
> a dedicated ops structure now, so that other SoCs can cleanly hook into
> it without having to rewrite the logic later.
AFAIK it's pretty normal not to add new hooks before they are
required. I think the approach taken in this series makes sense, as
it's the developer adding support for SoC #2 who best knows what the
differences are on their platform versus what exists upstream.
Similarly, the developer adding support for SoC #3 may have different
requirements to e850 and gs101 and that developer is best placed to
refactor and add hooks or quirks that are required for that platform.
Let's not try to boil the ocean with this series, it's targeting GS101
support. We can evolve it for future SoCs as those requirements and
differences become clear.
Peter
Peter
^ permalink raw reply
* [PATCH] arm64: tlb: Flush walk cache when unsharing PMD tables
From: Zeng Heng @ 2026-05-21 7:30 UTC (permalink / raw)
To: will, catalin.marinas, akpm, npiggin, aneesh.kumar, peterz
Cc: linux-kernel, wangkefeng.wang, linux-arm-kernel, linux-mm,
linux-arch
From: Zeng Heng <zengheng4@huawei.com>
When huge_pmd_unshare() is called to unshare a PMD table, the
tlb_unshare_pmd_ptdesc() function sets tlb->unshared_tables=true
but the aarch64 tlb_flush() only checked tlb->freed_tables to
determine whether to use TLBF_NONE (vae1is, invalidates walk
cache) or TLBF_NOWALKCACHE (vale1is, leaf-only).
This caused the stale PMD page table entry to remain in the walk cache
after unshare, potentially leading to incorrect page table walks.
Fix by including unshared_tables in the check, so that when
unsharing tables, TLBF_NONE is used and the walk cache is properly
invalidated.
Here is the detailed distinction between vae1is and vale1is:
| Instruction Combination | Actual Invalidation Scope |
| ------------------------ | --------------------------------------------------|
| `VAE1IS` + TTL=`0` | All entries at all levels (full invalidation) |
| `VAE1IS` + TTL=`2` (L2) | Non-leaf at Level 0/1 + leaf at Level 2 |
| `VALE1IS` + TTL=`0` | Leaf entries at all levels (non-leaf not cleared) |
| `VALE1IS` + TTL=`2` (L2) | Leaf entry at Level 2 only |
Signed-off-by: Zeng Heng <zengheng4@huawei.com>
---
arch/arm64/include/asm/tlb.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 10869d7731b8..751bd57bc3ba 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -53,7 +53,8 @@ static inline int tlb_get_level(struct mmu_gather *tlb)
static inline void tlb_flush(struct mmu_gather *tlb)
{
struct vm_area_struct vma = TLB_FLUSH_VMA(tlb->mm, 0);
- tlbf_t flags = tlb->freed_tables ? TLBF_NONE : TLBF_NOWALKCACHE;
+ tlbf_t flags = (tlb->freed_tables || tlb->unshared_tables) ?
+ TLBF_NONE : TLBF_NOWALKCACHE;
unsigned long stride = tlb_get_unmap_size(tlb);
int tlb_level = tlb_get_level(tlb);
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2] iommu: Allow device driver to use its own PASID space for SVA
From: Joonwon Kang @ 2026-05-21 8:25 UTC (permalink / raw)
To: baolu.lu
Cc: Alexander.Grest, alexander.shishkin, amhetre, bp, dave.hansen,
easwar.hariharan, hpa, iommu, jacob.jun.pan, jgg, joonwonkang,
joro, jpb, kas, kees, kevin.tian, linux-arm-kernel, linux-kernel,
mingo, nicolinc, peterz, praan, robin.murphy, ryasuoka, smostafa,
sohil.mehta, tglx, will, x86, xin
In-Reply-To: <fc024071-2f82-412e-aea2-459d171b89f9@linux.intel.com>
Hi Baolu, thanks for your review.
> On 5/20/26 23:07, Joonwon Kang wrote:
> > For SVA, the IOMMU core always allocates PASID from the global PASID
> > space. The use of this global PASID space comes from the limitation of
> > the ENQCMD instruction in Intel CPUs that it fetches its PASID operand
> > from IA32_PASID, which is per-process; when a process wants to
> > communicate with multiple devices with the ENQCMD instruction, it cannot
> > change its PASID for each device without the kernel's intervention. Also
> > note that ARM introduced a similar instruction, which is ST64BV0.
> >
> > Due to this nature, SVA with ARM SMMU v3 has been found not working in
> > our environment when other modules/devices compete for PASID. The
> > environment looks as follows:
> >
> > - The device is not a PCIe device.
> > - The device is to use SVA.
> > - The supported SSID/PASID space is very small for the device; only 1 to
> > 3 SSIDs are supported.
> >
> > With this setup, when other modules have allocated all the PASIDs that
> > our device is expected to use from the global PASID space via APIs like
> > iommu_alloc_global_pasid() or iommu_sva_bind_device(), SVA binding to
> > our device fails due to the lack of available PASIDs.
> >
> > This commit resolves the issue by allowing device driver to maintain its
> > own PASID space and assign a PASID from that for the process-device bond
> > via a new API called `iommu_sva_bind_device_pasid(dev, mm, pasid)`. Doing
> > that, however, will disallow the process to execute the ENQCMD-like
> > instructions at EL0. It is because the process cannot change its PASID in
> > IA32_PASID(or ACCDATA_EL1 on ARM) for each device without the kernel's
> > intervention. For this reason, calling `iommu_sva_bind_device()` and then
> > `iommu_sva_bind_device_pasid()` for the same process will not be allowed
> > and vice versa.
> >
> > Currently, there is a limitation that a process simultaneously doing SVA
> > with multiple devices with different PASIDs is not supported. So, calling
> > `iommu_sva_bind_device_pasid()` multiple times for the same process with
> > different devices will not be allowed for now while that for
> > `iommu_sva_bind_device()` will be.
> >
> > Another limitation is that a process cannot do `iommu_sva_bind_device()`
> > if it has ever done `iommu_sva_bind_device_pasid()` even though it has
> > been unbound after use.
> >
> > Suggested-by: Jason Gunthorpe<jgg@ziepe.ca>
> > Suggested-by: Kevin Tian<kevin.tian@intel.com>
> > Signed-off-by: Joonwon Kang<joonwonkang@google.com>
> > ---
> > v2: Reuse iommu_mm->pasid after SVA bound by iommu_sva_bind_device_pasid()
> > is unbound.
> > v1: Initial version.
> >
> > arch/x86/kernel/traps.c | 9 +--
> > drivers/iommu/iommu-sva.c | 151 +++++++++++++++++++++++++++++---------
> > include/linux/iommu.h | 14 +++-
> > 3 files changed, 134 insertions(+), 40 deletions(-)
> >
> > diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> > index 0ca3912ecb7f..0131c8e5fb10 100644
> > --- a/arch/x86/kernel/traps.c
> > +++ b/arch/x86/kernel/traps.c
> > @@ -857,13 +857,12 @@ static bool try_fixup_enqcmd_gp(void)
> > return false;
> >
> > /*
> > - * If the mm has not been allocated a
> > - * PASID, the #GP can not be fixed up.
> > + * If the mm has not been allocated a PASID or ENQCMD has been
> > + * disallowed, the #GP can not be fixed up.
> > */
> > - if (!mm_valid_pasid(current->mm))
> > - return false;
> > -
> > pasid = mm_get_enqcmd_pasid(current->mm);
> > + if (pasid == IOMMU_PASID_INVALID)
> > + return false;
> >
> > /*
> > * Did this thread already have its PASID activated?
> > diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c
> > index bc7c7232a43e..a83333651ad0 100644
> > --- a/drivers/iommu/iommu-sva.c
> > +++ b/drivers/iommu/iommu-sva.c
> > @@ -10,6 +10,9 @@
> >
> > #include "iommu-priv.h"
> >
> > +/* Whether pasid is to be allocated from the global PASID space */
> > +#define IOMMU_PASID_GLOBAL_ANY IOMMU_NO_PASID
> > +
> > static DEFINE_MUTEX(iommu_sva_lock);
> > static bool iommu_sva_present;
> > static LIST_HEAD(iommu_sva_mms);
> > @@ -17,10 +20,11 @@ static struct iommu_domain *iommu_sva_domain_alloc(struct device *dev,
> > struct mm_struct *mm);
> >
> > /* Allocate a PASID for the mm within range (inclusive) */
> > -static struct iommu_mm_data *iommu_alloc_mm_data(struct mm_struct *mm, struct device *dev)
> > +static struct iommu_mm_data *iommu_alloc_mm_data(struct mm_struct *mm,
> > + struct device *dev,
> > + ioasid_t pasid)
> > {
> > struct iommu_mm_data *iommu_mm;
> > - ioasid_t pasid;
> >
> > lockdep_assert_held(&iommu_sva_lock);
> >
> > @@ -30,8 +34,27 @@ static struct iommu_mm_data *iommu_alloc_mm_data(struct mm_struct *mm, struct de
> > iommu_mm = mm->iommu_mm;
> > /* Is a PASID already associated with this mm? */
> > if (iommu_mm) {
> > + if ((pasid == IOMMU_PASID_GLOBAL_ANY && !iommu_mm->pasid_global) ||
> > + (pasid != IOMMU_PASID_GLOBAL_ANY && iommu_mm->pasid_global))
> > + return ERR_PTR(-EBUSY);
> > +
> > + if (!iommu_mm->pasid_global) {
> > + if (list_empty(&iommu_mm->sva_domains))
> > + iommu_mm->pasid = pasid;
> > +
> > + if (pasid != iommu_mm->pasid) {
> > + /*
> > + * Currently, a process simultaneously doing
> > + * SVA with multiple devices with different
> > + * PASIDs is not supported.
> > + */
>
> I am a bit confused by the change in this helper and the comments above.
>
> Currently, when an mm is bound to a device, it uses a PASID allocated
> from the global pool. That implies that all devices access the
> application's address space with the same PASID. Now we want to extend
> this by allowing the device driver to manage the PASID for SVA, which
> should mean different devices might use different PASIDs to access the
> application's address space. But this does not seem to match the logic
> in this helper.
>
> Perhaps I overlooked something?
>
I think your understanding is correct. In the long run, the limitations in the
comment and also in the commit message should be removed. I left the work to a
later patch as I am focusing on removing the main blocker first, which is that
a process is blocked by another irrelevant process for doing SVA as described
in the commit message. Currently, SVA for a process with different PASIDs will
only be allowed one after another, not simultaneously, and the current users of
`iommu_sva_bind_device()` should not be affected by this patch.
So, this patch should be enough to fix our current main problem. Can we leave
it to a later patch? or do you think we should remove the limitations now
although there is no requirement yet?
Thanks,
Joonwon Kang
> > + return ERR_PTR(-ENOSPC);
> > + }
> > + }
> > +
> > if (iommu_mm->pasid >= dev->iommu->max_pasids)
> > return ERR_PTR(-EOVERFLOW);
> > +
> > return iommu_mm;
> > }
^ permalink raw reply
* [PATCH net-next v4 6/6] net: phy: air_an8801: ensure maximum available speed link use
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
To ensure that the Airoha AN8801R PHY uses the maximum available link
speed, an additional register write is needed to configure the function
mode for either 1G or 100M/10M operation after link detection.
So, in air_an8801 driver, implement a custom read_status callback, that
after genphy_read_status determines the link speed, sets the bit 0 of
the link mode register (REG_LINK_MODE) if the detected speed is 1Gbps,
or unsets it otherwise.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_an8801.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
index 73f94e84da07..c64fa153b738 100644
--- a/drivers/net/phy/air_an8801.c
+++ b/drivers/net/phy/air_an8801.c
@@ -977,6 +977,48 @@ static int an8801r_config_init(struct phy_device *phydev)
return 0;
}
+static int an8801r_read_status(struct phy_device *phydev)
+{
+ int prev_speed, ret;
+ u32 val;
+
+ prev_speed = phydev->speed;
+
+ ret = genphy_read_status(phydev);
+ if (ret)
+ return ret;
+
+ if (!phydev->link) {
+ phydev->speed = SPEED_UNKNOWN;
+ return 0;
+ }
+
+ if (prev_speed != phydev->speed) {
+ /* Ensure that PHY switches to 1G speed when available,
+ * by configuring the function mode for either 1G or 100M/10M
+ * operation.
+ * Therefore, set the link mode register, after read_status
+ * determines the link speed.
+ */
+ val = phydev->speed == SPEED_1000 ?
+ AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+ ret = an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LINK_MODE,
+ AN8801_BPBUS_LINK_MODE_1000,
+ val);
+ if (ret) {
+ /* Restore previous speed on failure to ensure this
+ * register setting is retried on the next poll
+ */
+ phydev->speed = prev_speed;
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int an8801r_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -1074,6 +1116,7 @@ static struct phy_driver airoha_driver[] = {
.suspend = an8801r_suspend,
.resume = an8801r_resume,
.config_aneg = genphy_config_aneg,
+ .read_status = an8801r_read_status,
.config_intr = an8801r_config_intr,
.handle_interrupt = an8801r_handle_interrupt,
.set_wol = an8801r_set_wol,
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 5/6] net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
speeds, and Wake on LAN and PHY interrupts.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8801.c | 1101 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1108 insertions(+)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d969a792beb5..099f25dceabb 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -90,6 +90,12 @@ config AS21XXX_PHY
AS21210PB1 that all register with the PHY ID 0x7500 0x7500
before the firmware is loaded.
+config AIR_AN8801_PHY
+ tristate "Airoha AN8801 Gigabit PHY"
+ select AIR_NET_PHYLIB
+ help
+ Currently supports the Airoha AN8801R PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7cf1fa9e12cb..de660ae94945 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -29,6 +29,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
+obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
new file mode 100644
index 000000000000..73f94e84da07
--- /dev/null
+++ b/drivers/net/phy/air_an8801.c
@@ -0,0 +1,1101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for the Airoha AN8801 Gigabit PHY.
+ *
+ * Copyright (C) 2025 Airoha Technology Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/pm_wakeirq.h>
+
+#include "air_phy_lib.h"
+
+#define AN8801R_PHY_ID 0xc0ff0421
+
+/* MII Registers */
+
+/* MII Registers - Airoha Page 1 */
+#define AN8801_EXT_REG_PHY 0x14
+#define AN8801_EXT_PHY_STATUS0 GENMASK(1, 0)
+#define AN8801_EXT_PHY_DOWNSHIFT_CTL GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
+#define AN8801_EXT_PHY_DOWNSHIFT_EN BIT(4)
+#define AN8801_EXT_PHY_CTRL0 BIT(5)
+#define AN8801_EXT_PHY_STATUS1 GENMASK(8, 6)
+#define AN8801_EXT_PHY_CTRL1 GENMASK(14, 9)
+
+/* MII Registers - Airoha Page 4 */
+#define AN8801_PBUS_ACCESS BIT(28)
+#define AN8801_PBUS_EPHY_ACCESS BIT(24)
+#define AN8801_PBUS_CL22_ACCESS BIT(23)
+
+/* BPBUS Registers */
+#define AN8801_BPBUS_REG_LED_GPIO 0x54
+#define AN8801_BPBUS_REG_LED_ID_SEL 0x58
+#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3))
+#define LED_ID_GPIO_SEL_MASK(gpio) (0x7 << ((gpio) * 3))
+#define AN8801_BPBUS_REG_GPIO_MODE 0x70
+#define AN8801_BPBUS_REG_PHY_IRQ_GPIO 0x7c
+#define AN8801_PHY_IRQ_GPIO_NUM_MASK GENMASK(19, 16)
+#define AN8801_PHY_IRQ_GPIO_NUM 1
+
+#define AN8801_BPBUS_REG_CKO 0x1a4
+#define AN8801_CKO_OUTPUT_MODE_AUTO 3
+
+#define AN8801_BPBUS_REG_LINK_MODE 0x5054
+#define AN8801_BPBUS_LINK_MODE_1000 BIT(0)
+
+#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004
+#define AN8801_BYP_PTP_SGMII_TO_GPHY BIT(8)
+#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0)
+
+#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024
+#define RGMII_DELAY_STEP_MASK GENMASK(2, 0)
+#define RGMII_DELAY_NO_STEP 0
+#define RGMII_DELAY_STEP_1 1
+#define RGMII_DELAY_STEP_2 2
+#define RGMII_DELAY_STEP_3 3
+#define RGMII_DELAY_STEP_4 4
+#define RGMII_DELAY_STEP_5 5
+#define RGMII_DELAY_STEP_6 6
+#define RGMII_DELAY_STEP_7 7
+#define RGMII_TXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII TX delay setting, corresponding to a 1.883ns delay */
+#define AN8801_RGMII_TXDELAY_DEFAULT RGMII_DELAY_STEP_4
+
+#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c
+#define RGMII_RXDELAY_ALIGN BIT(4)
+#define RGMII_RXDELAY_FORCE_MODE BIT(24)
+
+/* Default RGMII RX delay setting, corresponding to a 1.992ns delay,
+ * when align bit is set or -0.008ns otherwise.
+ */
+#define AN8801_RGMII_RXDELAY_DEFAULT RGMII_DELAY_NO_STEP
+
+#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */
+#define AN8801_EFIFO_ALL_EN GENMASK(7, 0)
+#define AN8801_EFIFO_RX_EN BIT(0)
+#define AN8801_EFIFO_TX_EN BIT(1)
+#define AN8801_EFIFO_RX_CLK_EN BIT(2)
+#define AN8801_EFIFO_TX_CLK_EN BIT(3)
+#define AN8801_EFIFO_RX_EEE_EN BIT(4)
+#define AN8801_EFIFO_TX_EEE_EN BIT(5)
+#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6)
+#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7)
+
+#define AN8801_BPBUS_REG_WOL_MAC_16_47 0x285114
+#define AN8801_BPBUS_REG_WOL_MAC_0_15 0x285118
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL1 0x285400
+#define AN8801_WOL_WAKE_MAGIC_EN GENMASK(3, 1)
+#define AN8801_WOL_WAKE_LNKCHG_EN BIT(4)
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL2 0x285404
+#define AN8801_WAKE_OUT_TYPE_PULSE BIT(0) /* Set/Unset: Pulse/Static */
+#define AN8801_WAKE_OUT_POLARITY_NEG BIT(1) /* Set/Unset: Negative/Positive */
+#define AN8801_WAKE_OUT_WIDTH GENMASK(3, 2)
+#define AN8801_WAKE_OUT_84MS 0
+#define AN8801_WAKE_OUT_168MS 1
+#define AN8801_WAKE_OUT_336MS 2
+#define AN8801_WAKE_OUT_672MS 3
+#define AN8801_WAKE_OUT_EN BIT(4)
+#define AN8801_PME_WAKEUP_CLR BIT(8)
+
+#define AN8801_BPBUS_REG_WAKE_IRQ_EN 0x285700
+#define AN8801_BPBUS_REG_WAKE_IRQ_STS 0x285704
+#define AN8801_IRQ_WAKE_LNKCHG BIT(0) /* Wake on link change */
+#define AN8801_IRQ_WAKE_UNIPKT BIT(1) /* Wake on unicast packet */
+#define AN8801_IRQ_WAKE_MULPKT BIT(2) /* Wake on multicast packet */
+#define AN8801_IRQ_WAKE_BCPKT BIT(3) /* Wake on broadcast packet */
+#define AN8801_IRQ_WAKE_MAGICPKT BIT(4) /* Wake on magic packet */
+#define AN8801_IRQ_WAKE_ALL GENMASK(4, 0)
+
+/* MDIO_MMD_VEND1 Registers */
+#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE 0x13
+#define AN8801_PHY_PAIR_DLY_SEL_A_GBE GENMASK(14, 12)
+#define AN8801_PHY_PAIR_DLY_SEL_B_GBE GENMASK(10, 8)
+#define AN8801_PHY_PAIR_DLY_SEL_C_GBE GENMASK(6, 4)
+#define AN8801_PHY_PAIR_DLY_SEL_D_GBE GENMASK(2, 0)
+#define AN8801_PHY_RXADC_CTRL 0xd8
+#define AN8801_PHY_RXADC_SAMP_PHSEL_A BIT(12)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_B BIT(8)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_C BIT(4)
+#define AN8801_PHY_RXADC_SAMP_PHSEL_D BIT(0)
+#define AN8801_PHY_RXADC_REV_0 0xd9
+#define AN8801_PHY_RXADC_REV_MASK_A GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_B GENMASK(7, 0)
+#define AN8801_PHY_RXADC_REV_1 0xda
+#define AN8801_PHY_RXADC_REV_MASK_C GENMASK(15, 8)
+#define AN8801_PHY_RXADC_REV_MASK_D GENMASK(7, 0)
+
+/* MDIO_MMD_VEND2 Registers */
+#define LED_BCR 0x21
+#define LED_BCR_MODE_MASK GENMASK(1, 0)
+#define LED_BCR_TIME_TEST BIT(2)
+#define LED_BCR_CLK_EN BIT(3)
+#define LED_BCR_EVT_ALL BIT(4)
+#define LED_BCR_EXT_CTRL BIT(15)
+#define LED_BCR_MODE_DISABLE 0
+#define LED_BCR_MODE_2LED 1
+#define LED_BCR_MODE_3LED_1 2
+#define LED_BCR_MODE_3LED_2 3
+
+#define LED_ON_DUR 0x22
+#define LED_ON_DUR_MASK GENMASK(15, 0)
+
+#define LED_BLINK_DUR 0x23
+#define LED_BLINK_DUR_MASK GENMASK(15, 0)
+
+#define LED_ON_CTRL(i) (0x24 + ((i) * 2))
+#define LED_ON_EVT_MASK GENMASK(6, 0)
+#define LED_ON_EVT_LINK_1000M BIT(0)
+#define LED_ON_EVT_LINK_100M BIT(1)
+#define LED_ON_EVT_LINK_10M BIT(2)
+#define LED_ON_EVT_LINK_DN BIT(3)
+#define LED_ON_EVT_FDX BIT(4)
+#define LED_ON_EVT_HDX BIT(5)
+#define LED_ON_EVT_FORCE BIT(6)
+#define LED_ON_POL BIT(14)
+#define LED_ON_EN BIT(15)
+
+#define LED_BLINK_CTRL(i) (0x25 + ((i) * 2))
+#define LED_BLINK_EVT_MASK GENMASK(9, 0)
+#define LED_BLINK_EVT_1000M_TX BIT(0)
+#define LED_BLINK_EVT_1000M_RX BIT(1)
+#define LED_BLINK_EVT_100M_TX BIT(2)
+#define LED_BLINK_EVT_100M_RX BIT(3)
+#define LED_BLINK_EVT_10M_TX BIT(4)
+#define LED_BLINK_EVT_10M_RX BIT(5)
+#define LED_BLINK_EVT_COLLISION BIT(6)
+#define LED_BLINK_EVT_RX_CRC_ERR BIT(7)
+#define LED_BLINK_EVT_RX_IDLE_ERR BIT(8)
+#define LED_BLINK_EVT_FORCE BIT(9)
+
+#define AN8801R_NUM_LEDS 3
+#define AN8801_PERIOD_SHIFT 15
+#define AN8801_PERIOD_UNIT 32768 /* (1 << AN8801_PERIOD_SHIFT) */
+#define AN8801_MAX_PERIOD_MS 2147
+
+#define AN8801_LED_DURATION_UNIT_US 32768
+
+#define AN8801_REG_PHY_INTERNAL0 0x600
+#define AN8801_REG_PHY_INTERNAL1 0x601
+#define AN8801_PHY_INTFUNC_MASK GENMASK(15, 0) /* PHY internal functions */
+
+enum an8801r_led_fn {
+ AN8801R_LED_FN_NONE,
+ AN8801R_LED_FN_LINK,
+ AN8801R_LED_FN_ACTIVITY,
+ AN8801R_LED_FN_MAX,
+};
+
+struct an8801r_priv {
+ bool wake_magic_enabled;
+ bool wake_lnkchg_enabled;
+};
+
+static const unsigned long an8801r_led_trig = BIT(TRIGGER_NETDEV_LINK) |
+ BIT(TRIGGER_NETDEV_LINK_10) |
+ BIT(TRIGGER_NETDEV_LINK_100) |
+ BIT(TRIGGER_NETDEV_LINK_1000) |
+ BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_RX_ERR) |
+ BIT(TRIGGER_NETDEV_TX);
+
+static int an8801_buckpbus_reg_rmw(struct phy_device *phydev,
+ u32 addr, u32 mask, u32 set)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, set);
+}
+
+static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, mask);
+}
+
+static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev,
+ u32 addr, u32 mask)
+{
+ return air_phy_buckpbus_reg_modify(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ mask, 0);
+}
+
+static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr,
+ u32 data)
+{
+ return air_phy_buckpbus_reg_write(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static int an8801_buckpbus_reg_read(struct phy_device *phydev, u32 addr,
+ u32 *data)
+{
+ return air_phy_buckpbus_reg_read(phydev,
+ addr | AN8801_PBUS_ACCESS,
+ data);
+}
+
+static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms)
+{
+ u32 req_ns, regval;
+
+ if (req_ms > AN8801_MAX_PERIOD_MS)
+ req_ms = AN8801_MAX_PERIOD_MS;
+
+ req_ns = req_ms * NSEC_PER_MSEC;
+
+ /* Round to the nearest period unit... */
+ regval = req_ns + (AN8801_PERIOD_UNIT / 2);
+
+ /* ...and now divide by the full period */
+ regval >>= AN8801_PERIOD_SHIFT;
+
+ return regval;
+}
+
+static int an8801r_led_blink_set(struct phy_device *phydev, u8 index,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ u32 hw_delay_on, hw_delay_off;
+ bool blink;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ if (delay_on && delay_off) {
+ blink = true;
+
+ if (*delay_on == 0 || *delay_off == 0) {
+ *delay_on = 64;
+ *delay_off = 64;
+ }
+
+ hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on);
+ hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off);
+ } else {
+ blink = false;
+ }
+
+ if (blink) {
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR,
+ (hw_delay_on + hw_delay_off) &
+ LED_BLINK_DUR_MASK);
+ if (ret)
+ goto error;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR,
+ hw_delay_on);
+ if (ret)
+ goto error;
+ }
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK,
+ blink ? LED_BLINK_EVT_FORCE : 0);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ 0);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, blink ? LED_ON_EN : 0);
+
+error:
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, 0);
+ return ret;
+}
+
+static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index,
+ enum led_brightness value)
+{
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK,
+ (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN);
+}
+
+static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index,
+ unsigned long *rules)
+{
+ int on, blink;
+
+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index));
+ if (on < 0)
+ return on;
+
+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index));
+ if (blink < 0)
+ return blink;
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_10, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_100M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_100, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+
+ if (FIELD_GET(LED_ON_EVT_LINK_10M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_100M, on) &&
+ FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+ __set_bit(TRIGGER_NETDEV_LINK, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_RX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_RX, blink))
+ __set_bit(TRIGGER_NETDEV_RX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_100M_TX, blink) ||
+ FIELD_GET(LED_BLINK_EVT_1000M_TX, blink))
+ __set_bit(TRIGGER_NETDEV_TX, rules);
+
+ if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink))
+ __set_bit(TRIGGER_NETDEV_RX_ERR, rules);
+
+ return 0;
+}
+
+static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink)
+{
+ /* All combinations of the supported triggers are allowed */
+ if (rules & ~an8801r_led_trig)
+ return -EOPNOTSUPP;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+ *on |= LED_ON_EVT_LINK_10M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+ *on |= LED_ON_EVT_LINK_100M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+ *on |= LED_ON_EVT_LINK_1000M;
+
+ if (test_bit(TRIGGER_NETDEV_LINK, &rules)) {
+ *on |= LED_ON_EVT_LINK_10M;
+ *on |= LED_ON_EVT_LINK_100M;
+ *on |= LED_ON_EVT_LINK_1000M;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_RX;
+ *blink |= LED_BLINK_EVT_100M_RX;
+ *blink |= LED_BLINK_EVT_1000M_RX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_TX, &rules)) {
+ *blink |= LED_BLINK_EVT_10M_TX;
+ *blink |= LED_BLINK_EVT_100M_TX;
+ *blink |= LED_BLINK_EVT_1000M_TX;
+ }
+
+ if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules))
+ *blink |= LED_BLINK_EVT_RX_CRC_ERR;
+
+ return 0;
+}
+
+static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ return an8801r_led_trig_to_hw(rules, &on, &blink);
+}
+
+static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index,
+ unsigned long rules)
+{
+ u16 on = 0, blink = 0;
+ int ret;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ ret = an8801r_led_trig_to_hw(rules, &on, &blink);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EVT_MASK, on);
+ if (ret)
+ return ret;
+
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+ LED_BLINK_EVT_MASK, blink);
+ if (ret)
+ return ret;
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_EN, on | blink ? LED_ON_EN : 0);
+}
+
+static int an8801r_led_polarity_set(struct phy_device *phydev, int index,
+ unsigned long modes)
+{
+ bool active_high = true;
+ unsigned long mode;
+
+ if (index >= AN8801R_NUM_LEDS)
+ return -EINVAL;
+
+ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+ switch (mode) {
+ case PHY_LED_ACTIVE_HIGH:
+ break;
+ case PHY_LED_ACTIVE_LOW:
+ active_high = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+ LED_ON_POL, active_high ? LED_ON_POL : 0);
+}
+
+static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg)
+{
+ int led_id, ret;
+
+ /* Set LED BCR Enable */
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR,
+ LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+ if (ret)
+ return ret;
+
+ for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) {
+ unsigned long led_trigger = 0;
+ u32 led_gpio = led_id + 1;
+
+ switch (led_cfg[led_id]) {
+ case AN8801R_LED_FN_LINK:
+ led_trigger = BIT(TRIGGER_NETDEV_LINK);
+ break;
+ case AN8801R_LED_FN_ACTIVITY:
+ led_trigger = BIT(TRIGGER_NETDEV_RX) |
+ BIT(TRIGGER_NETDEV_TX);
+ break;
+ default:
+ led_trigger = 0;
+ break;
+ }
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_LED_GPIO,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_rmw(phydev,
+ AN8801_BPBUS_REG_LED_ID_SEL,
+ LED_ID_GPIO_SEL_MASK(led_gpio),
+ LED_ID_GPIO_SEL(led_id,
+ led_gpio));
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_GPIO_MODE,
+ BIT(led_gpio));
+ if (ret)
+ return ret;
+
+ if (!led_trigger)
+ continue;
+
+ ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static int an8801r_reset_wake(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val = 0;
+ int ret;
+
+ /* Enable wakeup clear and disable wake up output */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_PME_WAKEUP_CLR |
+ AN8801_WAKE_OUT_POLARITY_NEG);
+ if (ret)
+ return ret;
+
+ /* Clear WAKEUP_CTL1 register before enabling the wakeup events
+ * again
+ */
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ 0);
+ if (ret)
+ return ret;
+
+ if (priv->wake_magic_enabled)
+ reg_val |= AN8801_WOL_WAKE_MAGIC_EN;
+
+ if (priv->wake_lnkchg_enabled)
+ reg_val |= AN8801_WOL_WAKE_LNKCHG_EN;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* Disable wake up clear and re-enable wake up output */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+ AN8801_WAKE_OUT_POLARITY_NEG |
+ AN8801_WAKE_OUT_EN);
+}
+
+static int an8801r_ack_interrupt(struct phy_device *phydev)
+{
+ int ret;
+
+ /* Reset wake status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+
+ /* Clear the interrupts by writing the reg */
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ AN8801_IRQ_WAKE_ALL);
+}
+
+static int an8801r_config_intr(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK,
+ AN8801_PHY_IRQ_GPIO_NUM);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+ 0);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ return an8801r_ack_interrupt(phydev);
+}
+
+static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev)
+{
+ u32 irq_status = 0;
+ bool irq_handled = false;
+ int ret;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+ &irq_status);
+ if (ret)
+ return IRQ_NONE;
+
+ ret = an8801r_ack_interrupt(phydev);
+ if (ret)
+ return IRQ_NONE;
+
+ if (irq_status & AN8801_IRQ_WAKE_MAGICPKT) {
+ pm_wakeup_event(&phydev->mdio.dev, 0);
+ irq_handled = true;
+ }
+
+ if (irq_status & AN8801_IRQ_WAKE_LNKCHG) {
+ phy_trigger_machine(phydev);
+ irq_handled = true;
+ }
+
+ return irq_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static void an8801r_get_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ u32 reg_val;
+ int ret;
+
+ /* If the PHY is not capable of waking the system, then WoL can not
+ * be supported.
+ */
+ if (!device_can_wakeup(&phydev->mdio.dev)) {
+ wol->supported = 0;
+ return;
+ }
+
+ wol->supported = WAKE_MAGIC;
+ wol->wolopts = 0;
+
+ ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+ ®_val);
+ if (ret)
+ return;
+
+ if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
+ wol->wolopts |= WAKE_MAGIC;
+ else
+ wol->wolopts &= ~WAKE_MAGIC;
+}
+
+static int an8801r_set_wol(struct phy_device *phydev,
+ struct ethtool_wolinfo *wol)
+{
+ struct net_device *attach_dev = phydev->attached_dev;
+ const unsigned char *macaddr = attach_dev->dev_addr;
+ struct an8801r_priv *priv = phydev->priv;
+ u32 reg_val;
+ int ret;
+
+ if (!device_can_wakeup(&phydev->mdio.dev))
+ return -EOPNOTSUPP;
+
+ if (wol->wolopts & ~WAKE_MAGIC)
+ return -EINVAL;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ /* MAC bits 16..47 */
+ reg_val = (macaddr[2] << 24) | (macaddr[3] << 16);
+ reg_val |= (macaddr[4] << 8) | (macaddr[5]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_16_47,
+ reg_val);
+ if (ret)
+ return ret;
+
+ /* MAC bits 0..15 */
+ reg_val = (macaddr[0] << 8) | (macaddr[1]);
+
+ ret = an8801_buckpbus_reg_write(phydev,
+ AN8801_BPBUS_REG_WOL_MAC_0_15,
+ reg_val);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+
+ } else {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_MAGIC_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_MAGICPKT);
+ if (ret)
+ return ret;
+ }
+
+ priv->wake_magic_enabled = !!(wol->wolopts & WAKE_MAGIC);
+
+ return device_set_wakeup_enable(&phydev->mdio.dev,
+ priv->wake_magic_enabled);
+}
+
+static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *leds;
+ u32 function_enum_idx;
+ int ret = 0;
+
+ if (!np)
+ return 0;
+
+ /* If devicetree is present, leds configuration is required */
+ leds = of_get_child_by_name(np, "leds");
+ if (!leds)
+ return 0;
+
+ for_each_available_child_of_node_scoped(leds, led) {
+ u32 led_idx;
+
+ ret = of_property_read_u32(led, "reg", &led_idx);
+ if (ret)
+ goto out;
+
+ if (led_idx >= AN8801R_NUM_LEDS) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ret = of_property_read_u32(led, "function-enumerator",
+ &function_enum_idx);
+ if (ret) {
+ function_enum_idx = AN8801R_LED_FN_NONE;
+ ret = 0;
+ }
+
+ if (function_enum_idx >= AN8801R_LED_FN_MAX) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ led_cfg[led_idx] = function_enum_idx;
+ }
+out:
+ of_node_put(leds);
+ return ret;
+}
+
+static int an8801r_rgmii_rxdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable RX delay insertion */
+ reg_val = delay_steps | RGMII_RXDELAY_FORCE_MODE;
+
+ /* Set align bit to add extra offset for RX delay */
+ reg_val |= RGMII_RXDELAY_ALIGN;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_txdelay(struct phy_device *phydev, bool enable,
+ u16 delay_steps)
+{
+ u32 reg_val;
+
+ if (delay_steps > RGMII_DELAY_STEP_MASK)
+ return -EINVAL;
+
+ if (enable) {
+ /* Set force mode bit to enable TX delay insertion */
+ reg_val = delay_steps | RGMII_TXDELAY_FORCE_MODE;
+ } else {
+ reg_val = 0;
+ }
+
+ return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
+ reg_val);
+}
+
+static int an8801r_rgmii_delay_config(struct phy_device *phydev)
+{
+ bool enable_delay;
+ u16 delay_step;
+ int ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_TXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ ret = an8801r_rgmii_txdelay(phydev, enable_delay, delay_step);
+ if (ret)
+ return ret;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+ enable_delay = true;
+ delay_step = AN8801_RGMII_RXDELAY_DEFAULT;
+ } else {
+ enable_delay = false;
+ delay_step = RGMII_DELAY_NO_STEP;
+ }
+
+ return an8801r_rgmii_rxdelay(phydev, enable_delay, delay_step);
+}
+
+static int an8801r_config_init(struct phy_device *phydev)
+{
+ u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
+ int ret;
+
+ ret = an8801r_of_init_leds(phydev, led_default_function);
+ if (ret)
+ return ret;
+
+ /* Disable Low Power Mode (LPM) */
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
+ FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
+ if (ret)
+ return ret;
+
+ /* Set the PHY to perform auto-downshift after 3 auto-negotiation
+ * attempts
+ */
+ ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
+ AN8801_EXT_REG_PHY,
+ FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
+ FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
+ AN8801_EXT_PHY_DOWNSHIFT_EN);
+ if (ret < 0)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP,
+ AN8801_BYP_PTP_RGMII_TO_GPHY);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0),
+ AN8801_EFIFO_RX_EN |
+ AN8801_EFIFO_TX_EN |
+ AN8801_EFIFO_RX_CLK_EN |
+ AN8801_EFIFO_TX_CLK_EN |
+ AN8801_EFIFO_RX_EEE_EN |
+ AN8801_EFIFO_TX_EEE_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2),
+ AN8801_EFIFO_ALL_EN);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ AN8801_PHY_TX_PAIR_DLY_SEL_GBE,
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |
+ FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
+ AN8801_PHY_RXADC_SAMP_PHSEL_A |
+ AN8801_PHY_RXADC_SAMP_PHSEL_C);
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1));
+ if (ret)
+ return ret;
+
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1));
+ if (ret)
+ return ret;
+
+ ret = an8801r_rgmii_delay_config(phydev);
+ if (ret)
+ return ret;
+
+ ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO,
+ AN8801_CKO_OUTPUT_MODE_AUTO);
+ if (ret)
+ return ret;
+
+ ret = an8801r_led_init(phydev, led_default_function);
+ if (ret) {
+ phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int an8801r_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct an8801r_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->wake_lnkchg_enabled = true;
+
+ phydev->priv = priv;
+
+ /* Mark this PHY as wakeup capable and register the interrupt as a
+ * wakeup IRQ if the PHY is marked as a wakeup source in devicetree,
+ * and the interrupt is valid.
+ */
+ if (of_property_read_bool(dev->of_node, "wakeup-source") &&
+ phy_interrupt_is_valid(phydev)) {
+ device_set_wakeup_capable(dev, true);
+ devm_pm_set_wake_irq(dev, phydev->irq);
+ }
+
+ return 0;
+}
+
+static int an8801r_suspend(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ /* If the PHY may wake up by a wake-on-line event, disable the link
+ * interrupt to only keep the WOL magic interrupt enabled
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = false;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_clear_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ if (ret)
+ return ret;
+ }
+
+ /* Reset Wol status */
+ ret = an8801r_reset_wake(phydev);
+ if (ret)
+ return ret;
+ }
+
+ if (!phydev->wol_enabled)
+ return genphy_suspend(phydev);
+
+ return 0;
+}
+
+static int an8801r_resume(struct phy_device *phydev)
+{
+ struct an8801r_priv *priv = phydev->priv;
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret)
+ return ret;
+
+ /* Restore the interrupt enable so phylib can receive link
+ * state interrupts.
+ */
+ if (device_may_wakeup(&phydev->mdio.dev)) {
+ priv->wake_lnkchg_enabled = true;
+
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKEUP_CTL1,
+ AN8801_WOL_WAKE_LNKCHG_EN);
+ if (ret)
+ return ret;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ ret = an8801_buckpbus_reg_set_bits(phydev,
+ AN8801_BPBUS_REG_WAKE_IRQ_EN,
+ AN8801_IRQ_WAKE_LNKCHG);
+ }
+ }
+
+ return ret;
+}
+
+static struct phy_driver airoha_driver[] = {
+{
+ PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
+ .name = "Airoha AN8801R",
+ .probe = an8801r_probe,
+ .config_init = an8801r_config_init,
+ .suspend = an8801r_suspend,
+ .resume = an8801r_resume,
+ .config_aneg = genphy_config_aneg,
+ .config_intr = an8801r_config_intr,
+ .handle_interrupt = an8801r_handle_interrupt,
+ .set_wol = an8801r_set_wol,
+ .get_wol = an8801r_get_wol,
+ .read_page = air_phy_read_page,
+ .write_page = air_phy_write_page,
+ .flags = PHY_ALWAYS_CALL_SUSPEND,
+ .led_brightness_set = an8801r_led_brightness_set,
+ .led_blink_set = an8801r_led_blink_set,
+ .led_hw_is_supported = an8801r_led_hw_is_supported,
+ .led_hw_control_set = an8801r_led_hw_control_set,
+ .led_hw_control_get = an8801r_led_hw_control_get,
+ .led_polarity_set = an8801r_led_polarity_set,
+} };
+module_phy_driver(airoha_driver);
+
+static struct mdio_device_id __maybe_unused an8801_tbl[] = {
+ { PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) },
+ { }
+};
+MODULE_DEVICE_TABLE(mdio, an8801_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8801 PHY driver");
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 4/6] net: phy: Rename Airoha common BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
Rename the BuckPBus register accessors functions present in air_phy_lib
and their calls in air_en8811h driver, so all exported functions start
with the same prefix.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 110 +++++++++++++++++++++---------------------
drivers/net/phy/air_phy_lib.c | 18 +++----
drivers/net/phy/air_phy_lib.h | 12 ++---
3 files changed, 71 insertions(+), 69 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 2498bd3f7993..a42898ae4135 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -287,8 +287,8 @@ static int en8811h_wait_mcu_ready(struct phy_device *phydev)
{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
@@ -313,28 +313,29 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 set1,
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
@@ -346,8 +347,8 @@ static void en8811h_print_fw_version(struct phy_device *phydev)
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
@@ -372,8 +373,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -414,14 +415,14 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -433,8 +434,8 @@ static int en8811h_load_firmware(struct phy_device *phydev)
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
@@ -460,8 +461,8 @@ static int en8811h_restart_mcu(struct phy_device *phydev)
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
@@ -755,7 +756,7 @@ static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
@@ -767,9 +768,9 @@ static int an8811hb_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
@@ -777,8 +778,8 @@ static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
@@ -788,7 +789,7 @@ static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
@@ -854,7 +855,7 @@ static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw,
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
@@ -866,9 +867,9 @@ static int en8811h_clk_enable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
@@ -876,8 +877,8 @@ static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
@@ -887,7 +888,7 @@ static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
@@ -998,9 +999,9 @@ static int an8811hb_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1039,9 +1040,9 @@ static int en8811h_probe(struct phy_device *phydev)
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
@@ -1061,9 +1062,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
@@ -1074,9 +1075,9 @@ static int an8811hb_config_serdes_polarity(struct phy_device *phydev)
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
@@ -1110,9 +1111,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
@@ -1264,8 +1266,8 @@ static int en8811h_read_status(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index aba4f95fe9e6..859fa41406d1 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -137,8 +137,8 @@ static int __air_buckpbus_reg_modify(struct phy_device *phydev,
return 0;
}
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data)
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
{
int saved_page;
int ret = 0;
@@ -154,10 +154,10 @@ int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_read);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data)
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
{
int saved_page;
int ret = 0;
@@ -174,10 +174,10 @@ int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_write);
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set)
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
{
int saved_page;
int ret = 0;
@@ -194,7 +194,7 @@ int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
return phy_restore_page(phydev, saved_page, ret);
}
-EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify);
int air_phy_read_page(struct phy_device *phydev)
{
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index b637f3e0f2d5..a2f8b3725761 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -27,12 +27,12 @@
#define AIR_BPBUS_RD_DATA_HIGH 0x17
#define AIR_BPBUS_RD_DATA_LOW 0x18
-int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
- u32 mask, u32 set);
-int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
- u32 *pbus_data);
-int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
- u32 pbus_data);
+int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 3/6] net: phy: air_phy_lib: Factorize BuckPBus register accessors
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
In preparation of Airoha AN8801R PHY support, move the BuckPBus
register accessors and definitions, present in air_en8811h driver,
into the Airoha PHY shared code (air_phy_lib), so they will be usable
by the new driver without duplicating them.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/air_en8811h.c | 193 ------------------------------------------
drivers/net/phy/air_phy_lib.c | 181 +++++++++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 23 +++++
3 files changed, 204 insertions(+), 193 deletions(-)
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index be7c3426182a..2498bd3f7993 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -42,22 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_PHY_PAGE_STANDARD 0x0000
-#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-
-/* MII Registers Page 4*/
-#define AIR_BPBUS_MODE 0x10
-#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
-#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
-#define AIR_BPBUS_WR_ADDR_HIGH 0x11
-#define AIR_BPBUS_WR_ADDR_LOW 0x12
-#define AIR_BPBUS_WR_DATA_HIGH 0x13
-#define AIR_BPBUS_WR_DATA_LOW 0x14
-#define AIR_BPBUS_RD_ADDR_HIGH 0x15
-#define AIR_BPBUS_RD_ADDR_LOW 0x16
-#define AIR_BPBUS_RD_DATA_HIGH 0x17
-#define AIR_BPBUS_RD_DATA_LOW 0x18
-
/* Registers on MDIO_MMD_VEND1 */
#define EN8811H_PHY_FW_STATUS 0x8009
#define EN8811H_PHY_READY 0x02
@@ -245,183 +229,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int __air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_write(struct phy_device *phydev,
- u32 pbus_address, u32 pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_write(phydev, pbus_address,
- pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int pbus_data_low, pbus_data_high;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- *pbus_data = pbus_data_low | (pbus_data_high << 16);
- return 0;
-}
-
-static int air_buckpbus_reg_read(struct phy_device *phydev,
- u32 pbus_address, u32 *pbus_data)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
-static int __air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int pbus_data_low, pbus_data_high;
- u32 pbus_data_old, pbus_data_new;
- int ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
- if (pbus_data_high < 0)
- return pbus_data_high;
-
- pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
- if (pbus_data_low < 0)
- return pbus_data_low;
-
- pbus_data_old = pbus_data_low | (pbus_data_high << 16);
- pbus_data_new = (pbus_data_old & ~mask) | set;
- if (pbus_data_new == pbus_data_old)
- return 0;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
- upper_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
- lower_16_bits(pbus_address));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
- upper_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
- lower_16_bits(pbus_data_new));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int air_buckpbus_reg_modify(struct phy_device *phydev,
- u32 pbus_address, u32 mask, u32 set)
-{
- int saved_page;
- int ret = 0;
-
- saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-
- if (saved_page >= 0) {
- ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
- set);
- if (ret < 0)
- phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
- pbus_address, ret);
- }
-
- return phy_restore_page(phydev, saved_page, ret);
-}
-
static int __air_write_buf(struct phy_device *phydev, u32 address,
const struct firmware *fw)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
index 8ef5af4becf0..aba4f95fe9e6 100644
--- a/drivers/net/phy/air_phy_lib.c
+++ b/drivers/net/phy/air_phy_lib.c
@@ -10,11 +10,192 @@
#include <linux/export.h>
#include <linux/module.h>
#include <linux/phy.h>
+#include <linux/wordpart.h>
#include "air_phy_lib.h"
#define AIR_EXT_PAGE_ACCESS 0x1f
+static int __air_buckpbus_reg_read(struct phy_device *phydev,
+ u32 pbus_address, u32 *pbus_data)
+{
+ int pbus_data_low, pbus_data_high;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+}
+
+static int __air_buckpbus_reg_write(struct phy_device *phydev,
+ u32 pbus_address, u32 pbus_data)
+{
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int __air_buckpbus_reg_modify(struct phy_device *phydev,
+ u32 pbus_address, u32 mask, u32 set)
+{
+ int pbus_data_low, pbus_data_high;
+ u32 pbus_data_old, pbus_data_new;
+ int ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
+ if (pbus_data_new == pbus_data_old)
+ return 0;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
+ upper_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
+ lower_16_bits(pbus_address));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
+ upper_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
+ lower_16_bits(pbus_data_new));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_read);
+
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_write(phydev, pbus_address,
+ pbus_data);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_write);
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set)
+{
+ int saved_page;
+ int ret = 0;
+
+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+
+ if (saved_page >= 0) {
+ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
+ set);
+ if (ret < 0)
+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
+ pbus_address, ret);
+ }
+
+ return phy_restore_page(phydev, saved_page, ret);
+}
+EXPORT_SYMBOL_GPL(air_buckpbus_reg_modify);
+
int air_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
index 79367e8e5907..b637f3e0f2d5 100644
--- a/drivers/net/phy/air_phy_lib.h
+++ b/drivers/net/phy/air_phy_lib.h
@@ -10,6 +10,29 @@
#include <linux/phy.h>
+#define AIR_PHY_PAGE_STANDARD 0x0000
+#define AIR_PHY_PAGE_EXTENDED_1 0x0001
+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
+
+/* MII Registers Page 4*/
+#define AIR_BPBUS_MODE 0x10
+#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
+#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
+#define AIR_BPBUS_WR_ADDR_HIGH 0x11
+#define AIR_BPBUS_WR_ADDR_LOW 0x12
+#define AIR_BPBUS_WR_DATA_HIGH 0x13
+#define AIR_BPBUS_WR_DATA_LOW 0x14
+#define AIR_BPBUS_RD_ADDR_HIGH 0x15
+#define AIR_BPBUS_RD_ADDR_LOW 0x16
+#define AIR_BPBUS_RD_DATA_HIGH 0x17
+#define AIR_BPBUS_RD_DATA_LOW 0x18
+
+int air_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address,
+ u32 mask, u32 set);
+int air_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address,
+ u32 *pbus_data);
+int air_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address,
+ u32 pbus_data);
int air_phy_read_page(struct phy_device *phydev);
int air_phy_write_page(struct phy_device *phydev, int page);
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 1/6] dt-bindings: net: Add support for Airoha AN8801R GbE PHY
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a new binding to support the Airoha AN8801R Series Gigabit
Ethernet PHY.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../devicetree/bindings/net/airoha,an8801.yaml | 116 +++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
new file mode 100644
index 000000000000..fb2f70ceb33a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8801R Series PHY
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+ The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
+ with Single-port serdes interface for 1000Base-X/RGMII; this chip is
+ compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
+ and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
+ Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
+ Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
+ This PHY also supports up to three user-configurable LEDs, which are
+ usually used for LAN Activity, 100M, 1000M indication.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ethernet-phy-idc0ff.0421
+
+ reg:
+ maxItems: 1
+
+ leds:
+ type: object
+ description:
+ Describes the LEDs associated to the PHY
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^led@[0-2]$":
+ type: object
+ description: PHY LEDs
+ $ref: /schemas/leds/common.yaml#
+
+ properties:
+ reg:
+ enum: [0, 1, 2]
+
+ function-enumerator:
+ enum: [0, 1, 2]
+ description: |
+ Specifies a function for offloading LED functionality to the PHY:
+ 0 - No offloading
+ 1 - Link Availability
+ 2 - Network Activity
+
+ required:
+ - reg
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enable Wake-on-LAN support
+
+required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-idc0ff.0421";
+ reg = <0>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ default-state = "keep";
+ };
+ };
+ };
+ };
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 2/6] net: phy: Add Airoha phy library for shared code
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
In-Reply-To: <20260521-add-airoha-an8801-support-v4-0-1e4837d30ef4@collabora.com>
In preparation of Airoha AN8801R PHY support, split out the interface
functions that will be common between the already present air_en8811h
driver and the new one, and put them into a new library named
air_phy_lib.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_en8811h.c | 13 ++-----------
drivers/net/phy/air_phy_lib.c | 32 ++++++++++++++++++++++++++++++++
drivers/net/phy/air_phy_lib.h | 16 ++++++++++++++++
5 files changed, 57 insertions(+), 11 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 8b51bdc2e945..d969a792beb5 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,10 +92,16 @@ config AS21XXX_PHY
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ select AIR_NET_PHYLIB
select PHY_COMMON_PROPS
help
Currently supports the Airoha EN8811H PHY.
+config AIR_NET_PHYLIB
+ tristate
+ help
+ Airoha Ethernet PHY common library
+
config AMD_PHY
tristate "AMD and Altima PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 05e4878af27a..7cf1fa9e12cb 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,6 +30,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_AMCC_QT2025_PHY) += qt2025.o
obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c
index 29ae73e65caa..be7c3426182a 100644
--- a/drivers/net/phy/air_en8811h.c
+++ b/drivers/net/phy/air_en8811h.c
@@ -21,6 +21,8 @@
#include <linux/wordpart.h>
#include <linux/unaligned.h>
+#include "air_phy_lib.h"
+
#define EN8811H_PHY_ID 0x03a2a411
#define AN8811HB_PHY_ID 0xc0ff04a0
@@ -40,7 +42,6 @@
#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-#define AIR_EXT_PAGE_ACCESS 0x1f
#define AIR_PHY_PAGE_STANDARD 0x0000
#define AIR_PHY_PAGE_EXTENDED_4 0x0004
@@ -244,16 +245,6 @@ static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
BIT(TRIGGER_NETDEV_RX) |
BIT(TRIGGER_NETDEV_TX);
-static int air_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-}
-
-static int air_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-}
-
static int __air_buckpbus_reg_write(struct phy_device *phydev,
u32 pbus_address, u32 pbus_data)
{
diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c
new file mode 100644
index 000000000000..8ef5af4becf0
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Airoha Ethernet PHY common library
+ *
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/export.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+
+#include "air_phy_lib.h"
+
+#define AIR_EXT_PAGE_ACCESS 0x1f
+
+int air_phy_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+EXPORT_SYMBOL_GPL(air_phy_read_page);
+
+int air_phy_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+EXPORT_SYMBOL_GPL(air_phy_write_page);
+
+MODULE_DESCRIPTION("Airoha PHY Library");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Louis-Alexis Eyraud");
diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h
new file mode 100644
index 000000000000..79367e8e5907
--- /dev/null
+++ b/drivers/net/phy/air_phy_lib.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2026 Airoha Technology Corp.
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef __AIR_PHY_LIB_H
+#define __AIR_PHY_LIB_H
+
+#include <linux/phy.h>
+
+int air_phy_read_page(struct phy_device *phydev);
+int air_phy_write_page(struct phy_device *phydev, int page);
+
+#endif /* __AIR_PHY_LIB_H */
--
2.54.0
^ permalink raw reply related
* [PATCH net-next v4 0/6] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-05-21 8:21 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
Russell King
Cc: kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Louis-Alexis Eyraud
This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.
The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
- Energy Efficient Ethernet (802.3az)
- Full Duplex Control Flow (802.3x)
- auto-negotiation
- crossover detect and autocorrection,
- Wake-on-LAN with Magic Packet
- Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.
The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.
Since v2, the series also adds the air_phy_lib library, which goal is to
share common code between air_en8811h and air_an8801 drivers, and its use
in them. The first shared functions are the existing BuckPbus register
accessors and air_phy_read/write_page functions coming from air_en8811h
driver.
The series is based on net-next kernel tree (sha1: 830d8771ae3c) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.
[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Changes in v4:
- Rebased on net-next (830d8771ae3c)
- Added in patch 1 the missing function-enumator property description,
that should already have been present in v3
- Modified patch 1 and patch 5 subjects to use AN8801R and not AN8801/R
(detected by sashiko-nipa)
- Modified patch 3 to add missing wordpath.h include (detected by
sashiko.dev)
- Modified patch 5 to use NSEC_PER_MSEC definition instead of hardcoded
value in an8801r_led_blink_ms_to_hw
- Removed unnecessary RGMII_DELAY_STEP_MASK mask operation in
an8801r_rgmii_rxdelay and an8801r_rgmii_txdelay
- Removed extra empty line in an8801r_led_hw_control_set
- Improved AN8801_RGMII_TX/RXDELAY_DEFAULT definition comments
- Fixed inverted GENMASK arguments in AN8801_WAKE_OUT_WIDTH
definition (detected by sashiko-nipa)
- Fixed possible overflow when writing LED_BLINK_DUR register value
in an8801r_led_blink_set (detected by sashiko-nipa and sashiko.dev)
- Modified the an8801r_handle_interrupt to allow the WAKE_MAGICPKT and
WAKE_LNKCHG interrupts handling in the same call
(detected by sashiko-nipa and sashiko.dev)
- Add extra check in an8801r_set_wol to reject unsupported modes
(detected by sashiko-nipa)
- Fixed supported led trigger detection in an8801r_led_trig_to_hw
(detected by sashiko.dev)
- Fixed possible uninitialized return value in an8801r_of_init_leds
(detected by sashiko-nipa and sashiko.dev)
- Modified patch 6 to fix possible cases where the link mode register value
might not be updated (detected by sashiko-nipa)
- Added new reviewed-by trailers
- Link to v3: https://lore.kernel.org/r/20260512-add-airoha-an8801-support-v3-0-1edb34e363ae@collabora.com
Changes in v3:
- Rebased on net-next (7e0cccae6b45)
- Updated patch 1 to describe the function-enumator property for the
LEDs and its possible values
- Modified patch 2 to add missing includes in air_phy_lib source and
header files
- Split patch 3 in two so that the api call renames in air_en8811h
driver is done in a separate patch
- Simplified return code handling in several functions
- Fixed return code handling in several functions detected by AI
peer-reviews (netdev-ai or sashiko)
- Added additional interrupt enabled check before enabling/disabling
link changed interrupt in an8801r_suspend/resume callbacks
- Fixed register mask for GPIO LED selection register in
an8801r_led_init function
- Fixed potential uninitialized variable in an8801r_led_polarity_set
function
- Fixed LED blink register settings in an8801r_led_blink_set function
- Split an8801r_read_status function implementation in a separate patch
as requested and add comment to describe why the link mode register
needed to be modified after reading the link speed.
- Link to v2: https://lore.kernel.org/r/20260326-add-airoha-an8801-support-v2-0-1a42d6b6050f@collabora.com
Changes in v2:
- Rebased on net-next (d1e59a4697371)
- Fixed dt-bindings to remove the leds property from the required ones and
add wakeup-source as valid property
- Added new reviewed-by trailer for dt_bindings
- Added new patches (2 and 3) to create air_phy_lib, to share common code
between air_en8811h and air_an8801 drivers and use it in air_en8811h.
- Remove custom BuckPBus register accessor functions and definitions from
air_an8801 and use the ones from air_phy_lib. It also fixes a build
issue on v1 due to an uninitialized variable used in
__air_buckpbus_reg_read, that is now removed from driver code
- Added air_an8801_probe function to allocate the newly added private
data structure and detect if the PHY is wakeup capable and the interrupt
can be registered as a wakeup IRQ, and perform the needed actions
- Added an8801r_suspend and an8801r_resume functions to perform specific
actions when WoL is enabled (reset its status, enable/disable the Link
Changed interrupt) and call the genphy_suspend/resume functions if
needed
- Modified an8801r_get_wol to return WoL is not supported if the PHY
device is not wakeup capable
- Modified an8801r_set_wol to return EOPNOTSUPP error code if the PHY
device is not wakeup capable, and to update the wakeup flag according
to WoL mode
- Modified an8801r_config_init to remove EEE disabling and replace
__phy_write use by phy_write_paged
- Reworked an8801r_rgmii_delay_config and its subfunctions to fix a
double return use in PHY_INTERFACE_MODE_RGMII_ID case, replace the
magic value use for default TX and RX delay and handle better the
enable/disable the inserted delays for all RGMII modes
- Merged an8801r_did_interrupt function in an8801r_handle_interrupt
- Modified the an8801r_handle_interrupt processing to process differently
the Magic Packet (to notify system wakeup) and the Link Changed
interrupt (to notify PHY state machine)
- Splitted the reset WoL status part from an8801r_ack_interrupt and fix
an issue that in some random cases made WAKEUP_CTL1 register lose the
Magic Packet WoL settings
- Modified an8801r_of_init_leds function so it does not return an error
if the leds configuration is not present in devicetree
- Removed feature field and add PHY_ALWAYS_CALL_SUSPEND flag in
airoha_driver data structure
- Link to v1: https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-0-0ae4ee5a2f9d@collabora.com
---
AngeloGioacchino Del Regno (2):
dt-bindings: net: Add support for Airoha AN8801R GbE PHY
net: phy: Introduce Airoha AN8801R Gigabit Ethernet PHY driver
Louis-Alexis Eyraud (4):
net: phy: Add Airoha phy library for shared code
net: phy: air_phy_lib: Factorize BuckPBus register accessors
net: phy: Rename Airoha common BuckPBus register accessors
net: phy: air_an8801: ensure maximum available speed link use
.../devicetree/bindings/net/airoha,an8801.yaml | 116 ++
drivers/net/phy/Kconfig | 12 +
drivers/net/phy/Makefile | 2 +
drivers/net/phy/air_an8801.c | 1144 ++++++++++++++++++++
drivers/net/phy/air_en8811h.c | 316 +-----
drivers/net/phy/air_phy_lib.c | 213 ++++
drivers/net/phy/air_phy_lib.h | 39 +
7 files changed, 1584 insertions(+), 258 deletions(-)
---
base-commit: 830d8771ae3c7bc90a62dde76a6556e612529fbc
change-id: 20260303-add-airoha-an8801-support-57d544a4afed
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* Re: [PATCH v8 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY
From: Christian Marangi @ 2026-05-21 8:22 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Lorenzo Bianconi, Felix Fietkau, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <20260521-ambrosial-abiding-lyrebird-9dc86f@quoll>
On Thu, May 21, 2026 at 09:44:16AM +0200, Krzysztof Kozlowski wrote:
> On Wed, May 20, 2026 at 05:09:07PM +0200, Christian Marangi wrote:
> > Add documentation for Airoha AN7581 USB PHY that describe the USB PHY
> > for the USB controller.
> >
> > Airoha AN7581 SoC support a maximum of 2 USB port. The USB 2.0 mode is
> > always supported. The USB 3.0 mode is optional and depends on the Serdes
> > mode currently configured on the system for the relevant USB port.
> >
> > To correctly calibrate, the USB 2.0 port require correct value in
> > "airoha,usb2-monitor-clk-sel" property. Both the 2 USB 2.0 port permit
> > selecting one of the 4 monitor clock for calibration (internal clock not
> > exposed to the system) but each port have only one of the 4 actually
> > connected in HW hence the correct value needs to be specified in DT
> > based on board and the physical port. Normally it's monitor clock 1 for
> > USB1 and monitor clock 2 for USB2.
> >
> > To correctly setup the Serdes mode attached to the USB 3.0 mode, a phys
> > property is required with the phandle pointing to the correct Serdes port
> > provided by the SCU node.
>
>
> ^^^ here - required but:
>
I think I have to rephrase it. It's required if the USB3 is used/wanted. In
the other case for the USB2 phy is not needed.
I will bettet describe this in commit description and on the phys property
description.
> > + phys:
> > + items:
> > + - description: phandle to Serdes PHY
> > +
> > + '#phy-cells':
> > + description: The cell contains the mode, PHY_TYPE_USB2 or PHY_TYPE_USB3,
> > + as defined in dt-bindings/phy/phy.h.
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - airoha,usb2-monitor-clk-sel
>
> 'phys' is not required? I think you need it to configure the serdes
> correctly, no?
>
> > + - '#phy-cells'
> > +
> > +additionalProperties: false
>
> Best regards,
> Krzysztof
>
--
Ansuel
^ permalink raw reply
* Re: [PATCH v3 4/4] devfreq: Refcount governor modules while in use
From: zhenglifeng (A) @ 2026-05-21 8:13 UTC (permalink / raw)
To: Jie Zhan, cwchoi00, cw00.choi, myungjoo.ham, kyungmin.park,
linux-pm, linux-arm-kernel
Cc: linuxarm, tianyaxiong, zhangpengjie2, lihuisong, prime.zeng
In-Reply-To: <20260519113251.3745140-5-zhanjie9@hisilicon.com>
On 5/19/2026 7:32 PM, Jie Zhan wrote:
> A governor module can be inserted or removed dynamically when built as a
> kernel module. 'devfreq->governor' would become NULL if the governor
> module is removed when it's in use.
>
> Add a refcount mechanism for governor modules to prevent the governor
> module from being removed (except for force unload):
> 1. Add an optional 'owner' member to struct devfreq_governor so the devfreq
> core can identify the module that holds the governor code.
> 2. Get and put a refcount of the governor module when starting and stopping
> the governor.
>
> The new 'owner' field is optional:
> - Common governor modules (performance, powersave, simple_ondemand,
> userspace, passive) set 'owner' to THIS_MODULE.
> - Governors that are bundled into a device driver module must leave 'owner'
> NULL. The device's lifetime already pins that module, and setting
> 'owner' would create a self-reference that blocks the driver from being
> unloaded.
>
> As a result, a non-forced rmmod of an in-use stand-alone governor now
> fails with -EBUSY, e.g.:
>
> $ cat governor
> performance
> $ rmmod governor_performance
> rmmod: ERROR: Module governor_performance is in use
>
> Force unloads (rmmod -f, if configured) can't be blocked.
>
> Signed-off-by: Jie Zhan <zhanjie9@hisilicon.com>
> ---
> drivers/devfreq/devfreq.c | 17 ++++++++++++++++-
> drivers/devfreq/governor_passive.c | 1 +
> drivers/devfreq/governor_performance.c | 1 +
> drivers/devfreq/governor_powersave.c | 1 +
> drivers/devfreq/governor_simpleondemand.c | 1 +
> drivers/devfreq/governor_userspace.c | 1 +
> include/linux/devfreq-governor.h | 11 +++++++++++
> 7 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
> index 9e3e6a7348f8..1cee43636ded 100644
> --- a/drivers/devfreq/devfreq.c
> +++ b/drivers/devfreq/devfreq.c
> @@ -345,24 +345,37 @@ static int devfreq_set_governor(struct devfreq *df,
> __func__, df->governor->name, ret);
> return ret;
> }
> + module_put(old_gov->owner);
> }
>
> /* Start the new governor */
> + if (!try_module_get(new_gov->owner)) {
> + df->governor = NULL;
Shouldn't the old governor be restored here?
> + return -EINVAL;
> + }
> +
> df->governor = new_gov;
> ret = df->governor->event_handler(df, DEVFREQ_GOV_START, NULL);
> if (ret) {
> dev_warn(dev, "%s: Governor %s not started(%d)\n",
> __func__, df->governor->name, ret);
> + module_put(new_gov->owner);
>
> /* Restore previous governor */
> df->governor = old_gov;
> if (!df->governor)
> return ret;
>
> + if (!try_module_get(old_gov->owner)) {
> + df->governor = NULL;
> + return -EINVAL;
> + }
> +
> ret = df->governor->event_handler(df, DEVFREQ_GOV_START, NULL);
> if (ret) {
> dev_err(dev, "%s: restore Governor %s failed (%d)\n",
> __func__, df->governor->name, ret);
> + module_put(old_gov->owner);
> df->governor = NULL;
> return ret;
> }
> @@ -1040,9 +1053,11 @@ int devfreq_remove_device(struct devfreq *devfreq)
>
> devfreq_cooling_unregister(devfreq->cdev);
>
> - if (devfreq->governor)
> + if (devfreq->governor) {
> devfreq->governor->event_handler(devfreq,
> DEVFREQ_GOV_STOP, NULL);
> + module_put(devfreq->governor->owner);
> + }
> device_unregister(&devfreq->dev);
>
> return 0;
> diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
> index d7feecd900f1..3e63dd200a04 100644
> --- a/drivers/devfreq/governor_passive.c
> +++ b/drivers/devfreq/governor_passive.c
> @@ -449,6 +449,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
> static struct devfreq_governor devfreq_passive = {
> .name = DEVFREQ_GOV_PASSIVE,
> .flags = DEVFREQ_GOV_FLAG_IMMUTABLE,
> + .owner = THIS_MODULE,
> .get_target_freq = devfreq_passive_get_target_freq,
> .event_handler = devfreq_passive_event_handler,
> };
> diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/governor_performance.c
> index fdb22bf512cf..0a08b067ea6b 100644
> --- a/drivers/devfreq/governor_performance.c
> +++ b/drivers/devfreq/governor_performance.c
> @@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *devfreq,
>
> static struct devfreq_governor devfreq_performance = {
> .name = DEVFREQ_GOV_PERFORMANCE,
> + .owner = THIS_MODULE,
> .get_target_freq = devfreq_performance_func,
> .event_handler = devfreq_performance_handler,
> };
> diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governor_powersave.c
> index ee2d6ec8a512..3ae296d55e3e 100644
> --- a/drivers/devfreq/governor_powersave.c
> +++ b/drivers/devfreq/governor_powersave.c
> @@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devfreq,
>
> static struct devfreq_governor devfreq_powersave = {
> .name = DEVFREQ_GOV_POWERSAVE,
> + .owner = THIS_MODULE,
> .get_target_freq = devfreq_powersave_func,
> .event_handler = devfreq_powersave_handler,
> };
> diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/governor_simpleondemand.c
> index ac9c5e9e51a4..46287b279ded 100644
> --- a/drivers/devfreq/governor_simpleondemand.c
> +++ b/drivers/devfreq/governor_simpleondemand.c
> @@ -119,6 +119,7 @@ static struct devfreq_governor devfreq_simple_ondemand = {
> .name = DEVFREQ_GOV_SIMPLE_ONDEMAND,
> .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL
> | DEVFREQ_GOV_ATTR_TIMER,
> + .owner = THIS_MODULE,
> .get_target_freq = devfreq_simple_ondemand_func,
> .event_handler = devfreq_simple_ondemand_handler,
> };
> diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governor_userspace.c
> index 3906ebedbae8..b1acccc79f7f 100644
> --- a/drivers/devfreq/governor_userspace.c
> +++ b/drivers/devfreq/governor_userspace.c
> @@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *devfreq,
>
> static struct devfreq_governor devfreq_userspace = {
> .name = DEVFREQ_GOV_USERSPACE,
> + .owner = THIS_MODULE,
> .get_target_freq = devfreq_userspace_func,
> .event_handler = devfreq_userspace_handler,
> };
> diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-governor.h
> index dfdd0160a29f..ae1721e58401 100644
> --- a/include/linux/devfreq-governor.h
> +++ b/include/linux/devfreq-governor.h
> @@ -12,6 +12,7 @@
> #define __LINUX_DEVFREQ_DEVFREQ_H__
>
> #include <linux/devfreq.h>
> +struct module;
>
> #define DEVFREQ_NAME_LEN 16
>
> @@ -53,6 +54,15 @@
> * @name: Governor's name
> * @attrs: Governor's sysfs attribute flags
> * @flags: Governor's feature flags
> + * @owner: Optional, module that owns this governor.
> + * When set (typically to THIS_MODULE), the devfreq core
> + * takes a reference on @owner while this governor is in
> + * use so that the governor module cannot be removed,
> + * except by a forced unload. Governors that are bundled
> + * into a device driver module must leave @owner NULL: the
> + * device's lifetime already pins that module, and setting
> + * @owner would create a self-reference that prevents the
> + * driver from being unloaded.
> * @get_target_freq: Returns desired operating frequency for the device.
> * Basically, get_target_freq will run
> * devfreq_dev_profile.get_dev_status() to get the
> @@ -70,6 +80,7 @@ struct devfreq_governor {
> const char name[DEVFREQ_NAME_LEN];
> const u64 attrs;
> const u64 flags;
> + struct module *owner;
> int (*get_target_freq)(struct devfreq *this, unsigned long *freq);
> int (*event_handler)(struct devfreq *devfreq,
> unsigned int event, void *data);
^ permalink raw reply
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