* Re: [PATCH v7 1/9] arm64: dts: lx2160a-rev2: extend 32-bit, and add 64-bit pci regions
From: Josua Mayer @ 2026-05-24 15:03 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <20260524-lx2160-pci-v7-1-09370c23b952@solid-run.com>
Am 24.05.26 um 16:54 schrieb Josua Mayer:
> LX2160 SoC pci-e controller supports 64-bit memory regions up to 16GB,
> 32-bit regions up to 3GB and 16-bit regions up to 64k.
>
> For each pci-e controller:
> - extend the existing 32-bit regions to 3GB size
> - add 64-bit region
> See [1] and [2] for boot messages showing ranges before and after.
>
> On LX2160A Silicon revision 1, the pcie driver fails to program atu for
> ranges larger than 4GB [3]. Therefore changes are limited to revision 2.
>
> Similar memory allocation with similar flags was tested with UEFI and ACPI
> on pcie3 and pcie5, on a variety of nxp vendor fork versions.
>
> This patch was tested on Linux v7.1-rc1 and u-boot, with two pcie cards:
> - pcie5: Radeon Pro WX2100
> - pcie3: ADATA NVME
>
> This fixes allocation of large, and 64-bit BARs as requested by many pci
> cards - especially graphics processors or AI accelerators, e.g.:
>
> [ 2.941187] pci 0000:01:00.0: BAR 0: no space for [mem size 0x200000000 64bit pref]
> [ 2.948834] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x200000000 64bit pref]
>
> [1] example of new allocations (pcie5):
> [ 1.182745] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
> [ 1.182760] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
> [ 1.182771] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
> [ 1.182778] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000
> [ 1.183642] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
> [ 1.385429] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up
> [ 1.385481] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00
> [ 1.385484] pci_bus 0001:00: root bus resource [bus 00-ff]
> [ 1.385488] pci_bus 0001:00: root bus resource [mem 0xa400000000-0xa7ffffffff pref]
> [ 1.385491] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa0ffffffff] (bus address [0x40000000-0xffffffff])
> [ 1.385494] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff])
> [ 1.385516] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port
> [ 1.385538] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
> [ 1.385544] pci 0001:00:00.0: bridge window [io 0x11000-0x11fff]
> [ 1.385548] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff]
> [ 1.385605] pci 0001:00:00.0: supports D1 D2
> [ 1.385607] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot
> [ 1.386778] pci 0001:01:00.0: [1002:6995] type 00 class 0x030000 PCIe Legacy Endpoint
> [ 1.387336] pci 0001:01:00.0: BAR 0 [mem 0xa040000000-0xa04fffffff 64bit pref]
> [ 1.387368] pci 0001:01:00.0: BAR 2 [mem 0xa050000000-0xa0501fffff 64bit pref]
> [ 1.387385] pci 0001:01:00.0: BAR 4 [io 0x11000-0x110ff]
> [ 1.387402] pci 0001:01:00.0: BAR 5 [mem 0xa050200000-0xa05023ffff]
> [ 1.387418] pci 0001:01:00.0: ROM [mem 0xa050240000-0xa05025ffff pref]
> [ 1.387493] pci 0001:01:00.0: enabling Extended Tags
> [ 1.388960] pci 0001:01:00.0: supports D1 D2
>
> [2] example of previous allocations (pcie5):
> [ 1.716744] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
> [ 1.724060] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa07fffffff -> 0x0040000000
> [ 1.733277] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
> [ 1.836220] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up
> [ 1.842186] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00
> [ 1.848883] pci_bus 0001:00: root bus resource [bus 00-ff]
> [ 1.854363] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa07fffffff] (bus address [0x40000000-0x7fffffff])
> [ 1.864892] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port
> [ 1.872216] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
> [ 1.877438] pci 0001:00:00.0: bridge window [io 0x1000-0x1fff]
> [ 1.883526] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff]
>
> [3] error programming atu beyond 4GB:
> [ 1.716762] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
> [ 1.724080] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
> [ 1.732615] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
> [ 1.741142] layerscape-pcie 3800000.pcie: IO 0xa010000000..0xa01000ffff -> 0x0000000000
> [ 1.750379] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
> [ 1.759089] layerscape-pcie 3800000.pcie: Failed to set MEM range [mem 0xa400000000-0xa7ffffffff flags 0x2200]
> [ 1.769089] layerscape-pcie 3800000.pcie: probe with driver layerscape-pcie failed with error -22
>
> [4] pci bootloaderp atching related errors with IORESOURCE_MEM_64 flag:
> [ 0.967809] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
> [ 0.967830] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
> [ 0.967842] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
> [ 0.967849] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000
> [ 1.169315] pci 0000:01:00.0: [8086:1572] type 00 class 0x020000 PCIe Endpoint
> [ 1.169733] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x00ffffff 64bit pref]
> [ 1.169771] pci 0000:01:00.0: BAR 3 [mem 0x00000000-0x00007fff 64bit pref]
> [ 1.169796] pci 0000:01:00.0: ROM [mem 0x00000000-0x0007ffff pref]
> [ 1.173389] OF: /soc/pcie@3800000: no msi-map translation for id 0x100 on (null)
> [ 1.173515] OF: /soc/pcie@3800000: no iommu-map translation for id 0x100 on (null)
I meant to drop this bootloader error log, because after fixing the ranges flags
this is no longer an issue with this v7 patch.
^ permalink raw reply
* [PATCH v7 9/9] arm64: dts: Add support for LX2160 Twins board in single configuration
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
Add support for the SolidRun LX2160A Twins board in its single cpu
configuration.
The twins board is designed to host a pair of LX2160A CEX-7 modules,
sharing a single PCI-E connector in multi-host mode.
It may be assembled in two configurations (different assembly options
facilitating signal re-routing), with a single or with dual CEX-7
module. Their marketing names are:
- SolidWAN Single LX2160
- SolidWAN Dual LX2160
This patch adds the single configuration, featuring:
- 8x SFP (1Gbps)
- 8x SFP+ (1/10Gbps)
- PCI-E OCP card connector
- USB-3.0 front-panel header with single port
- microSD
- dual hot-swappable power supplies
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 8 +-
.../boot/dts/freescale/fsl-lx2160a-half-twins.dts | 830 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +-
4 files changed, 848 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..59eee431562ef 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -51,6 +51,8 @@ DTC_FLAGS_fsl-lx2160a-bluebox3-rev-a := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb
DTC_FLAGS_fsl-lx2160a-clearfog-cx := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
+DTC_FLAGS_fsl-lx2160a-half-twins := -Wno-interrupt_map
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
DTC_FLAGS_fsl-lx2160a-honeycomb := -Wno-interrupt_map
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
DTC_FLAGS_fsl-lx2160a-qds := -Wno-interrupt_map
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 2c86734c39ab2..16caa281ece02 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -65,7 +65,7 @@ i2c-mux@77 {
#size-cells = <0>;
reg = <0x77>;
- i2c@0 {
+ ddr_i2c: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -91,7 +91,7 @@ eeprom@57 {
};
};
- i2c@1 {
+ fan_i2c: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -102,7 +102,7 @@ fan-temperature-ctrlr@18 {
};
};
- i2c@2 {
+ power_i2c: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@@ -113,7 +113,7 @@ regulator@5c {
};
};
- i2c@3 {
+ i2c_smb: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
new file mode 100644
index 0000000000000..d16e273072754
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for single LX2160A CEX-7 on Twins board.
+//
+// Copyright 2022 SolidRun Ltd.
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2160a-cex7.dtsi"
+
+/ {
+ compatible = "solidrun,twins-single", "solidrun,lx2160a-cex7", "fsl,lx2160a";
+ model = "SolidRun LX2160A SolidWAN Single";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &expander0;
+ gpio5 = &expander1;
+ gpio6 = &expander2;
+ gpio7 = &expander3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c2;
+ i2c2 = &i2c4;
+ i2c3 = &fan_i2c;
+ i2c4 = &power_i2c;
+ i2c5 = &i2c_smb;
+ i2c6 = &sfp0_i2c;
+ i2c7 = &sfp1_i2c;
+ i2c8 = &sfp2_i2c;
+ i2c9 = &sfp3_i2c;
+ i2c10 = &twins_sfp_c1_at_i2c;
+ i2c11 = &twins_sfp_c1_ab_i2c;
+ i2c12 = &twins_sfp_c1_bt_i2c;
+ i2c13 = &twins_sfp_c1_bb_i2c;
+ i2c14 = &twins_sfp_c2_at_i2c;
+ i2c15 = &twins_sfp_c2_ab_i2c;
+ i2c16 = &twins_sfp_c2_bt_i2c;
+ i2c17 = &twins_sfp_c2_bb_i2c;
+ i2c18 = &twins_sfp_c3_at_i2c;
+ i2c19 = &twins_sfp_c3_ab_i2c;
+ i2c20 = &twins_sfp_c3_bt_i2c;
+ i2c21 = &twins_sfp_c3_bb_i2c;
+ i2c22 = &htwins_sfp_c3_at_i2c;
+ i2c23 = &htwins_sfp_c3_ab_i2c;
+ i2c24 = &htwins_sfp_c3_bt_i2c;
+ i2c25 = &htwins_sfp_c3_bb_i2c;
+ i2c26 = &ddr_i2c;
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_ht_c3_bt: led-sfp-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&expander3 14 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac5>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_ht_c3_bb: led-sfp-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&expander3 13 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac15>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_ht_c3_at: led-sfp-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ gpios = <&expander3 11 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac6>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_ht_c3_ab: led-sfp-4 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <4>;
+ gpios = <&expander3 12 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac11>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c1_bt: led-sfp-9 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <9>;
+ gpios = <&expander1 4 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac4>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c1_bb: led-sfp-10 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <10>;
+ gpios = <&expander1 3 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac17>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c1_at: led-sfp-11 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <11>;
+ gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac3>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c1_ab: led-sfp-12 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <12>;
+ gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac12>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c2_bt: led-sfp-13 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <13>;
+ gpios = <&expander1 10 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac8>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c2_bb: led-sfp-14 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <14>;
+ gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac16>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c2_at: led-sfp-15 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <15>;
+ gpios = <&expander1 5 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac7>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c2_ab: led-sfp-16 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <16>;
+ gpios = <&expander1 6 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac18>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c3_bt: led-sfp-17 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <17>;
+ gpios = <&expander1 14 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac10>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c3_bb: led-sfp-18 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <18>;
+ gpios = <&expander1 13 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac14>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c3_at: led-sfp-19 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <19>;
+ gpios = <&expander1 11 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac9>;
+ linux,default-trigger = "netdev";
+ };
+
+ led_c3_ab: led-sfp-20 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <20>;
+ gpios = <&expander1 12 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&dpmac13>;
+ linux,default-trigger = "netdev";
+ };
+
+ led-status {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <0>;
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-status-twin {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ led-fault {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_FAULT;
+ function-enumerator = <0>;
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ panic-indicator;
+ };
+
+ led-fault-twin {
+ color = <LED_COLOR_ID_YELLOW>;
+ default-state = "off";
+ function = LED_FUNCTION_FAULT;
+ function-enumerator = <1>;
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ /*
+ * This gpio controlled mux can route the tacho signals of 6 PWM FAN connectors
+ * to the tacho inputs of both CEX-7 modules (twins).
+ *
+ * The first twin controls this mux and monitors four fan connectors, two intended
+ * for itself, and two for the OCP card.
+ *
+ * The second twin monitors only two fan connectors intended for itself.
+ *
+ * The table below maps selector GPIO states to monitored fan connector per twin:
+ *
+ * | SEL1 | SEL0 | Twin 1 | Twin 2 |
+ * | ---: | ---: | :------| ------ |
+ * | 0 | 0 | J10 | J5024 |
+ * | 0 | 1 | J5016 | J5024 |
+ * | 1 | 0 | J5026 | J5025 |
+ * | 1 | 1 | J5013 | J5025 |
+ */
+ mux-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>, /* SEL0 */
+ <&expander0 15 GPIO_ACTIVE_HIGH>; /* SEL1 */
+ };
+
+ ht_c3_bt_sfp: sfp-1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_bt_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander2 13 GPIO_ACTIVE_LOW>;
+ };
+
+ ht_c3_bb_sfp: sfp-2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_bb_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander2 14 GPIO_ACTIVE_LOW>;
+ };
+
+ ht_c3_at_sfp: sfp-3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_at_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander2 11 GPIO_ACTIVE_LOW>;
+ };
+
+ ht_c3_ab_sfp: sfp-4 {
+ compatible = "sff,sfp";
+ i2c-bus = <&htwins_sfp_c3_ab_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander2 12 GPIO_ACTIVE_LOW>;
+ };
+
+ c1_bt_sfp: sfp-9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_bt_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ c1_bb_sfp: sfp-10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_bb_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ c1_at_sfp: sfp-11 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_at_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ c1_ab_sfp: sfp-12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c1_ab_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ };
+
+ c2_bt_sfp: sfp-13 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_bt_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 9 GPIO_ACTIVE_LOW>;
+ };
+
+ c2_bb_sfp: sfp-14 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_bb_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 10 GPIO_ACTIVE_LOW>;
+ };
+
+ c2_at_sfp: sfp-15 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_at_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+ };
+
+ c2_ab_sfp: sfp-16 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c2_ab_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
+ };
+
+ c3_bt_sfp: sfp-17 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_bt_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 13 GPIO_ACTIVE_LOW>;
+ };
+
+ c3_bb_sfp: sfp-18 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_bb_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ c3_at_sfp: sfp-19 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_at_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 11 GPIO_ACTIVE_LOW>;
+ };
+
+ c3_ab_sfp: sfp-20 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twins_sfp_c3_ab_i2c>;
+ maximum-power-milliwatt = <2000>;
+ mod-def0-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/*
+ * This board supports industrial grade temperatures,
+ * the LX2160A SoC maximum junction temperature is 105°C.
+ *
+ * Raise thermal thresholds to allow operation near maximum temperature.
+ */
+&ccn_dpaa_alert {
+ temperature = <100000>;
+};
+
+&ccn_dpaa_crit {
+ temperature = <105000>;
+};
+
+&cluster2_3_alert {
+ temperature = <100000>;
+};
+
+&cluster2_3_crit {
+ temperature = <105000>;
+};
+
+&cluster4_alert {
+ temperature = <100000>;
+};
+
+&cluster4_crit {
+ temperature = <105000>;
+};
+
+&cluster5_alert {
+ temperature = <100000>;
+};
+
+&cluster5_crit {
+ temperature = <105000>;
+};
+
+&cluster6_7_alert {
+ temperature = <100000>;
+};
+
+&cluster6_7_crit {
+ temperature = <105000>;
+};
+
+&dce_qbman_alert {
+ temperature = <100000>;
+};
+
+&dce_qbman_crit {
+ temperature = <105000>;
+};
+
+/* sfp port 11 */
+&dpmac3 {
+ managed = "in-band-status";
+ phys = <&serdes_1 7>;
+ sfp = <&c1_at_sfp>;
+};
+
+/* sfp port 9 */
+&dpmac4 {
+ managed = "in-band-status";
+ phys = <&serdes_1 6>;
+ sfp = <&c1_bt_sfp>;
+};
+
+/* sfp port 1 */
+&dpmac5 {
+ managed = "in-band-status";
+ phys = <&serdes_1 5>;
+ sfp = <&ht_c3_bt_sfp>;
+};
+
+/* sfp port 3 */
+&dpmac6 {
+ managed = "in-band-status";
+ phys = <&serdes_1 4>;
+ sfp = <&ht_c3_at_sfp>;
+};
+
+/* sfp port 15 */
+&dpmac7 {
+ managed = "in-band-status";
+ phys = <&serdes_1 3>;
+ sfp = <&c2_at_sfp>;
+};
+
+/* sfp port 13 */
+&dpmac8 {
+ managed = "in-band-status";
+ phys = <&serdes_1 2>;
+ sfp = <&c2_bt_sfp>;
+};
+
+/* sfp port 19 */
+&dpmac9 {
+ managed = "in-band-status";
+ phys = <&serdes_1 1>;
+ sfp = <&c3_at_sfp>;
+};
+
+/* sfp port 17 */
+&dpmac10 {
+ managed = "in-band-status";
+ phys = <&serdes_1 0>;
+ sfp = <&c3_bt_sfp>;
+};
+
+/* sfp port 4 */
+&dpmac11 {
+ managed = "in-band-status";
+ phys = <&serdes_2 0>;
+ sfp = <&ht_c3_ab_sfp>;
+};
+
+/* sfp port 12 */
+&dpmac12 {
+ managed = "in-band-status";
+ phys = <&serdes_2 1>;
+ sfp = <&c1_ab_sfp>;
+};
+
+/* sfp port 20 */
+&dpmac13 {
+ managed = "in-band-status";
+ phys = <&serdes_2 6>;
+ sfp = <&c3_ab_sfp>;
+};
+
+/* sfp port 18 */
+&dpmac14 {
+ managed = "in-band-status";
+ phys = <&serdes_2 7>;
+ sfp = <&c3_bb_sfp>;
+};
+
+/* sfp port 2 */
+&dpmac15 {
+ managed = "in-band-status";
+ phys = <&serdes_2 4>;
+ sfp = <&ht_c3_bb_sfp>;
+};
+
+/* sfp port 14 */
+&dpmac16 {
+ managed = "in-band-status";
+ phys = <&serdes_2 5>;
+ sfp = <&c2_bb_sfp>;
+};
+
+/* sfp port 10 */
+&dpmac17 {
+ /* override connection to on-COM phy */
+ /delete-property/ phy-handle;
+ /delete-property/ phy-connection-type;
+ managed = "in-band-status";
+ phys = <&serdes_2 2>;
+ sfp = <&c1_bb_sfp>;
+};
+
+/* sfp port 16 */
+&dpmac18 {
+ managed = "in-band-status";
+ phys = <&serdes_2 3>;
+ sfp = <&c2_ab_sfp>;
+};
+
+&esdhc0 {
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
+ pinctrl-names = "default";
+ /*
+ * Disable 1.8V modes so that microsd state is same between
+ * power-on-reset, u-boot and linux.
+ * This avoids sporadic read errors after hard reset with some cards.
+ */
+ no-1-8-v;
+ status = "okay";
+};
+
+&i2c2 {
+ expander0: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ expander1: gpio@21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ expander2: gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ expander3: gpio@25 {
+ compatible = "nxp,pca9555";
+ reg = <0x25>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* Half twins configuration; take over c3 from the other twin side */
+ i2c-mux@73 {
+ compatible = "nxp,pca9547";
+ reg = <0x73>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ htwins_sfp_c3_at_i2c: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ htwins_sfp_c3_ab_i2c: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ htwins_sfp_c3_bt_i2c: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ htwins_sfp_c3_bb_i2c: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2c-mux@76 {
+ compatible = "nxp,pca9547";
+ reg = <0x76>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ twins_sfp_c1_at_i2c: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c1_ab_i2c: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c1_bt_i2c: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c1_bb_i2c: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c2_at_i2c: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c2_ab_i2c: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ twins_sfp_c2_bt_i2c: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c2_bb_i2c: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c3_at_i2c: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c3_ab_i2c: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c3_bt_i2c: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ twins_sfp_c3_bb_i2c: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&pcie5 {
+ status = "okay";
+};
+
+&pcs_mdio3 {
+ status = "okay";
+};
+
+&pcs_mdio4 {
+ status = "okay";
+};
+
+&pcs_mdio5 {
+ status = "okay";
+};
+
+&pcs_mdio6 {
+ status = "okay";
+};
+
+&pcs_mdio7 {
+ status = "okay";
+};
+
+&pcs_mdio8 {
+ status = "okay";
+};
+
+&pcs_mdio9 {
+ status = "okay";
+};
+
+&pcs_mdio10 {
+ status = "okay";
+};
+
+&pcs_mdio11 {
+ status = "okay";
+};
+
+&pcs_mdio12 {
+ status = "okay";
+};
+
+&pcs_mdio13 {
+ status = "okay";
+};
+
+&pcs_mdio14 {
+ status = "okay";
+};
+
+&pcs_mdio15 {
+ status = "okay";
+};
+
+&pcs_mdio16 {
+ status = "okay";
+};
+
+&pcs_mdio17 {
+ status = "okay";
+};
+
+&pcs_mdio18 {
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ /*
+ * COM has a phy at address 1 connected to SoC Ethernet Controller 1.
+ * It competes for WRIOP MAC17, and no connector has been wired.
+ */
+ status = "disabled";
+};
+
+&serdes_2 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&wriop_alert {
+ temperature = <100000>;
+};
+
+&wriop_crit {
+ temperature = <105000>;
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 479982948ee53..1d73abffa6b72 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -499,13 +499,13 @@ ddr-ctrl5-thermal {
thermal-sensors = <&tmu 1>;
trips {
- ddr-cluster5-alert {
+ cluster5_alert: ddr-cluster5-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- ddr-cluster5-crit {
+ cluster5_crit: ddr-cluster5-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -519,13 +519,13 @@ wriop-thermal {
thermal-sensors = <&tmu 2>;
trips {
- wriop-alert {
+ wriop_alert: wriop-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- wriop-crit {
+ wriop_crit: wriop-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -539,13 +539,13 @@ dce-thermal {
thermal-sensors = <&tmu 3>;
trips {
- dce-qbman-alert {
+ dce_qbman_alert: dce-qbman-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- dce-qbman-crit {
+ dce_qbman_crit: dce-qbman-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -559,13 +559,13 @@ ccn-thermal {
thermal-sensors = <&tmu 4>;
trips {
- ccn-dpaa-alert {
+ ccn_dpaa_alert: ccn-dpaa-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- ccn-dpaa-crit {
+ ccn_dpaa_crit: ccn-dpaa-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -579,13 +579,13 @@ cluster4-thermal {
thermal-sensors = <&tmu 5>;
trips {
- clust4-hsio3-alert {
+ cluster4_alert: clust4-hsio3-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- clust4-hsio3-crit {
+ cluster4_crit: clust4-hsio3-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -599,13 +599,13 @@ cluster2-3-thermal {
thermal-sensors = <&tmu 6>;
trips {
- cluster2-3-alert {
+ cluster2_3_alert: cluster2-3-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- cluster2-3-crit {
+ cluster2_3_crit: cluster2-3-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
--
2.51.0
^ permalink raw reply related
* [PATCH v7 2/9] arm64: dts: lx2162a-clearfog: use rev2 SoC dtsi
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
LX2160A and LX2162A are different pakages of the same silicon.
While LX2160A had two revisions, LX2162A was released later based on
LX2160A revision 2.
Commit a8fe6c8dfc40 ("arm64: dts: fsl-lx2160a: add rev2 support") has
added a new soc dtsi for revision 2.
Update LX2162A Clearfog description to use revision 2 dtsi.
Fixes: 5093b190f9ce ("arm64: dts: freescale: Add support for LX2162 SoM & Clearfog Board") # no-stable
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 9d50d3e2761da..f95e9c19bfc75 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
--
2.51.0
^ permalink raw reply related
* [PATCH v7 7/9] arm64: dts: lx2160a-clearfog-itx: move shared includes to dts
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
Originally includes were defined hierarchically:
- CEX-7 Module includes SoC
- Clearfog-CX & Honeycomb common parts include CEX-7 Module
- Boards include common parts
This makes it difficult to modify the includes on a per-board level,
e.g. when adding a new board based on CEX-7 module but revision 2 SoC
(which now has its own soc dtsi).
Move includes of both SoC and CEX-7 module out of common parts and into
each board dts.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 --
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 1 -
arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts | 2 ++
4 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 56b74837ddd48..7df93bb37d13c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -4,8 +4,6 @@
//
// Copyright 2019 SolidRun Ltd.
-#include "fsl-lx2160a.dtsi"
-
/ {
model = "SolidRun LX2160A COM Express Type 7 module";
compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
index 86a9b771428dc..802d7611c6479 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 6388bd60ffdf5..170e5b0034f19 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -5,7 +5,6 @@
//
// Copyright 2019 SolidRun Ltd.
-#include "fsl-lx2160a-cex7.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
/ {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
index fe19f3009ea58..2b1e13053422b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-cex7.dtsi"
#include "fsl-lx2160a-clearfog-itx.dtsi"
/ {
--
2.51.0
^ permalink raw reply related
* [PATCH v7 6/9] arm64: dts: lx2160a-clearfog-itx: remove redundant dts version tag
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
The dts version tag should only appear in the top level dts file.
Since the cex-7 module and clearfog-itx are shared code intended for
inclusion, drop their dts version tags.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 --
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 90956ffb8ea9a..56b74837ddd48 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -4,8 +4,6 @@
//
// Copyright 2019 SolidRun Ltd.
-/dts-v1/;
-
#include "fsl-lx2160a.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 580ee9b3026e3..6388bd60ffdf5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -5,8 +5,6 @@
//
// Copyright 2019 SolidRun Ltd.
-/dts-v1/;
-
#include "fsl-lx2160a-cex7.dtsi"
#include <dt-bindings/input/linux-event-codes.h>
--
2.51.0
^ permalink raw reply related
* [PATCH v7 8/9] arm64: dts: lx2160a-cex7: add usb hub
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
LX2160A CEX-7 module provides a total of 4 USB ports to the carrier
board, one from first usb controller, and 3 from a hub behind the second
controller.
Both controllers currently have their status set okay in the module's
dtsi file. However devices should be disabled by default when
incomplete.
The first USB controller is only completed by a carrier board featuring
a device or USB connector.
The second controller hosts a USB hub and should therefore be active.
Add description for the USB hub, and enable the first controller only in
the carrier board description.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 29 +++++++++++++++++++---
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index 7df93bb37d13c..2c86734c39ab2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -13,6 +13,13 @@ aliases {
rtc0 = &com_rtc;
};
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ };
+
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "RT7290";
@@ -181,10 +188,24 @@ &pinmux_i2crv {
pinctrl-0 = <&gpio0_14_12_pins>;
};
-&usb0 {
- status = "okay";
-};
-
&usb1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
+
+ usb_hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ peer-hub = <&usb_hub_3_0>;
+ vdd2-supply = <&sb_3v3>;
+ vdd-supply = <&v_1_2>;
+ };
+
+ usb_hub_3_0: hub@2 {
+ compatible = "usb4b4,6500", "usb4b4,6504";
+ reg = <2>;
+ peer-hub = <&usb_hub_2_0>;
+ vdd2-supply = <&sb_3v3>;
+ vdd-supply = <&v_1_2>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 170e5b0034f19..4bc151d721ddf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -142,3 +142,7 @@ &uart0 {
&uart1 {
status = "okay";
};
+
+&usb0 {
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v7 5/9] dt-bindings: arm: fsl: Add solidrun lx2160a twins board
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
The SolidRun LX2160A Twins board supports two configurations, one with
with a single CEX-7 module, and one with two (dual).
The single configuration is a specific assembly that maximises
connectivity for single cpu by routing some second cpu resources to the
first via zero-Ohm resistors.
The dual configuration was not yet tested and is intentionally omitted.
Initial review strongly suggests that the dual configuration will have
different bindings, because from either cpu point of view the board
appears different (e.g. different number of sfp, fewer i2c gpio).
Add binding for the single variant only.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0023cd1268075..1f11c1208c248 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1868,6 +1868,7 @@ properties:
- enum:
- solidrun,clearfog-cx
- solidrun,honeycomb
+ - solidrun,twins-single
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
--
2.51.0
^ permalink raw reply related
* [PATCH v7 4/9] arm64: dts: lx2162a-clearfog: specify sfp ports led colour and function
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
The LX2162A Clearfog board has a green LED on each of four SFP ports.
Describe in device-tree that their colour is green and function "lan".
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 6fd85a5cac94e..99ee2b1c0f13b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include <dt-bindings/leds/common.h>
+
#include "fsl-lx2160a-rev2.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
@@ -38,6 +40,9 @@ leds {
compatible = "gpio-leds";
led_sfp_at: led-sfp-at {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
default-state = "off";
linux,default-trigger = "netdev";
@@ -45,6 +50,9 @@ led_sfp_at: led-sfp-at {
};
led_sfp_ab: led-sfp-ab {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
default-state = "off";
linux,default-trigger = "netdev";
@@ -52,6 +60,9 @@ led_sfp_ab: led-sfp-ab {
};
led_sfp_bt: led-sfp-bt {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
default-state = "off";
linux,default-trigger = "netdev";
@@ -59,6 +70,9 @@ led_sfp_bt: led-sfp-bt {
};
led_sfp_bb: led-sfp-bb {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <4>;
gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
default-state = "off";
linux,default-trigger = "netdev";
--
2.51.0
^ permalink raw reply related
* [PATCH v7 1/9] arm64: dts: lx2160a-rev2: extend 32-bit, and add 64-bit pci regions
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
LX2160 SoC pci-e controller supports 64-bit memory regions up to 16GB,
32-bit regions up to 3GB and 16-bit regions up to 64k.
For each pci-e controller:
- extend the existing 32-bit regions to 3GB size
- add 64-bit region
See [1] and [2] for boot messages showing ranges before and after.
On LX2160A Silicon revision 1, the pcie driver fails to program atu for
ranges larger than 4GB [3]. Therefore changes are limited to revision 2.
Similar memory allocation with similar flags was tested with UEFI and ACPI
on pcie3 and pcie5, on a variety of nxp vendor fork versions.
This patch was tested on Linux v7.1-rc1 and u-boot, with two pcie cards:
- pcie5: Radeon Pro WX2100
- pcie3: ADATA NVME
This fixes allocation of large, and 64-bit BARs as requested by many pci
cards - especially graphics processors or AI accelerators, e.g.:
[ 2.941187] pci 0000:01:00.0: BAR 0: no space for [mem size 0x200000000 64bit pref]
[ 2.948834] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x200000000 64bit pref]
[1] example of new allocations (pcie5):
[ 1.182745] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
[ 1.182760] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
[ 1.182771] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
[ 1.182778] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000
[ 1.183642] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
[ 1.385429] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up
[ 1.385481] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00
[ 1.385484] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 1.385488] pci_bus 0001:00: root bus resource [mem 0xa400000000-0xa7ffffffff pref]
[ 1.385491] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa0ffffffff] (bus address [0x40000000-0xffffffff])
[ 1.385494] pci_bus 0001:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff])
[ 1.385516] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port
[ 1.385538] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
[ 1.385544] pci 0001:00:00.0: bridge window [io 0x11000-0x11fff]
[ 1.385548] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff]
[ 1.385605] pci 0001:00:00.0: supports D1 D2
[ 1.385607] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot
[ 1.386778] pci 0001:01:00.0: [1002:6995] type 00 class 0x030000 PCIe Legacy Endpoint
[ 1.387336] pci 0001:01:00.0: BAR 0 [mem 0xa040000000-0xa04fffffff 64bit pref]
[ 1.387368] pci 0001:01:00.0: BAR 2 [mem 0xa050000000-0xa0501fffff 64bit pref]
[ 1.387385] pci 0001:01:00.0: BAR 4 [io 0x11000-0x110ff]
[ 1.387402] pci 0001:01:00.0: BAR 5 [mem 0xa050200000-0xa05023ffff]
[ 1.387418] pci 0001:01:00.0: ROM [mem 0xa050240000-0xa05025ffff pref]
[ 1.387493] pci 0001:01:00.0: enabling Extended Tags
[ 1.388960] pci 0001:01:00.0: supports D1 D2
[2] example of previous allocations (pcie5):
[ 1.716744] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
[ 1.724060] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa07fffffff -> 0x0040000000
[ 1.733277] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
[ 1.836220] layerscape-pcie 3800000.pcie: PCIe Gen.3 x8 link up
[ 1.842186] layerscape-pcie 3800000.pcie: PCI host bridge to bus 0001:00
[ 1.848883] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 1.854363] pci_bus 0001:00: root bus resource [mem 0xa040000000-0xa07fffffff] (bus address [0x40000000-0x7fffffff])
[ 1.864892] pci 0001:00:00.0: [1957:8d80] type 01 class 0x060400 PCIe Root Port
[ 1.872216] pci 0001:00:00.0: PCI bridge to [bus 01-ff]
[ 1.877438] pci 0001:00:00.0: bridge window [io 0x1000-0x1fff]
[ 1.883526] pci 0001:00:00.0: bridge window [mem 0xa040000000-0xa0502fffff]
[3] error programming atu beyond 4GB:
[ 1.716762] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
[ 1.724080] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
[ 1.732615] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
[ 1.741142] layerscape-pcie 3800000.pcie: IO 0xa010000000..0xa01000ffff -> 0x0000000000
[ 1.750379] layerscape-pcie 3800000.pcie: iATU: unroll F, 256 ob, 24 ib, align 4K, limit 4G
[ 1.759089] layerscape-pcie 3800000.pcie: Failed to set MEM range [mem 0xa400000000-0xa7ffffffff flags 0x2200]
[ 1.769089] layerscape-pcie 3800000.pcie: probe with driver layerscape-pcie failed with error -22
[4] pci bootloaderp atching related errors with IORESOURCE_MEM_64 flag:
[ 0.967809] layerscape-pcie 3800000.pcie: host bridge /soc/pcie@3800000 ranges:
[ 0.967830] layerscape-pcie 3800000.pcie: MEM 0xa400000000..0xa7ffffffff -> 0xa400000000
[ 0.967842] layerscape-pcie 3800000.pcie: MEM 0xa040000000..0xa0ffffffff -> 0x0040000000
[ 0.967849] layerscape-pcie 3800000.pcie: IO 0xa000010000..0xa00001ffff -> 0x0000000000
[ 1.169315] pci 0000:01:00.0: [8086:1572] type 00 class 0x020000 PCIe Endpoint
[ 1.169733] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x00ffffff 64bit pref]
[ 1.169771] pci 0000:01:00.0: BAR 3 [mem 0x00000000-0x00007fff 64bit pref]
[ 1.169796] pci 0000:01:00.0: ROM [mem 0x00000000-0x0007ffff pref]
[ 1.173389] OF: /soc/pcie@3800000: no msi-map translation for id 0x100 on (null)
[ 1.173515] OF: /soc/pcie@3800000: no iommu-map translation for id 0x100 on (null)
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 30 +++++++++++++---------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
index f54005e37924b..db1ebee53f6f0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
@@ -14,8 +14,9 @@ &pcie1 {
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -30,8 +31,9 @@ &pcie2 {
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -46,8 +48,9 @@ &pcie3 {
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -63,8 +66,9 @@ &pcie4 {
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -79,8 +83,9 @@ &pcie5 {
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
@@ -95,8 +100,9 @@ &pcie6 {
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
- ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
- 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, /* 16-Bit IO Window */
+ <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>, /* 32-Bit - non-prefetchable */
+ <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; /* 64-Bit - prefetchable - 16GB */
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
--
2.51.0
^ permalink raw reply related
* [PATCH v7 3/9] arm64: dts: lx2162a-clearfog: cleanup superfluous status properties
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
In-Reply-To: <20260524-lx2160-pci-v7-0-09370c23b952@solid-run.com>
The SoC dtsi has always enabled serdes block 1, enabled dpmac and
disabled pcie nodes.
Drop the superfluous status properties on these nodes.
Further drop crypto alias as SoM dtsi already set it.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index f95e9c19bfc75..6fd85a5cac94e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -14,7 +14,6 @@ / {
compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
aliases {
- crypto = &crypto;
i2c0 = &i2c0;
i2c1 = &i2c2;
i2c2 = &i2c4;
@@ -124,42 +123,36 @@ &dpmac11 {
phys = <&serdes_2 0>;
phy-handle = <ðernet_phy3>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac12 {
phys = <&serdes_2 1>;
phy-handle = <ðernet_phy1>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac13 {
phys = <&serdes_2 6>;
phy-handle = <ðernet_phy6>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac14 {
phys = <&serdes_2 7>;
phy-handle = <ðernet_phy8>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac15 {
phys = <&serdes_2 4>;
phy-handle = <ðernet_phy4>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac16 {
phys = <&serdes_2 5>;
phy-handle = <ðernet_phy2>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac17 {
@@ -170,14 +163,12 @@ &dpmac17 {
phys = <&serdes_2 2>;
phy-handle = <ðernet_phy5>;
phy-connection-type = "sgmii";
- status = "okay";
};
&dpmac18 {
phys = <&serdes_2 3>;
phy-handle = <ðernet_phy7>;
phy-connection-type = "sgmii";
- status = "okay";
};
&emdio1 {
@@ -314,14 +305,6 @@ pcieclk_i2c: i2c@2 {
};
};
-&pcie3 {
- status = "disabled";
-};
-
-&pcie4 {
- status = "disabled";
-};
-
&pcs_mdio3 {
status = "okay";
};
@@ -370,10 +353,6 @@ &pcs_mdio18 {
status = "okay";
};
-&serdes_1 {
- status = "okay";
-};
-
&serdes_2 {
status = "okay";
};
--
2.51.0
^ permalink raw reply related
* [PATCH v7 0/9] arm64: dts: lx2160a: cleanups, add new board, large pci bars
From: Josua Mayer @ 2026-05-24 14:54 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Yazan Shhady, Jon Nettleton, linux-arm-kernel, devicetree,
linux-kernel, imx, Josua Mayer
This patch-set is made of 3 parts:
1. Extend lx2160 pci node ranges to support 16-bit, and large 64-bit
bars. LX2160A SoC has always supported this, and SolidRun carried it
in vendor fork for several years now.
2. Cleanup some status properties in LX2162A Clearfog dts.
3. Add description for solidrun twins baord with single LX2160A CEX-7
module.
There are no inter-dependencies between the parts and they may apply
individually if necessary.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v7:
- Dropped pcie silicon 1 changes because they add too much noise.
- Changed pcie range flags per sashiko feedback.
This also fixed bootloader patching issues seen previously.
- Added CEX-7 module onboard USB Hub.
- Keep first usb controller disabled in cex-7 module.
- Added reasoning for adding nly single configuration binding to commit
description.
(Reported-by: Krzysztof Kozlowski <krzk@kernel.org>)
- Squashed DT label commits with their user (twins board dts).
(Reported-by: Krzysztof Kozlowski <krzk@kernel.org>)
- Link to v6: https://lore.kernel.org/r/20260512-lx2160-pci-v6-0-d0ff72d3c983@solid-run.com
Changes in v6:
- Add explanation why IORESOURCE_MEM_64 flag is not set.
- Fixed pci bar size 1GB/4GB typo in pcie4 node.
- Enable twins board pcie controller node.
- Fixed function-enumerator value for led-sfp-3.
- Reverted accidental change of clearfog-cx soc revision.
- Link to v5: https://lore.kernel.org/r/20260510-lx2160-pci-v5-0-540b83852227@solid-run.com
Changes in v5:
- add new board
- add cleanups to existing solidrun boards
- pci: extend to lx2160a-rev2 dtsi
- pci: remove non-standard flags to pass dtbs_check
- Link to v4: https://lore.kernel.org/r/20260302-lx2160-pci-v4-1-30a30dc47ec6@solid-run.com
Changes in v4
- dropped accidentally added empty line at top of file:
- actually drop RFC prefix
- rebased on v7.0-rc1 and re-tested on v7.0-rc2
- Link to v3: https://lore.kernel.org/r/20250907-lx2160-pci-v3-1-bb66cc41b8f9@solid-run.com
Changes in v3:
- dropped rfc label
- adjusted flags
- split 16GB area into 4x4GB sections.
- enhance commit description with details explanation
- Link to v2: https://lore.kernel.org/r/20240429-lx2160-pci-v2-1-1b94576d6263@solid-run.com
Changes in v2:
- adjusted flags to fix several errors during probe and bar allocation
- explicitly tested with 2 pci cards on Debian (Linux 6.1)
- still rfc because a limitation in designware pci driver
- Link to v1: https://lore.kernel.org/r/20240321-lx2160-pci-v1-1-3673708f7eb6@solid-run.com
---
Josua Mayer (9):
arm64: dts: lx2160a-rev2: extend 32-bit, and add 64-bit pci regions
arm64: dts: lx2162a-clearfog: use rev2 SoC dtsi
arm64: dts: lx2162a-clearfog: cleanup superfluous status properties
arm64: dts: lx2162a-clearfog: specify sfp ports led colour and function
dt-bindings: arm: fsl: Add solidrun lx2160a twins board
arm64: dts: lx2160a-clearfog-itx: remove redundant dts version tag
arm64: dts: lx2160a-clearfog-itx: move shared includes to dts
arm64: dts: lx2160a-cex7: add usb hub
arm64: dts: Add support for LX2160 Twins board in single configuration
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 41 +-
.../boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 +
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 7 +-
.../boot/dts/freescale/fsl-lx2160a-half-twins.dts | 830 +++++++++++++++++++++
.../boot/dts/freescale/fsl-lx2160a-honeycomb.dts | 2 +
.../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 30 +-
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 +-
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 37 +-
10 files changed, 915 insertions(+), 61 deletions(-)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20240118-lx2160-pci-4bdb196e58f3
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply
* [PATCH] arm64: dts: marvell: armada-37xx: mark EIP97 as dma-coherent
From: Aleksander Jan Bajkowski @ 2026-05-24 12:44 UTC (permalink / raw)
To: andrew, gregory.clement, sebastian.hesselbarth, robh, krzk+dt,
conor+dt, linux-arm-kernel, devicetree, linux-kernel
Cc: Aleksander Jan Bajkowski
Armada 37xx has coherent bus, similar to Armada 7k/8k. Cache
synchronization consumes a lot of CPU cycles. Enabling coherent DMA
increases IOPS performance up to 4 times. Some numbers:
Data length
Algo MB 16 64 128 256 1024 1424 4096
DES-ECB 1 +21 % +5 % +5 % +7 % +7 % +3 % +20 %
AES-ECB-128 1 +21 % +6 % +6 % +6 % +9 % +8 % +22 %
AES-CBC-128 1 +21 % +5 % +5 % +5 % +6 % +7 % +23 %
AES-CBC-256 1 +23 % +7 % +8 % +6 % +11 % +13 % +20 %
Data length
Algo MB 16 64 256 512 1024 1420 4096 8192
AES-GCM-128 1 +44 % +42 % +31 % +32 % +27 % +30 % +32 % +30 %
AES-GCM-128 8 +319 % +326 % +163 % +148 % +75 % +72 % +74 % +41 %
AES-GCM-128 4096 +123 % +128 % +90 % +83 % +116 % +59 % +38 % +28 %
Data length
Algo MB 16 64 256 1024 2048 4096 8192
MD5 1 +21 % +15 % +29 % +25 % +50 % +16 % +20 %
SHA1 1 +24 % +22 % +27 % +22 % +18 % +20 % +20 %
SHA256 1 +30 % +24 % +25 % +26 % +21 % +41 % +19 %
SHA512 1 +4 % +3 % +8 % +10 % +24 % +10 % +11 %
Tested on Armada 3720. Platform passes testmgr selftests.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 360fc24fdde2..8418777042b8 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -437,6 +437,7 @@ crypto: crypto@90000 {
interrupt-names = "ring0", "ring1", "ring2",
"ring3", "eip", "mem";
clocks = <&nb_periph_clk 15>;
+ dma-coherent;
};
rwtm: mailbox@b0000 {
--
2.53.0
^ permalink raw reply related
* sunxi: Watchdog reboot fails on Allwinner R40 after Linux boot
From: Fabio Estevam @ 2026-05-24 12:41 UTC (permalink / raw)
To: Guenter Roeck, wens, Jernej Skrabec, Samuel Holland,
Andre Przywara
Cc: moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-sunxi, linux-watchdog, Otavio Salvador
Hi,
I am seeing a reboot failure on an Allwinner R40-based board
(Boardcon EMA40i) running mainline Linux v6.18 or also 7.1.0-rc4-next-20260522.
This board hasn't been upstreamed yet, but I plan to do so soon.
The board reboots correctly from U-Boot 2026.04 using the sunxi watchdog,
but Linux fails to reboot even when programming the watchdog
registers with the exact same values used by U-Boot.
The board hangs with:
[ 10.736509] reboot: Restarting system
The watchdog node is:
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
The hardware watchdog appears correctly:
[ 0.178494] sunxi-wdt 1c20c90.watchdog: Watchdog enabled (timeout=16
sec, nowayout=0)
I instrumented U-Boot and confirmed reboot goes through
drivers/watchdog/sunxi_wdt.c().
The final register state before a successful reboot in U-Boot is:
ctrl = 0x00000001
cfg = 0x00000003
mode = 0x00000003
and the board immediately resets.
However, under Linux, even direct MMIO writes do not reboot
the board:
devmem 0x01c20c94 32 0x00000003
devmem 0x01c20c90 32 0x00000001
No reset occurs.
I also tested:
- clk_ignore_unused
- removing the watchdog DT node entirely
- nosmp
- maxcpus=1
- psci=off
No change.
I compared:
- Watchdog registers
- CCU registers
- PRCM/RTC regions
- AXP22x PMIC registers
between U-Boot and Linux, and did not find an obvious difference that
explains the failure.
The board hardware connects the R40 RESET/AP-RESET signal to
the AXP22x PWROK input.
The PMIC power-off register works correctly from Linux:
i2cset -f -y 0 0x34 0x32 0x80
but this powers off the board instead of rebooting it.
Has anyone seen similar reboot failures on R40/sun8i platforms,
or is there any known erratum/workaround related to the watchdog
reset propagation after Linux runtime initialization?
Thanks,
Fabio Estevam
^ permalink raw reply
* Re: [PATCH v6 08/10] arm64: dts: lx2160a: add labels to thermal trip-point nodes
From: Josua Mayer @ 2026-05-24 12:12 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Shawn Guo, Li Yang, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring, Krzysztof Kozlowski, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Yazan Shhady, Jon Nettleton, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <20260514-kind-antique-ocelot-d34abe@quoll>
Am 14.05.26 um 08:41 schrieb Krzysztof Kozlowski:
> On Tue, May 12, 2026 at 04:39:03PM +0200, Josua Mayer wrote:
>> LX2160A SoC dtsi defines rather conservative thermal trip points,
>> alert at 85°C and critical at 95°C.
>>
>> This is okay for most boards, however the SoC maximum junction
>> temperature is 105°C in both commercial and industrial version.
>>
>> Industrial grade boards need to change the thresholds to avoid premature
>> thermal shutdown in high-temeprature environments.
>>
>> Add labels to all thermal trip point nodes, enabling board dts to
>> reference them and modify properties.
> This is dead code or no-op. Labels should be referenced, otherwise you
> are changing here nothing.
>
> Squash the patches with the user of this label.
Will do, thanks.
^ permalink raw reply
* [PATCH v6 2/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-05-24 12:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer
In-Reply-To: <20260524-imx8dxl-sr-som-v6-0-37932c6eb7e4@solid-run.com>
Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1)
and its corresponding evaluation carrier board, the HummingBoard
Telematics (revision 2.0).
The SoM features:
- eMMC
- GNSS with 1PPS
- V2X DSRC Radio
- Secure Element for V2X Applications
- Inertial Sensor
- Pressure Sensor
- Compass
The HummingBoard Telematics carrier board features:
- Cellular Modem
- WiFi & Bluetooth
- RTC with backup battery
- CAN
- 100Base-TX Ethernet
- 100Base-T1 Ethernet
- Multi-interface I/O connector
- Multi-interface add-on board connector
The multi-interface I/O connector supplies power and provides basic I/O
(Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level
GPIOs). The SolidRun Evaluation Kit includes a suitable cable and
adapter board that breaks these out into RJ45, USB Type-A, microUSB
Console, and Terminal Block connectors.
The multi-interface add-on board connector provides additional
interfaces (5x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular
modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on
interfaces are disabled by default in the base device tree and are
intended to be enabled and extended via device tree overlays.
Note that a few components physically present on the SoM were omitted
from this description due to a lack of upstream bindings and drivers:
- Pressure Sensor
- V2X DSRC Radio
- Secure Element
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 560 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 +++++++++++++++++
3 files changed, 1020 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..7db459f666610 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -111,6 +111,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
+DTC_FLAGS_imx8dxl-hummingboard-telematics := -@
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-hummingboard-telematics.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
new file mode 100644
index 0000000000000..3095dc87f188d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
@@ -0,0 +1,560 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "imx8dxl-sr-som.dtsi"
+
+/ {
+ compatible = "solidrun,imx8dxl-hummingboard-telematics",
+ "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL HummingBoard Telematics";
+
+ aliases {
+ /* override ethernet aliases from imx8dxl.dtsi */
+ ethernet0 = &eqos;
+ ethernet1 = &switch_port1;
+ ethernet2 = &switch_port2;
+ ethernet3 = &switch_port3;
+ ethernet4 = &switch_port4;
+ ethernet5 = &switch_port5;
+ ethernet6 = &switch_port6;
+ ethernet7 = &switch_port7;
+ ethernet8 = &switch_port8;
+ ethernet9 = &switch_port9;
+ ethernet10 = &switch_port10;
+ gpio8 = &tca6408_u2;
+ mmc2 = &usdhc3;
+ rtc0 = &carrier_rtc;
+ rtc1 = &rtc;
+ serial1 = &lpuart1;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ v_1_1: regulator-1-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v1";
+ pinctrl-0 = <®ulator_1v1_pins>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_5_0: regulator-5-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v0";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ /* can transceiver builtin regulator (STBN1 pin) */
+ reg_flexcan1_stby: regulator-flexcan1-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan1-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* can transceiver builtin regulator (STBN2 pin) */
+ reg_flexcan2_stby: regulator-flexcan2-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan2-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ modem_vbat: regulator-modem-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "modem-vbat";
+ pinctrl-0 = <®ulator_modem_vbat_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3600000>;
+ regulator-min-microvolt = <3600000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * Cellular Modem uses VBAT, RESET_N and PWRKEY for
+ * power-sequencing. USB core does not currently
+ * support this, keep vbat on permanently and let
+ * userspace deal with reset/pwrkey.
+ */
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ pinctrl-0 = <®ulator_usb1_vbus_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dma_apbh {
+ status = "disabled";
+};
+
+&eqos {
+ /* delays are added by connected ethernet-switch cpu port */
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+ pinctrl-0 = <&eqos_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-0 = <&flexcan1_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan1_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&flexcan2 {
+ pinctrl-0 = <&flexcan2_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan2_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&i2c2 {
+ /* routed to J14: SDA(51), SCL(53) */
+
+ /* regulator@18 */
+
+ tca6408_u2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2",
+ "DIG_OUT1", "DIG_OUT2", "", "";
+ interrupts-extended = <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&tca6408_u2_int_pins>;
+ pinctrl-names = "default";
+ };
+
+ carrier_rtc: rtc@32 {
+ compatible = "epson,rx8111";
+ reg = <0x32>;
+ };
+};
+
+&iomuxc {
+ bluetooth_pins: pinctrl-bluetooth-grp {
+ fsl,pins = <
+ /* BT_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061
+ >;
+ };
+
+ eqos_pins: pinctrl-eqos-grp {
+ fsl,pins = <
+ /* MDIO to Switch */
+ /* enet0 mdio pads supplied with 3.3v */
+ /* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
+ /* RGMII to Switch */
+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
+ >;
+ };
+
+ flexcan1_pins: pinctrl-flexcan1-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021
+ IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021
+ >;
+ };
+
+ flexcan2_pins: pinctrl-flexcan2-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021
+ IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021
+ >;
+ };
+
+ lpspi0_pins: pinctrl-lpspi0-grp {
+ fsl,pins = <
+ IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
+ IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
+ IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
+ IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021
+ IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021
+ >;
+ };
+
+ lpuart1_pins: pinctrl-lpuart1-grp {
+ fsl,pins = <
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ >;
+ };
+
+ modem_pins: pinctrl-lte-grp {
+ fsl,pins = <
+ /* modem RESET_N: io open drain drive 2mA */
+ IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061
+
+ /* modem PWRKEY: io open drain with pull-up, drive 2mA */
+ IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021
+ >;
+ };
+
+ regulator_1v1_pins: pinctrl-regulator-1-1-grp {
+ fsl,pins = <
+ /* SW_PE: io without pull-up */
+ IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061
+ >;
+ };
+
+ regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
+ fsl,pins = <
+ /*
+ * RF_PWR: io without pull-up,
+ * has either external pull-up (R1117) or pull-down (R1118).
+ * With pull-up Modem will boot at system power-up,
+ * with pull-down modem will enter power-down mode once
+ * vbat is enabled -> toggle pwrkey to boot modem.
+ * Hence pull-up (R1117) is preferred.
+ */
+ IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061
+ >;
+ };
+
+ regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
+ fsl,pins = <
+ /* regulator enable: open-drain with pull-up & low drive strength */
+ IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021
+ >;
+ };
+
+ switch_pins: pinctrl-switch-grp {
+ fsl,pins = <
+ /* SW_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021
+
+ /* SW_CORE_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021
+
+ /* INT_N: io without pull-up */
+ IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021
+ >;
+ };
+
+ tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp {
+ fsl,pins = <
+ /* gpio-expander interrupt: io with pull-up */
+ IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021
+ >;
+ };
+
+ usdhc3_pins: pinctrl-usdhc3-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021
+ >;
+ };
+
+ wifi_pins: pinctrl-wifi-grp {
+ fsl,pins = <
+ /* WL_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061
+ >;
+ };
+};
+
+&lpspi0 {
+ cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&lpspi0_pins>, <&switch_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethernet-switch@0 {
+ compatible = "nxp,sja1110a";
+ reg = <0>;
+ reset-gpios = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <4000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ switch_port1: port@1 {
+ reg = <0x1>;
+ phy-handle = <&switch_port1_base_tx_phy>;
+ phy-mode = "internal";
+ };
+
+ /* CPU */
+ switch_port2: port@2 {
+ reg = <0x2>;
+ ethernet = <&eqos>;
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+ };
+
+ /* sgmii on addon board connector J21 */
+ switch_port3: port@3 {
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* sgmii on addon board connector J21 */
+ switch_port4: port@4 {
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port5: port@5 {
+ reg = <0x5>;
+ phy-handle = <&switch_port5_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port6: port@6 {
+ reg = <0x6>;
+ phy-handle = <&switch_port6_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port7: port@7 {
+ reg = <0x7>;
+ phy-handle = <&switch_port7_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port8: port@8 {
+ reg = <0x8>;
+ phy-handle = <&switch_port8_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port9: port@9 {
+ reg = <0x9>;
+ phy-handle = <&switch_port9_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ switch_port10: port@a {
+ reg = <0xa>;
+ phy-handle = <&switch_port10_base_t1_phy>;
+ phy-mode = "internal";
+ };
+ };
+
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ compatible = "nxp,sja1110-base-t1-mdio";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port5_base_t1_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port6_base_t1_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port7_base_t1_phy: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port8_base_t1_phy: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port9_base_t1_phy: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ switch_port10_base_t1_phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x6>;
+ };
+ };
+
+ mdio@1 {
+ compatible = "nxp,sja1110-base-tx-mdio";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ switch_port1_base_tx_phy: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ };
+ };
+};
+
+/* bluetooth */
+&lpuart1 {
+ pinctrl-0 = <&lpuart1_pins>, <&bluetooth_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&osc_32k>;
+ clock-names = "lpo";
+ /* Murata 1MW module supports max. 3M baud */
+ max-speed = <3000000>;
+ shutdown-gpios = <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>;
+ /* link fixed supplies to avoid fall-back lookup by name */
+ vbat-supply = <&v_3_3>;
+ vddio-supply = <&v_1_8>;
+ };
+};
+
+&lsio_gpio1 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "CELL_RESET_N", "CELL_PWRKEY", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <&vbus1>;
+};
+
+/* cellular modem */
+&usbotg2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adp-disable;
+ disable-over-current;
+ dr_mode = "host";
+ hnp-disable;
+ pinctrl-0 = <&modem_pins>;
+ pinctrl-names = "default";
+ power-active-high;
+ srp-disable;
+ vbus-supply = <&v_5_0>;
+ status = "okay";
+
+ usb-device@1 {
+ compatible = "usb2c7c,125";
+ reg = <1>;
+ vbus-supply = <&v_3_3>;
+ vdd-supply = <&modem_vbat>;
+ };
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc3 {
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc3_pins>, <&wifi_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
new file mode 100644
index 0000000000000..93a0eb4d7f770
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "imx8dxl.dtsi"
+/ {
+ compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL SoM";
+
+ aliases {
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart0;
+ serial2 = &lpuart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ imx8dxl-cm4 {
+ compatible = "fsl,imx8qxp-cm4";
+ clocks = <&clk_dummy>;
+ mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+ fsl,entry-address = <0x34fe0000>;
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&gnss_pps_pins>;
+ pinctrl-names = "default";
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ pinctrl-0 = <®ulator_1_2_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_6: regulator-1-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v6";
+ pinctrl-0 = <®ulator_1_6_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1600000>;
+ regulator-min-microvolt = <1600000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ v_1_8_se: regulator-1-8-secure-element {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8-se";
+ pinctrl-0 = <®ulator_1_8_se_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x98000000 0 0x14000000>;
+ reusable;
+ size = <0 0x14000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: memory0@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: memory-rsc-table@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory-vdevbuffer@90400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ /*
+ * Memory reserved for optee usage. Please do not use.
+ * This will be automatically added to dtb if OP-TEE is installed.
+ * optee@96000000 {
+ * reg = <0 0x96000000 0 0x2000000>;
+ * no-map;
+ * };
+ */
+ };
+
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&i2c3_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ magnetometer@1e {
+ compatible = "st,iis2mdc";
+ reg = <0x1e>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <10 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&magnetometer_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+
+ /* pressure-sensor@5c */
+
+ inertial-sensor@6b {
+ compatible = "st,ism330dhcx";
+ reg = <0x6b>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&imu_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog>;
+ pinctrl-names = "default";
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
+ >;
+ };
+
+ dsrc_pins: pinctrl-dsrc-grp {
+ fsl,pins = <
+ /* reset: io without pull */
+ IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060
+
+ /*
+ * boot0: io without pull
+ * After reset, this pin selects radio boot media:
+ * - 0: flash spi
+ * - 1: slave sdio
+ * Once the firmware boots however, the radio controls
+ * this pin for flow-control to signal readiness.
+ */
+ IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060
+ >;
+ };
+
+ gnss_pins: pinctrl-gnss-grp {
+ fsl,pins = <
+ /* gps reset: input with pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021
+ /* gps interrupt: io without pull-up */
+ IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061
+ >;
+ };
+
+ gnss_pps_pins: pinctrl-gnss-pps-grp {
+ fsl,pins = <
+ /* gps timepulse: input without pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061
+ >;
+ };
+
+ i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021
+ >;
+ };
+
+ i2c2_pins: pinctrl-i2c2-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
+ >;
+ };
+
+ i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021
+ >;
+ };
+
+ i2c3_pins: pinctrl-i2c3-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
+ >;
+ };
+
+ imu_pins: pinctrl-imu-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041
+ >;
+ };
+
+ lpspi2_pins: pinctrl-lpspi2-grp {
+ fsl,pins = <
+ IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c
+ IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c
+ IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c
+ IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021
+ >;
+ };
+
+ lpuart0_pins: pinctrl-lpuart0-grp {
+ fsl,pins = <
+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ lpuart2_pins: pinctrl-lpuart2-grp {
+ fsl,pins = <
+ IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ magnetometer_pins: pinctrl-magnetometer-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041
+ >;
+ };
+
+ regulator_1_2_pins: pinctrl-regulator-1-2-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061
+ >;
+ };
+
+ regulator_1_6_pins: pinctrl-regulator-1-6-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061
+ >;
+ };
+
+ regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element power switch: io with pull-down */
+ IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041
+ >;
+ };
+
+ se_pins: pinctrl-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element reset: io with pull-up */
+ IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021
+
+ /*
+ * v2x-secure-element gpio0: io with pull-up
+ * pulled low by sxf after boot indicating ready for commands
+ */
+ IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021
+
+ /* v2x-secure-element gpio1: io with pull-up */
+ IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021
+ >;
+ };
+
+ usdhc1_pins: pinctrl-usdhc1-grp {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ >;
+ };
+};
+
+&lpspi2 {
+ cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&lpspi2_pins>, <&se_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* console */
+&lpuart0 {
+ pinctrl-0 = <&lpuart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* gnss */
+&lpuart2 {
+ pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lsio_gpio3 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&lsio_mu5 {
+ status = "okay";
+};
+
+/* OTG port for boot */
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "peripheral";
+ hnp-disable;
+ power-active-high;
+ srp-disable;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-0 = <&usdhc1_pins>;
+ pinctrl-1 = <&usdhc1_pins>;
+ pinctrl-2 = <&usdhc1_pins>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
+
+/* DSRC Radio */
+&usdhc2 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ max-frequency = <40000000>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v6 1/2] dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
From: Josua Mayer @ 2026-05-24 12:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
In-Reply-To: <20260524-imx8dxl-sr-som-v6-0-37932c6eb7e4@solid-run.com>
Add binding for the SolidRun i.MX8DXL based System on Module, and the
reference HummingBoard Telematics.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0023cd1268075..17cd47e8efce8 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1394,6 +1394,13 @@ properties:
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
+ - description: SolidRun i.MX8DXL SoM based boards
+ items:
+ - enum:
+ - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board
+ - const: solidrun,imx8dxl-sr-som
+ - const: fsl,imx8dxl
+
- description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
items:
- enum:
--
2.51.0
^ permalink raw reply related
* [PATCH v6 0/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-05-24 12:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
Add bindings and description for SolidRUn i.MX8DXL based SoM and
HummingBoard Telematics.
Modify SJA1110 Ethernet Switch bindings to allow SPI Mode 0.
This patch-set is based on v7.0-rc2, because rc1 was experiencing
deadlocks with imx8qxp clock driver.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v6:
- Remove stray /delete-property/ from aliases.
- Fix name collision for bluetooth "vbat" regulator.
- Kernel can't power-sequence cellular modem, ensure userspace can:
Drop reset-gpios, set vbat always-on, define gpio line-name for
powerkey and reset.
- Link to v5: https://lore.kernel.org/r/20260513-imx8dxl-sr-som-v5-0-d0899b371c38@solid-run.com
Changes in v5:
- Change cpu port phy-mode to rgmii-id, and set zero delays. Delays are
added by connected ethernet switch port.
- Added ethernet aliases for all switch ports.
- Removed undocumented reset-duration-us property from usb modem node.
- Fix T1 interface count in commit message.
- Change USB-A Port dr_mode to host.
- Add cap-sdio-irq for wifi.
- Link to v4: https://lore.kernel.org/r/20260511-imx8dxl-sr-som-v4-0-64381b3bf80d@solid-run.com
Changes in v4:
- picked up acked-by adnrew lunn
- Link to v3: https://lore.kernel.org/r/20260430-imx8dxl-sr-som-v3-0-ce2b86cf75bc@solid-run.com
Changes in v3:
- rebased on v7.1-rc1.
- dropped dsa swtch port labels, should be handled by udev rules if
required.
- Fixed spelling error in alias comment.
- Dropped superfluous status okay properties from switch sub-nodes.
- Link to v2: https://lore.kernel.org/r/20260409-imx8dxl-sr-som-v2-0-83ff20629ba0@solid-run.com
Changes in v2:
- Dropped accidental change to unrelated imx8mp-sr-som.dtsi file.
- Fixed phy-mode on fixed link between cpu and ethernet switch.
(Reported-by: Andrew Lunn <andrew@lunn.ch>)
- Removed spi-cpol property from ethernet-switch on spi bus, fixing
sja1110a driver probe.
- Changed SJA1110 bindings to allow removing spi-cpol property.
- Aligned comments on all ethernet switch port nodes to be consistent.
- Dropped regulator-always-on from dsrc radio power-supplies.
- Link to v1: https://lore.kernel.org/r/20260408-imx8dxl-sr-som-v1-0-ce5a39acd713@solid-run.com
---
Josua Mayer (2):
dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 560 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 +++++++++++++++++
4 files changed, 1027 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260408-imx8dxl-sr-som-f141ec343173
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply
* Re: [PATCH v4 2/2] dt-bindings: pwm: stmpe: drop legacy binding
From: Uwe Kleine-König @ 2026-05-24 11:21 UTC (permalink / raw)
To: Manish Baing
Cc: lee, robh, krzk+dt, conor+dt, mcoquelin.stm32, alexandre.torgue,
linusw, linux-pwm, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, Conor Dooley
In-Reply-To: <20260523173251.72540-3-manishbaing2789@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 554 bytes --]
On Sat, May 23, 2026 at 05:32:51PM +0000, Manish Baing wrote:
> The st,stmpe-pwm binding is already covered by the MFD schema
> Documentation/devicetree/bindings/mfd/st,stmpe.yaml. Remove the
> obsolete and redundant text binding file.
>
> Signed-off-by: Manish Baing <manishbaing2789@gmail.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Uwe Kleine-König <ukleinek@kernel.org>
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git pwm/for-next
with Rob's ack from v2.
Best regards
Uwe
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH] ARM: entry: use byte load for KASAN VMAP stack shadow
From: Karl Mehltretter @ 2026-05-24 7:49 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Russell King (Oracle), linux-arm-kernel,
linux-kernel, stable
In-Reply-To: <CAD++jLnhONOMn=7hG-EC_uB80nxXfAnRMuZC2xoJjf2Xzcaiuw@mail.gmail.com>
On Sun, May 24, 2026 at 12:08:57AM +0100, Linus Walleij wrote:
> Please put this patch into Russell's patch tracker.
Done: https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=9475/1
Thanks,
Karl
^ permalink raw reply
* Re: [PATCH v2 2/3] ASoC: sunxi: sun4i-spdif: Resume device before kcontrol register access
From: Chen-Yu Tsai @ 2026-05-24 7:36 UTC (permalink / raw)
To: Bui Duc Phuc
Cc: broonie, codekipper, jernej.skrabec, lgirdwood, linux-arm-kernel,
linux-kernel, linux-sound, linux-sunxi, nichen, perex, samuel,
tiwai
In-Reply-To: <CAABR9nEB8jizn+NrVgrjcOOJRtaU0u+TH705unMTh7HYO=8Wcg@mail.gmail.com>
On Sat, May 23, 2026 at 4:55 PM Bui Duc Phuc <phucduc.bui@gmail.com> wrote:
>
> Hi Chen-Yu,
>
> On Sat, May 23, 2026 at 2:19 AM Chen-Yu Tsai <wens@kernel.org> wrote:
> > And when you do add patches due to Sashiko raising an issue, please
> > do mention it in the commit message.
> >
>
> As mentioned in the v1 discussion , this issue was originally reported
> by Sashiko.
> I'll add the Reported-by tag in the next revision.
> v1 links:
> https://lore.kernel.org/all/20260513105003.81880-1-phucduc.bui@gmail.com/
>
> > Did you actually reproduce the issue, or did you add the patch simply
> > because Sashiko mentioned it?
> >
> Since I lack Sunxi hardware, I couldn't reproduce it or perform runtime testing.
> But I did compile-test the patch.
> The patch aims to fix unsafe register accesses that occur before ensuring the
> device is runtime-resumed.
When you submit a patch, it is expected that you already tested it.
If you only compile tested it, please remember to say so in the
footer (or mark the patch as RFT) so that others can test for you
and the maintainer knows the status.
And if possible, provide a scheme to test it.
> > On sunxi, either it will hang the system because the bus transaction
> > got ignored, or it won't as something else enabled the clock.
> >
>
> If Sunxi's PM design already guarantees safe access here,
> feel free to reject the patch.
I can't say that it does. But since the only control that SPDIF gives
is the IEC958 status, and that doesn't appear in the standard mixer apps,
it's unlikely that a _user_ will trigger it. Plus the control was added
after the basic structure of the driver was done, so there is definitely
some possibility of a crash.
But what you wrote in the commit message doesn't match the actual hardware
behavior, like I wrote.
ChenYu
^ permalink raw reply
* Re: [PATCH] ARM: io: avoid KASAN instrumentation of raw halfword I/O
From: Karl Mehltretter @ 2026-05-24 8:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Abbott Liu, Ard Biesheuvel, Florian Fainelli,
linux-arm-kernel, linux-kernel, stable
In-Reply-To: <CAD++jL=jrk4EYo+5mhp1cpy2cfsA966MVmbohWhcZdx_SObD_w@mail.gmail.com>
On Sun, May 24, 2026 at 12:11:36AM +0100, Linus Walleij wrote:
> Please put this patch into Russell's patch tracker.
Done: https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=9474/1
Thanks,
Karl
^ permalink raw reply
* Re: [PATCH RFC 00/12] arm64: mediatek: Add M.2 E-key slot on Chromebooks
From: Chen-Yu Tsai @ 2026-05-24 8:06 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
linux-pm, linux-usb, devicetree, linux-mediatek, linux-arm-kernel,
linux-kernel, Manivannan Sadhasivam
In-Reply-To: <CAMRc=MdnjRRMVzxPkkrPhQ4dz7rsK8-HKUp9cQ0z11apL3escQ@mail.gmail.com>
On Wed, May 20, 2026 at 7:01 PM Bartosz Golaszewski <brgl@kernel.org> wrote:
>
> On Fri, May 15, 2026 at 11:02 AM Chen-Yu Tsai <wenst@chromium.org> wrote:
> >
> > Hi everyone,
> >
> > This series is my attempt at enabling power sequencing for USB to support
> > the USB connection on M.2 E-key slots. M.2 E-key was enabled in v7.1-rc1
> > with just PCIe and UART supported [1].
> >
> > Most of the series is based on next-20260508, while the DT changes also
> > depend on some other DT cleanup patches I sent [2][3].
> >
> >
> > Patch 1 reworks the power sequencing framework to allow matching against
> > different USB ports. The consumer API gains an "index" parameter (which
> > is the USB port number on the hub), while the provider API is reworked
> > to pass the index to the matching function of the providing driver.
> >
>
> Sigh... I would really prefer to avoid going in this direction. IMO
> it's not very clear what this index actually refers to in generic
> terms, given that pwrseq is flexible on purpose and there's no
> specific, well-defined DT property which could have an "index".
>
> > Patch 2 implements the index matching in the pcie-m2 driver. Matching
> > only happens when a valid (>= 0) index is given.
> >
> > Patch 3 reworks the power sequencing targets for the E-key connector in
> > the pcie-m2 driver to add targets for USB and SDIO. The former is used
> > later on in this series.
> >
> > Patch 4 reworks the USB hub driver to return the actual error code from
> > hub_configure() in hub_probe(). This is needed in the next patch to
> > correctly return -EPROBE_DEFER.
> >
> > Patch 5 lets the USB hub driver look for power sequencers for each port.
> > Currently this only works for M.2 E-key connections, but it could be
> > extended to cover other cases. It should also make port reset via turning
> > off the port VBUS work, even when VBUS is not directly controlled by the
> > hub.
> >
> > I expect some discussion on this patch, because a) it adds some
> > OF-specific code into an otherwise generic (core) driver, and
> > b) it doesn't yet handle USB 2.0 / 3.x shared ports; it ends up powering
> > on the port twice, which negates the port reset part.
> >
>
> I understand that you do this because the port device has no OF node
> assigned. If we wanted to call pwrseq_get() for the port device, is
> there really no other way to associate it with the correct pwrseq
> provider?
I suppose we could tie the "port@X" node to the usb port device, but
AFAIK no other subsystem does this so we would be introducing a new
pattern.
In the M.2 pwrseq driver, we would have to match by port node instead
of its parent device node. We may end up with different behavior for
the USB target vs the other targets.
Also, the "port@X" nodes only exist for the OF graph connections to
connectors and/or muxes (this series doesn't deal with the latter).
For directly connected devices, there is a "device@X" child node
directly under the USB hub node. That node is what gets tied to the
the USB device.
> Does the child index in hub_configure() relate to the port index as
> defined by the unit address of the port DT node? I'm talking about the
> X in port@X?
Yes. The downstream port numbers start at 1. I believe 0 corresponds
to the upstream port.
> > Patch 6 reverts an incorrectly modeled OF graph connection for the
> > MediaTek XHCI controller.
> >
> > Patch 7 then adds a proper representation.
> >
> > Patches 8 through 12 enable the M.2 E-key slots (used for WiFi/BT) and
> > USB type-A connectors found on MediaTek-based Chromebooks. These are
> > provided in this series for reference. The USB type-A connector changes,
> > while not directly related, have overlapping context, and was easier to
> > include. They were also used to test some extra local changes I tried
> > to convert the USB A connector from an onboard USB device to a power
> > sequencing provider.
> >
> >
> > As this series changes existing power sequencing API, and also uses the
> > changed API in subsequent patches, I think the best way to merge this
> > is for Bartosz to take the power sequencing patches and provide an
> > immutable tag for Greg to merge and then merge the USB patches.
> >
> > The DT patches can go through the soc tree once all the driver and DT
> > binding changes are merged.
> >
> >
> > Thanks
> > ChenYu
> >
> > P.S. I'll be at Embedded Recipes if anyone wants to discuss details.
> >
>
> I'll be there too! Or should i say "here"? I live here after all. :) Let's talk!
Sure!
Thanks
ChenYu
^ permalink raw reply
* Re: [PATCH v2 3/3] ASoC: sunxi: sun4i-spdif: Reorder clock enable sequence
From: Chen-Yu Tsai @ 2026-05-24 7:41 UTC (permalink / raw)
To: Bui Duc Phuc
Cc: broonie, codekipper, jernej.skrabec, lgirdwood, linux-arm-kernel,
linux-kernel, linux-sound, linux-sunxi, nichen, perex, samuel,
tiwai
In-Reply-To: <CAABR9nEFGOX5GnQ9qpJY-T-92dA_kDcVS+qBz1ior590G_x6gw@mail.gmail.com>
On Sat, May 23, 2026 at 3:11 PM Bui Duc Phuc <phucduc.bui@gmail.com> wrote:
>
> Hi Chen-yu,
>
> Thanks for your feedback
>
> On Sat, May 23, 2026 at 2:20 AM Chen-Yu Tsai <wens@kernel.org> wrote:
> > > Enable the APB bus clock before the SPDIF module clock
> > > during runtime resume, as register accesses depend on the
> > > bus clock being enabled first.
> >
> > That does not even matter here. Access will only happen once the runtime
> > PM callbacks return.
> >
>
> I understand your point that sun4i-spdif doesn't immediately access
> registers within the current runtime_resume path, so the order might
> not trigger a failure right now.
>
> However, if we look at the peer driver for the same Sunxi SoC family,
> sun4i-i2s.c:
> Links:
> https://elixir.bootlin.com/linux/v7.0-rc5/source/sound/soc/sunxi/sun4i-i2s.c#L1296
> In sun4i_i2s_runtime_resume(), the sequence is strictly enforced as:
>
> 1. Enable bus clock
> 2. Access and restore/sync I2S registers
> 3. Enable module clock
>
> Since both IP blocks belong to the same Sunxi platform and share similar
> bus/module clock relationships, shouldn't we maintain architectural
> consistency across these drivers?
>
> Enforcing the "bus clock before module clock" order keeps the dependency
> ordering aligned with the actual hardware roles, where the bus clock is
> required for register access while the module clock drives the functional
> audio path.
>
> Wouldn't keeping this order also make the runtime PM behavior more
> consistent and easier to follow across the Sunxi audio drivers?
This should be your primary motivation for the patch, i.e. what you
put in the commit message as the reason for this patch. What you
currently have doesn't make sense, as I already mentioned.
Some background though, sunxi is done mostly by volunteers, so we're
not overly concerned with rigidness or aligning different drivers,
unless they share a common library, such as all the clk or pinctrl
drivers.
ChenYu
^ permalink raw reply
* Re: [PATCH v2] ARM: OMAP2+: Add CFI type for omap4_finish_suspend
From: kernel test robot @ 2026-05-24 6:01 UTC (permalink / raw)
To: Mithil Bavishi, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Russell King
Cc: llvm, oe-kbuild-all, Sami Tolvanen, Kees Cook, Nathan Chancellor,
linux-arm-kernel, linux-omap, linux-kernel, Mithil Bavishi
In-Reply-To: <20260522233036.12277-1-bavishimithil@gmail.com>
Hi Mithil,
kernel test robot noticed the following build errors:
[auto build test ERROR on tmlind-omap/for-next]
[also build test ERROR on linus/master v7.1-rc4 next-20260522]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Mithil-Bavishi/ARM-OMAP2-Add-CFI-type-for-omap4_finish_suspend/20260523-073206
base: https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git for-next
patch link: https://lore.kernel.org/r/20260522233036.12277-1-bavishimithil%40gmail.com
patch subject: [PATCH v2] ARM: OMAP2+: Add CFI type for omap4_finish_suspend
config: arm-defconfig (https://download.01.org/0day-ci/archive/20260524/202605241332.fXvCYBR2-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 5bac06718f502014fade905512f1d26d578a18f3)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260524/202605241332.fXvCYBR2-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202605241332.fXvCYBR2-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/arm/mach-omap2/sleep44xx.S:61:1: error: invalid instruction
SYM_TYPED_FUNC_START(omap4_finish_suspend)
^
vim +61 arch/arm/mach-omap2/sleep44xx.S
33
34 /*
35 * =============================
36 * == CPU suspend finisher ==
37 * =============================
38 *
39 * void omap4_finish_suspend(unsigned long cpu_state)
40 *
41 * This function code saves the CPU context and performs the CPU
42 * power down sequence. Calling WFI effectively changes the CPU
43 * power domains states to the desired target power state.
44 *
45 * @cpu_state : contains context save state (r0)
46 * 0 - No context lost
47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
50 * @return: This function never returns for CPU OFF and DORMANT power states.
51 * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
52 * from this follows a full CPU reset path via ROM code to CPU restore code.
53 * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
54 * It returns to the caller for CPU INACTIVE and ON power states or in case
55 * CPU failed to transition to targeted OFF/DORMANT state.
56 *
57 * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
58 * stack frame and it expects the caller to take care of it. Hence the entire
59 * stack frame is saved to avoid possible stack corruption.
60 */
> 61 SYM_TYPED_FUNC_START(omap4_finish_suspend)
62 stmfd sp!, {r4-r12, lr}
63 cmp r0, #0x0
64 beq do_WFI @ No lowpower state, jump to WFI
65
66 /*
67 * Flush all data from the L1 data cache before disabling
68 * SCTLR.C bit.
69 */
70 bl omap4_get_sar_ram_base
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
72 cmp r9, #0x1 @ Check for HS device
73 bne skip_secure_l1_clean
74 mov r0, #SCU_PM_NORMAL
75 mov r1, #0xFF @ clean seucre L1
76 stmfd r13!, {r4-r12, r14}
77 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
78 DO_SMC
79 ldmfd r13!, {r4-r12, r14}
80 skip_secure_l1_clean:
81 bl v7_flush_dcache_all
82
83 /*
84 * Clear the SCTLR.C bit to prevent further data cache
85 * allocation. Clearing SCTLR.C would make all the data accesses
86 * strongly ordered and would not hit the cache.
87 */
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
91 isb
92
93 bl v7_invalidate_l1
94
95 /*
96 * Switch the CPU from Symmetric Multiprocessing (SMP) mode
97 * to AsymmetricMultiprocessing (AMP) mode by programming
98 * the SCU power status to DORMANT or OFF mode.
99 * This enables the CPU to be taken out of coherency by
100 * preventing the CPU from receiving cache, TLB, or BTB
101 * maintenance operations broadcast by other CPUs in the cluster.
102 */
103 bl omap4_get_sar_ram_base
104 mov r8, r0
105 ldr r9, [r8, #OMAP_TYPE_OFFSET]
106 cmp r9, #0x1 @ Check for HS device
107 bne scu_gp_set
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
109 ands r0, r0, #0x0f
110 ldreq r0, [r8, #SCU_OFFSET0]
111 ldrne r0, [r8, #SCU_OFFSET1]
112 mov r1, #0x00
113 stmfd r13!, {r4-r12, r14}
114 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
115 DO_SMC
116 ldmfd r13!, {r4-r12, r14}
117 b skip_scu_gp_set
118 scu_gp_set:
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
120 ands r0, r0, #0x0f
121 ldreq r1, [r8, #SCU_OFFSET0]
122 ldrne r1, [r8, #SCU_OFFSET1]
123 bl omap4_get_scu_base
124 bl scu_power_mode
125 skip_scu_gp_set:
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
127 tst r0, #(1 << 18)
128 mrcne p15, 0, r0, c1, c0, 1
129 bicne r0, r0, #(1 << 6) @ Disable SMP bit
130 mcrne p15, 0, r0, c1, c0, 1
131 isb
132 dsb
133 #ifdef CONFIG_CACHE_L2X0
134 /*
135 * Clean and invalidate the L2 cache.
136 * Common cache-l2x0.c functions can't be used here since it
137 * uses spinlocks. We are out of coherency here with data cache
138 * disabled. The spinlock implementation uses exclusive load/store
139 * instruction which can fail without data cache being enabled.
140 * OMAP4 hardware doesn't support exclusive monitor which can
141 * overcome exclusive access issue. Because of this, CPU can
142 * lead to deadlock.
143 */
144 bl omap4_get_sar_ram_base
145 mov r8, r0
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
147 ands r5, r5, #0x0f
148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
149 ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
150 cmp r0, #3
151 bne do_WFI
152 #ifdef CONFIG_PL310_ERRATA_727915
153 mov r0, #0x03
154 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
155 DO_SMC
156 #endif
157 bl omap4_get_l2cache_base
158 mov r2, r0
159 ldr r0, =0xffff
160 str r0, [r2, #L2X0_CLEAN_INV_WAY]
161 wait:
162 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
163 ldr r1, =0xffff
164 ands r0, r0, r1
165 bne wait
166 #ifdef CONFIG_PL310_ERRATA_727915
167 mov r0, #0x00
168 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
169 DO_SMC
170 #endif
171 l2x_sync:
172 bl omap4_get_l2cache_base
173 mov r2, r0
174 mov r0, #0x0
175 str r0, [r2, #L2X0_CACHE_SYNC]
176 sync:
177 ldr r0, [r2, #L2X0_CACHE_SYNC]
178 ands r0, r0, #0x1
179 bne sync
180 #endif
181
182 do_WFI:
183 bl omap_do_wfi
184
185 /*
186 * CPU is here when it failed to enter OFF/DORMANT or
187 * no low power state was attempted.
188 */
189 mrc p15, 0, r0, c1, c0, 0
190 tst r0, #(1 << 2) @ Check C bit enabled?
191 orreq r0, r0, #(1 << 2) @ Enable the C bit
192 mcreq p15, 0, r0, c1, c0, 0
193 isb
194
195 /*
196 * Ensure the CPU power state is set to NORMAL in
197 * SCU power state so that CPU is back in coherency.
198 * In non-coherent mode CPU can lock-up and lead to
199 * system deadlock.
200 */
201 mrc p15, 0, r0, c1, c0, 1
202 tst r0, #(1 << 6) @ Check SMP bit enabled?
203 orreq r0, r0, #(1 << 6)
204 mcreq p15, 0, r0, c1, c0, 1
205 isb
206 bl omap4_get_sar_ram_base
207 mov r8, r0
208 ldr r9, [r8, #OMAP_TYPE_OFFSET]
209 cmp r9, #0x1 @ Check for HS device
210 bne scu_gp_clear
211 mov r0, #SCU_PM_NORMAL
212 mov r1, #0x00
213 stmfd r13!, {r4-r12, r14}
214 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
215 DO_SMC
216 ldmfd r13!, {r4-r12, r14}
217 b skip_scu_gp_clear
218 scu_gp_clear:
219 bl omap4_get_scu_base
220 mov r1, #SCU_PM_NORMAL
221 bl scu_power_mode
222 skip_scu_gp_clear:
223 isb
224 dsb
225 ldmfd sp!, {r4-r12, pc}
226 SYM_FUNC_END(omap4_finish_suspend)
227
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH] ARM: io: avoid KASAN instrumentation of raw halfword I/O
From: Linus Walleij @ 2026-05-23 22:11 UTC (permalink / raw)
To: Karl Mehltretter
Cc: Russell King, Abbott Liu, Ard Biesheuvel, Florian Fainelli,
linux-arm-kernel, linux-kernel, stable
In-Reply-To: <20260522212018.25295-1-kmehltretter@gmail.com>
On Fri, May 22, 2026 at 11:20 PM Karl Mehltretter
<kmehltretter@gmail.com> wrote:
> Commit 421015713b30 ("ARM: 9017/2: Enable KASan for ARM") made KASAN
> instrument ARM C memory accesses. For CPUs before ARMv6, __raw_readw()
> and __raw_writew() are C volatile halfword accesses, so KASAN instruments
> them as normal memory accesses.
>
> That is not valid for MMIO. On the QEMU versatilepb machine with an
> ARM926EJ-S CPU and CONFIG_KASAN=y, PL011 probing traps while registering
> the UART:
>
> Unable to handle kernel paging request at virtual address bd23e207
> PC is at __asan_store2+0x2c/0x9c
> LR is at pl011_register_port+0x4c/0x19c
>
> Keep the existing volatile halfword access, but move the pre-ARMv6
> definitions into __no_kasan_or_inline functions so raw MMIO halfword
> accesses are not instrumented by KASAN. The ARMv6-and-newer inline
> assembly path is unchanged.
>
> Fixes: 421015713b30 ("ARM: 9017/2: Enable KASan for ARM")
> Cc: stable@vger.kernel.org # v5.11+
> Assisted-by: Codex:gpt-5
> Signed-off-by: Karl Mehltretter <kmehltretter@gmail.com>
That makes sense.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Please put this patch into Russell's patch tracker.
Yours,
Linus Walleij
^ permalink raw reply
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