* Re: [PATCH v01] mailbox/pcc.c: add query channel function
From: kernel test robot @ 2026-06-05 6:54 UTC (permalink / raw)
To: Adam Young, Sudeep Holla, Jassi Brar, Rafael J. Wysocki,
Saket Dumbre, Len Brown
Cc: llvm, oe-kbuild-all, linux-kernel, linux-hwmon, linux-acpi,
Andi Shyti, Guenter Roeck, Huisong Li, MyungJoo Ham,
Kyungmin Park, Chanwoo Choi, linux-arm-kernel
In-Reply-To: <20260604203749.168752-1-admiyo@os.amperecomputing.com>
Hi Adam,
kernel test robot noticed the following build warnings:
[auto build test WARNING on jassibrar-mailbox/for-next]
[also build test WARNING on rafael-pm/linux-next rafael-pm/bleeding-edge soc/for-next linus/master v6.16-rc1 next-20260604]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Adam-Young/mailbox-pcc-c-add-query-channel-function/20260605-044323
base: https://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox.git for-next
patch link: https://lore.kernel.org/r/20260604203749.168752-1-admiyo%40os.amperecomputing.com
patch subject: [PATCH v01] mailbox/pcc.c: add query channel function
config: x86_64-kexec (https://download.01.org/0day-ci/archive/20260605/202606050825.2uv1FZrY-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project f43d6834093b19baf79beda8c0337ab020ac5f17)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260605/202606050825.2uv1FZrY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202606050825.2uv1FZrY-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> Warning: drivers/mailbox/pcc.c:358 function parameter 'q_chan' not described in 'pcc_mbox_query_channel'
>> Warning: drivers/mailbox/pcc.c:358 function parameter 'subspace_id' not described in 'pcc_mbox_query_channel'
>> Warning: drivers/mailbox/pcc.c:358 function parameter 'q_chan' not described in 'pcc_mbox_query_channel'
>> Warning: drivers/mailbox/pcc.c:358 function parameter 'subspace_id' not described in 'pcc_mbox_query_channel'
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [PATCH] pinctrl: aspeed: Fix GPIO mux value for ADC-capable balls
From: Billy Tsai @ 2026-06-05 6:38 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij, Joel Stanley, Bartosz Golaszewski
Cc: linux-aspeed, openbmc, linux-gpio, linux-arm-kernel, linux-kernel,
Billy Tsai
aspeed_g7_soc1_gpio_request_enable() unconditionally writes mux
function 0 to route the requested pin to GPIO. This is wrong for the
ADC-capable balls W17 through AB19 (ADC0-ADC15), where function 0
selects the ADC input and function 1 selects GPIO. Requesting one of
those GPIOs therefore muxed the ball to ADC instead.
Write mux value 1 for balls W17 through AB19 so the GPIO function is
actually selected.
Fixes: 4af4eb66aac3 ("pinctrl: aspeed: Add AST2700 SoC1 support")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
index a1ef52ad5c75..50027d69c342 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
@@ -691,12 +691,21 @@ static int aspeed_g7_soc1_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct aspeed_g7_soc1_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct aspeed_g7_field field;
+ unsigned int val = 0;
int ret = -ENOTSUPP;
if (pin <= AC24) {
+ /*
+ * Balls W17 through AB19 are the ADC-capable pins: mux
+ * function 0 selects the ADC input and function 1 selects
+ * GPIO, unlike all other pins where function 0 is GPIO.
+ */
+ if (pin >= W17 && pin <= AB19)
+ val = 1;
field = aspeed_g7_soc1_pinmux_field_from_pin(pin);
ret = regmap_update_bits(pctl->regmap, field.reg,
- field.mask << field.shift, 0);
+ field.mask << field.shift,
+ val << field.shift);
}
return ret;
---
base-commit: 57ae58c5506ade17df728d676a0c73c705f21f57
change-id: 20260605-pinctrl-fix-76644e70f601
Best regards,
--
Billy Tsai <billy_tsai@aspeedtech.com>
^ permalink raw reply related
* [PATCH v3 12/14] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Support Engicam MicroGEA-STM32MP257 SoM with:
- 8 GB eMMC Flash
- 2 GB LPDDR4 DRAM
The SoM also provides an Ethernet MAC, but Ethernet support is not
enabled at this stage due to a known silicon limitation documented in
[1].
This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC
errors"), where CRC errors may occur in ETH1 RMII direct mode when
directly connected to I/Os.
The workaround requires use of the Ethernet switch (ETHSW), which
introduces additional DT bindings and topology complexity. This is
intended to be addressed in a separate patch series.
[1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
Changes in v3:
- Fix a typo in the URL
.../dts/st/stm32mp257-engicam-microgea.dtsi | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
new file mode 100644
index 000000000000..67be66cd1930
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ * Copyright (C) 2026 Engicam srl
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "Engicam MicroGEA STM32MP257 SoM";
+ compatible = "engicam,microgea-stm32mp257", "st,stm32mp257";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+};
+
+&scmi_regu {
+ scmi_vddio1: regulator@0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ scmi_vddcore: regulator@b {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK2>;
+ regulator-name = "vddcore";
+ };
+ scmi_v1v8: regulator@e {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK5>;
+ regulator-name = "v1v8";
+ };
+ scmi_v3v3: regulator@10 {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK7>;
+ regulator-name = "v3v3";
+ };
+ scmi_vdd3v3_usb: regulator@14 {
+ reg = <VOLTD_SCMI_STPMIC2_LDO4>;
+ regulator-name = "vdd3v3_usb";
+ };
+};
+
+/* eMMC */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&scmi_v3v3>;
+ vqmmc-supply = <&scmi_vddio2>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 13/14] arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Support for Engicam MicroGEA-STM32MP257-RMM board with:
- 8 GB eMMC Flash
- 2 GB LPDDR4 DRAM
- CAN
- LEDs
- LCD panel with touchscreen
- Micro SD card connector
- Audio codec
- Buzzer
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v2)
Changes in v2:
- Drop the clocks property from the sai1 node in stm32mp257-engicam-microgea-rmm.dts
to avoid overriding the peripheral bus clock reference defined in the base
SoC device tree. Suggested by Sashiko.
- Reference the existing labeled nodes directly at the root level using
&sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of
redefining the entire node structure and redeclaring the labels. Suggested by Sashiko.
- Drop the #clock-cells property from sai1a and remove the reference to sai1a from
the clocks array in sai1b, relying strictly on the st,sync property to handle
internal synchronization.
arch/arm64/boot/dts/st/Makefile | 1 +
.../st/stm32mp257-engicam-microgea-rmm.dts | 319 ++++++++++++++++++
2 files changed, 320 insertions(+)
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile
index 63908113ae36..386eca593c54 100644
--- a/arch/arm64/boot/dts/st/Makefile
+++ b/arch/arm64/boot/dts/st/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_STM32) += \
stm32mp215f-dk.dtb \
stm32mp235f-dk.dtb \
+ stm32mp257-engicam-microgea-rmm.dtb \
stm32mp257f-dk.dtb \
stm32mp257f-ev1.dtb
diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
new file mode 100644
index 000000000000..0212c03aae1a
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ * Copyright (C) 2026 Engicam srl
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "stm32mp257-engicam-microgea.dtsi"
+
+/ {
+ model = "Engicam MicroGEA STM32MP257D RMM Board";
+ compatible = "engicam,microgea-stm32mp257-rmm",
+ "engicam,microgea-stm32mp257", "st,stm32mp257";
+
+ aliases {
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ serial0 = &usart2;
+ serial1 = &usart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <85>;
+ pwms = <&pwm2 0 100000 0>;
+ };
+
+ buzzer {
+ compatible = "pwm-beeper";
+ pwms = <&pwm4 0 1000000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ lcd-supply = <®_3v3>;
+ status = "disabled";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ status = "okay";
+ };
+
+ led-1 {
+ gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+
+ mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_ext_pwr: regulator-ext-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ext-pwr";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpiog 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP25-RMM";
+ widgets = "Headphone", "Headphone Jack",
+ "Microphone", "Microphone Jack";
+ routing = "Headphone Jack", "HP_OUT",
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ dais = <&sai1a_port &sai1b_port>;
+ status = "okay";
+ };
+};
+
+&arm_wdt {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5306";
+ reg = <0x38>;
+ interrupt-parent = <&gpiob>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-1 = <&i2c2_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&mclk>;
+
+ VDDA-supply = <®_3v3>;
+ VDDIO-supply = <®_3v3>;
+ VDDD-supply = <®_1v8>;
+
+ sgtl5000_port: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgtl5000_tx_endpoint: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sai1a_endpoint>;
+ frame-master = <&sgtl5000_tx_endpoint>;
+ bitclock-master = <&sgtl5000_tx_endpoint>;
+ };
+
+ sgtl5000_rx_endpoint: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&sai1b_endpoint>;
+ frame-master = <&sgtl5000_rx_endpoint>;
+ bitclock-master = <&sgtl5000_rx_endpoint>;
+ };
+ };
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1a_pins_a>, <&sai1b_pins_a>;
+ pinctrl-1 = <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>;
+ status = "okay";
+};
+
+&sai1a {
+ dma-names = "tx";
+ status = "okay";
+
+ sai1a_port: port {
+ sai1a_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_tx_endpoint>;
+ dai-format = "i2s";
+ mclk-fs = <512>;
+ };
+ };
+};
+
+&sai1b {
+ dma-names = "rx";
+ st,sync = <&sai1a 2>;
+ clocks = <&rcc CK_KER_SAI1>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai1b_port: port {
+ sai1b_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_rx_endpoint>;
+ dai-format = "i2s";
+ mclk-fs = <512>;
+ };
+ };
+};
+
+/* MicroSD */
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&scmi_v3v3>;
+ vqmmc-supply = <&scmi_vddio1>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_a>;
+ pinctrl-1 = <&spi1_sleep_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpioh 8 GPIO_ACTIVE_HIGH>, <&gpioh 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ display: display@0 {
+ compatible = "rocktech,rk050hr345-ct106a", "ilitek,ili9806e";
+ reg = <0>;
+ vdd-supply = <®_3v3>;
+ spi-max-frequency = <10000000>;
+ reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <<dc_out>;
+ };
+ };
+ };
+};
+
+&timers2 {
+ status = "okay";
+
+ pwm2: pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+};
+
+&timers4 {
+ status = "okay";
+
+ pwm4: pwm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ status = "okay";
+ };
+};
+
+&usart1 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-1 = <&usart1_idle_pins_b>;
+ pinctrl-2 = <&usart1_sleep_pins_b>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 11/14] arm64: dts: st: add usart1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the usart1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 46c5197dcd63..a72c458b2c6e 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -766,6 +766,39 @@ pins {
};
};
+ /omit-if-no-ref/
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 8, AF6)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('B', 10, ANALOG)>; /* USART1_RX */
+ };
+ };
+
/omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 10/14] arm64: dts: st: add spi1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the spi1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 62f898a55d45..46c5197dcd63 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -702,6 +702,30 @@ pins {
};
};
+ /omit-if-no-ref/
+ spi1_pins_a: spi1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 6, AF3)>, /* SPI1_SCK */
+ <STM32_PINMUX('I', 5, AF3)>; /* SPI1_MOSI */
+ drive-push-pull;
+ bias-disable;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 12, AF3)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ spi1_sleep_pins_a: spi1-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 6, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('I', 5, ANALOG)>, /* SPI1_MOSI */
+ <STM32_PINMUX('F', 12, ANALOG)>; /* SPI1_MISO */
+ };
+ };
+
/omit-if-no-ref/
spi3_pins_a: spi3-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 09/14] arm64: dts: st: add sdmmc2 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the sdmmc2 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index ab1e62cf2bfc..62f898a55d45 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -622,6 +622,86 @@ pins {
};
};
+ /omit-if-no-ref/
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, AF12)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, AF12)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 13, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 10, AF12)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('E', 9, AF12)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 6, AF12)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('E', 7, AF12)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 10, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('E', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
/omit-if-no-ref/
spi3_pins_a: spi3-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 08/14] arm64: dts: st: add sai1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the sai1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index eab8ebe71660..ab1e62cf2bfc 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -520,6 +520,51 @@ pins {
};
};
+ /omit-if-no-ref/
+ sai1a_pins_a: sai1a-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 9, AF3)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, AF3)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, AF3)>; /* SAI1_SCK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 11, AF3)>; /* SAI1_MCLK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, ANALOG)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 11, ANALOG)>; /* SAI1_MCLK_A */
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, AF4)>; /* SAI1_SD_B */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 06/14] arm64: dts: st: add can1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the can1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 05bd07a0a561..4be01a6574c7 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -331,6 +331,28 @@ pins {
};
};
+ /omit-if-no-ref/
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF7)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ m_can1_sleep_pins_a: m-can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
/omit-if-no-ref/
ospi_port1_clk_pins_a: ospi-port1-clk-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 07/14] arm64: dts: st: add pwm2/pwm4 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 4be01a6574c7..eab8ebe71660 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -433,6 +433,23 @@ pins {
};
};
+ /omit-if-no-ref/
+ pwm2_pins_a: pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 7, AF7)>; /* TIM2_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 7, ANALOG)>; /* TIM2_CH1 */
+ };
+ };
+
/omit-if-no-ref/
pwm3_pins_a: pwm3-0 {
pins {
@@ -450,6 +467,23 @@ pins {
};
};
+ /omit-if-no-ref/
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, AF7)>; /* TIM4_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>; /* TIM4_CH1 */
+ };
+ };
+
/omit-if-no-ref/
pwm8_pins_a: pwm8-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 05/14] arm64: dts: st: add ltdc pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the LTDC pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index db485b9ed904..05bd07a0a561 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -260,6 +260,77 @@ pins {
};
};
+ /omit-if-no-ref/
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('G', 2, AF13)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 1, AF13)>, /* LCD_VSYNC */
+ <STM32_PINMUX('C', 5, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 4, AF10)>, /* LCD_R0 */
+ <STM32_PINMUX('F', 7, AF13)>, /* LCD_R1 */
+ <STM32_PINMUX('C', 11, AF13)>, /* LCD_R2 */
+ <STM32_PINMUX('A', 1, AF11)>, /* LCD_R3 */
+ <STM32_PINMUX('B', 15, AF13)>, /* LCD_R4 */
+ <STM32_PINMUX('G', 3, AF13)>, /* LCD_R5 */
+ <STM32_PINMUX('A', 10, AF12)>, /* LCD_R6 */
+ <STM32_PINMUX('G', 7, AF13)>, /* LCD_R7 */
+ <STM32_PINMUX('F', 8, AF13)>, /* LCD_G0 */
+ <STM32_PINMUX('H', 5, AF10)>, /* LCD_G1 */
+ <STM32_PINMUX('C', 9, AF13)>, /* LCD_G2 */
+ <STM32_PINMUX('C', 10, AF13)>, /* LCD_G3 */
+ <STM32_PINMUX('A', 6, AF10)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 11, AF13)>, /* LCD_G5 */
+ <STM32_PINMUX('G', 12, AF13)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 9, AF12)>, /* LCD_G7 */
+ <STM32_PINMUX('F', 6, AF13)>, /* LCD_B0 */
+ <STM32_PINMUX('A', 3, AF11)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 15, AF13)>, /* LCD_B2 */
+ <STM32_PINMUX('I', 0, AF13)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 1, AF13)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 7, AF10)>, /* LCD_B5 */
+ <STM32_PINMUX('F', 5, AF13)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 4, AF13)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 1, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('G', 3, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('A', 10, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('H', 5, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('A', 6, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('F', 5, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 4, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
/omit-if-no-ref/
ospi_port1_clk_pins_a: ospi-port1-clk-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 04/14] arm64: dts: st: add i2c1 pins for stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add the i2c1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 456ece7f8ebc..db485b9ed904 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -203,6 +203,25 @@ pins {
};
};
+ /omit-if-no-ref/
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 13, AF9)>, /* I2C1_SCL */
+ <STM32_PINMUX('A', 2, AF10)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ i2c1_sleep_pins_a: i2c1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('A', 2, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
/omit-if-no-ref/
i2c2_pins_a: i2c2-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v3 03/14] arm64: dts: st: add CAN1 support on stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
The controller is compliant with ISO 11898-1: 2015 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification
version 1.0.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v2)
Changes in v2:
- Add resets property to dts CAN node. Suggested by Sashiko.
arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index eeceb086252b..7e82f01fdc10 100644
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -43,6 +43,22 @@ &optee {
};
&rifsc {
+ m_can1: can@402d0000 {
+ compatible = "bosch,m_can";
+ reg = <0x402d0000 0x400>, <0x40310000 0xd50>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&rcc CK_BUS_FDCAN>, <&rcc CK_KER_FDCAN>;
+ clock-names = "hclk", "cclk";
+ resets = <&rcc FDCAN_R>;
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ access-controllers = <&rifsc 56>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+ };
+
ethernet2: ethernet@482d0000 {
compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
reg = <0x482d0000 0x4000>;
--
2.43.0
^ permalink raw reply related
* [PATCH v3 02/14] arm64: dts: st: add SDMMC2 support on stm32mp25
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
The SDMMC2 controller supports SD cards, eMMC memories and SDIO devices.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
Changes in v3:
- Add power-domains property. Suggested by Sashiko.
arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 673fbc5632e6..faa1355948e8 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -1667,6 +1667,22 @@ sdmmc1: mmc@48220000 {
status = "disabled";
};
+ sdmmc2: mmc@48230000 {
+ compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00353180>;
+ reg = <0x48230000 0x400>, <0x44230800 0x8>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CK_KER_SDMMC2>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ access-controllers = <&rifsc 77>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+ };
+
ethernet1: ethernet@482c0000 {
compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
reg = <0x482c0000 0x4000>;
--
2.43.0
^ permalink raw reply related
* [PATCH v3 01/14] dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Conor Dooley, Alexandre Torgue, Amelie Delaunay,
Christophe Parant, Conor Dooley, Himanshu Bhavani,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260605062900.368376-1-dario.binacchi@amarulasolutions.com>
Add devicetree bindings for Engicam MicroGEA-STM32MP257-RMM board based
on the Engicam MicroGEA-STM32MP257 SoM (System-on-Module).
The use of an enum for a single element is justified by the future
addition of other boards based on the same SoM.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
(no changes since v2)
Changes in v2:
- Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32:
support Engicam MicroGEA-STM32MP257-RMM board"
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
index c6af3a46364f..c5ce81e3ce45 100644
--- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
@@ -203,6 +203,13 @@ properties:
- st,stm32mp257f-ev1
- const: st,stm32mp257
+ - description: Engicam MicroGEA STM32MP257 SoM based Boards
+ items:
+ - enum:
+ - engicam,microgea-stm32mp257-rmm
+ - const: engicam,microgea-stm32mp257
+ - const: st,stm32mp257
+
- description: ST STM32MP235 based Boards
items:
- enum:
--
2.43.0
^ permalink raw reply related
* [PATCH v3 00/14] arm64: support Engicam MicroGEA-STM32MP257-RMM board
From: Dario Binacchi @ 2026-06-05 6:27 UTC (permalink / raw)
To: linux-kernel
Cc: domenico.acri, francesco.utel, michael, linux-amarula,
Dario Binacchi, Alexandre Torgue, Amelie Delaunay,
Bjorn Andersson, Christophe Parant, Conor Dooley,
Dmitry Baryshkov, Eric Biggers, Florian Fainelli,
Geert Uytterhoeven, Himanshu Bhavani, Huang Shijie,
Krzysztof Kozlowski, Krzysztof Kozlowski, Luca Weiss,
Maxime Coquelin, Michal Simek, Rob Herring, Sven Peter,
devicetree, linux-arm-kernel, linux-stm32
This series adds initial support for the Engicam MicroGEA-STM32MP257-RMM
board based on the MicroGEA-STM32MP257 SoM.
The support includes device tree descriptions for both the SoM and the
carrier board, together with the required pinctrl definitions for the
peripherals used.
The series also updates the arm64 defconfig accordingly.
Changes in v3:
- Add power-domains property in the SDMMC2 node.
- Drop patch "arm64: defconfig: cleanup the defconfig"
Changes in v2:
- Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32:
support Engicam MicroGEA-STM32MP257-RMM board"
- Add resets property to dts CAN node. Suggested by Sashiko.
- Drop the clocks property from the sai1 node in stm32mp257-engicam-microgea-rmm.dts
to avoid overriding the peripheral bus clock reference defined in the base
SoC device tree. Suggested by Sashiko.
- Reference the existing labeled nodes directly at the root level using
&sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of
redefining the entire node structure and redeclaring the labels. Suggested by Sashiko.
- Drop the #clock-cells property from sai1a and remove the reference to sai1a from
the clocks array in sai1b, relying strictly on the st,sync property to handle
internal synchronization.
Dario Binacchi (14):
dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board
arm64: dts: st: add SDMMC2 support on stm32mp25
arm64: dts: st: add CAN1 support on stm32mp25
arm64: dts: st: add i2c1 pins for stm32mp25
arm64: dts: st: add ltdc pins for stm32mp25
arm64: dts: st: add can1 pins for stm32mp25
arm64: dts: st: add pwm2/pwm4 pins for stm32mp25
arm64: dts: st: add sai1 pins for stm32mp25
arm64: dts: st: add sdmmc2 pins for stm32mp25
arm64: dts: st: add spi1 pins for stm32mp25
arm64: dts: st: add usart1 pins for stm32mp25
arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM
arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board
arm64: defconfig: enable configs for Engicam MicroGEA-STM32MP257-RMM
.../devicetree/bindings/arm/stm32/stm32.yaml | 7 +
arch/arm64/boot/dts/st/Makefile | 1 +
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 328 ++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 +
arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 +
.../st/stm32mp257-engicam-microgea-rmm.dts | 319 +++++++++++++++++
.../dts/st/stm32mp257-engicam-microgea.dtsi | 64 ++++
arch/arm64/configs/defconfig | 4 +
8 files changed, 755 insertions(+)
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
--
2.43.0
base-commit: ba3e43a9e601636f5edb54e259a74f96ca3b8fd8
branch: stm32mp257d-microgea-v3
^ permalink raw reply
* Re: [PATCH v14 29/44] arm64: RMI: Runtime faulting of memory
From: Gavin Shan @ 2026-06-05 6:23 UTC (permalink / raw)
To: Steven Price, kvm, kvmarm
Cc: Catalin Marinas, Marc Zyngier, Will Deacon, James Morse,
Oliver Upton, Suzuki K Poulose, Zenghui Yu, linux-arm-kernel,
linux-kernel, Joey Gouly, Alexandru Elisei, Christoffer Dall,
Fuad Tabba, linux-coco, Ganapatrao Kulkarni, Shanker Donthineni,
Alper Gun, Aneesh Kumar K . V, Emi Kisanuki, Vishal Annapurve,
WeiLin.Chang, Lorenzo.Pieralisi2
In-Reply-To: <20260513131757.116630-30-steven.price@arm.com>
Hi Steve,
On 5/13/26 11:17 PM, Steven Price wrote:
> At runtime if the realm guest accesses memory which hasn't yet been
> mapped then KVM needs to either populate the region or fault the guest.
>
> For memory in the lower (protected) region of IPA a fresh page is
> provided to the RMM which will zero the contents. For memory in the
> upper (shared) region of IPA, the memory from the memslot is mapped
> into the realm VM non secure.
>
> Signed-off-by: Steven Price <steven.price@arm.com>
> ---
> Changes since v13:
> * Numerous changes due to rebasing.
> * Fix addr_range_desc() to encode the correct block size.
> Changes since v12:
> * Switch to RMM v2.0 range based APIs.
> Changes since v11:
> * Adapt to upstream changes.
> Changes since v10:
> * RME->RMI renaming.
> * Adapt to upstream gmem changes.
> Changes since v9:
> * Fix call to kvm_stage2_unmap_range() in kvm_free_stage2_pgd() to set
> may_block to avoid stall warnings.
> * Minor coding style fixes.
> Changes since v8:
> * Propagate the may_block flag.
> * Minor comments and coding style changes.
> Changes since v7:
> * Remove redundant WARN_ONs for realm_create_rtt_levels() - it will
> internally WARN when necessary.
> Changes since v6:
> * Handle PAGE_SIZE being larger than RMM granule size.
> * Some minor renaming following review comments.
> Changes since v5:
> * Reduce use of struct page in preparation for supporting the RMM
> having a different page size to the host.
> * Handle a race when delegating a page where another CPU has faulted on
> a the same page (and already delegated the physical page) but not yet
> mapped it. In this case simply return to the guest to either use the
> mapping from the other CPU (or refault if the race is lost).
> * The changes to populate_par_region() are moved into the previous
> patch where they belong.
> Changes since v4:
> * Code cleanup following review feedback.
> * Drop the PTE_SHARED bit when creating unprotected page table entries.
> This is now set by the RMM and the host has no control of it and the
> spec requires the bit to be set to zero.
> Changes since v2:
> * Avoid leaking memory if failing to map it in the realm.
> * Correctly mask RTT based on LPA2 flag (see rtt_get_phys()).
> * Adapt to changes in previous patches.
> ---
> arch/arm64/include/asm/kvm_emulate.h | 8 ++
> arch/arm64/include/asm/kvm_rmi.h | 12 ++
> arch/arm64/kvm/mmu.c | 128 ++++++++++++++++----
> arch/arm64/kvm/rmi.c | 173 +++++++++++++++++++++++++++
> 4 files changed, 301 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
> index 2e69fe494716..8b6f9d26b5d8 100644
> --- a/arch/arm64/include/asm/kvm_emulate.h
> +++ b/arch/arm64/include/asm/kvm_emulate.h
> @@ -712,6 +712,14 @@ static inline bool kvm_realm_is_created(struct kvm *kvm)
> return kvm_is_realm(kvm) && kvm_realm_state(kvm) != REALM_STATE_NONE;
> }
>
> +static inline gpa_t kvm_gpa_from_fault(struct kvm *kvm, phys_addr_t ipa)
> +{
> + if (!kvm_is_realm(kvm))
> + return ipa;
> +
> + return ipa & ~BIT(kvm->arch.realm.ia_bits - 1);
> +}
> +
> static inline bool vcpu_is_rec(const struct kvm_vcpu *vcpu)
> {
> return kvm_is_realm(vcpu->kvm);
> diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_rmi.h
> index a2b6bc412a22..b65cfec10dee 100644
> --- a/arch/arm64/include/asm/kvm_rmi.h
> +++ b/arch/arm64/include/asm/kvm_rmi.h
> @@ -6,6 +6,7 @@
> #ifndef __ASM_KVM_RMI_H
> #define __ASM_KVM_RMI_H
>
> +#include <asm/kvm_pgtable.h>
> #include <asm/rmi_smc.h>
>
> /**
> @@ -97,6 +98,17 @@ void kvm_realm_unmap_range(struct kvm *kvm,
> unsigned long size,
> bool unmap_private,
> bool may_block);
> +int realm_map_protected(struct kvm *kvm,
> + unsigned long base_ipa,
> + kvm_pfn_t pfn,
> + unsigned long size,
> + struct kvm_mmu_memory_cache *memcache);
> +int realm_map_non_secure(struct realm *realm,
> + unsigned long ipa,
> + kvm_pfn_t pfn,
> + unsigned long size,
> + enum kvm_pgtable_prot prot,
> + struct kvm_mmu_memory_cache *memcache);
>
> static inline bool kvm_realm_is_private_address(struct realm *realm,
> unsigned long addr)
> diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
> index ac2a0f0106b0..776ffe56d17e 100644
> --- a/arch/arm64/kvm/mmu.c
> +++ b/arch/arm64/kvm/mmu.c
> @@ -334,8 +334,15 @@ static void __unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64
>
> lockdep_assert_held_write(&kvm->mmu_lock);
> WARN_ON(size & ~PAGE_MASK);
> - WARN_ON(stage2_apply_range(mmu, start, end, KVM_PGT_FN(kvm_pgtable_stage2_unmap),
> - may_block));
> +
> + if (kvm_is_realm(kvm)) {
> + kvm_realm_unmap_range(kvm, start, size, !only_shared,
> + may_block);
> + } else {
> + WARN_ON(stage2_apply_range(mmu, start, end,
> + KVM_PGT_FN(kvm_pgtable_stage2_unmap),
> + may_block));
> + }
> }
>
> void kvm_stage2_unmap_range(struct kvm_s2_mmu *mmu, phys_addr_t start,
> @@ -358,7 +365,10 @@ static void stage2_flush_memslot(struct kvm *kvm,
> phys_addr_t addr = memslot->base_gfn << PAGE_SHIFT;
> phys_addr_t end = addr + PAGE_SIZE * memslot->npages;
>
> - kvm_stage2_flush_range(&kvm->arch.mmu, addr, end);
> + if (kvm_is_realm(kvm))
> + kvm_realm_unmap_range(kvm, addr, end - addr, false, true);
> + else
> + kvm_stage2_flush_range(&kvm->arch.mmu, addr, end);
> }
>
> /**
> @@ -1103,6 +1113,10 @@ void stage2_unmap_vm(struct kvm *kvm)
> struct kvm_memory_slot *memslot;
> int idx, bkt;
>
> + /* For realms this is handled by the RMM so nothing to do here */
> + if (kvm_is_realm(kvm))
> + return;
> +
> idx = srcu_read_lock(&kvm->srcu);
> mmap_read_lock(current->mm);
> write_lock(&kvm->mmu_lock);
> @@ -1528,6 +1542,29 @@ static bool kvm_vma_mte_allowed(struct vm_area_struct *vma)
> return vma->vm_flags & VM_MTE_ALLOWED;
> }
>
> +static int realm_map_ipa(struct kvm *kvm, phys_addr_t ipa,
> + kvm_pfn_t pfn, unsigned long map_size,
> + enum kvm_pgtable_prot prot,
> + struct kvm_mmu_memory_cache *memcache)
> +{
> + struct realm *realm = &kvm->arch.realm;
> +
> + /*
> + * Write permission is required for now even though it's possible to
> + * map unprotected pages (granules) as read-only. It's impossible to
> + * map protected pages (granules) as read-only.
> + */
> + if (WARN_ON(!(prot & KVM_PGTABLE_PROT_W)))
> + return -EFAULT;
> +
I'm a bit concerned with this. We don't have KVM_PGTABLE_PROT_W set in @prot
if the stage2 fault is raised due to memory read. With -EFAULT returned to VMM
(e.g. QEMU), the vCPU continuous execution is stopped and system won't be
working any more.
> + ipa = ALIGN_DOWN(ipa, PAGE_SIZE);
> + if (!kvm_realm_is_private_address(realm, ipa))
> + return realm_map_non_secure(realm, ipa, pfn, map_size, prot,
> + memcache);
> +
> + return realm_map_protected(kvm, ipa, pfn, map_size, memcache);
> +}
> +
> static bool kvm_vma_is_cacheable(struct vm_area_struct *vma)
> {
> switch (FIELD_GET(PTE_ATTRINDX_MASK, pgprot_val(vma->vm_page_prot))) {
> @@ -1604,27 +1641,52 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd)
> bool write_fault, exec_fault;
> enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_SHARED;
> enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R;
> - struct kvm_pgtable *pgt = s2fd->vcpu->arch.hw_mmu->pgt;
> + struct kvm_vcpu *vcpu = s2fd->vcpu;
> + struct kvm_pgtable *pgt = vcpu->arch.hw_mmu->pgt;
> + gpa_t gpa = kvm_gpa_from_fault(vcpu->kvm, s2fd->fault_ipa);
> unsigned long mmu_seq;
> struct page *page;
> - struct kvm *kvm = s2fd->vcpu->kvm;
> + struct kvm *kvm = vcpu->kvm;
> void *memcache;
> kvm_pfn_t pfn;
> gfn_t gfn;
> int ret;
>
> - memcache = get_mmu_memcache(s2fd->vcpu);
> - ret = topup_mmu_memcache(s2fd->vcpu, memcache);
> + if (kvm_is_realm(vcpu->kvm)) {
> + /* check for memory attribute mismatch */
> + bool is_priv_gfn = kvm_mem_is_private(kvm, gpa >> PAGE_SHIFT);
> + /*
> + * For Realms, the shared address is an alias of the private
> + * PA with the top bit set. Thus if the fault address matches
> + * the GPA then it is the private alias.
> + */
> + bool is_priv_fault = (gpa == s2fd->fault_ipa);
> +
> + if (is_priv_gfn != is_priv_fault) {
> + kvm_prepare_memory_fault_exit(vcpu, gpa, PAGE_SIZE,
> + kvm_is_write_fault(vcpu),
> + false,
> + is_priv_fault);
> + /*
> + * KVM_EXIT_MEMORY_FAULT requires an return code of
> + * -EFAULT, see the API documentation
> + */
> + return -EFAULT;
> + }
> + }
> +
> + memcache = get_mmu_memcache(vcpu);
> + ret = topup_mmu_memcache(vcpu, memcache);
> if (ret)
> return ret;
>
> if (s2fd->nested)
> gfn = kvm_s2_trans_output(s2fd->nested) >> PAGE_SHIFT;
> else
> - gfn = s2fd->fault_ipa >> PAGE_SHIFT;
> + gfn = gpa >> PAGE_SHIFT;
>
> - write_fault = kvm_is_write_fault(s2fd->vcpu);
> - exec_fault = kvm_vcpu_trap_is_exec_fault(s2fd->vcpu);
> + write_fault = kvm_is_write_fault(vcpu);
> + exec_fault = kvm_vcpu_trap_is_exec_fault(vcpu);
>
> VM_WARN_ON_ONCE(write_fault && exec_fault);
>
> @@ -1634,7 +1696,7 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd)
>
> ret = kvm_gmem_get_pfn(kvm, s2fd->memslot, gfn, &pfn, &page, NULL);
> if (ret) {
> - kvm_prepare_memory_fault_exit(s2fd->vcpu, s2fd->fault_ipa, PAGE_SIZE,
> + kvm_prepare_memory_fault_exit(vcpu, gpa, PAGE_SIZE,
> write_fault, exec_fault, false);
> return ret;
> }
> @@ -1654,14 +1716,20 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd)
> kvm_fault_lock(kvm);
> if (mmu_invalidate_retry(kvm, mmu_seq)) {
> ret = -EAGAIN;
> - goto out_unlock;
> + goto out_release_page;
> + }
> +
> + if (kvm_is_realm(kvm)) {
> + ret = realm_map_ipa(kvm, s2fd->fault_ipa, pfn,
> + PAGE_SIZE, KVM_PGTABLE_PROT_R | KVM_PGTABLE_PROT_W, memcache);
> + goto out_release_page;
> }
>
> ret = KVM_PGT_FN(kvm_pgtable_stage2_map)(pgt, s2fd->fault_ipa, PAGE_SIZE,
> __pfn_to_phys(pfn), prot,
> memcache, flags);
>
> -out_unlock:
> +out_release_page:
> kvm_release_faultin_page(kvm, page, !!ret, prot & KVM_PGTABLE_PROT_W);
> kvm_fault_unlock(kvm);
>
> @@ -1847,7 +1915,7 @@ static int kvm_s2_fault_get_vma_info(const struct kvm_s2_fault_desc *s2fd,
> * mapping size to ensure we find the right PFN and lay down the
> * mapping in the right place.
> */
> - s2vi->gfn = ALIGN_DOWN(s2fd->fault_ipa, s2vi->vma_pagesize) >> PAGE_SHIFT;
> + s2vi->gfn = kvm_gpa_from_fault(kvm, ALIGN_DOWN(s2fd->fault_ipa, s2vi->vma_pagesize)) >> PAGE_SHIFT;
>
> s2vi->mte_allowed = kvm_vma_mte_allowed(vma);
>
> @@ -2056,6 +2124,9 @@ static int kvm_s2_fault_map(const struct kvm_s2_fault_desc *s2fd,
> prot &= ~KVM_NV_GUEST_MAP_SZ;
> ret = KVM_PGT_FN(kvm_pgtable_stage2_relax_perms)(pgt, gfn_to_gpa(gfn),
> prot, flags);
> + } else if (kvm_is_realm(kvm)) {
> + ret = realm_map_ipa(kvm, s2fd->fault_ipa, pfn, mapping_size,
> + prot, memcache);
> } else {
> ret = KVM_PGT_FN(kvm_pgtable_stage2_map)(pgt, gfn_to_gpa(gfn), mapping_size,
> __pfn_to_phys(pfn), prot,
For the case kvm_is_realm(), need we adjust 's2fd->fault_ipa' for the sake of
huge pages. In kvm_s2_fault_map(), @gfn and @pfn may have been adjusted by
transparent_hugepage_adjust() to be aligned with huge page size. If the
adjustment happened in transparent_hugepage_adjust(), we need to align
s2fd->fault_ipa down to the huge page size either.
> @@ -2214,6 +2285,13 @@ int kvm_handle_guest_sea(struct kvm_vcpu *vcpu)
> return 0;
> }
>
> +static bool shared_ipa_fault(struct kvm *kvm, phys_addr_t fault_ipa)
> +{
> + gpa_t gpa = kvm_gpa_from_fault(kvm, fault_ipa);
> +
> + return (gpa != fault_ipa);
> +}
> +
> /**
> * kvm_handle_guest_abort - handles all 2nd stage aborts
> * @vcpu: the VCPU pointer
> @@ -2324,8 +2402,9 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
> nested = &nested_trans;
> }
>
> - gfn = ipa >> PAGE_SHIFT;
> + gfn = kvm_gpa_from_fault(vcpu->kvm, ipa) >> PAGE_SHIFT;
> memslot = gfn_to_memslot(vcpu->kvm, gfn);
> +
> hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
> write_fault = kvm_is_write_fault(vcpu);
> if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
> @@ -2368,7 +2447,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
> * of the page size.
> */
> ipa |= FAR_TO_FIPA_OFFSET(kvm_vcpu_get_hfar(vcpu));
> - ret = io_mem_abort(vcpu, ipa);
> + ret = io_mem_abort(vcpu, kvm_gpa_from_fault(vcpu->kvm, ipa));
> goto out_unlock;
> }
>
> @@ -2396,7 +2475,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
> !write_fault &&
> !kvm_vcpu_trap_is_exec_fault(vcpu));
>
> - if (kvm_slot_has_gmem(memslot))
> + if (kvm_slot_has_gmem(memslot) && !shared_ipa_fault(vcpu->kvm, fault_ipa))
> ret = gmem_abort(&s2fd);
> else
> ret = user_mem_abort(&s2fd);
> @@ -2433,6 +2512,10 @@ bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
> if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm))
> return false;
>
> + /* We don't support aging for Realms */
> + if (kvm_is_realm(kvm))
> + return true;
> +
> return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt,
> range->start << PAGE_SHIFT,
> size, true);
> @@ -2449,6 +2532,10 @@ bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
> if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm))
> return false;
>
> + /* We don't support aging for Realms */
> + if (kvm_is_realm(kvm))
> + return true;
> +
> return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt,
> range->start << PAGE_SHIFT,
> size, false);
> @@ -2628,10 +2715,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
> return -EFAULT;
>
> /*
> - * Only support guest_memfd backed memslots with mappable memory, since
> - * there aren't any CoCo VMs that support only private memory on arm64.
> + * Only support guest_memfd backed memslots with mappable memory,
> + * unless the guest is a CCA realm guest.
> */
> - if (kvm_slot_has_gmem(new) && !kvm_memslot_is_gmem_only(new))
> + if (kvm_slot_has_gmem(new) && !kvm_memslot_is_gmem_only(new) &&
> + !kvm_is_realm(kvm))
> return -EINVAL;
>
> hva = new->userspace_addr;
> diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c
> index cae29fd3353c..761b38a4071c 100644
> --- a/arch/arm64/kvm/rmi.c
> +++ b/arch/arm64/kvm/rmi.c
> @@ -597,6 +597,179 @@ static int realm_data_map_init(struct kvm *kvm, unsigned long ipa,
> return ret;
> }
>
> +static unsigned long addr_range_desc(unsigned long phys, unsigned long size)
> +{
> + unsigned long out = 0;
> +
> + switch (size) {
> + case P4D_SIZE:
> + out = 3 | (1 << 2);
> + break;
> + case PUD_SIZE:
> + out = 2 | (1 << 2);
> + break;
> + case PMD_SIZE:
> + out = 1 | (1 << 2);
> + break;
> + case PAGE_SIZE:
> + out = 0 | (1 << 2);
> + break;
> + default:
> + /*
> + * Only support mapping at the page level granulatity when
> + * it's an unusual length. This should get us back onto a larger
> + * block size for the subsequent mappings.
> + */
> + out = 0 | ((MIN(size >> PAGE_SHIFT, PTRS_PER_PTE - 1)) << 2);
> + break;
> + }
> +
> + WARN_ON(phys & ~PAGE_MASK);
> +
> + out |= phys & PAGE_MASK;
> +
> + return out;
> +}
> +
> +int realm_map_protected(struct kvm *kvm,
> + unsigned long ipa,
> + kvm_pfn_t pfn,
> + unsigned long map_size,
> + struct kvm_mmu_memory_cache *memcache)
> +{
> + struct realm *realm = &kvm->arch.realm;
> + phys_addr_t phys = __pfn_to_phys(pfn);
> + phys_addr_t base_phys = phys;
> + phys_addr_t rd = virt_to_phys(realm->rd);
> + unsigned long base_ipa = ipa;
> + unsigned long ipa_top = ipa + map_size;
> + int ret = 0;
> +
> + if (WARN_ON(!IS_ALIGNED(map_size, PAGE_SIZE) ||
> + !IS_ALIGNED(ipa, map_size)))
> + return -EINVAL;
> +
> + if (rmi_delegate_range(phys, map_size)) {
> + /*
> + * It's likely we raced with another VCPU on the same
> + * fault. Assume the other VCPU has handled the fault
> + * and return to the guest.
> + */
> + return 0;
> + }
> +
> + while (ipa < ipa_top) {
> + unsigned long flags = RMI_ADDR_TYPE_SINGLE;
> + unsigned long range_desc = addr_range_desc(phys, ipa_top - ipa);
> + unsigned long out_top;
> +
> + ret = rmi_rtt_data_map(rd, ipa, ipa_top, flags, range_desc,
> + &out_top);
> +
> + if (RMI_RETURN_STATUS(ret) == RMI_ERROR_RTT) {
> + /* Create missing RTTs and retry */
> + int level = RMI_RETURN_INDEX(ret);
> +
> + WARN_ON(level == KVM_PGTABLE_LAST_LEVEL);
> + ret = realm_create_rtt_levels(realm, ipa, level,
> + KVM_PGTABLE_LAST_LEVEL,
> + memcache);
> + if (ret)
> + goto err_undelegate;
> +
> + ret = rmi_rtt_data_map(rd, ipa, ipa_top, flags,
> + range_desc, &out_top);
> + }
> +
> + if (WARN_ON(ret))
> + goto err_undelegate;
> +
> + phys += out_top - ipa;
> + ipa = out_top;
> + }
> +
> + return 0;
> +
> +err_undelegate:
> + realm_unmap_private_range(kvm, base_ipa, ipa, true);
> + if (WARN_ON(rmi_undelegate_range(base_phys, map_size))) {
> + /* Page can't be returned to NS world so is lost */
> + get_page(phys_to_page(base_phys));
> + }
> + return -ENXIO;
> +}
> +
> +int realm_map_non_secure(struct realm *realm,
> + unsigned long ipa,
> + kvm_pfn_t pfn,
> + unsigned long size,
> + enum kvm_pgtable_prot prot,
> + struct kvm_mmu_memory_cache *memcache)
> +{
> + unsigned long attr, flags = 0;
> + phys_addr_t rd = virt_to_phys(realm->rd);
> + phys_addr_t phys = __pfn_to_phys(pfn);
> + unsigned long ipa_top = ipa + size;
> + int ret;
> +
> + if (WARN_ON(!IS_ALIGNED(size, PAGE_SIZE) ||
> + !IS_ALIGNED(ipa, size)))
> + return -EINVAL;
> +
> + switch (prot & (KVM_PGTABLE_PROT_DEVICE | KVM_PGTABLE_PROT_NORMAL_NC)) {
> + case KVM_PGTABLE_PROT_DEVICE | KVM_PGTABLE_PROT_NORMAL_NC:
> + return -EINVAL;
> + case KVM_PGTABLE_PROT_DEVICE:
> + attr = MT_S2_FWB_DEVICE_nGnRE;
> + break;
> + case KVM_PGTABLE_PROT_NORMAL_NC:
> + attr = MT_S2_FWB_NORMAL_NC;
> + break;
> + default:
> + attr = MT_S2_FWB_NORMAL;
> + }
> +
> + flags |= FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_MEMATTR, attr);
> +
> + if (prot & KVM_PGTABLE_PROT_R)
> + flags |= FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_S2AP, RMI_S2AP_DIRECT_READ);
> + if (prot & KVM_PGTABLE_PROT_W)
> + flags |= FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_S2AP, RMI_S2AP_DIRECT_WRITE);
> +
> + flags |= RMI_ADDR_TYPE_SINGLE;
> +
> + while (ipa < ipa_top) {
> + unsigned long range_desc = addr_range_desc(phys, ipa_top - ipa);
> + unsigned long out_top;
> +
> + ret = rmi_rtt_unprot_map(rd, ipa, ipa_top, flags, range_desc,
> + &out_top);
> +
> + if (RMI_RETURN_STATUS(ret) == RMI_ERROR_RTT) {
> + /* Create missing RTTs and retry */
> + int level = RMI_RETURN_INDEX(ret);
> +
> + WARN_ON(level == KVM_PGTABLE_LAST_LEVEL);
> + ret = realm_create_rtt_levels(realm, ipa, level,
> + KVM_PGTABLE_LAST_LEVEL,
> + memcache);
> + if (ret)
> + return ret;
> +
> + ret = rmi_rtt_unprot_map(rd, ipa, ipa_top, flags,
> + range_desc, &out_top);
> + }
> +
> + if (WARN_ON(ret))
> + return ret;
> +
> + phys += out_top - ipa;
> + ipa = out_top;
> + }
> +
> + return 0;
> +}
> +
> static int populate_region_cb(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
> struct page *src_page, void *opaque)
> {
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH v3 4/6] mm/vmalloc: Extend page table walk to support larger page_shift sizes and eliminate page table rewalk
From: Dev Jain @ 2026-06-05 6:02 UTC (permalink / raw)
To: Wen Jiang
Cc: linux-mm, linux-arm-kernel, catalin.marinas, will, akpm, urezki,
baohua, Xueyuan.chen21, rppt, david, ryan.roberts,
anshuman.khandual, ajd, linux-kernel, jiangwen6
In-Reply-To: <CAHKocdEfX3dgUr3O6q1WOe4PddN2=LKfX6Y5DfrfTwF9MM5J3w@mail.gmail.com>
On 28/05/26 9:09 am, Wen Jiang wrote:
> On Wed, 27 May 2026 at 13:59, Dev Jain <dev.jain@arm.com> wrote:
>>
>>
>>
>> On 22/05/26 11:01 am, Wen Jiang wrote:
>> From: "Barry Song (Xiaomi)" <baohua@kernel.org>
>>
>> vmap_pages_range_noflush_walk() (formerly vmap_small_pages_range_noflush())
>> provides a clean interface by taking struct page **pages and mapping them
>> via direct PTE iteration. This avoids the page table rewalk seen when
>> using vmap_range_noflush() for page_shift values other than PAGE_SHIFT.
>>
>> Extend it to support larger page_shift values, and add PMD- and
>> contiguous-PTE mappings as well. Rename it to vmap_pages_range_noflush_walk()
>> since it now handles more than just small pages.
>>
>> For vmalloc() allocations with VM_ALLOW_HUGE_VMAP, we no longer need to
>> iterate over pages one by one via vmap_range_noflush(), which would
>> otherwise lead to page table rewalk. The code is now unified with the
>> PAGE_SHIFT case by simply calling vmap_pages_range_noflush_walk().
>>
>> Signed-off-by: Barry Song (Xiaomi) <baohua@kernel.org>
>> Signed-off-by: Wen Jiang <jiangwen6@xiaomi.com>
>> Tested-by: Xueyuan Chen <xueyuan.chen21@gmail.com>
>> ---
>> mm/vmalloc.c | 71 +++++++++++++++++++++++++++++-----------------------
>> 1 file changed, 40 insertions(+), 31 deletions(-)
>>
>> diff --git a/mm/vmalloc.c b/mm/vmalloc.c
>> index 53fd4ee460ea4..deb764abc0571 100644
>> --- a/mm/vmalloc.c
>> +++ b/mm/vmalloc.c
>> @@ -543,8 +543,10 @@ void vunmap_range(unsigned long addr, unsigned long end)
>>
>> static int vmap_pages_pte_range(pmd_t *pmd, unsigned long addr,
>> unsigned long end, pgprot_t prot, struct page **pages, int *nr,
>> - pgtbl_mod_mask *mask)
>> + pgtbl_mod_mask *mask, unsigned int shift)
>> {
>> + unsigned long pfn, size;
>> + unsigned int steps;
>> int err = 0;
>> pte_t *pte;
>>
>> @@ -575,9 +577,10 @@ static int vmap_pages_pte_range(pmd_t *pmd, unsigned long addr,
>> break;
>> }
>>
>> - set_pte_at(&init_mm, addr, pte, mk_pte(page, prot));
>> - (*nr)++;
>> - } while (pte++, addr += PAGE_SIZE, addr != end);
>> + pfn = page_to_pfn(page);
>> + size = vmap_set_ptes(pte, addr, end, pfn, prot, shift);
>> + steps = PFN_DOWN(size);
>> + } while (pte += steps, *nr += steps, addr += size, addr != end);
>>
>> lazy_mmu_mode_disable();
>> *mask |= PGTBL_PTE_MODIFIED;
>> @@ -587,7 +590,7 @@ static int vmap_pages_pte_range(pmd_t *pmd, unsigned long addr,
>>
>> static int vmap_pages_pmd_range(pud_t *pud, unsigned long addr,
>> unsigned long end, pgprot_t prot, struct page **pages, int *nr,
>> - pgtbl_mod_mask *mask)
>> + pgtbl_mod_mask *mask, unsigned int shift)
>> {
>> pmd_t *pmd;
>> unsigned long next;
>>> @@ -597,7 +600,27 @@ static int vmap_pages_pmd_range(pud_t *pud, unsigned long addr,
>>> return -ENOMEM;
>>> do {
>>> next = pmd_addr_end(addr, end);
>>> - if (vmap_pages_pte_range(pmd, addr, next, prot, pages, nr, mask))
>>> +
>>> + if (shift == PMD_SHIFT) {
>>> + struct page *page = pages[*nr];
>>> + phys_addr_t phys_addr;
>>> +
>>> + if (WARN_ON(!page))
>>> + return -ENOMEM;
>>> + if (WARN_ON(!pfn_valid(page_to_pfn(page))))
>>> + return -EINVAL;
>>
>>
>> So I know these !page and !pfn_valid checks have been copied from vmap_pages_pte_range,
>> but do they mean anything?
>>
>> I think pfn_valid() makes sense in that someone may take a random VA/PA, convert it into a struct
>> page and pass to vmap layer. But I don't see how anyone would pass page == NULL? At the
>> very least, returning ENOMEM does not make sense because the pages are not being
>> allocated by vmap() but have already been allocated.
>
> Hi Dev,
>
> vmap() is EXPORT_SYMBOL with many callers across drivers, each
> constructing the pages array differently. The !page check guards
> against malformed arrays at this API boundary.
>
> The same -ENOMEM issue also exists in vmap_pages_pte_range().
> Should I fix both in this patchset or leave it as a separate cleanup?
>
>>
>>> +
>>> + phys_addr = page_to_phys(page);
>>> +
>>> + if (vmap_try_huge_pmd(pmd, addr, next, phys_addr, prot,
>>> + shift)) {
>>> + *mask |= PGTBL_PMD_MODIFIED;
>>> + *nr += 1 << (shift - PAGE_SHIFT);
>>> + continue;
>>> + }
>>> + }
>>> +
>>> + if (vmap_pages_pte_range(pmd, addr, next, prot, pages, nr, mask, shift))
>>> return -ENOMEM;
>>> } while (pmd++, addr = next, addr != end);
>>> return 0;
>>> @@ -605,7 +628,7 @@ static int vmap_pages_pmd_range(pud_t *pud, unsigned long addr,
>>>
>>> static int vmap_pages_pud_range(p4d_t *p4d, unsigned long addr,
>>> unsigned long end, pgprot_t prot, struct page **pages, int *nr,
>>> - pgtbl_mod_mask *mask)
>>> + pgtbl_mod_mask *mask, unsigned int shift)
>>> {
>>> pud_t *pud;
>>> unsigned long next;
>>> @@ -615,7 +638,7 @@ static int vmap_pages_pud_range(p4d_t *p4d, unsigned long addr,
>>> return -ENOMEM;
>>> do {
>>> next = pud_addr_end(addr, end);
>>> - if (vmap_pages_pmd_range(pud, addr, next, prot, pages, nr, mask))
>>> + if (vmap_pages_pmd_range(pud, addr, next, prot, pages, nr, mask, shift))
>>> return -ENOMEM;
>>> } while (pud++, addr = next, addr != end);
>>> return 0;
>>> @@ -623,7 +646,7 @@ static int vmap_pages_pud_range(p4d_t *p4d, unsigned long addr,
>>>
>>> static int vmap_pages_p4d_range(pgd_t *pgd, unsigned long addr,
>>> unsigned long end, pgprot_t prot, struct page **pages, int *nr,
>>> - pgtbl_mod_mask *mask)
>>> + pgtbl_mod_mask *mask, unsigned int shift)
>>> {
>>> p4d_t *p4d;
>>> unsigned long next;
>>> @@ -633,14 +656,14 @@ static int vmap_pages_p4d_range(pgd_t *pgd, unsigned long addr,
>>> return -ENOMEM;
>>> do {
>>> next = p4d_addr_end(addr, end);
>>> - if (vmap_pages_pud_range(p4d, addr, next, prot, pages, nr, mask))
>>> + if (vmap_pages_pud_range(p4d, addr, next, prot, pages, nr, mask, shift))
>>> return -ENOMEM;
>>> } while (p4d++, addr = next, addr != end);
>>> return 0;
>>> }
>>>
>>> -static int vmap_small_pages_range_noflush(unsigned long addr, unsigned long end,
>>> - pgprot_t prot, struct page **pages)
>>> +static int vmap_pages_range_noflush_walk(unsigned long addr, unsigned long end,
>>> + pgprot_t prot, struct page **pages, unsigned int shift)
>>> {
>>> unsigned long start = addr;
>>> pgd_t *pgd;
>>> @@ -655,7 +678,7 @@ static int vmap_small_pages_range_noflush(unsigned long addr, unsigned long end,
>>> next = pgd_addr_end(addr, end);
>>> if (pgd_bad(*pgd))
>>> mask |= PGTBL_PGD_MODIFIED;
>>> - err = vmap_pages_p4d_range(pgd, addr, next, prot, pages, &nr, &mask);
>>> + err = vmap_pages_p4d_range(pgd, addr, next, prot, pages, &nr, &mask, shift);
>>> if (err)
>>> break;
>>> } while (pgd++, addr = next, addr != end);
>>> @@ -678,27 +701,13 @@ static int vmap_small_pages_range_noflush(unsigned long addr, unsigned long end,
>>> int __vmap_pages_range_noflush(unsigned long addr, unsigned long end,
>>> pgprot_t prot, struct page **pages, unsigned int page_shift)
>>> {
>>> - unsigned int i, nr = (end - addr) >> PAGE_SHIFT;
>>> -
>>> WARN_ON(page_shift < PAGE_SHIFT);
>>>
>>> - if (!IS_ENABLED(CONFIG_HAVE_ARCH_HUGE_VMALLOC) ||
>>> - page_shift == PAGE_SHIFT)
>>> - return vmap_small_pages_range_noflush(addr, end, prot, pages);
>>> + if (!IS_ENABLED(CONFIG_HAVE_ARCH_HUGE_VMALLOC))
>>> + page_shift = PAGE_SHIFT;
>>>
>>> - for (i = 0; i < nr; i += 1U << (page_shift - PAGE_SHIFT)) {
>>> - int err;
>>> -
>>> - err = vmap_range_noflush(addr, addr + (1UL << page_shift),
>>> - page_to_phys(pages[i]), prot,
>>> - page_shift);
>>> - if (err)
>>> - return err;
>>> -
>>> - addr += 1UL << page_shift;
>>> - }
>>> -
>>> - return 0;
>>> + return vmap_pages_range_noflush_walk(addr, end, prot, pages,
>>> + min(page_shift, PMD_SHIFT));
>>
>>
>> We can easily extend to PUD huge mappings right? Not sure whether we
>> should keep everything symmetric to how vmap_range_noflush() operates
>> right now, since P4D mappings don't exist, but PUD looks worthwhile.
>>
>
> PUD mapping requires 1GB of contiguous physical memory, but the buddy
> allocator's MAX_PAGE_ORDER is 10 (4MB on 4K pages). So page_shift
> passed to vmap_pages_range_noflush_walk() never exceeds PMD_SHIFT.
Can we then just drop the min()? You can guard the try_huge_pmd with
shift >= PMD_SHIFT - the walker has the necessary ingredients to work
with a shift > PMD_SHIFT, so let us not confuse by this min() truncation.
>
> Thanks,
> Wen
>>> }
>>>
>>> int vmap_pages_range_noflush(unsigned long addr, unsigned long end,
>>
^ permalink raw reply
* Re: [PATCH v2] KVM/arm64: vgic-its: Make ABI commit helpers return void
From: Oliver Upton @ 2026-06-05 6:01 UTC (permalink / raw)
To: Jackie Liu; +Cc: maz, linux-arm-kernel, yuzenghui, will, kvmarm
In-Reply-To: <20260604075147.53299-1-liu.yun@linux.dev>
On Thu, Jun 04, 2026 at 03:51:47PM +0800, Jackie Liu wrote:
> From: Jackie Liu <liuyun01@kylinos.cn>
>
> The return values of vgic_its_set_abi() and vgic_its_commit_v0() are always
> 0 and do not carry useful error information. Simplify by changing them to
> void.
>
> Suggested-by: Oliver Upton <oupton@kernel.org>
> Signed-off-by: Jackie Liu <liuyun01@kylinos.cn>
Reviewed-by: Oliver Upton <oupton@kernel.org>
Thanks,
Oliver
> ---
> arch/arm64/kvm/vgic/vgic-its.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c
> index 1d7e5d560af4..ca48b34dec20 100644
> --- a/arch/arm64/kvm/vgic/vgic-its.c
> +++ b/arch/arm64/kvm/vgic/vgic-its.c
> @@ -27,7 +27,7 @@ static struct kvm_device_ops kvm_arm_vgic_its_ops;
>
> static int vgic_its_save_tables_v0(struct vgic_its *its);
> static int vgic_its_restore_tables_v0(struct vgic_its *its);
> -static int vgic_its_commit_v0(struct vgic_its *its);
> +static void vgic_its_commit_v0(struct vgic_its *its);
> static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
> struct kvm_vcpu *filter_vcpu, bool needs_inv);
>
> @@ -168,7 +168,7 @@ struct vgic_its_abi {
> int ite_esz;
> int (*save_tables)(struct vgic_its *its);
> int (*restore_tables)(struct vgic_its *its);
> - int (*commit)(struct vgic_its *its);
> + void (*commit)(struct vgic_its *its);
> };
>
> #define ABI_0_ESZ 8
> @@ -192,13 +192,13 @@ inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
> return &its_table_abi_versions[its->abi_rev];
> }
>
> -static int vgic_its_set_abi(struct vgic_its *its, u32 rev)
> +static void vgic_its_set_abi(struct vgic_its *its, u32 rev)
> {
> const struct vgic_its_abi *abi;
>
> its->abi_rev = rev;
> abi = vgic_its_get_abi(its);
> - return abi->commit(its);
> + abi->commit(its);
> }
>
> /*
> @@ -472,7 +472,8 @@ static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
>
> if (rev >= NR_ITS_ABIS)
> return -EINVAL;
> - return vgic_its_set_abi(its, rev);
> + vgic_its_set_abi(its, rev);
> + return 0;
> }
>
> static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
> @@ -1888,14 +1889,11 @@ static int vgic_its_create(struct kvm_device *dev, u32 type)
> its->baser_coll_table = INITIAL_BASER_VALUE |
> ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
> dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
> -
> dev->private = its;
>
> - ret = vgic_its_set_abi(its, NR_ITS_ABIS - 1);
> -
> + vgic_its_set_abi(its, NR_ITS_ABIS - 1);
> mutex_unlock(&dev->kvm->arch.config_lock);
> -
> - return ret;
> + return 0;
> }
>
> static void vgic_its_destroy(struct kvm_device *kvm_dev)
> @@ -2610,7 +2608,7 @@ static int vgic_its_restore_tables_v0(struct vgic_its *its)
> return ret;
> }
>
> -static int vgic_its_commit_v0(struct vgic_its *its)
> +static void vgic_its_commit_v0(struct vgic_its *its)
> {
> const struct vgic_its_abi *abi;
>
> @@ -2623,7 +2621,6 @@ static int vgic_its_commit_v0(struct vgic_its *its)
>
> its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
> << GITS_BASER_ENTRY_SIZE_SHIFT);
> - return 0;
> }
>
> static void vgic_its_reset(struct kvm *kvm, struct vgic_its *its)
> --
> 2.54.0
>
>
^ permalink raw reply
* Re: [PATCH] KVM: arm64: vgic: Check the interrupt is still ours before migrating it
From: Oliver Upton @ 2026-06-05 6:00 UTC (permalink / raw)
To: Hyunwoo Kim
Cc: maz, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will, Sascha.Bischoff, jic23, timothy.hayes,
eric.auger, christoffer.dall, andre.przywara, linux-arm-kernel,
kvmarm
In-Reply-To: <aiHnI1mu6SGQrgnz@v4bel>
On Fri, Jun 05, 2026 at 05:59:15AM +0900, Hyunwoo Kim wrote:
> vgic_prune_ap_list() drops both ap_list_lock and irq_lock while migrating
> an interrupt to another vCPU. After reacquiring the locks it only checks
> that the affinity is unchanged (target_vcpu == vgic_target_oracle(irq))
> before moving the interrupt, which assumes that an interrupt whose affinity
> is preserved is still queued on this vCPU's ap_list.
>
> That assumption no longer holds if the interrupt is taken off the ap_list
> while the locks are dropped. vgic_flush_pending_lpis() removes the
> interrupt from the list and sets irq->vcpu to NULL, but leaves
> enabled/pending/target_vcpu untouched. As the interrupt is still enabled
> and pending, vgic_target_oracle() returns the same target_vcpu, so the
> affinity check passes and list_del() is run a second time on an entry that
> has already been removed.
>
> Also check that the interrupt is still assigned to this vCPU
> (irq->vcpu == vcpu) before moving it.
>
> Fixes: 0919e84c0fc1 ("KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework")
> Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
Looking at this and the other VGIC patch you sent (which should've been
a combined series), are you trying to deal with a vCPU writing to
another vCPU's redistributor? I.e. vCPU B setting GICR_CTLR.EnableLPIs=0
behind the back of vCPU A?
That is extremely relevant information as the off-the-cuff reaction is
that no race exists. But since the GIC architecture is awesome and
allows for this sort of insanity, it obviously does....
Anyway, for LPIs resident on a particular RD, there's zero expectation
that the pending state is preserved when EnableLPIs=0. So I'd rather
vgic_flush_pending_lpis() just invalidate the pending state.
Beyond that, I see two other fixes for lifetime issues around the
vgic_irq in the middle of migration. I'd like to see explicit RCU
protection around the release && reacquire of the ap_list_lock rather
than depending on the precondition that IRQs are disabled.
Then vgic_flush_pending_lpis() should leave IRQs intact that are pending
a migration (e.g. irq->vcpu != vgic_target_oracle()) as the only expectation
we need to uphold is that LPIs resident on the RD have the pending state cleared.
Although I think we could benefit from the wetware implementation of the
GIC giving this a once over too. Any thoughts Marc?
Thanks,
Oliver
> ---
> arch/arm64/kvm/vgic/vgic.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index 1e9fe8764584..18b280de9a29 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -818,15 +818,16 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
> raw_spin_lock(&irq->irq_lock);
>
> /*
> - * If the affinity has been preserved, move the
> - * interrupt around. Otherwise, it means things have
> - * changed while the interrupt was unlocked, and we
> - * need to replay this.
> + * If the interrupt is still ours and its affinity has
> + * been preserved, move it around. Otherwise, it means
> + * things have changed while the interrupt was unlocked
> + * (it may even have been taken off the list with its
> + * affinity left untouched), and we need to replay this.
> *
> * In all cases, we cannot trust the list not to have
> * changed, so we restart from the beginning.
> */
> - if (target_vcpu == vgic_target_oracle(irq)) {
> + if (irq->vcpu == vcpu && target_vcpu == vgic_target_oracle(irq)) {
> struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu;
>
> list_del(&irq->ap_list);
> --
> 2.43.0
>
^ permalink raw reply
* [PATCH v4 2/2] ARM: dts: aspeed: add 'resets' to video node
From: Haiyue Wang @ 2026-06-05 5:52 UTC (permalink / raw)
To: linux-clk, devicetree, linux-aspeed
Cc: Haiyue Wang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Hans Verkuil, Jammy Huang,
moderated list:ARM/ASPEED MACHINE SUPPORT, open list
In-Reply-To: <20260605055712.118501-1-haiyuewa@163.com>
The aspeed video (be compatible for ast2400, ast2500, ast2600) now needs
the reset DTS handle specified, otherwise it will fail to load:
[ 4.809494] aspeed-video 1e700000.video: irq 57
[ 4.809977] aspeed-video 1e700000.video: Unable to get reset
[ 4.810341] aspeed-video 1e700000.video: probe with driver aspeed-video failed with error -2
Fixes: e83f8dd668ea ("media: aspeed: Fix dram hang at res-change")
Signed-off-by: Haiyue Wang <haiyuewa@163.com>
---
arch/arm/boot/dts/aspeed/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 1 +
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi
index c3d4d916c69b..1547e28d77e2 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi
@@ -242,6 +242,7 @@ video: video@1e700000 {
<&syscon ASPEED_CLK_GATE_ECLK>;
clock-names = "vclk", "eclk";
interrupts = <7>;
+ resets = <&syscon ASPEED_RESET_VIDEO>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
index 39500bdb4747..793570ca2518 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi
@@ -296,6 +296,7 @@ video: video@1e700000 {
<&syscon ASPEED_CLK_GATE_ECLK>;
clock-names = "vclk", "eclk";
interrupts = <7>;
+ resets = <&syscon ASPEED_RESET_VIDEO>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 189bc3bbb47c..3adf48987a17 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -428,6 +428,7 @@ video: video@1e700000 {
<&syscon ASPEED_CLK_GATE_ECLK>;
clock-names = "vclk", "eclk";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon ASPEED_RESET_VIDEO>;
status = "disabled";
};
--
2.54.0
^ permalink raw reply related
* Re: [PATCH] KVM: arm64: vgic: Use list_del_rcu() when flushing pending LPIs
From: Oliver Upton @ 2026-06-05 5:47 UTC (permalink / raw)
To: Hyunwoo Kim
Cc: maz, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will, Sascha.Bischoff, jic23, linux-arm-kernel,
kvmarm
In-Reply-To: <aiHrGM1f8czcUby4@v4bel>
Hi Hyunwoo,
On Fri, Jun 05, 2026 at 06:16:08AM +0900, Hyunwoo Kim wrote:
> vgic_v3_fold_lr_state() walks the ap_list from last_lr_irq without holding
> the ap_list_lock, relying on vgic_irq being freed via kfree_rcu() and on
> interrupts being disabled. vgic_flush_pending_lpis() removes entries with
> list_del(), which clobbers a node's next pointer, so when another vCPU
> disables LPIs via GICR_CTLR the walk can follow the clobbered next pointer
> from a removed node, or from the node that last_lr_irq points to.
>
> Remove entries with list_del_rcu() so that the next pointer stays valid
> until the walk completes.
>
> Fixes: 3cfd59f81e0f ("KVM: arm64: GICv3: Handle LR overflow when EOImode==0")
> Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
Changing only one of the writer paths to use the rculist helpers does
not make the ap_list an rculist. Insertions are not RCU-safe, nor are
deleations from vgic_prune_ap_list().
And TBH, the real bug here is the fact that vgic_v3_fold_lr_state() isn't
taking the ap_list_lock.
Thanks,
Oliver
> ---
> arch/arm64/kvm/vgic/vgic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index 1e9fe8764584d..73efc0f95bfb1 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -204,7 +204,7 @@ void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu)
> list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
> if (irq_is_lpi(vcpu->kvm, irq->intid)) {
> raw_spin_lock(&irq->irq_lock);
> - list_del(&irq->ap_list);
> + list_del_rcu(&irq->ap_list);
> irq->vcpu = NULL;
> raw_spin_unlock(&irq->irq_lock);
> deleted |= vgic_put_irq_norelease(vcpu->kvm, irq);
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH] KVM: arm64: Reallocate the nested_mmus array under the mmu_lock
From: Hyunwoo Kim @ 2026-06-05 5:35 UTC (permalink / raw)
To: Oliver Upton
Cc: maz, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will, christoffer.dall, linux-arm-kernel, kvmarm,
imv4bel
In-Reply-To: <aiH7xKnprU9bUap5@kernel.org>
On Thu, Jun 04, 2026 at 03:27:16PM -0700, Oliver Upton wrote:
> Hi,
>
> The shortlog is very confusing, since "allocate behind $LOCK" is usually
> something alarming. Maybe instead:
>
> KVM: arm64: Reassign nested_mmus array behind mmu_lock
heh, that's confusing indeed. I'll change it that way.
>
> On Fri, Jun 05, 2026 at 03:30:00AM +0900, Hyunwoo Kim wrote:
> > Code that walks kvm->arch.nested_mmus[] holds kvm->mmu_lock. By contrast,
> > kvm_vcpu_init_nested() reallocates the array and frees the old buffer while
> > holding only kvm->arch.config_lock, so a walker can reference the freed
> > array.
>
> It wouldn't hurt to share slightly more information here. Are you
> dealing with a concurrent MMU notifier?
Yes. The MMU notifier path also walks nested_mmus[] under mmu_lock.
kvm_vcpu_init_nested() holds only config_lock, so if a notifier fires
during vCPU init, it races with the array realloc and free.
Here's the reworked changelog. Should I send v2?
kvm->arch.nested_mmus[] is walked under kvm->mmu_lock, including from the
MMU notifier path (kvm_unmap_gfn_range() -> kvm_nested_s2_unmap()), which
can run at any time. kvm_vcpu_init_nested() reallocates the array and frees
the old buffer while holding only kvm->arch.config_lock, so such a walker
can reference the freed array.
Allocate the new array outside of mmu_lock, as the allocation can sleep.
Under the lock, copy the existing entries, fix up the back pointers and
reassign the array. Free the old buffer after dropping the lock, as
kvfree() can sleep as well.
>
> > Allocate the new array outside the lock, as the allocation can sleep, and
> > do only the copy and the pointer swap under the mmu_lock. After the swap no
> > walker can reach the old buffer, so free it once the lock has been
> > released.
> >
> > Fixes: 4f128f8e1aaac ("KVM: arm64: nv: Support multiple nested Stage-2 mmu structures")
> > Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
>
> The diff itself LGTM
>
> Reviewed-by: Oliver Upton <oupton@kernel.org>
Thanks for the review.
>
> Thanks,
> Oliver
>
> > ---
> > arch/arm64/kvm/nested.c | 33 ++++++++++++++++++++-------------
> > 1 file changed, 20 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> > index 38f672e940878..6f7bc9a9992e0 100644
> > --- a/arch/arm64/kvm/nested.c
> > +++ b/arch/arm64/kvm/nested.c
> > @@ -89,21 +89,28 @@ int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu)
> > * again, and there is no reason to affect the whole VM for this.
> > */
> > num_mmus = atomic_read(&kvm->online_vcpus) * S2_MMU_PER_VCPU;
> > - tmp = kvrealloc(kvm->arch.nested_mmus,
> > - size_mul(sizeof(*kvm->arch.nested_mmus), num_mmus),
> > - GFP_KERNEL_ACCOUNT | __GFP_ZERO);
> > - if (!tmp)
> > - return -ENOMEM;
> >
> > - swap(kvm->arch.nested_mmus, tmp);
> > + if (num_mmus > kvm->arch.nested_mmus_size) {
> > + tmp = kvcalloc(num_mmus, sizeof(*tmp), GFP_KERNEL_ACCOUNT);
> > + if (!tmp)
> > + return -ENOMEM;
> >
> > - /*
> > - * If we went through a realocation, adjust the MMU back-pointers in
> > - * the previously initialised kvm_pgtable structures.
> > - */
> > - if (kvm->arch.nested_mmus != tmp)
> > - for (int i = 0; i < kvm->arch.nested_mmus_size; i++)
> > - kvm->arch.nested_mmus[i].pgt->mmu = &kvm->arch.nested_mmus[i];
> > + write_lock(&kvm->mmu_lock);
> > +
> > + if (kvm->arch.nested_mmus_size) {
> > + memcpy(tmp, kvm->arch.nested_mmus,
> > + size_mul(sizeof(*tmp), kvm->arch.nested_mmus_size));
> > +
> > + for (int i = 0; i < kvm->arch.nested_mmus_size; i++)
> > + tmp[i].pgt->mmu = &tmp[i];
> > + }
> > +
> > + swap(kvm->arch.nested_mmus, tmp);
> > +
> > + write_unlock(&kvm->mmu_lock);
> > +
> > + kvfree(tmp);
> > + }
> >
> > for (int i = kvm->arch.nested_mmus_size; !ret && i < num_mmus; i++)
> > ret = init_nested_s2_mmu(kvm, &kvm->arch.nested_mmus[i]);
> > --
> > 2.43.0
> >
Best regards,
Hyunwoo Kim
^ permalink raw reply
* Re: [PATCH v2 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control
From: Rob Herring (Arm) @ 2026-06-05 4:40 UTC (permalink / raw)
To: joakim.zhang
Cc: krzk+dt, cix-kernel-upstream, sboyd, conor+dt, mturquette,
bmasney, devicetree, p.zabel, gary.yang, linux-kernel,
linux-arm-kernel, linux-clk
In-Reply-To: <20260605032225.523669-2-joakim.zhang@cixtech.com>
On Fri, 05 Jun 2026 11:22:21 +0800, joakim.zhang@cixtech.com wrote:
> From: Joakim Zhang <joakim.zhang@cixtech.com>
>
> The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related clock, reset
> and control registers in a dedicated CRU block. Software reset lines are
> exposed on the syscon parent via #reset-cells, following the same model
> as the existing Sky1 FCH and S5 system control bindings.
>
> Add the cix,sky1-audss-system-control compatible to
> cix,sky1-system-control.yaml for the MFD/syscon parent node, and define
> AUDSS software reset indices in
> include/dt-bindings/reset/cix,sky1-audss-system-control.h for I2S, HDA,
> DMAC, mailbox, watchdog and timer blocks.
>
> Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com>
> ---
> .../soc/cix/cix,sky1-system-control.yaml | 39 ++++++++++++++++---
> .../reset/cix,sky1-audss-system-control.h | 27 +++++++++++++
> 2 files changed, 61 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml: Unresolvable reference: /schemas/clock/cix,sky1-audss-clock.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: system-controller@7110000 (cix,sky1-audss-system-control): clock-controller: False schema does not allow {'compatible': ['cix,sky1-audss-clock'], 'power-domains': [[4294967295, 0]], '#clock-cells': 1, 'clocks': [[4294967295, 0], [4294967295, 1], [4294967295, 2], [4294967295, 3], [4294967295, 4], [4294967295, 5]], 'clock-names': ['audio_clk0', 'audio_clk1', 'audio_clk2', 'audio_clk3', 'audio_clk4', 'audio_clk5'], 'resets': [[4294967295, 0]]}
from schema $id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.example.dtb: /example-1/system-controller@7110000/clock-controller: failed to match any schema with compatible: ['cix,sky1-audss-clock']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260605032225.523669-2-joakim.zhang@cixtech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH] phy: freescale: imx8qm-lvds-phy: Fix missing pm_runtime_disable() on probe error path
From: Liu Ying @ 2026-06-05 3:44 UTC (permalink / raw)
To: Felix Gu
Cc: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-phy, imx,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260604-lvds-v1-1-b8e1ff1bdee7@gmail.com>
On Thu, Jun 04, 2026 at 10:39:07PM +0800, Felix Gu wrote:
> If mixel_lvds_phy_reset() fails in probe after pm_runtime_enable(),
> the function returns directly without calling pm_runtime_disable(),
> leaving runtime PM permanently enabled for the device.
>
> Fix this by using devm_pm_runtime_enable() so that cleanup is
> automatic on any probe failure or driver unbind. This also allows
> removing the manual err label and the .remove callback.
>
> Fixes: 06ff622d61d2 ("phy: freescale: Add i.MX8qm Mixel LVDS PHY support")
> Signed-off-by: Felix Gu <ustc.gu@gmail.com>
> ---
> drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c | 24 +++++++-----------------
> 1 file changed, 7 insertions(+), 17 deletions(-)
It would be good if the patch subject prefix can be changed to
"phy: freescale: phy-fsl-imx8qm-lvds-phy:".
With that done:
Acked-by: Liu Ying <victor.liu@nxp.com>
--
Regards,
Liu Ying
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