* Re: [PATCH] KVM: arm64: Set a linux errno on SMCCC error in kvm_call_hyp_nvhe()
From: Will Deacon @ 2026-06-05 11:23 UTC (permalink / raw)
To: Vincent Donnefort
Cc: maz, oliver.upton, joey.gouly, suzuki.poulose, yuzenghui,
catalin.marinas, linux-arm-kernel, kvmarm, kernel-team, tabba
In-Reply-To: <20260603110312.2909844-1-vdonnefort@google.com>
On Wed, Jun 03, 2026 at 12:03:12PM +0100, Vincent Donnefort wrote:
> If the HVC called in kvm_call_hyp_nvhe() fails with an SMCCC error code,
> we WARN. However, the returned value isn't initialized and the caller
> might get garbage or 0 which is likely to be interpreted as success.
>
> Set a default -EPERM error value, ensuring all callers get the message
> when SMCCC calls fail.
>
> Signed-off-by: Vincent Donnefort <vdonnefort@google.com>
>
> ---
>
> I have encountered this issue while working on a follow-up contribution to the
> hypervisor tracing. In that case it completely crashed the kernel because
> IS_ERR() failed on that res.a1 value.
>
> Now, if it makes that function more robust, I do not believe it is fixing any
> existing bug which is why I haven't added a "Fixes:" tag.
>
> In case we want to stick one, here it is:
>
> Fixes: 054698316d87 ("KVM: arm64: nVHE: Migrate hyp interface to SMCCC")
>
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index a49042bfa801..6b8fd494792c 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -1273,13 +1273,14 @@ void kvm_arm_resume_guest(struct kvm *kvm);
> #define vcpu_has_run_once(vcpu) (!!READ_ONCE((vcpu)->pid))
>
> #ifndef __KVM_NVHE_HYPERVISOR__
> -#define kvm_call_hyp_nvhe(f, ...) \
> +#define kvm_call_hyp_nvhe(f, ...) \
> ({ \
> struct arm_smccc_res res; \
> \
> arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
> ##__VA_ARGS__, &res); \
> - WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
> + if (WARN_ON(res.a0 != SMCCC_RET_SUCCESS)) \
> + res.a1 = -EPERM; \
> \
> res.a1; \
> })
Looks like the only error code we return to the host is
SMCCC_RET_NOT_SUPPORTED, so maybe -EOPNOTSUPP would be more appropriate?
Either way:
Acked-by: Will Deacon <will@kernel.org>
Will
^ permalink raw reply
* Re: [PATCH v14 29/44] arm64: RMI: Runtime faulting of memory
From: Gavin Shan @ 2026-06-05 11:20 UTC (permalink / raw)
To: Steven Price, kvm, kvmarm
Cc: Catalin Marinas, Marc Zyngier, Will Deacon, James Morse,
Oliver Upton, Suzuki K Poulose, Zenghui Yu, linux-arm-kernel,
linux-kernel, Joey Gouly, Alexandru Elisei, Christoffer Dall,
Fuad Tabba, linux-coco, Ganapatrao Kulkarni, Shanker Donthineni,
Alper Gun, Aneesh Kumar K . V, Emi Kisanuki, Vishal Annapurve,
WeiLin.Chang, Lorenzo.Pieralisi2
In-Reply-To: <20260513131757.116630-30-steven.price@arm.com>
Hi Steve,
On 5/13/26 11:17 PM, Steven Price wrote:
> At runtime if the realm guest accesses memory which hasn't yet been
> mapped then KVM needs to either populate the region or fault the guest.
>
> For memory in the lower (protected) region of IPA a fresh page is
> provided to the RMM which will zero the contents. For memory in the
> upper (shared) region of IPA, the memory from the memslot is mapped
> into the realm VM non secure.
>
> Signed-off-by: Steven Price <steven.price@arm.com>
> ---
> Changes since v13:
> * Numerous changes due to rebasing.
> * Fix addr_range_desc() to encode the correct block size.
> Changes since v12:
> * Switch to RMM v2.0 range based APIs.
> Changes since v11:
> * Adapt to upstream changes.
> Changes since v10:
> * RME->RMI renaming.
> * Adapt to upstream gmem changes.
> Changes since v9:
> * Fix call to kvm_stage2_unmap_range() in kvm_free_stage2_pgd() to set
> may_block to avoid stall warnings.
> * Minor coding style fixes.
> Changes since v8:
> * Propagate the may_block flag.
> * Minor comments and coding style changes.
> Changes since v7:
> * Remove redundant WARN_ONs for realm_create_rtt_levels() - it will
> internally WARN when necessary.
> Changes since v6:
> * Handle PAGE_SIZE being larger than RMM granule size.
> * Some minor renaming following review comments.
> Changes since v5:
> * Reduce use of struct page in preparation for supporting the RMM
> having a different page size to the host.
> * Handle a race when delegating a page where another CPU has faulted on
> a the same page (and already delegated the physical page) but not yet
> mapped it. In this case simply return to the guest to either use the
> mapping from the other CPU (or refault if the race is lost).
> * The changes to populate_par_region() are moved into the previous
> patch where they belong.
> Changes since v4:
> * Code cleanup following review feedback.
> * Drop the PTE_SHARED bit when creating unprotected page table entries.
> This is now set by the RMM and the host has no control of it and the
> spec requires the bit to be set to zero.
> Changes since v2:
> * Avoid leaking memory if failing to map it in the realm.
> * Correctly mask RTT based on LPA2 flag (see rtt_get_phys()).
> * Adapt to changes in previous patches.
> ---
> arch/arm64/include/asm/kvm_emulate.h | 8 ++
> arch/arm64/include/asm/kvm_rmi.h | 12 ++
> arch/arm64/kvm/mmu.c | 128 ++++++++++++++++----
> arch/arm64/kvm/rmi.c | 173 +++++++++++++++++++++++++++
> 4 files changed, 301 insertions(+), 20 deletions(-)
>
[...]
> @@ -1604,27 +1641,52 @@ static int gmem_abort(const struct kvm_s2_fault_desc *s2fd)
> bool write_fault, exec_fault;
> enum kvm_pgtable_walk_flags flags = KVM_PGTABLE_WALK_SHARED;
> enum kvm_pgtable_prot prot = KVM_PGTABLE_PROT_R;
> - struct kvm_pgtable *pgt = s2fd->vcpu->arch.hw_mmu->pgt;
> + struct kvm_vcpu *vcpu = s2fd->vcpu;
> + struct kvm_pgtable *pgt = vcpu->arch.hw_mmu->pgt;
> + gpa_t gpa = kvm_gpa_from_fault(vcpu->kvm, s2fd->fault_ipa);
> unsigned long mmu_seq;
> struct page *page;
> - struct kvm *kvm = s2fd->vcpu->kvm;
> + struct kvm *kvm = vcpu->kvm;
> void *memcache;
> kvm_pfn_t pfn;
> gfn_t gfn;
> int ret;
>
> - memcache = get_mmu_memcache(s2fd->vcpu);
> - ret = topup_mmu_memcache(s2fd->vcpu, memcache);
> + if (kvm_is_realm(vcpu->kvm)) {
> + /* check for memory attribute mismatch */
> + bool is_priv_gfn = kvm_mem_is_private(kvm, gpa >> PAGE_SHIFT);
> + /*
> + * For Realms, the shared address is an alias of the private
> + * PA with the top bit set. Thus if the fault address matches
> + * the GPA then it is the private alias.
> + */
> + bool is_priv_fault = (gpa == s2fd->fault_ipa);
> +
> + if (is_priv_gfn != is_priv_fault) {
> + kvm_prepare_memory_fault_exit(vcpu, gpa, PAGE_SIZE,
> + kvm_is_write_fault(vcpu),
> + false,
> + is_priv_fault);
> + /*
> + * KVM_EXIT_MEMORY_FAULT requires an return code of
> + * -EFAULT, see the API documentation
> + */
> + return -EFAULT;
> + }
> + }
> +
For a Realm, gmem_abort() is called by kvm_handle_guest_abort() only when
we're faulting in the private (protected) space.
if (kvm_slot_has_gmem(memslot) && !shared_ipa_fault(vcpu->kvm, fault_ipa))
ret = gmem_abort(&s2fd);
else
ret = user_mem_abort(&s2fd);
With the condition, this block of code can be simplied to handle conversion
(shared -> private) instead of both directions.
/* Convert the shared address to the private adress for Realm */
if (kvm_is_realm(vcpu->kvm) &&
!kvm_mem_is_private(kvm, gpa >> PAGE_SHIFT)) {
/*
* KVM_EXIT_MEMORY_FAULT requires an return code of
* -EFAULT, see the API documentation
*/
kvm_prepare_memory_fault_exit(vcpu, gpa, PAGE_SIZE,
kvm_is_write_fault(vcpu),
false, true);
return -EFAULT;
}
[...]
> @@ -2396,7 +2475,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
> !write_fault &&
> !kvm_vcpu_trap_is_exec_fault(vcpu));
>
> - if (kvm_slot_has_gmem(memslot))
> + if (kvm_slot_has_gmem(memslot) && !shared_ipa_fault(vcpu->kvm, fault_ipa))
> ret = gmem_abort(&s2fd);
> else
> ret = user_mem_abort(&s2fd);
gmem_abort() is only called for faults in the protected (private) space.
Thanks,
Gavin
^ permalink raw reply
* [PATCH v4 5/5] phy: fsl-imx8mq-usb: keep PHY power domain runtime always-on for i.MX8MP
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Xu Yang
In-Reply-To: <20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com>
From: Xu Yang <xu.yang_2@nxp.com>
On i.MX8MP, the USB PHY has a dedicated power domain that was previously
never powered off at runtime. With the introduction of runtime PM support,
the power domain will be powered off if the device is runtime suspended,
which breaks USB wakeup functionality.
To preserve wakeup functionality, mark the PHY power domain as runtime
always-on for i.MX8MP platform. To limit the behavior to i.MX8MP, add a
new imx95_usb_phy_ops for i.MX95 and introduce usb_phy_is_imx8mp() helper
to identify i.MX8MP PHY instance.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- no changes
Changes in v3:
- new patch
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index e24f46d7924b..c8b93ae2035f 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -9,6 +9,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
@@ -660,13 +661,20 @@ static const struct phy_ops imx8mp_usb_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct phy_ops imx95_usb_phy_ops = {
+ .init = imx8mp_usb_phy_init,
+ .power_on = imx8mq_phy_power_on,
+ .power_off = imx8mq_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
static const struct of_device_id imx8mq_usb_phy_of_match[] = {
{.compatible = "fsl,imx8mq-usb-phy",
.data = &imx8mq_usb_phy_ops,},
{.compatible = "fsl,imx8mp-usb-phy",
.data = &imx8mp_usb_phy_ops,},
{.compatible = "fsl,imx95-usb-phy",
- .data = &imx8mp_usb_phy_ops,},
+ .data = &imx95_usb_phy_ops,},
{ }
};
MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
@@ -679,6 +687,11 @@ static const struct regmap_config imx_cr_regmap_config = {
.max_register = 0x7,
};
+static bool usb_phy_is_imx8mp(const void *data)
+{
+ return data == &imx8mp_usb_phy_ops;
+}
+
static int imx8mq_usb_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -723,6 +736,9 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
if (!phy_ops)
return -EINVAL;
+ if (usb_phy_is_imx8mp(phy_ops))
+ dev_pm_genpd_rpm_always_on(dev, true);
+
imx_phy->phy = devm_phy_create(dev, NULL, phy_ops);
if (IS_ERR(imx_phy->phy))
return PTR_ERR(imx_phy->phy);
--
2.34.1
^ permalink raw reply related
* [PATCH v4 4/5] phy: fsl-imx8mq-usb: add control register regmap
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Xu Yang
In-Reply-To: <20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com>
From: Xu Yang <xu.yang_2@nxp.com>
The CR port is a simple 16-bit data/address parallel port that is
accessed through 32-bit MMIO registers for on-chip access to the
control registers inside the USB 3.0 femtoPHY. Add control register
regmap and export these registers by debugfs to help PHY's diagnostic.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- improve commit message as Haibo's suggestion
Changes in v3:
- drop Frank's tag because it includes other changes
- new patch
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index 27aa696f5dd4..e24f46d7924b 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
-/* Copyright (c) 2017 NXP. */
+/* Copyright 2017-2026 NXP. */
#include <linux/bitfield.h>
#include <linux/clk.h>
@@ -11,6 +11,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
+#include <linux/regmap.h>
#include <linux/usb/typec_mux.h>
#define PHY_CTRL0 0x0
@@ -56,6 +57,8 @@
#define PHY_CTRL6_ALT_CLK_EN BIT(1)
#define PHY_CTRL6_ALT_CLK_SEL BIT(0)
+#define PHY_CRCTL 0x30
+
#define PHY_TUNE_DEFAULT 0xffffffff
#define TCA_CLK_RST 0x00
@@ -119,6 +122,7 @@ struct imx8mq_usb_phy {
void __iomem *base;
struct regulator *vbus;
struct tca_blk *tca;
+ struct regmap *cr_regmap;
u32 pcs_tx_swing_full;
u32 pcs_tx_deemph_3p5db;
u32 tx_vref_tune;
@@ -667,6 +671,14 @@ static const struct of_device_id imx8mq_usb_phy_of_match[] = {
};
MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
+static const struct regmap_config imx_cr_regmap_config = {
+ .name = "cr",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x7,
+};
+
static int imx8mq_usb_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -696,6 +708,13 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
if (IS_ERR(imx_phy->base))
return PTR_ERR(imx_phy->base);
+ imx_phy->cr_regmap = devm_regmap_init_mmio(dev, imx_phy->base + PHY_CRCTL,
+ &imx_cr_regmap_config);
+ if (IS_ERR(imx_phy->cr_regmap)) {
+ dev_warn(dev, "Fail to init debug register regmap\n");
+ imx_phy->cr_regmap = NULL;
+ }
+
ret = devm_pm_runtime_set_active_enabled(dev);
if (ret)
return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
@@ -731,6 +750,9 @@ static int imx8mq_usb_phy_runtime_suspend(struct device *dev)
{
struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
+ if (imx_phy->cr_regmap)
+ regcache_cache_only(imx_phy->cr_regmap, true);
+
clk_disable_unprepare(imx_phy->alt_clk);
clk_disable_unprepare(imx_phy->clk);
@@ -752,6 +774,9 @@ static int imx8mq_usb_phy_runtime_resume(struct device *dev)
return ret;
}
+ if (imx_phy->cr_regmap)
+ regcache_cache_only(imx_phy->cr_regmap, false);
+
return 0;
}
--
2.34.1
^ permalink raw reply related
* [PATCH v4 3/5] phy: fsl-imx8mq-usb: add runtime PM support
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Xu Yang
In-Reply-To: <20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com>
From: Xu Yang <xu.yang_2@nxp.com>
Add runtime PM to ensure the PHY is properly powered and clocked during
register access, preventing potential system hangs.
It guards register access in the following scenarios:
- PHY operations: init() and power_on/off() callbacks are guarded by
phy core
- Type-C orientation switching when PHY/Controller are suspended which
needs explicitly care
- Future PHY control port register regmap debugfs access
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- replace guard() with PM_RUNTIME_ACQUIRE()
Changes in v3:
- new patch
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 62 +++++++++++++++++++++---------
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index 591ddf346061..27aa696f5dd4 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -9,6 +9,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/usb/typec_mux.h>
@@ -136,17 +137,15 @@ static int tca_blk_typec_switch_set(struct typec_switch_dev *sw,
{
struct imx8mq_usb_phy *imx_phy = typec_switch_get_drvdata(sw);
struct tca_blk *tca = imx_phy->tca;
- int ret;
if (tca->orientation == orientation)
return 0;
- ret = clk_prepare_enable(imx_phy->clk);
- if (ret)
- return ret;
+ PM_RUNTIME_ACQUIRE(&imx_phy->phy->dev, pm);
+ if (PM_RUNTIME_ACQUIRE_ERR(&pm))
+ return -ENXIO;
tca_blk_orientation_set(tca, orientation);
- clk_disable_unprepare(imx_phy->clk);
return 0;
}
@@ -620,16 +619,6 @@ static int imx8mq_phy_power_on(struct phy *phy)
if (ret)
return ret;
- ret = clk_prepare_enable(imx_phy->clk);
- if (ret)
- return ret;
-
- ret = clk_prepare_enable(imx_phy->alt_clk);
- if (ret) {
- clk_disable_unprepare(imx_phy->clk);
- return ret;
- }
-
/* Disable rx term override */
value = readl(imx_phy->base + PHY_CTRL6);
value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
@@ -648,8 +637,6 @@ static int imx8mq_phy_power_off(struct phy *phy)
value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL;
writel(value, imx_phy->base + PHY_CTRL6);
- clk_disable_unprepare(imx_phy->alt_clk);
- clk_disable_unprepare(imx_phy->clk);
regulator_disable(imx_phy->vbus);
return 0;
@@ -686,6 +673,7 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct imx8mq_usb_phy *imx_phy;
const struct phy_ops *phy_ops;
+ int ret;
imx_phy = devm_kzalloc(dev, sizeof(*imx_phy), GFP_KERNEL);
if (!imx_phy)
@@ -693,13 +681,13 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, imx_phy);
- imx_phy->clk = devm_clk_get(dev, "phy");
+ imx_phy->clk = devm_clk_get_enabled(dev, "phy");
if (IS_ERR(imx_phy->clk)) {
dev_err(dev, "failed to get imx8mq usb phy clock\n");
return PTR_ERR(imx_phy->clk);
}
- imx_phy->alt_clk = devm_clk_get_optional(dev, "alt");
+ imx_phy->alt_clk = devm_clk_get_optional_enabled(dev, "alt");
if (IS_ERR(imx_phy->alt_clk))
return dev_err_probe(dev, PTR_ERR(imx_phy->alt_clk),
"Failed to get alt clk\n");
@@ -708,6 +696,10 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
if (IS_ERR(imx_phy->base))
return PTR_ERR(imx_phy->base);
+ ret = devm_pm_runtime_set_active_enabled(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
+
phy_ops = of_device_get_match_data(dev);
if (!phy_ops)
return -EINVAL;
@@ -735,11 +727,43 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static int imx8mq_usb_phy_runtime_suspend(struct device *dev)
+{
+ struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(imx_phy->alt_clk);
+ clk_disable_unprepare(imx_phy->clk);
+
+ return 0;
+}
+
+static int imx8mq_usb_phy_runtime_resume(struct device *dev)
+{
+ struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_prepare_enable(imx_phy->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(imx_phy->alt_clk);
+ if (ret) {
+ clk_disable_unprepare(imx_phy->clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+static DEFINE_RUNTIME_DEV_PM_OPS(imx8mq_usb_phy_pm_ops, imx8mq_usb_phy_runtime_suspend,
+ imx8mq_usb_phy_runtime_resume, NULL);
+
static struct platform_driver imx8mq_usb_phy_driver = {
.probe = imx8mq_usb_phy_probe,
.driver = {
.name = "imx8mq-usb-phy",
.of_match_table = imx8mq_usb_phy_of_match,
+ .pm = pm_ptr(&imx8mq_usb_phy_pm_ops),
.suppress_bind_attrs = true,
}
};
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/5] phy: fsl-imx8mq-usb: set usb phy to be wakeup capable
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Xu Yang
In-Reply-To: <20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com>
From: Xu Yang <xu.yang_2@nxp.com>
Set PHY wakeup capable because this PHY supports remote wakeup function.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- add Rb tag
Changes in v3:
- no changes
Changes in v2:
- no changes
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index 88b804b2c982..591ddf346061 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -728,6 +728,7 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
"failed to get tca\n");
imx8m_get_phy_tuning_data(imx_phy);
+ device_set_wakeup_capable(dev, true);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
--
2.34.1
^ permalink raw reply related
* [PATCH v4 0/5] phy: fsl-imx8mq-usb: few improvements
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Felix Gu, stable,
Xu Yang
This patchset is a continuous of v2, it mainly resolves some concerns
reported by sashiko-bot.
Patch #1 fix Type-C switch resource leak if probe() fails.
Patch #3 add runtime PM support to avoid register access issue if the
USB controller enters into runtime suspended state, in this state
accessing USB PHY register may lack some resources. This will also
avoid regulator leak if power_on() fails.
Patch #4 add debug control register regmap
Patch #5 correct i.MX8MP USB runtime wakeup issue after introduce runtime
PM support.
---
Changes in v4:
- add Rb tag
- replace guard() with PM_RUNTIME_ACQUIRE()
- Link to v3: https://patch.msgid.link/20260603-imx8mp-usb-phy-improvement-v3-0-7afb8f89abc6@nxp.com
Link to v2:
- https://lore.kernel.org/linux-phy/20260512101046.1498096-1-xu.yang_2@nxp.com/
- https://lore.kernel.org/linux-phy/20260512101212.1498223-1-xu.yang_2@nxp.com/
---
Felix Gu (1):
phy: fsl-imx8mq-usb: fix typec switch leak on probe error path
Xu Yang (4):
phy: fsl-imx8mq-usb: set usb phy to be wakeup capable
phy: fsl-imx8mq-usb: add runtime PM support
phy: fsl-imx8mq-usb: add control register regmap
phy: fsl-imx8mq-usb: keep PHY power domain runtime always-on for i.MX8MP
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 127 ++++++++++++++++++++---------
1 file changed, 90 insertions(+), 37 deletions(-)
---
base-commit: 08484c504b55a98bd100527fbe10a3caf55ff3ff
change-id: 20260602-imx8mp-usb-phy-improvement-4272d308d862
Best regards,
--
Xu Yang <xu.yang_2@nxp.com>
^ permalink raw reply
* [PATCH v4 1/5] phy: fsl-imx8mq-usb: fix typec switch leak on probe error path
From: Xu Yang @ 2026-06-05 11:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Jun Li
Cc: linux-phy, imx, linux-arm-kernel, linux-kernel, Felix Gu, stable,
Xu Yang
In-Reply-To: <20260605-imx8mp-usb-phy-improvement-v4-0-b2ddf2f3862c@nxp.com>
From: Felix Gu <ustc.gu@gmail.com>
If probe fails after imx95_usb_phy_get_tca() succeeds, the typec
switch leaks because the only cleanup path was in .remove, which
never runs on probe failure.
Use devm_add_action_or_reset() so the switch is cleaned up on both
probe failure and driver removal. The .remove callback and
imx95_usb_phy_put_tca() are no longer needed.
Fixes: b58f0f86fd61 ("phy: fsl-imx8mq-usb: add tca function driver for imx95")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v4:
- add my signed-off tag
Changes in v3:
- add R-b tag
- cc statble
- drop "sw = data" conversion
---
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 27 +++++++--------------------
1 file changed, 7 insertions(+), 20 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index b05d80e849a1..88b804b2c982 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -173,9 +173,9 @@ static struct typec_switch_dev *tca_blk_get_typec_switch(struct platform_device
return sw;
}
-static void tca_blk_put_typec_switch(struct typec_switch_dev *sw)
+static void tca_blk_put_typec_switch(void *data)
{
- typec_switch_unregister(sw);
+ typec_switch_unregister(data);
}
static void tca_blk_orientation_set(struct tca_blk *tca,
@@ -248,6 +248,7 @@ static struct tca_blk *imx95_usb_phy_get_tca(struct platform_device *pdev,
struct device *dev = &pdev->dev;
struct resource *res;
struct tca_blk *tca;
+ int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
@@ -266,17 +267,11 @@ static struct tca_blk *imx95_usb_phy_get_tca(struct platform_device *pdev,
tca->orientation = TYPEC_ORIENTATION_NORMAL;
tca->sw = tca_blk_get_typec_switch(pdev, imx_phy);
- return tca;
-}
-
-static void imx95_usb_phy_put_tca(struct imx8mq_usb_phy *imx_phy)
-{
- struct tca_blk *tca = imx_phy->tca;
-
- if (!tca)
- return;
+ ret = devm_add_action_or_reset(&pdev->dev, tca_blk_put_typec_switch, tca->sw);
+ if (ret)
+ return ERR_PTR(ret);
- tca_blk_put_typec_switch(tca->sw);
+ return tca;
}
static u32 phy_tx_vref_tune_from_property(u32 percent)
@@ -739,16 +734,8 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static void imx8mq_usb_phy_remove(struct platform_device *pdev)
-{
- struct imx8mq_usb_phy *imx_phy = platform_get_drvdata(pdev);
-
- imx95_usb_phy_put_tca(imx_phy);
-}
-
static struct platform_driver imx8mq_usb_phy_driver = {
.probe = imx8mq_usb_phy_probe,
- .remove = imx8mq_usb_phy_remove,
.driver = {
.name = "imx8mq-usb-phy",
.of_match_table = imx8mq_usb_phy_of_match,
--
2.34.1
^ permalink raw reply related
* [BOOTWRAPPER PATCH v4 2/2] Add support for GICv5
From: Vladimir Murzin @ 2026-06-05 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
In-Reply-To: <20260605104853.2406-1-vladimir.murzin@arm.com>
Performs the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Tested-by: Sascha Bischoff <sascha.bischoff@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 131 +++++++++++++++++++++++++++++++++
configure.ac | 7 +-
scripts/FDT.pm | 16 ++++
scripts/findbase-by-regname.pl | 44 +++++++++++
6 files changed, 213 insertions(+), 3 deletions(-)
create mode 100644 common/gic-v5.c
create mode 100755 scripts/findbase-by-regname.pl
diff --git a/Makefile.am b/Makefile.am
index 2710494..aacd639 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -82,6 +82,13 @@ PSCI_NODE :=
CPU_NODES :=
endif
+if GICV5
+GIC_IRS_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase-by-regname.pl $(KERNEL_DTB) "el3-config" 'arm,gic-v5-irs')
+GIC_IWB_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,gic-v5-iwb')
+DEFINES += -DGIC_IRS_BASE=$(GIC_IRS_BASE)
+DEFINES += -DGIC_IWB_BASE=$(GIC_IWB_BASE)
+endif
+
if GICV3
GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,gic-v3')
GIC_RDIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,gic-v3')
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ac50474..af4191c 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -128,6 +128,7 @@
#define ID_AA64PFR1_EL1_THE BITS(51, 48)
#define ID_AA64PFR2_EL1 s3_0_c0_c4_2
+#define ID_AA64PFR2_EL1_GCIE BITS(15, 12)
#define ID_AA64PFR2_EL1_FPMR BITS(35, 32)
#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
@@ -169,6 +170,11 @@
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7
+
#define VSTCR_EL2 s3_4_c2_c6_2
#define VSCTLR_EL2 s3_4_c2_c0_0
@@ -245,6 +251,11 @@ static inline int has_gicv3_sysreg(void)
return !!mrs_field(ID_AA64PFR0_EL1, GIC);
}
+static inline int has_gicv5_sysreg(void)
+{
+ return !!mrs_field(ID_AA64PFR2_EL1, GCIE);
+}
+
#endif /* !__ASSEMBLY__ */
#endif
diff --git a/common/gic-v5.c b/common/gic-v5.c
new file mode 100644
index 0000000..711366d
--- /dev/null
+++ b/common/gic-v5.c
@@ -0,0 +1,131 @@
+/*
+ * gic-v5.c
+ *
+ * Copyright (C) 2025 ARM Limited. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE.txt file.
+ */
+
+#include <stdint.h>
+
+#include <cpu.h>
+#include <gic.h>
+#include <asm/io.h>
+
+#define IWB_IDR0 0x0
+#define IWB_IDR0_IW_RANGE_SHIFT 0x0
+#define IWB_IDR0_IW_RANGE_MASK 0x7ff
+
+#define IWB_CR0 0x80
+#define IWB_CR0_IWBEN (1 << 0)
+#define IWB_CR0_IDLE (1 << 1)
+
+#define IWB_WENABLE_STATUSR 0xc0
+#define IWB_WENABLE_STATUSR_IDLE (1 << 0)
+
+#define IWB_WDOMAIN_STATUSR 0xc4
+#define IWB_WDOMAIN_STATUSR_IDLE (1 << 0)
+
+#define IWB_WENABLER 0x2000
+#define IWB_WDOMAINR 0x8000
+
+#define IRS_IDR6 0x0018
+#define IRS_IDR6_SPI_IRS_RANGE_MASK 0x1ffffff
+
+#define IRS_IDR7 0x001c
+#define IRS_IDR7_SPI_BASE_MASK 0xffffff
+
+#define IRS_SPI_SELR 0x108
+#define IRS_SPI_DOMAINR 0x10c
+
+#define IRS_SPI_STATUSR 0x0118
+#define IRS_SPI_STATUSR_IDLE (1 << 0)
+
+static void gic_iwb_init(void) {
+ void *iwb_ptr = (void *)GIC_IWB_BASE;
+ unsigned int num;
+ unsigned int i;
+
+ /* Get number of implemented wire control registers */
+ num = ((raw_readl(iwb_ptr + IWB_IDR0) >> IWB_IDR0_IW_RANGE_SHIFT) & IWB_IDR0_IW_RANGE_MASK) + 1;
+
+ /* Disable all wires */
+ for (i = 0; i < num; i++)
+ raw_writel(0, iwb_ptr + IWB_WENABLER + i * 4);
+
+ while (!(raw_readl(iwb_ptr + IWB_WENABLE_STATUSR) & IWB_WENABLE_STATUSR_IDLE));
+
+ /* Assign all wires to Non-Secure domain */
+ for (i = 0; i < num * 2; i++)
+ raw_writel(0x55555555, iwb_ptr + IWB_WDOMAINR + i * 4);
+
+ while (!(raw_readl(iwb_ptr + IWB_WDOMAIN_STATUSR) & IWB_WDOMAIN_STATUSR_IDLE));
+
+ /* Enable IWB */
+ raw_writel(IWB_CR0_IWBEN, iwb_ptr + IWB_CR0);
+
+ while (!(raw_readl(iwb_ptr + IWB_CR0) & IWB_CR0_IDLE));
+}
+
+static void gic_irs_init(void) {
+ void *irs_ptr = (void *)GIC_IRS_BASE;
+ unsigned int range;
+ unsigned int base;
+ unsigned int i;
+
+ /* Get the range of implemented SPIs */
+ base = raw_readl(irs_ptr + IRS_IDR7) & IRS_IDR7_SPI_BASE_MASK;
+ range = raw_readl(irs_ptr + IRS_IDR6) & IRS_IDR6_SPI_IRS_RANGE_MASK;
+
+ for (i = base; i < base + range; i++) {
+ /* Select SPI */
+ raw_writel(i, irs_ptr + IRS_SPI_SELR);
+ while (!(raw_readl(irs_ptr + IRS_SPI_STATUSR) & IRS_SPI_STATUSR_IDLE));
+
+ /* Assign SPI to Non-Secure domain */
+ raw_writel(1, irs_ptr + IRS_SPI_DOMAINR);
+ while (!(raw_readl(irs_ptr + IRS_SPI_STATUSR) & IRS_SPI_STATUSR_IDLE));
+ }
+}
+
+static void gic_ppi_init(void) {
+ uint64_t val = 0;
+
+ val |= 1UL << (2 * 31); // Trace Buffer Unit
+ val |= 1UL << (2 * 30); // EL1 Physical Timer
+ val |= 1UL << (2 * 28); // Non-secure EL2 Virtual Timer
+ val |= 1UL << (2 * 27); // EL1 Virtual Timer
+ val |= 1UL << (2 * 26); // Non-secure EL2 Physical Timer
+ val |= 1UL << (2 * 25); // GIC maintenance interrupt
+ val |= 1UL << (2 * 24); // Generic CTI interrupt trigger event
+ val |= 1UL << (2 * 23); // PMU overflow interrupt request
+ val |= 1UL << (2 * 22); // Debug communication channel
+ val |= 1UL << (2 * 21); // Profiling Buffer management interrupt request
+ val |= 1UL << (2 * 15); // Hardware accelerator for cleaning Dirty state interrupt
+ val |= 1UL << (2 * 3); // Reserved for software usage
+
+ /* Assign PPI to Non-Secure domain */
+ msr(ICC_PPI_DOMAINR0_EL3, val);
+ isb();
+}
+
+void gic_secure_init(void)
+{
+ /*
+ * If GICv5 is not available, skip initialisation. The OS will probably
+ * fail with a warning, but this should be easier to debug than a
+ * failure within the boot wrapper.
+ */
+ if (!has_gicv5_sysreg())
+ return;
+
+ if (this_cpu_logical_id() == 0) {
+ gic_iwb_init();
+ gic_irs_init();
+ }
+
+ gic_ppi_init();
+
+ return;
+}
diff --git a/configure.ac b/configure.ac
index 6f486c4..f4faff7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -141,18 +141,19 @@ AC_SUBST([XEN_CMDLINE], [$X_CMDLINE])
AC_ARG_WITH([gic],
- AS_HELP_STRING([--with-gic={v2|v3}], [select GIC version]),
+ AS_HELP_STRING([--with-gic={v2|v3|v5}], [select GIC version]),
[GIC_VERSION=$withval],
[GIC_VERSION=v2])
AS_CASE([$GIC_VERSION],
- [v2|v3], [],
- [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2 or v3)])])
+ [v2|v3|v5], [],
+ [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2, v3, or v5)])])
AC_SUBST([GIC_VERSION], [$GIC_VERSION])
AM_CONDITIONAL([GICV2], [test "x$GIC_VERSION" = "xv2"])
AM_CONDITIONAL([GICV3], [test "x$GIC_VERSION" = "xv3"])
+AM_CONDITIONAL([GICV5], [test "x$GIC_VERSION" = "xv5"])
# Ensure that we have all the needed programs
diff --git a/scripts/FDT.pm b/scripts/FDT.pm
index 9adf70b..3f49ba6 100755
--- a/scripts/FDT.pm
+++ b/scripts/FDT.pm
@@ -322,6 +322,22 @@ sub get_num_reg_cells
return ($ac, $sc);
}
+sub get_regname_idx
+{
+ my $self = shift;
+ my $regname = shift;
+
+ my $prop = $self->get_property("reg-names");
+
+ return undef if (not defined($prop));
+
+ my @names = $prop->read_strings();
+
+ my ($idx) = grep { $names[$_] eq $regname } 0 .. $#names;
+
+ return $idx;
+}
+
sub translate_address
{
my $self = shift;
diff --git a/scripts/findbase-by-regname.pl b/scripts/findbase-by-regname.pl
new file mode 100755
index 0000000..49cd0ce
--- /dev/null
+++ b/scripts/findbase-by-regname.pl
@@ -0,0 +1,44 @@
+#!/usr/bin/perl -w
+# Find device register base addresses.
+#
+# Usage: ./$0 <DTB> <regname> <compatible ...>
+#
+# Copyright (C) 2026 ARM Limited. All rights reserved.
+#
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE.txt file.
+
+use warnings;
+use strict;
+
+use FDT;
+
+my $filename = shift;
+die("No filename provided") unless defined($filename);
+
+my $regname = shift;
+die("no reg regname provided") unless defined($regname);
+
+my @compats = shift;
+
+open (my $fh, "<:raw", $filename) or die("Unable to open file '$filename'");
+
+my $fdt = FDT->parse($fh) or die("Unable to parse DTB");
+
+my $root = $fdt->get_root();
+
+my @devs = ();
+for my $compat (@compats) {
+ push @devs, $root->find_compatible($compat);
+}
+
+# We only care about finding the first matching device
+my $dev = shift @devs;
+die("No matching devices found") if (not defined($dev));
+
+my $idx = $dev->get_regname_idx($regname);
+die("Cannot find reg name $regname") if (not defined($idx));
+my ($addr, $size) = $dev->get_translated_reg($idx);
+die("Cannot find reg entry $idx") if (not defined($addr) or not defined($size));
+
+printf("0x%016x\n", $addr);
--
2.34.1
^ permalink raw reply related
* [BOOTWRAPPER PATCH v4 1/2] Introduce --with-gic option
From: Vladimir Murzin @ 2026-06-05 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
In-Reply-To: <20260605104853.2406-1-vladimir.murzin@arm.com>
We are about to add support for another GIC version, so introduce a
new --with-gic option to select the desired GIC version at configure
time. The default remains v2, preserving existing behavior. However,
for GICv3, we replace the previous --enable-gicv3 option with
--with-gic=v3 which is backward-incompatible change (yet I hope we can
live with that).
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
---
Makefile.am | 8 +++++---
common/{gic.c => gic-v2.c} | 0
configure.ac | 23 ++++++++++++++++-------
3 files changed, 21 insertions(+), 10 deletions(-)
rename common/{gic.c => gic-v2.c} (100%)
diff --git a/Makefile.am b/Makefile.am
index 0178e5d..2710494 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -87,15 +87,17 @@ GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNE
GIC_RDIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,gic-v3')
DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE)
DEFINES += -DGIC_RDIST_BASE=$(GIC_RDIST_BASE)
-COMMON_OBJ += gic-v3.o
-else
+endif
+
+if GICV2
GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,cortex-a15-gic')
GIC_CPU_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,cortex-a15-gic')
DEFINES += -DGIC_CPU_BASE=$(GIC_CPU_BASE)
DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE)
-COMMON_OBJ += gic.o
endif
+COMMON_OBJ += gic-$(GIC_VERSION).o
+
if KERNEL_32
MBOX_OFFSET := 0x7ff8
TEXT_LIMIT := 0x3000
diff --git a/common/gic.c b/common/gic-v2.c
similarity index 100%
rename from common/gic.c
rename to common/gic-v2.c
diff --git a/configure.ac b/configure.ac
index 42858df..6f486c4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -139,12 +139,21 @@ AC_ARG_WITH([xen-cmdline],
[X_CMDLINE=$withval])
AC_SUBST([XEN_CMDLINE], [$X_CMDLINE])
-# Allow a user to pass --enable-gicv3
-AC_ARG_ENABLE([gicv3],
- AS_HELP_STRING([--enable-gicv3], [enable GICv3 instead of GICv2]),
- [USE_GICV3=$enableval])
-AM_CONDITIONAL([GICV3], [test "x$USE_GICV3" = "xyes"])
-AS_IF([test "x$USE_GICV3" = "xyes"], [], [USE_GICV3=no])
+
+AC_ARG_WITH([gic],
+ AS_HELP_STRING([--with-gic={v2|v3}], [select GIC version]),
+ [GIC_VERSION=$withval],
+ [GIC_VERSION=v2])
+
+AS_CASE([$GIC_VERSION],
+ [v2|v3], [],
+ [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2 or v3)])])
+
+AC_SUBST([GIC_VERSION], [$GIC_VERSION])
+
+AM_CONDITIONAL([GICV2], [test "x$GIC_VERSION" = "xv2"])
+AM_CONDITIONAL([GICV3], [test "x$GIC_VERSION" = "xv3"])
+
# Ensure that we have all the needed programs
AC_PROG_CC
@@ -174,7 +183,7 @@ echo " Device tree compiler: ${DTC}"
echo " Linux kernel command line: ${CMDLINE}"
echo " Embedded initrd: ${FILESYSTEM:-NONE}"
echo " Use PSCI? ${USE_PSCI}"
-echo " Use GICv3? ${USE_GICV3}"
+echo " GIC version: ${GIC_VERSION}"
echo " Boot-wrapper execution state: AArch${BOOTWRAPPER_ES}"
echo " Kernel execution state: AArch${KERNEL_ES}"
echo " Xen image ${XEN_IMAGE:-NONE}"
--
2.34.1
^ permalink raw reply related
* [BOOTWRAPPER PATCH v4 0/2] Support GICv5
From: Vladimir Murzin @ 2026-06-05 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
Small series adding GICv5 to the list of supported GIC
versions. Minimal implementation, just enough for Fast Models.
Thanks!
Changelog:
v3 -> v4
- Fixed stray new line at the EOF (per Sascha)
- Added more tags from Sascha Bischoff
v2 -> v3
- Fixed code formatting and incorrect comments (per Sascha)
- Fixed spelling and grammar mistakes (per Sascha)
- Added tags from Sascha Bischoff
v1 -> v2
- Assign SW_PPI to NS domain (per Sascha)
Vladimir Murzin (2):
Introduce --with-gic option
Add support for GICv5
Makefile.am | 15 +++-
arch/aarch64/include/asm/cpu.h | 11 +++
common/{gic.c => gic-v2.c} | 0
common/gic-v5.c | 131 +++++++++++++++++++++++++++++++++
configure.ac | 24 ++++--
scripts/FDT.pm | 16 ++++
scripts/findbase-by-regname.pl | 44 +++++++++++
7 files changed, 231 insertions(+), 10 deletions(-)
rename common/{gic.c => gic-v2.c} (100%)
create mode 100644 common/gic-v5.c
create mode 100755 scripts/findbase-by-regname.pl
--
2.34.1
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: dma: fsl-edma: add dma-channel-mask property description
From: Laurentiu Mihalcea @ 2026-06-05 10:44 UTC (permalink / raw)
To: Joy Zou, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Frank Li, Peng Fan, Ye Li
Cc: devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260211-b4-imx95-v2x-v4-1-10852754b267@nxp.com>
On 2/11/2026 1:28 AM, Joy Zou wrote:
> Add documentation for the dma-channel-mask property in the fsl-edma
> binding. This property uses an inverted bit definition: bit value 0
> indicates the channel is available, while bit value 1 indicates
> unavailable.
>
> That was already used widely for i.MX8, i.MX9. Correcting the definition
> will break backward compatibility. This reversal only impacts the eDMA
> dts node and driver, and doesn't impact DMA consumer. Therefore,
> keep the inverted definition.
>
> Also add a note at the top of the binding to highlight this inverted
> definition to prevent confusion.
>
> Signed-off-by: Joy Zou <joy.zou@nxp.com>
Hi,
I believe this patch hasn't been picked up yet even though it's been ACK'd by one of the
DT binding maintainers.
Frank Li, can you please take it into your tree?
Thanks,
Laurentiu
^ permalink raw reply
* Re: [PATCH v7 00/10] clk: realtek: Add RTD1625 clock support
From: Yu-Chun Lin @ 2026-06-05 10:33 UTC (permalink / raw)
To: eleanor.lin
Cc: afaerber, bmasney, conor+dt, cy.huang, cylee12, devicetree,
james.tai, jyanchou, krzk+dt, linux-arm-kernel, linux-clk,
linux-kernel, linux-realtek-soc, mturquette, p.zabel, robh, sboyd,
stanley_chang
In-Reply-To: <20260508111641.3192177-1-eleanor.lin@realtek.com>
Hi everyone,
Just a gentle ping on this thread.
Although I haven't received any feedback from reviewers over the past
month, I noticed that the AI robot has provided several helpful comments
[1].
I will address these issues and plan to send out v8 patchset next week.
[1] https://sashiko.dev/#/patchset/20260508111641.3192177-1-eleanor.lin%40realtek.com
Thanks,
Yu-Chun
^ permalink raw reply
* Re: [PATCH v6 1/4] media: dt-bindings: mediatek: Add AIE face detection support for MT8188
From: Krzysztof Kozlowski @ 2026-06-05 10:31 UTC (permalink / raw)
To: Sarang Chaudhari, Rob Herring, AngeloGioacchino Del Regno,
Mauro Carvalho Chehab, linux-kernel, linux-arm-kernel,
linux-mediatek
Cc: zhaoyuan.chen, Teddy.Chen, Project_Global_Chrome_Upstream_Group
In-Reply-To: <20260605082816.2589809-1-sarang.chaudhari@mediatek.com>
On 05/06/2026 10:28, Sarang Chaudhari wrote:
> Add YAML device tree bindings for the MediaTek AI Engine (AIE) hardware
> accelerator found in MT8188 SoCs. The AIE provides hardware-accelerated
> face detection, facial landmark detection, and face attribute analysis
> capabilities.
v6 and still not following Linux kernel process...
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.
Please kindly resend and include all necessary To/Cc entries.
> +F: Documentation/devicetree/bindings/media/mediatek,mt8188-aie.yaml
> +F: drivers/media/platform/mediatek/aie/
There is no such directory. Apply THIS patch and test.
> +F: include/uapi/linux/mtk_aie_v4l2_controls.h
> +
> MEDIATEK MDP DRIVER
> M: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
> S: Supported
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level detector
From: Yu-Chun Lin [林祐君] @ 2026-06-05 10:19 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, TY_Chang[張子逸]
Cc: CY_Huang[黃鉦晏],
Stanley Chang[昌育德],
James Tai [戴志峰], afaerber@suse.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-realtek-soc@lists.infradead.org
In-Reply-To: <4d96835a-a273-4c46-85a2-03c059934650@kernel.org>
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Thursday, June 4, 2026 8:49 PM
> To: Yu-Chun Lin [林祐君] <eleanor.lin@realtek.com>; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; TY_Chang[張子逸]
> <tychang@realtek.com>
> Cc: CY_Huang[黃鉦晏] <cy.huang@realtek.com>; Stanley Chang[昌育德]
> <stanley_chang@realtek.com>; James Tai [戴志峰] <james.tai@realtek.com>;
> afaerber@suse.com; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-realtek-soc@lists.infradead.org
> Subject: Re: [PATCH 1/3] dt-bindings: soc: realtek: Add Realtek DHC I/O level
> detector
>
> On 04/06/2026 13:18, Yu-Chun Lin wrote:
> > From: Tzuyi Chang <tychang@realtek.com>
> >
> > Add device tree binding documentation for the Realtek DHC I/O level
> > detector.
> >
> > This hardware block is responsible for detecting the I/O signaling
> > levels (e.g., 1.8V or 3.3V) of various interfaces (RGMII, SDIO, eMMC,
> > etc.) and applying the corresponding pad configurations via pinctrl
> > states.
> >
> > Signed-off-by: Tzuyi Chang <tychang@realtek.com>
> > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> > ---
> > .../realtek/realtek,rtd1625-io-detect.yaml | 77 +++++++++++++++++++
> > 1 file changed, 77 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-detec
> > t.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-det
> > ect.yaml
> > b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io-det
> > ect.yaml
> > new file mode 100644
> > index 000000000000..badf27212dfd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1625-io
> > +++ -detect.yaml
> > @@ -0,0 +1,77 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # Copyright 2026
> > +Realtek Semiconductor Corporation %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/soc/realtek/realtek,rtd1625-io-detect.y
> > +aml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Realtek DHC I/O Level Detector
> > +
> > +maintainers:
> > + - Tzuyi Chang <tychang@realtek.com>
> > +
> > +description: |
>
> Drop |
>
> > + The Realtek DHC I/O Level Detector is a hardware block that detects
> > + I/O signaling levels (such as 1.8V or 3.3V) to determine the
> > + correct pad configurations for specific IP blocks.
> > +
> > +properties:
> > + compatible:
> > + const: realtek,rtd1625-io-detect
> > +
>
> No resources here, so does not look like a real device, but driver instantiation.
>
Hi Krzysztof,
You're right, It shouldn't introduce a device node just for a software driver.
For v2, we'll drop this binding and the device node, and revisit the approach.
Best regards,
Yu-Chun
>
> > + pinctrl-names:
> > + items:
> > + - const: rgmii_1v8
> > + - const: rgmii_3v3
> > + - const: sdio_1v8
> > + - const: sdio_3v3
> > + - const: csi_1v8
> > + - const: csi_3v3
> > + - const: sd_1v8
> > + - const: sd_3v3
> > + - const: uart1_1v8
> > + - const: uart1_3v3
> > + - const: aio_1v8
> > + - const: aio_3v3
> > + - const: emmc_1v8
> > + - const: emmc_3v3
> > +
> > + realtek,iso-pinctrl:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + Pinctrl phandle containing I/O detection registers.
>
> MMIO registers are in 'reg' property.
>
> > +
> > +required:
> > + - compatible
> > + - pinctrl-names
> > + - realtek,iso-pinctrl
> Best regards,
> Krzysztof
^ permalink raw reply
* [PATCH v3 3/3] soc: qcom: ubwc: Add Shikra UBWC config
From: Nabige Aala @ 2026-06-05 10:18 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Loic Poulain, Bjorn Andersson, Konrad Dybcio, Will Deacon,
Robin Murphy, Joerg Roedel (AMD)
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
iommu, linux-arm-kernel, Nabige Aala, Dmitry Baryshkov
In-Reply-To: <20260605-shikra-display-v3-0-9846ba5fe635@oss.qualcomm.com>
Add UBWC configuration for the Shikra platform. Shikra shares the
same hardware as QCM2290 (Agatti), so reuse qcm2290_data for the
UBWC settings
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
drivers/soc/qcom/ubwc_config.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 3fe47d8f0f63..1a2e54c6480d 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -278,6 +278,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
{ .compatible = "qcom,sdm660", .data = &msm8937_data },
{ .compatible = "qcom,sdm670", .data = &sdm670_data, },
{ .compatible = "qcom,sdm845", .data = &sdm845_data, },
+ { .compatible = "qcom,shikra", .data = &qcm2290_data, },
{ .compatible = "qcom,sm4250", .data = &sm6115_data, },
{ .compatible = "qcom,sm6115", .data = &sm6115_data, },
{ .compatible = "qcom,sm6125", .data = &sm6125_data, },
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/3] arm64: defconfig: Enable ILI7807S DSI panel driver
From: Nabige Aala @ 2026-06-05 10:18 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Loic Poulain, Bjorn Andersson, Konrad Dybcio, Will Deacon,
Robin Murphy, Joerg Roedel (AMD)
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
iommu, linux-arm-kernel, Nabige Aala, Dmitry Baryshkov
In-Reply-To: <20260605-shikra-display-v3-0-9846ba5fe635@oss.qualcomm.com>
Enable the ILI7807S 1080x1920 video-mode DSI panel driver as a module,
used on the Shikra CQM EVK board.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 909f3c188e75..a6d72ff63e57 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1005,6 +1005,7 @@ CONFIG_DRM_MXSFB=m
CONFIG_DRM_IMX_LCDIF=m
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_ILITEK_ILI7807S=m
CONFIG_DRM_PANEL_LVDS=m
CONFIG_DRM_PANEL_HIMAX_HX8279=m
CONFIG_DRM_PANEL_HIMAX_HX83112A=m
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: display: msm: qcm2290: Add Shikra MDSS
From: Nabige Aala @ 2026-06-05 10:18 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Loic Poulain, Bjorn Andersson, Konrad Dybcio, Will Deacon,
Robin Murphy, Joerg Roedel (AMD)
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
iommu, linux-arm-kernel, Nabige Aala
In-Reply-To: <20260605-shikra-display-v3-0-9846ba5fe635@oss.qualcomm.com>
Shikra reuses the same MDSS/DPU 6.5 hardware as QCM2290. Extend
the existing qcm2290 bindings to cover Shikra by adding fallback
compatible chains for MDSS, DPU and DSI controller nodes rather
than introducing a separate binding file.
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
.../bindings/display/msm/dsi-controller-main.yaml | 4 ++++
.../bindings/display/msm/qcom,qcm2290-dpu.yaml | 7 +++++--
.../bindings/display/msm/qcom,qcm2290-mdss.yaml | 22 +++++++++++++++-------
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index dbc0613e427e..ab2cfd6d6e3e 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -57,6 +57,10 @@ properties:
- const: qcom,eliza-dsi-ctrl
- const: qcom,sm8750-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
+ - items:
+ - const: qcom,shikra-dsi-ctrl
+ - const: qcom,qcm2290-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml
index be6cd8adb3b6..e166a73651df 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml
@@ -13,8 +13,11 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
- const: qcom,qcm2290-dpu
-
+ oneOf:
+ - const: qcom,qcm2290-dpu
+ - items:
+ - const: qcom,shikra-dpu
+ - const: qcom,qcm2290-dpu
reg:
items:
- description: Address offset and size for mdp register set
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
index bb09ecd1a5b4..ef21b2c263f2 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm QCM220 Display MDSS
+title: Qualcomm QCM2290 and Shikra Display MDSS
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
@@ -12,13 +12,18 @@ maintainers:
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
- are mentioned for QCM2290 target.
+ are mentioned for QCM2290 and Shikra targets. Shikra uses the same MDSS/DPU/DSI
+ hardware as QCM2290 (DPU 6.5) and shares the same register layout.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
- const: qcom,qcm2290-mdss
+ oneOf:
+ - const: qcom,qcm2290-mdss
+ - items:
+ - const: qcom,shikra-mdss
+ - const: qcom,qcm2290-mdss
clocks:
items:
@@ -52,7 +57,11 @@ patternProperties:
properties:
compatible:
- const: qcom,qcm2290-dpu
+ oneOf:
+ - const: qcom,qcm2290-dpu
+ - items:
+ - const: qcom,shikra-dpu
+ - const: qcom,qcm2290-dpu
"^dsi@[0-9a-f]+$":
type: object
@@ -60,9 +69,8 @@ patternProperties:
properties:
compatible:
- items:
- - const: qcom,qcm2290-dsi-ctrl
- - const: qcom,mdss-dsi-ctrl
+ contains:
+ const: qcom,qcm2290-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/3] Add Shikra (QCM2390) display support
From: Nabige Aala @ 2026-06-05 10:18 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krishna Manikandan,
Loic Poulain, Bjorn Andersson, Konrad Dybcio, Will Deacon,
Robin Murphy, Joerg Roedel (AMD)
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
iommu, linux-arm-kernel, Nabige Aala, Dmitry Baryshkov
Shikra (QCM2390) is a Qualcomm SoC based on the QCM2290 family that
reuses the same MDSS/DPU 6.5 hardware as QCM2290. This series enables
the display subsystem for Shikra by adding DT binding updates for MDSS,
DSI controller and DPU, arm64 defconfig enablement for the ILI7807S DSI
panel, and UBWC configuration mapping Shikra to qcm2290_data.
Driver and SMMU support are covered by the existing qcom,qcm2290-mdss
fallback compatible string — no separate drm/msm or IOMMU patches are
required.
Tested on Shikra CQM EVK board with ILI7807S DSI panel. Display
pipeline probes cleanly and panel renders correctly.
Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
Nabige Aala (3):
dt-bindings: display: msm: qcm2290: Add Shikra MDSS
arm64: defconfig: Enable ILI7807S DSI panel driver
soc: qcom: ubwc: Add Shikra UBWC config
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 4 ++++
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml | 7 +++++--
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml | 22 +++++++++++++++-------
arch/arm64/configs/defconfig | 1 +
drivers/soc/qcom/ubwc_config.c | 1 +
5 files changed, 26 insertions(+), 9 deletions(-)
---
Prerequisite-Message-Id: <20260518-ili7807s-panel-v1-0-d7b048163b1c@oss.qualcomm.com>
---
Changes in v3:
- Use a fallback compatible chain for qcom,shikra-dsi-ctrl
in dsi-controller-main.yaml instead of a standalone enum entry, with
qcom,qcm2290-dsi-ctrl and qcom,mdss-dsi-ctrl as fallbacks
- Replace oneOf in qcm2290-mdss patternProperties DSI compatible with
contains: qcom,qcm2290-dsi-ctrl to avoid duplicating full chain
validation already handled by dsi-controller-main.yaml
- Drop unnecessary select: block from qcom,qcm2290-mdss.yaml; default
dt-validate compatible matching is sufficient
- Remove self from qcom,qcm2290-mdss.yaml maintainers list
- Link to v2: https://patch.msgid.link/20260604-shikra-display-v2-0-b3c1b2b67edc@oss.qualcomm.com
Changes in v2:
- Drop drm/msm/mdss: Shikra support patch; driver reuse is handled via
the qcom,qcm2290-mdss fallback compatible string (per Dmitry's review)
- Drop iommu/arm-smmu: Shikra SMMU client table patch; not required with
fallback compatible approach
- Fix UBWC config to map qcom,shikra to qcm2290_data instead of
no_ubwc_data; Shikra shares UBWC support with QCM2290
- Refactor series from 5 patches to 3 patches
- Link to v1: https://patch.msgid.link/20260603-shikra-display-v1-0-aeac1b94faa7@oss.qualcomm.com
---
Nabige Aala (3):
dt-bindings: display: msm: qcm2290: Add Shikra MDSS
arm64: defconfig: Enable ILI7807S DSI panel driver
soc: qcom: ubwc: Add Shikra UBWC config
.../bindings/display/msm/dsi-controller-main.yaml | 4 ++++
.../bindings/display/msm/qcom,qcm2290-dpu.yaml | 7 +++++--
.../bindings/display/msm/qcom,qcm2290-mdss.yaml | 22 +++++++++++++++-------
arch/arm64/configs/defconfig | 1 +
drivers/soc/qcom/ubwc_config.c | 1 +
5 files changed, 26 insertions(+), 9 deletions(-)
---
base-commit: 3a34f9c13cc0688f8db2a0db8506bf8c0d90737d
change-id: 20260603-shikra-display-07767208fa90
Best regards,
--
Nabige Aala <nabige.aala@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v6 0/3] arm64: dts: rockchip: add Vicharak Axon board support
From: Krzysztof Kozlowski @ 2026-06-05 10:15 UTC (permalink / raw)
To: Hrushiraj Gandhi
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260601162143.170030-1-hrushirajg23@gmail.com>
On Mon, Jun 01, 2026 at 09:51:39PM +0530, Hrushiraj Gandhi wrote:
> This series adds initial device tree support for the Vicharak Axon
> single-board computer, which is based on the Rockchip RK3588 SoC.
>
> The Vicharak Axon is a feature-rich SBC targeting developer and embedded
> use cases. It ships with:
Slow down, please. One patchset per 24h.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] pinctrl: Move Airoha driver to dedicated directory
From: Lorenzo Bianconi @ 2026-06-05 9:49 UTC (permalink / raw)
To: Christian Marangi
Cc: Linus Walleij, Sean Wang, Matthias Brugger,
AngeloGioacchino Del Regno, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel
In-Reply-To: <20260605071233.28873-1-ansuelsmth@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 5747 bytes --]
> In preparation for additional SoC support, move the Airoha pinctrl driver
> for AN7581 SoC to a dedicated directory.
>
> This is to tidy things up and keep code organized without polluting the
> Mediatek driver directory.
>
> The driver doesn't depend on any generic or common code from the Mediatek
> codebase so it can be safely moved without any modification.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> MAINTAINERS | 2 +-
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/airoha/Kconfig | 20 +++++++++++++++++++
> drivers/pinctrl/airoha/Makefile | 3 +++
> .../{mediatek => airoha}/pinctrl-airoha.c | 0
> drivers/pinctrl/mediatek/Kconfig | 17 +---------------
> drivers/pinctrl/mediatek/Makefile | 1 -
> 8 files changed, 27 insertions(+), 18 deletions(-)
> create mode 100644 drivers/pinctrl/airoha/Kconfig
> create mode 100644 drivers/pinctrl/airoha/Makefile
> rename drivers/pinctrl/{mediatek => airoha}/pinctrl-airoha.c (100%)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 21c0ef0b9ce5..38bf92149a15 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21024,7 +21024,7 @@ M: Lorenzo Bianconi <lorenzo@kernel.org>
> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> F: Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml
> -F: drivers/pinctrl/mediatek/pinctrl-airoha.c
> +F: drivers/pinctrl/airoha/pinctrl-airoha.c
>
> PIN CONTROLLER - AMD
> M: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 03f2e3ee065f..e0babad31445 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -679,6 +679,7 @@ config PINCTRL_RP1
> multi function device.
>
> source "drivers/pinctrl/actions/Kconfig"
> +source "drivers/pinctrl/airoha/Kconfig"
> source "drivers/pinctrl/aspeed/Kconfig"
> source "drivers/pinctrl/bcm/Kconfig"
> source "drivers/pinctrl/berlin/Kconfig"
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index f7d5d5f76d0c..36c55858801f 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -66,6 +66,7 @@ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
> obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
>
> obj-y += actions/
> +obj-y += airoha/
> obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-y += bcm/
> obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
> diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
> new file mode 100644
> index 000000000000..03adaeae8fc3
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/Kconfig
> @@ -0,0 +1,20 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +menu "Airoha pinctrl drivers"
> + depends on ARCH_AIROHA || COMPILE_TEST
> +
> +config PINCTRL_AIROHA
> + tristate "Airoha EN7581 pin control"
> + depends on OF
> + depends on ARM64 || COMPILE_TEST
> + select PINMUX
> + select GENERIC_PINCONF
> + select GENERIC_PINCTRL_GROUPS
> + select GENERIC_PINMUX_FUNCTIONS
> + select GPIOLIB
> + select GPIOLIB_IRQCHIP
> + select REGMAP_MMIO
> + help
> + Say yes here to support pin controller and gpio driver
> + on Airoha EN7581 SoC.
> +
> +endmenu
> diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
> new file mode 100644
> index 000000000000..a25b744dd7a8
> --- /dev/null
> +++ b/drivers/pinctrl/airoha/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> similarity index 100%
> rename from drivers/pinctrl/mediatek/pinctrl-airoha.c
> rename to drivers/pinctrl/airoha/pinctrl-airoha.c
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index 4819617d9368..97980cc28b9c 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
> menu "MediaTek pinctrl drivers"
> - depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST
> + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST
>
> config EINT_MTK
> tristate "MediaTek External Interrupt Support"
> @@ -126,21 +126,6 @@ config PINCTRL_MT8127
> select PINCTRL_MTK
>
> # For ARMv8 SoCs
> -config PINCTRL_AIROHA
> - tristate "Airoha EN7581 pin control"
> - depends on OF
> - depends on ARM64 || COMPILE_TEST
> - select PINMUX
> - select GENERIC_PINCONF
> - select GENERIC_PINCTRL_GROUPS
> - select GENERIC_PINMUX_FUNCTIONS
> - select GPIOLIB
> - select GPIOLIB_IRQCHIP
> - select REGMAP_MMIO
> - help
> - Say yes here to support pin controller and gpio driver
> - on Airoha EN7581 SoC.
> -
> config PINCTRL_MT2712
> bool "MediaTek MT2712 pin control"
> depends on OF
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index ae765bd99965..6dc17b0c23f9 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -8,7 +8,6 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o
> obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o
>
> # SoC Drivers
> -obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
> obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
> obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
> obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH v7 6/6] media: mediatek: encoder: Add MT8196 encoder compatible data
From: Irui Wang @ 2026-06-05 9:35 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski, angelogioacchino.delregno,
nicolas.dufresne, Tiffany Lin, kyrie wu
Cc: Yunfei Dong, Maoguang Meng, Longfei Wang, Irui Wang,
Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com>
MT8196 encoder use common firmware interface, add compatible data to
support MT8196 encoding, and need set dma mask to support 34bit.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
---
.../vcodec/encoder/mtk_vcodec_enc_drv.c | 22 +++++++++++++++++++
.../vcodec/encoder/mtk_vcodec_enc_drv.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index 5f1feb3b07a6..bc6dfb564026 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -20,6 +20,8 @@
#include "mtk_vcodec_enc_pm.h"
#include "../common/mtk_vcodec_intr.h"
+#define VENC_DMA_BIT_MASK 34
+
static const struct mtk_video_fmt mtk_video_formats_output[] = {
{
.fourcc = V4L2_PIX_FMT_NV12M,
@@ -298,6 +300,9 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
goto err_res;
}
+ if (dev->venc_pdata->set_dma_bit_mask)
+ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(VENC_DMA_BIT_MASK));
+
mutex_init(&dev->enc_mutex);
mutex_init(&dev->dev_mutex);
spin_lock_init(&dev->dev_ctx_lock);
@@ -461,6 +466,22 @@ static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
.fw_init = mtk_vcodec_fw_scp_init,
};
+static const struct mtk_vcodec_enc_pdata mt8196_pdata = {
+ .venc_model_num = 8196,
+ .capture_formats = mtk_video_formats_capture_h264,
+ .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
+ .output_formats = mtk_video_formats_output,
+ .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
+ .min_bitrate = 64,
+ .max_bitrate = 100000000,
+ .core_id = VENC_SYS,
+ .uses_common_fw_iface = true,
+ .set_dma_bit_mask = true,
+ .fw_type = VCP,
+ .fw_init = mtk_vcodec_fw_vcp_init,
+ .ipi_id = VCP_IPI_ENCODER,
+};
+
static const struct of_device_id mtk_vcodec_enc_match[] = {
{.compatible = "mediatek,mt8173-vcodec-enc",
.data = &mt8173_avc_pdata},
@@ -470,6 +491,7 @@ static const struct of_device_id mtk_vcodec_enc_match[] = {
{.compatible = "mediatek,mt8188-vcodec-enc", .data = &mt8188_pdata},
{.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
{.compatible = "mediatek,mt8195-vcodec-enc", .data = &mt8195_pdata},
+ {.compatible = "mediatek,mt8196-vcodec-enc", .data = &mt8196_pdata},
{},
};
MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index 8a69168c350e..1aad27008ce6 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -32,6 +32,7 @@
* @core_id: stand for h264 or vp8 encode index
* @uses_34bit: whether the encoder uses 34-bit iova
* @uses_common_fw_iface: whether the encoder uses common driver interface
+ * @set_dma_bit_mask: whether the encoder need set extra DMA bit mask
* @fw_type: firmware type (VPU, SCP, or VCP)
* @fw_init: firmware-specific initialization callback
* @ipi_id: IPI ID for encoder communication with firmware
@@ -48,6 +49,7 @@ struct mtk_vcodec_enc_pdata {
u8 core_id;
bool uses_34bit;
bool uses_common_fw_iface;
+ bool set_dma_bit_mask;
enum mtk_vcodec_fw_type fw_type;
struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_use);
int ipi_id;
--
2.45.2
^ permalink raw reply related
* [PATCH v7 5/6] media: mediatek: encoder: Add support for VCP encode process
From: Irui Wang @ 2026-06-05 9:35 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski, angelogioacchino.delregno,
nicolas.dufresne, Tiffany Lin, kyrie wu
Cc: Yunfei Dong, Maoguang Meng, Longfei Wang, Irui Wang,
Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com>
Adapt the encoder driver to support VCP firmware interface.
Use platform data fw_type to identify VCP firmware and perform
VCP-specific operations:
- Allocate RC buffers using the VCP device
- Send shared memory address to VCP firmware
- Map the encoder VSI address to the CPU address space using the
VCP shared memory address.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
---
.../mediatek/vcodec/common/mtk_vcodec_fw.c | 6 +++++
.../mediatek/vcodec/common/mtk_vcodec_fw.h | 1 +
.../vcodec/common/mtk_vcodec_fw_priv.h | 1 +
.../vcodec/common/mtk_vcodec_fw_vcp.c | 6 +++++
.../vcodec/encoder/venc/venc_common_if.c | 22 ++++++++++++++-----
.../mediatek/vcodec/encoder/venc_vpu_if.c | 16 ++++++++++++--
6 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index 9df64200d933..7619ccd1f538 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -90,3 +90,9 @@ int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw)
return fw->type;
}
EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type);
+
+struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw)
+{
+ return fw->ops->get_fw_dev(fw);
+}
+EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_dev);
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
index 142e2e87905c..8ff6fcc114e3 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.h
@@ -42,5 +42,6 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id,
void *buf, unsigned int len, unsigned int wait);
int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw);
int mtk_vcodec_fw_get_ipi(enum mtk_vcodec_fw_type type, int hw_id);
+struct device *mtk_vcodec_fw_get_dev(struct mtk_vcodec_fw *fw);
#endif /* _MTK_VCODEC_FW_H_ */
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
index 0a2a9b010244..710c83c871f4 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_priv.h
@@ -29,6 +29,7 @@ struct mtk_vcodec_fw_ops {
int (*ipi_send)(struct mtk_vcodec_fw *fw, int id, void *buf,
unsigned int len, unsigned int wait);
void (*release)(struct mtk_vcodec_fw *fw);
+ struct device *(*get_fw_dev)(struct mtk_vcodec_fw *fw);
};
#if IS_ENABLED(CONFIG_VIDEO_MEDIATEK_VCODEC_VPU)
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
index 061a61bda33f..72627fef0ac5 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw_vcp.c
@@ -494,6 +494,11 @@ static void mtk_vcodec_vcp_release(struct mtk_vcodec_fw *fw)
fw->vcp->is_register_done = false;
}
+static struct device *mtk_vcodec_vcp_get_fw_dev(struct mtk_vcodec_fw *fw)
+{
+ return fw->vcp->vcp_device->dev;
+}
+
static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
.load_firmware = mtk_vcodec_vcp_load_firmware,
.get_vdec_capa = mtk_vcodec_vcp_get_vdec_capa,
@@ -501,6 +506,7 @@ static const struct mtk_vcodec_fw_ops mtk_vcodec_vcp_msg = {
.ipi_register = mtk_vcodec_vcp_set_ipi_register,
.ipi_send = mtk_vcodec_vcp_ipi_send,
.release = mtk_vcodec_vcp_release,
+ .get_fw_dev = mtk_vcodec_vcp_get_fw_dev,
};
struct mtk_vcodec_fw *mtk_vcodec_fw_vcp_init(void *priv, enum mtk_vcodec_fw_use fw_use)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
index 0efb13aef8d6..5ee138f0b2e7 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
@@ -481,7 +481,11 @@ static void venc_free_rc_buf(struct venc_inst *inst,
int i;
struct device *dev;
- dev = &inst->ctx->dev->plat_dev->dev;
+ if (inst->ctx->dev->venc_pdata->fw_type == VCP)
+ dev = mtk_vcodec_fw_get_dev(inst->ctx->dev->fw_handler);
+ else
+ dev = &inst->ctx->dev->plat_dev->dev;
+
mtk_venc_mem_free(inst, dev, &bufs->rc_code);
for (i = 0; i < core_num; i++)
@@ -530,12 +534,18 @@ static int venc_alloc_rc_buf(struct venc_inst *inst,
struct device *dev;
void *tmp_va;
- dev = &inst->ctx->dev->plat_dev->dev;
- if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
- return -ENOMEM;
+ if (inst->ctx->dev->venc_pdata->fw_type == VCP) {
+ dev = mtk_vcodec_fw_get_dev(fw);
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+ return -ENOMEM;
+ } else {
+ dev = &inst->ctx->dev->plat_dev->dev;
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+ return -ENOMEM;
- tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
- memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+ tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
+ memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+ }
for (i = 0; i < core_num; i++) {
if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i]))
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
index 7772b8442ebc..1da9043fd4f6 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_vpu_if.c
@@ -8,16 +8,26 @@
#include "venc_ipi_msg.h"
#include "venc_vpu_if.h"
+#define VSI_OFFSET_MASK 0x0FFFFFFF
+
static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data)
{
const struct venc_vpu_ipi_msg_init_comm *msg = data;
struct mtk_vcodec_fw *fw = vpu->ctx->dev->fw_handler;
+ u64 pa_start, vsi_offset;
vpu->inst_addr = msg->init_ack.vpu_inst_addr;
- vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, vpu->inst_addr);
+
+ if (vpu->ctx->dev->venc_pdata->fw_type == VCP) {
+ pa_start = (u64)fw->vcp->iova_addr;
+ vsi_offset = (msg->vpu_vsi_addr & VSI_OFFSET_MASK) - (pa_start & VSI_OFFSET_MASK);
+ vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, ENCODER_MEM) + vsi_offset;
+ } else {
+ vpu->vsi = mtk_vcodec_fw_map_dm_addr(fw, msg->vpu_vsi_addr);
+ }
/* Firmware version field value is unspecified on MT8173. */
- if (mtk_vcodec_fw_get_type(fw) == VPU)
+ if (vpu->ctx->dev->venc_pdata->fw_type == VPU)
return;
/* Check firmware version. */
@@ -155,6 +165,8 @@ int vpu_enc_init(struct venc_vpu_inst *vpu)
out.base.venc_inst = (unsigned long)vpu;
if (MTK_ENC_DRV_IS_COMM(vpu->ctx)) {
out.codec_type = vpu->ctx->q_data[MTK_Q_DATA_DST].fmt->fourcc;
+ if (vpu->ctx->dev->venc_pdata->fw_type == VCP)
+ out.shared_iova = vpu->ctx->dev->fw_handler->vcp->iova_addr;
msg_size = sizeof(struct venc_ap_ipi_msg_init_comm);
} else {
msg_size = sizeof(struct venc_ap_ipi_msg_init);
--
2.45.2
^ permalink raw reply related
* [PATCH v7 3/6] media: mediatek: encoder: Add a new encoder driver interface
From: Irui Wang @ 2026-06-05 9:35 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski, angelogioacchino.delregno,
nicolas.dufresne, Tiffany Lin, kyrie wu
Cc: Yunfei Dong, Maoguang Meng, Longfei Wang, Irui Wang,
Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com>
Introduce a new encoder kernel driver interface to ensure compatibility
with the updated encoder software driver running in firmware.
The new driver interface is expected to support more encoder formats,
share more encode parameters between kernel and firmware.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
.../platform/mediatek/vcodec/encoder/Makefile | 1 +
.../mediatek/vcodec/encoder/mtk_vcodec_enc.c | 14 +-
.../vcodec/encoder/mtk_vcodec_enc_drv.h | 8 +-
.../vcodec/encoder/venc/venc_common_if.c | 674 ++++++++++++++++++
.../vcodec/encoder/venc/venc_h264_if.c | 8 +-
.../mediatek/vcodec/encoder/venc_drv_if.h | 11 +-
6 files changed, 698 insertions(+), 18 deletions(-)
create mode 100644 drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/Makefile b/drivers/media/platform/mediatek/vcodec/encoder/Makefile
index e621b5b7e5e6..9d3229d56e39 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/Makefile
+++ b/drivers/media/platform/mediatek/vcodec/encoder/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) += mtk-vcodec-enc.o
mtk-vcodec-enc-y := venc/venc_vp8_if.o \
venc/venc_h264_if.o \
+ venc/venc_common_if.o \
mtk_vcodec_enc.o \
mtk_vcodec_enc_drv.o \
mtk_vcodec_enc_pm.o \
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
index fcf0e4f90429..b2f911746c01 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
@@ -81,11 +81,11 @@ static int vidioc_venc_s_ctrl(struct v4l2_ctrl *ctrl)
break;
case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_PROFILE val = %d", ctrl->val);
- p->h264_profile = ctrl->val;
+ p->profile = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_LEVEL val = %d", ctrl->val);
- p->h264_level = ctrl->val;
+ p->level = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:
mtk_v4l2_venc_dbg(2, ctx, "V4L2_CID_MPEG_VIDEO_H264_I_PERIOD val = %d", ctrl->val);
@@ -367,8 +367,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ctx *ctx,
mtk_v4l2_venc_err(ctx, "Unsupported fourcc =%d", q_data_src->fmt->fourcc);
break;
}
- param->h264_profile = enc_params->h264_profile;
- param->h264_level = enc_params->h264_level;
+ param->profile = enc_params->profile;
+ param->level = enc_params->level;
/* Config visible resolution */
param->width = q_data_src->visible_width;
@@ -384,8 +384,8 @@ static void mtk_venc_set_param(struct mtk_vcodec_enc_ctx *ctx,
mtk_v4l2_venc_dbg(0, ctx,
"fmt 0x%x, P/L %d/%d w/h %d/%d buf %d/%d fps/bps %d/%d gop %d i_per %d",
- param->input_yuv_fmt, param->h264_profile,
- param->h264_level, param->width, param->height,
+ param->input_yuv_fmt, param->profile,
+ param->level, param->width, param->height,
param->buf_width, param->buf_height,
param->frm_rate, param->bitrate,
param->gop_size, param->intra_period);
@@ -1139,6 +1139,8 @@ static void mtk_venc_worker(struct work_struct *work)
frm_buf.fb_addr[i].size =
(size_t)src_buf->vb2_buf.planes[i].length;
}
+ frm_buf.num_planes = src_buf->vb2_buf.num_planes;
+
bs_buf.va = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
bs_buf.dma_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
bs_buf.size = (size_t)dst_buf->vb2_buf.planes[0].length;
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index 6c7e8da6d8ee..029133e48073 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -77,8 +77,8 @@ enum mtk_encode_param {
* @framerate_denom: frame rate denominator. ex: framerate_num=30 and
* framerate_denom=1 means FPS is 30
* @h264_max_qp: Max value for H.264 quantization parameter
- * @h264_profile: V4L2 defined H.264 profile
- * @h264_level: V4L2 defined H.264 level
+ * @profile: V4L2 defined profile
+ * @level: V4L2 defined level
* @force_intra: force/insert intra frame
*/
struct mtk_enc_params {
@@ -92,8 +92,8 @@ struct mtk_enc_params {
unsigned int framerate_num;
unsigned int framerate_denom;
unsigned int h264_max_qp;
- unsigned int h264_profile;
- unsigned int h264_level;
+ unsigned int profile;
+ unsigned int level;
unsigned int force_intra;
};
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
new file mode 100644
index 000000000000..0efb13aef8d6
--- /dev/null
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_common_if.c
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include "../mtk_vcodec_enc.h"
+#include "../mtk_vcodec_enc_drv.h"
+#include "../venc_drv_base.h"
+#include "../venc_drv_if.h"
+#include "../venc_vpu_if.h"
+#include "../../common/mtk_vcodec_intr.h"
+#include "../../common/mtk_vcodec_util.h"
+
+#define SEQ_HEADER_SIZE 1024
+#define PPS_SIZE 128
+#define MAX_DPB_SIZE 16
+#define MAX_VENC_CORE 3
+#define VENC_CONFIG_LENGTH 115
+#define VENC_CONFIG_DATA 128
+#define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098
+
+/**
+ * enum venc_bs_mode - encode bitstream mode
+ * @VENC_BS_MODE_SPS: encode sps
+ * @VENC_BS_MODE_PPS: encode pps
+ * @VENC_BS_MODE_VPS: encode vps
+ * @VENC_BS_MODE_SEQ_HDR: encode sequence header
+ * @VENC_BS_MODE_FRAME: encode frame
+ * @VENC_BS_MODE_FRAME_FINAL: encode final frame
+ * @VENC_BS_MODE_MAX: max value
+ */
+enum venc_bs_mode {
+ VENC_BS_MODE_SPS = 0,
+ VENC_BS_MODE_PPS,
+ VENC_BS_MODE_VPS,
+ VENC_BS_MODE_SEQ_HDR,
+ VENC_BS_MODE_FRAME,
+ VENC_BS_MODE_FRAME_FINAL,
+ VENC_BS_MODE_MAX
+};
+
+/**
+ * struct venc_config - Structure for encoder configuration
+ * AP-W/R : AP is writer/reader on this item
+ * MCU-W/R: MCU is write/reader on this item
+ * @input_fourcc: input format fourcc
+ * @bitrate: target bitrate (in bps)
+ * @pic_w: visible width of resolution
+ * @pic_h: visible height of resolution
+ * @buf_w: buffer alignment width of resolution
+ * @buf_h: buffer alignment height of resolution
+ * @gop_size: group of picture size (IDR frame period)
+ * @intra_period: I frame period
+ * @framerate: frame rate in fps
+ * @profile: profile_idc in SPS
+ * @level: level_idc in SPS
+ * @core_num: encoder core num
+ * @dpb_size: encode dpb size
+ * @reserved: reserved fields config
+ */
+struct venc_config {
+ __u32 input_fourcc;
+ __u32 bitrate;
+ __u32 pic_w;
+ __u32 pic_h;
+ __u32 buf_w;
+ __u32 buf_h;
+ __u32 gop_size;
+ __u32 intra_period;
+ __u32 framerate;
+ __u32 profile;
+ __u32 level;
+ __u32 core_num;
+ __u32 dpb_size;
+ __u32 reserved[VENC_CONFIG_LENGTH];
+};
+
+/**
+ * struct venc_config_data - Structure for configuration data
+ * @config_data: extended configuration data besides the basic configuration
+ */
+struct venc_config_data {
+ unsigned int config_data[VENC_CONFIG_DATA];
+};
+
+/**
+ * struct venc_work_buf - Structure for working buffer information
+ * AP-W/R : AP is writer/reader on this item
+ * MCU-W/R: MCU is write/reader on this item
+ * @iova: IO virtual address
+ * @pa: physical address
+ * @pa_64: for 64bit pa padding
+ * @va: virtual address
+ * @va_padding: for 64bit va padding
+ * @size: buffer size
+ * @size_padding: for 64bit size padding
+ */
+struct venc_work_buf {
+ unsigned long long iova;
+ union {
+ unsigned int pa;
+ unsigned long long pa_64;
+ };
+ union {
+ void *va;
+ unsigned long long va_padding;
+ };
+ union {
+ unsigned int size;
+ unsigned long long size_padding;
+ };
+};
+
+/**
+ * struct venc_work_buf_list - Structure for encode working buffer list
+ * @rc_code: RC code buffer
+ * @rc_info: RC info buffer
+ * @luma: luma buffer
+ * @chroma: chroma buffer
+ * @sub_luma: sub luma buffer
+ * @sub_write: sub write buffer
+ * @col_mv: col_mv buffer
+ * @wpp: wpp buffer
+ * @wpp_nbm: wpp nbm buffer
+ * @skip_frame: skip frame buffer
+ */
+struct venc_work_buf_list {
+ struct venc_work_buf rc_code;
+ struct venc_work_buf rc_info[MAX_VENC_CORE];
+ struct venc_work_buf luma[MAX_DPB_SIZE];
+ struct venc_work_buf chroma[MAX_DPB_SIZE];
+ struct venc_work_buf sub_luma[MAX_DPB_SIZE];
+ struct venc_work_buf sub_write[MAX_DPB_SIZE];
+ struct venc_work_buf col_mv[MAX_DPB_SIZE];
+ struct venc_work_buf wpp[MAX_VENC_CORE];
+ struct venc_work_buf wpp_nbm[MAX_VENC_CORE];
+ struct venc_work_buf skip_frame;
+};
+
+/**
+ * struct venc_info - Structure for encode frame and bs information
+ * @fb_addr: frame buffer address array
+ * @fb_size: frame buffer size array
+ * @bs_addr: bitstream buffer address
+ * @bs_size: bitstream buffer size
+ */
+struct venc_info {
+ unsigned long long fb_addr[VIDEO_MAX_PLANES];
+ unsigned int fb_size[VIDEO_MAX_PLANES];
+ unsigned long long bs_addr;
+ unsigned long long bs_size;
+};
+
+/**
+ * struct venc_vsi - Structure for VCP driver control and info share
+ * AP-W/R : AP is writer/reader on this item
+ * VCP-W/R: VCP is write/reader on this item
+ * @config: encoder configuration
+ * @data: encoder configuration data
+ * @bufs: encoder working buffers
+ * @venc: encoder information
+ */
+struct venc_vsi {
+ struct venc_config config;
+ struct venc_config_data data;
+ struct venc_work_buf_list bufs;
+ struct venc_info venc;
+};
+
+/**
+ * struct venc_inst - Structure for encoder instance
+ * @hw_base: hardware io address
+ * @pps_buf: PPS buffer
+ * @seq_buf: sequence header buffer
+ * @work_buf_allocated: work buffer allocated or not
+ * @frm_cnt: encoded frame count
+ * @skip_frm_cnt: encoded skip frame count
+ * @prepend_hdr: prepend header flag
+ * @vpu_inst: vpu instance
+ * @vsi: encode vsi
+ * @ctx: encoder context
+ */
+struct venc_inst {
+ void __iomem *hw_base;
+ struct mtk_vcodec_mem pps_buf;
+ struct mtk_vcodec_mem seq_buf;
+ bool work_buf_allocated;
+ unsigned int frm_cnt;
+ unsigned int skip_frm_cnt;
+ unsigned int prepend_hdr;
+ struct venc_vpu_inst vpu_inst;
+ struct venc_vsi *vsi;
+ struct mtk_vcodec_enc_ctx *ctx;
+};
+
+static int venc_init(struct mtk_vcodec_enc_ctx *ctx)
+{
+ int ret = 0;
+ struct venc_inst *inst;
+
+ inst = kzalloc_obj(*inst, GFP_KERNEL);
+ if (!inst)
+ return -ENOMEM;
+
+ inst->ctx = ctx;
+ inst->vpu_inst.ctx = ctx;
+ inst->vpu_inst.id = ctx->dev->venc_pdata->ipi_id;
+ inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx->dev->reg_base, VENC_SYS);
+
+ ret = vpu_enc_init(&inst->vpu_inst);
+ inst->vsi = (struct venc_vsi *)inst->vpu_inst.vsi;
+
+ if (ret) {
+ kfree(inst);
+ return ret;
+ }
+
+ ctx->drv_handle = inst;
+
+ return 0;
+}
+
+static inline u32 venc_read_reg(struct venc_inst *inst, u32 addr)
+{
+ return readl(inst->hw_base + addr);
+}
+
+static unsigned int venc_wait_encode_done(struct venc_inst *inst)
+{
+ unsigned int irq_status = 0;
+ struct mtk_vcodec_enc_ctx *ctx = (struct mtk_vcodec_enc_ctx *)inst->ctx;
+
+ if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED,
+ WAIT_INTR_TIMEOUT_MS, 0)) {
+ irq_status = ctx->irq_status;
+ mtk_venc_debug(ctx, "irq_status %x <-", irq_status);
+ }
+ return irq_status;
+}
+
+static void venc_set_bufs(struct venc_inst *inst,
+ struct venc_frm_buf *frm_buf,
+ struct mtk_vcodec_mem *bs_buf)
+{
+ unsigned int i;
+
+ if (frm_buf) {
+ for (i = 0; i < frm_buf->num_planes; i++) {
+ inst->vsi->venc.fb_addr[i] = frm_buf->fb_addr[i].dma_addr;
+ inst->vsi->venc.fb_size[i] = frm_buf->fb_addr[i].size;
+ mtk_venc_debug(inst->ctx, "%s: fb_buf[%d]: %llx(%d)\n",
+ __func__, i,
+ inst->vsi->venc.fb_addr[i],
+ inst->vsi->venc.fb_size[i]);
+ }
+ }
+
+ if (bs_buf) {
+ inst->vsi->venc.bs_addr = bs_buf->dma_addr;
+ inst->vsi->venc.bs_size = bs_buf->size;
+ mtk_venc_debug(inst->ctx, "%s: bs_buf: %llx(%d)\n",
+ __func__,
+ inst->vsi->venc.bs_addr,
+ (unsigned int)inst->vsi->venc.bs_size);
+ }
+}
+
+static int venc_encode_sps(struct venc_inst *inst,
+ struct mtk_vcodec_mem *bs_buf,
+ unsigned int *bs_size)
+{
+ int ret = 0;
+ unsigned int irq_status;
+
+ venc_set_bufs(inst, NULL, bs_buf);
+ ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_SPS, NULL, bs_buf, NULL);
+ if (ret)
+ return ret;
+
+ irq_status = venc_wait_encode_done(inst);
+ if (irq_status != MTK_VENC_IRQ_STATUS_SPS) {
+ mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_SPS);
+ return -EINVAL;
+ }
+
+ *bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+ mtk_venc_debug(inst->ctx, "sps bs size %d <-", *bs_size);
+
+ return ret;
+}
+
+static int venc_encode_pps(struct venc_inst *inst,
+ struct mtk_vcodec_mem *bs_buf,
+ unsigned int *bs_size)
+{
+ int ret = 0;
+ unsigned int irq_status;
+
+ venc_set_bufs(inst, NULL, bs_buf);
+ ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_PPS, NULL, bs_buf, NULL);
+ if (ret)
+ return ret;
+
+ irq_status = venc_wait_encode_done(inst);
+ if (irq_status != MTK_VENC_IRQ_STATUS_PPS) {
+ mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_PPS);
+ return -EINVAL;
+ }
+
+ *bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+ mtk_venc_debug(inst->ctx, "pps bs size %d <-", *bs_size);
+
+ return ret;
+}
+
+static int venc_encode_header(struct venc_inst *inst,
+ struct mtk_vcodec_mem *bs_buf,
+ unsigned int *bs_size)
+{
+ int ret = 0;
+ unsigned int bs_size_sps;
+ unsigned int bs_size_pps;
+
+ ret = venc_encode_sps(inst, bs_buf, &bs_size_sps);
+ if (ret)
+ return ret;
+
+ ret = venc_encode_pps(inst, &inst->pps_buf, &bs_size_pps);
+ if (ret)
+ return ret;
+
+ memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps);
+ *bs_size = bs_size_sps + bs_size_pps;
+
+ return ret;
+}
+
+static int venc_encode_frame(struct venc_inst *inst,
+ struct venc_frm_buf *frm_buf,
+ struct mtk_vcodec_mem *bs_buf,
+ unsigned int *bs_size)
+{
+ int ret = 0;
+ unsigned int irq_status;
+
+ venc_set_bufs(inst, frm_buf, bs_buf);
+ ret = vpu_enc_encode(&inst->vpu_inst, VENC_BS_MODE_FRAME, frm_buf, bs_buf, NULL);
+ if (ret)
+ return ret;
+
+ irq_status = venc_wait_encode_done(inst);
+ if (irq_status != MTK_VENC_IRQ_STATUS_FRM) {
+ mtk_venc_err(inst->ctx, "expect irq status %d", MTK_VENC_IRQ_STATUS_FRM);
+ return -EINVAL;
+ }
+
+ *bs_size = venc_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
+
+ ++inst->frm_cnt;
+
+ return ret;
+}
+
+static int venc_encode(void *handle,
+ enum venc_start_opt opt,
+ struct venc_frm_buf *frm_buf,
+ struct mtk_vcodec_mem *bs_buf,
+ struct venc_done_result *result)
+{
+ int ret = 0;
+ struct venc_inst *inst = (struct venc_inst *)handle;
+ struct mtk_vcodec_enc_ctx *ctx;
+ unsigned int bs_size_hdr;
+
+ if (WARN_ON(!inst || !inst->vsi))
+ return -EINVAL;
+
+ ctx = inst->ctx;
+
+ mtk_venc_debug(ctx, "%s: opt: %d\n", __func__, opt);
+
+ enable_irq(ctx->dev->enc_irq);
+ switch (opt) {
+ case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: {
+ ret = venc_encode_header(inst, bs_buf, &bs_size_hdr);
+ if (ret)
+ goto encode_err;
+
+ result->bs_size = bs_size_hdr;
+ result->is_key_frm = false;
+ break;
+ }
+
+ case VENC_START_OPT_ENCODE_FRAME: {
+ if (!inst->prepend_hdr) {
+ ret = venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size);
+ if (ret)
+ goto encode_err;
+
+ result->is_key_frm = inst->vpu_inst.is_key_frm;
+ break;
+ }
+
+ ret = venc_encode_header(inst, &inst->seq_buf, &bs_size_hdr);
+ if (ret)
+ goto encode_err;
+
+ ret = venc_encode_frame(inst, frm_buf, bs_buf, &result->bs_size);
+ if (ret)
+ goto encode_err;
+
+ memmove(bs_buf->va + bs_size_hdr, bs_buf->va, result->bs_size);
+ memcpy(bs_buf->va, inst->seq_buf.va, bs_size_hdr);
+ result->bs_size += bs_size_hdr;
+
+ inst->prepend_hdr = 0;
+ result->is_key_frm = inst->vpu_inst.is_key_frm;
+ break;
+ }
+
+ default:
+ mtk_venc_err(inst->ctx, "venc_opt %d not supported", opt);
+ ret = -EINVAL;
+ break;
+ }
+
+encode_err:
+ disable_irq(ctx->dev->enc_irq);
+ mtk_venc_debug(ctx, "opt %d, return %d", opt, ret);
+
+ return ret;
+}
+
+static int mtk_venc_mem_alloc(struct venc_inst *inst,
+ struct device *dev,
+ struct venc_work_buf *buf)
+{
+ dma_addr_t dma_addr;
+
+ if (WARN_ON(!dev || !buf))
+ return -EINVAL;
+
+ if (buf->size == 0)
+ return 0;
+
+ buf->va = dma_alloc_coherent(dev, buf->size, &dma_addr, GFP_KERNEL);
+ if (!buf->va)
+ return -ENOMEM;
+
+ buf->iova = (unsigned long long)dma_addr;
+
+ mtk_venc_debug(inst->ctx, "allocate buffer, size: %d, va: %p, iova: 0x%llx",
+ buf->size, buf->va, buf->iova);
+
+ return 0;
+}
+
+static void mtk_venc_mem_free(struct venc_inst *inst,
+ struct device *dev,
+ struct venc_work_buf *buf)
+{
+ if (WARN_ON(!dev || !buf))
+ return;
+
+ if (!buf->va)
+ return;
+
+ mtk_venc_debug(inst->ctx, "free buffer, size: %d, va: %p, iova: 0x%llx",
+ buf->size, buf->va, buf->iova);
+
+ dma_free_coherent(dev, buf->size, buf->va, buf->iova);
+ buf->va = NULL;
+ buf->iova = 0;
+ buf->size = 0;
+}
+
+static void venc_free_rc_buf(struct venc_inst *inst,
+ struct venc_work_buf_list *bufs,
+ unsigned int core_num)
+{
+ int i;
+ struct device *dev;
+
+ dev = &inst->ctx->dev->plat_dev->dev;
+ mtk_venc_mem_free(inst, dev, &bufs->rc_code);
+
+ for (i = 0; i < core_num; i++)
+ mtk_venc_mem_free(inst, dev, &bufs->rc_info[i]);
+}
+
+static void venc_free_work_buf(struct venc_inst *inst)
+{
+ int i;
+ struct venc_work_buf_list *bufs = &inst->vsi->bufs;
+ unsigned int core_num = inst->vsi->config.core_num;
+ unsigned int dpb_size = inst->vsi->config.dpb_size;
+ struct device *dev;
+
+ if (bufs->rc_code.va)
+ venc_free_rc_buf(inst, bufs, core_num);
+
+ dev = &inst->ctx->dev->plat_dev->dev;
+
+ for (i = 0; i < core_num; i++) {
+ mtk_venc_mem_free(inst, dev, &bufs->wpp[i]);
+ mtk_venc_mem_free(inst, dev, &bufs->wpp_nbm[i]);
+ }
+
+ for (i = 0; i < dpb_size; i++) {
+ mtk_venc_mem_free(inst, dev, &bufs->luma[i]);
+ mtk_venc_mem_free(inst, dev, &bufs->chroma[i]);
+ mtk_venc_mem_free(inst, dev, &bufs->sub_luma[i]);
+ mtk_venc_mem_free(inst, dev, &bufs->sub_write[i]);
+ mtk_venc_mem_free(inst, dev, &bufs->col_mv[i]);
+ }
+
+ if (inst->pps_buf.va)
+ mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf);
+
+ if (inst->seq_buf.va)
+ mtk_vcodec_mem_free(inst->ctx, &inst->seq_buf);
+}
+
+static int venc_alloc_rc_buf(struct venc_inst *inst,
+ struct venc_work_buf_list *bufs,
+ unsigned int core_num)
+{
+ int i;
+ struct mtk_vcodec_fw *fw = inst->ctx->dev->fw_handler;
+ struct device *dev;
+ void *tmp_va;
+
+ dev = &inst->ctx->dev->plat_dev->dev;
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_code))
+ return -ENOMEM;
+
+ tmp_va = mtk_vcodec_fw_map_dm_addr(fw, bufs->rc_code.pa);
+ memcpy(bufs->rc_code.va, tmp_va, bufs->rc_code.size);
+
+ for (i = 0; i < core_num; i++) {
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->rc_info[i]))
+ goto err_rc_buf;
+ }
+
+ return 0;
+
+err_rc_buf:
+ venc_free_rc_buf(inst, bufs, core_num);
+
+ return -ENOMEM;
+}
+
+static int venc_alloc_work_buf(struct venc_inst *inst)
+{
+ int i, ret;
+ struct venc_work_buf_list *bufs = &inst->vsi->bufs;
+ unsigned int core_num = inst->vsi->config.core_num;
+ unsigned int dpb_size = inst->vsi->config.dpb_size;
+ struct device *dev;
+
+ if (bufs->rc_code.size != 0) {
+ ret = venc_alloc_rc_buf(inst, bufs, core_num);
+ if (ret) {
+ mtk_venc_err(inst->ctx, "cannot allocate rc buf");
+ return -ENOMEM;
+ }
+ }
+
+ dev = &inst->ctx->dev->plat_dev->dev;
+
+ for (i = 0; i < core_num; i++) {
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->wpp[i]) ||
+ mtk_venc_mem_alloc(inst, dev, &bufs->wpp_nbm[i]))
+ goto err_alloc;
+ }
+
+ for (i = 0; i < dpb_size; i++) {
+ if (mtk_venc_mem_alloc(inst, dev, &bufs->luma[i]) ||
+ mtk_venc_mem_alloc(inst, dev, &bufs->chroma[i]) ||
+ mtk_venc_mem_alloc(inst, dev, &bufs->sub_luma[i]) ||
+ mtk_venc_mem_alloc(inst, dev, &bufs->sub_write[i]) ||
+ mtk_venc_mem_alloc(inst, dev, &bufs->col_mv[i]))
+ goto err_alloc;
+ }
+
+ /* the pps_buf and seq_buf are used by AP side only */
+ inst->pps_buf.size = PPS_SIZE;
+ ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf);
+ if (ret) {
+ mtk_venc_err(inst->ctx, "cannot allocate pps_buf");
+ goto err_alloc;
+ }
+
+ inst->seq_buf.size = SEQ_HEADER_SIZE;
+ ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->seq_buf);
+ if (ret) {
+ mtk_venc_err(inst->ctx, "cannot allocate seq_buf");
+ goto err_alloc;
+ }
+ return 0;
+
+err_alloc:
+ venc_free_work_buf(inst);
+ return -ENOMEM;
+}
+
+static int venc_set_param(void *handle,
+ enum venc_set_param_type type,
+ struct venc_enc_param *enc_prm)
+{
+ int ret = 0;
+ struct venc_inst *inst = (struct venc_inst *)handle;
+
+ switch (type) {
+ case VENC_SET_PARAM_ENC:
+ if (WARN_ON(!inst->vsi))
+ return -EINVAL;
+ inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
+ inst->vsi->config.bitrate = enc_prm->bitrate;
+ inst->vsi->config.pic_w = enc_prm->width;
+ inst->vsi->config.pic_h = enc_prm->height;
+ inst->vsi->config.buf_w = enc_prm->buf_width;
+ inst->vsi->config.buf_h = enc_prm->buf_height;
+ inst->vsi->config.gop_size = enc_prm->gop_size;
+ inst->vsi->config.framerate = enc_prm->frm_rate;
+ inst->vsi->config.intra_period = enc_prm->intra_period;
+ inst->vsi->config.profile = enc_prm->profile;
+ inst->vsi->config.level = enc_prm->level;
+
+ ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
+ if (ret)
+ break;
+
+ if (inst->work_buf_allocated) {
+ venc_free_work_buf(inst);
+ inst->work_buf_allocated = false;
+ }
+ ret = venc_alloc_work_buf(inst);
+ if (ret)
+ break;
+ inst->work_buf_allocated = true;
+ break;
+ case VENC_SET_PARAM_PREPEND_HEADER:
+ inst->prepend_hdr = 1;
+ break;
+ default:
+ ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
+ break;
+ }
+
+ return ret;
+}
+
+static int venc_deinit(void *handle)
+{
+ int ret = 0;
+ struct venc_inst *inst = (struct venc_inst *)handle;
+
+ ret = vpu_enc_deinit(&inst->vpu_inst);
+
+ if (inst->work_buf_allocated)
+ venc_free_work_buf(inst);
+
+ kfree(inst);
+
+ return ret;
+}
+
+const struct venc_common_if venc_if = {
+ .init = venc_init,
+ .encode = venc_encode,
+ .set_param = venc_set_param,
+ .deinit = venc_deinit,
+};
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
index d2f4d732d2f7..320c505cdb21 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc/venc_h264_if.c
@@ -723,9 +723,9 @@ static void h264_enc_set_vsi_configs(struct venc_h264_inst *inst,
inst->vsi->config.framerate = enc_prm->frm_rate;
inst->vsi->config.intra_period = enc_prm->intra_period;
inst->vsi->config.profile =
- h264_get_profile(inst, enc_prm->h264_profile);
+ h264_get_profile(inst, enc_prm->profile);
inst->vsi->config.level =
- h264_get_level(inst, enc_prm->h264_level);
+ h264_get_level(inst, enc_prm->level);
inst->vsi->config.wfd = 0;
}
@@ -742,9 +742,9 @@ static void h264_enc_set_vsi_34_configs(struct venc_h264_inst *inst,
inst->vsi_34->config.framerate = enc_prm->frm_rate;
inst->vsi_34->config.intra_period = enc_prm->intra_period;
inst->vsi_34->config.profile =
- h264_get_profile(inst, enc_prm->h264_profile);
+ h264_get_profile(inst, enc_prm->profile);
inst->vsi_34->config.level =
- h264_get_level(inst, enc_prm->h264_level);
+ h264_get_level(inst, enc_prm->level);
inst->vsi_34->config.wfd = 0;
}
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
index 889440a436b6..3c2a1b5e9312 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.h
@@ -66,8 +66,8 @@ enum venc_set_param_type {
* struct venc_enc_prm - encoder settings for VENC_SET_PARAM_ENC used in
* venc_if_set_param()
* @input_fourcc: input yuv format
- * @h264_profile: V4L2 defined H.264 profile
- * @h264_level: V4L2 defined H.264 level
+ * @profile: V4L2 defined profile
+ * @level: V4L2 defined level
* @width: image width
* @height: image height
* @buf_width: buffer width
@@ -79,8 +79,8 @@ enum venc_set_param_type {
*/
struct venc_enc_param {
enum venc_yuv_fmt input_yuv_fmt;
- unsigned int h264_profile;
- unsigned int h264_level;
+ unsigned int profile;
+ unsigned int level;
unsigned int width;
unsigned int height;
unsigned int buf_width;
@@ -107,9 +107,11 @@ struct venc_frame_info {
/*
* struct venc_frm_buf - frame buffer information used in venc_if_encode()
* @fb_addr: plane frame buffer addresses
+ * @num_planes: number of planes
*/
struct venc_frm_buf {
struct mtk_vcodec_fb fb_addr[MTK_VCODEC_MAX_PLANES];
+ unsigned int num_planes;
};
/*
@@ -124,6 +126,7 @@ struct venc_done_result {
extern const struct venc_common_if venc_h264_if;
extern const struct venc_common_if venc_vp8_if;
+extern const struct venc_common_if venc_if;
/*
* venc_if_init - Create the driver handle
--
2.45.2
^ permalink raw reply related
* [PATCH v7 2/6] media: mediatek: encoder: Add new platform data members
From: Irui Wang @ 2026-06-05 9:35 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Krzysztof Kozlowski, angelogioacchino.delregno,
nicolas.dufresne, Tiffany Lin, kyrie wu
Cc: Yunfei Dong, Maoguang Meng, Longfei Wang, Irui Wang,
Project_Global_Chrome_Upstream_Group, linux-media, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20260605093519.13695-1-irui.wang@mediatek.com>
Add new platform data members to support different encoder ICs:
- venc_model_num: encoder model number
- fw_type: firmware type (VPU, SCP, or VCP)
- fw_init: firmware-specific initialization callback
- ipi_id: IPI ID for encoder communication
This centralizes all static platform configuration in the platform
data structure, eliminating the need for runtime device tree parsing
and the per-device fw_init callback pointer. Each platform's pdata
now directly specifies its firmware initialization function.
Changes:
1. Add venc_model_num to pdata and remove mtk_vcodec_enc_get_chip_name()
2. Add fw_type to pdata for each platform (VPU or SCP)
3. Add ipi_id field declaration to pdata
4. Remove device tree parsing for fw_type
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
---
.../mediatek/vcodec/common/mtk_vcodec_fw.c | 3 +-
.../mediatek/vcodec/encoder/mtk_vcodec_enc.c | 22 +---------
.../vcodec/encoder/mtk_vcodec_enc_drv.c | 40 +++++++++++--------
.../vcodec/encoder/mtk_vcodec_enc_drv.h | 10 ++++-
4 files changed, 36 insertions(+), 39 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
index a2e6a01272b2..9df64200d933 100644
--- a/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
+++ b/drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_fw.c
@@ -23,8 +23,9 @@ struct mtk_vcodec_fw *mtk_vcodec_fw_select(void *priv, enum mtk_vcodec_fw_type t
{
if (fw_use == ENCODER) {
struct mtk_vcodec_enc_dev *enc_dev = priv;
+ const struct mtk_vcodec_enc_pdata *pdata = enc_dev->venc_pdata;
- return enc_dev->fw_init(priv, fw_use);
+ return pdata->fw_init(priv, fw_use);
}
if (fw_use == DECODER) {
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
index 48cb5dded70a..fcf0e4f90429 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc.c
@@ -198,33 +198,15 @@ static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
pdata->num_output_formats);
}
-static int mtk_vcodec_enc_get_chip_name(struct mtk_vcodec_enc_ctx *ctx)
-{
- struct device *dev = &ctx->dev->plat_dev->dev;
-
- if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-enc"))
- return 8173;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-enc"))
- return 8183;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-enc"))
- return 8192;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-enc"))
- return 8195;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-enc"))
- return 8188;
- else
- return 8173;
-}
-
static int vidioc_venc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
struct mtk_vcodec_enc_ctx *ctx = file_to_enc_ctx(file);
+ const struct mtk_vcodec_enc_pdata *pdata = ctx->dev->venc_pdata;
struct device *dev = &ctx->dev->plat_dev->dev;
- int platform_name = mtk_vcodec_enc_get_chip_name(ctx);
strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
- snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", platform_name);
+ snprintf(cap->card, sizeof(cap->card), "MT%d video encoder", pdata->venc_model_num);
return 0;
}
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index dc54d445d98d..5f1feb3b07a6 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -245,8 +245,6 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
{
struct mtk_vcodec_enc_dev *dev;
struct video_device *vfd_enc;
- phandle rproc_phandle;
- enum mtk_vcodec_fw_type fw_type;
int ret;
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
@@ -256,25 +254,17 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
INIT_LIST_HEAD(&dev->ctx_list);
dev->plat_dev = pdev;
- if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
- &rproc_phandle)) {
- fw_type = VPU;
- dev->fw_init = mtk_vcodec_fw_vpu_init;
- } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
- &rproc_phandle)) {
- fw_type = SCP;
- dev->fw_init = mtk_vcodec_fw_scp_init;
- } else {
- dev_err(&pdev->dev, "[MTK VCODEC] Could not get venc IPI device");
+ dev->venc_pdata = of_device_get_match_data(&pdev->dev);
+ if (!dev->venc_pdata) {
+ dev_err(&pdev->dev, "Failed to get match data");
return -ENODEV;
}
- dma_set_max_seg_size(&pdev->dev, UINT_MAX);
-
- dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, ENCODER);
+ dev->fw_handler = mtk_vcodec_fw_select(dev, dev->venc_pdata->fw_type, ENCODER);
if (IS_ERR(dev->fw_handler))
return PTR_ERR(dev->fw_handler);
- dev->venc_pdata = of_device_get_match_data(&pdev->dev);
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+
ret = mtk_vcodec_init_enc_clk(dev);
if (ret < 0) {
dev_err(&pdev->dev, "[MTK VCODEC] Failed to get mtk vcodec clock source!");
@@ -389,6 +379,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
}
static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
+ .venc_model_num = 8173,
.capture_formats = mtk_video_formats_capture_h264,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
.output_formats = mtk_video_formats_output,
@@ -396,9 +387,12 @@ static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
.min_bitrate = 64,
.max_bitrate = 60000000,
.core_id = VENC_SYS,
+ .fw_type = VPU,
+ .fw_init = mtk_vcodec_fw_vpu_init,
};
static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
+ .venc_model_num = 8173,
.capture_formats = mtk_video_formats_capture_vp8,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_vp8),
.output_formats = mtk_video_formats_output,
@@ -406,9 +400,12 @@ static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
.min_bitrate = 64,
.max_bitrate = 9000000,
.core_id = VENC_LT_SYS,
+ .fw_type = VPU,
+ .fw_init = mtk_vcodec_fw_vpu_init,
};
static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
+ .venc_model_num = 8183,
.uses_ext = true,
.capture_formats = mtk_video_formats_capture_h264,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -417,9 +414,12 @@ static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
.min_bitrate = 64,
.max_bitrate = 40000000,
.core_id = VENC_SYS,
+ .fw_type = SCP,
+ .fw_init = mtk_vcodec_fw_scp_init,
};
static const struct mtk_vcodec_enc_pdata mt8188_pdata = {
+ .venc_model_num = 8188,
.uses_ext = true,
.capture_formats = mtk_video_formats_capture_h264,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -429,9 +429,12 @@ static const struct mtk_vcodec_enc_pdata mt8188_pdata = {
.max_bitrate = 50000000,
.core_id = VENC_SYS,
.uses_34bit = true,
+ .fw_type = SCP,
+ .fw_init = mtk_vcodec_fw_scp_init,
};
static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
+ .venc_model_num = 8192,
.uses_ext = true,
.capture_formats = mtk_video_formats_capture_h264,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -440,9 +443,12 @@ static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
.min_bitrate = 64,
.max_bitrate = 100000000,
.core_id = VENC_SYS,
+ .fw_type = SCP,
+ .fw_init = mtk_vcodec_fw_scp_init,
};
static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
+ .venc_model_num = 8195,
.uses_ext = true,
.capture_formats = mtk_video_formats_capture_h264,
.num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
@@ -451,6 +457,8 @@ static const struct mtk_vcodec_enc_pdata mt8195_pdata = {
.min_bitrate = 64,
.max_bitrate = 100000000,
.core_id = VENC_SYS,
+ .fw_type = SCP,
+ .fw_init = mtk_vcodec_fw_scp_init,
};
static const struct of_device_id mtk_vcodec_enc_match[] = {
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
index 934ff648125d..6c7e8da6d8ee 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.h
@@ -20,6 +20,7 @@
/**
* struct mtk_vcodec_enc_pdata - compatible data for each IC
*
+ * @venc_model_num: encoder model number
* @uses_ext: whether the encoder uses the extended firmware messaging format
* @min_bitrate: minimum supported encoding bitrate
* @max_bitrate: maximum supported encoding bitrate
@@ -29,8 +30,12 @@
* @num_output_formats: number of entries in output_formats
* @core_id: stand for h264 or vp8 encode index
* @uses_34bit: whether the encoder uses 34-bit iova
+ * @fw_type: firmware type (VPU, SCP, or VCP)
+ * @fw_init: firmware-specific initialization callback
+ * @ipi_id: IPI ID for encoder communication with firmware
*/
struct mtk_vcodec_enc_pdata {
+ u16 venc_model_num;
bool uses_ext;
u64 min_bitrate;
u64 max_bitrate;
@@ -40,6 +45,9 @@ struct mtk_vcodec_enc_pdata {
size_t num_output_formats;
u8 core_id;
bool uses_34bit;
+ enum mtk_vcodec_fw_type fw_type;
+ struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_use);
+ int ipi_id;
};
/*
@@ -174,7 +182,6 @@ struct mtk_vcodec_enc_ctx {
* @venc_pdata: encoder IC-specific data
*
* @fw_handler: used to communicate with the firmware.
- * @fw_init: firmware-specific init callback selected at probe time
* @id_counter: used to identify current opened instance
*
* @enc_mutex: encoder hardware lock.
@@ -202,7 +209,6 @@ struct mtk_vcodec_enc_dev {
const struct mtk_vcodec_enc_pdata *venc_pdata;
struct mtk_vcodec_fw *fw_handler;
- struct mtk_vcodec_fw *(*fw_init)(void *priv, enum mtk_vcodec_fw_use fw_use);
u64 id_counter;
/* encoder hardware mutex lock */
--
2.45.2
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