* Re: [PATCH v2] nvme-apple: Prevent shared tags across queues on Apple A11
From: Sven Peter @ 2026-06-07 9:40 UTC (permalink / raw)
To: Nick Chan, Janne Grunau, Neal Gompa, Keith Busch, Jens Axboe,
Christoph Hellwig, Sagi Grimberg
Cc: asahi, linux-arm-kernel, linux-nvme, linux-kernel, stable
In-Reply-To: <20260607-prevent-tag-collision-t8015-v2-1-dc4ef4fb42bc@gmail.com>
On 07.06.26 08:10, Nick Chan wrote:
> On Apple A11, tags of pending commands must be unique across the admin
> and IO queues, else the firmware crashes with
> "duplicate tag error for tag N", with N being the tag.
>
> Apply the existing workaround for M1 of reserving two tags for the admin
> queue to A11.
>
> Cc: stable@vger.kernel.org
> Fixes: 04d8ecf37b5e ("nvme: apple: Add Apple A11 support")
> Signed-off-by: Nick Chan <towinchenmi@gmail.com>
> ---
Reviewed-by: Sven Peter <sven@kernel.org>
Best,
Sven
^ permalink raw reply
* Re: [PATCH v6 1/3] dt-bindings: vendor-prefixes: add vicharak
From: Krzysztof Kozlowski @ 2026-06-07 9:13 UTC (permalink / raw)
To: Hrushiraj Gandhi, Heiko Stuebner
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260601162143.170030-2-hrushirajg23@gmail.com>
On 01/06/2026 18:21, Hrushiraj Gandhi wrote:
> Add the vendor prefix for Vicharak Computers Pvt. Ltd.
>
> Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Drop the patch, it was already sent by someone else.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/2] arm64: dts: rockchip: add Vicharak Axon board
From: Krzysztof Kozlowski @ 2026-06-07 8:45 UTC (permalink / raw)
To: Hrushiraj Gandhi
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260601132529.139172-2-hrushirajg23@gmail.com>
On Mon, Jun 01, 2026 at 06:55:28PM +0530, Hrushiraj Gandhi wrote:
> Add initial support for the Vicharak Axon single-board computer based on
> the Rockchip RK3588 SoC.
>
> The board supports:
>
> - eMMC storage
> - microSD card
> - Gigabit Ethernet
> - HDMI output (dual HDMI)
> - HDMI input
> - USB 2.0 host ports
> - PCIe 2.0 slots
> - PCIe 3.0 x4 slot
> - SATA
> - RTC
> - Status LEDs
>
> The board uses an RK806 PMIC and provides the regulators required by
> the RK3588 SoC.
>
> Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../dts/rockchip/rk3588-vicharak-axon.dts | 1038 +++++++++++++++++
> 2 files changed, 1039 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index cb55c6b70d0e..fcb115b02eff 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -179,6 +179,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vicharak-axon.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts
> new file mode 100644
> index 000000000000..fecd13a52e88
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts
> @@ -0,0 +1,1038 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/soc/rockchip,vop2.h>
> +#include <dt-bindings/usb/pd.h>
> +#include "rk3588.dtsi"
> +
> +/ {
> + model = "Vicharak Axon";
> + compatible = "vicharak,axon", "rockchip,rk3588";
> +
> + aliases {
> + mmc0 = &sdmmc;
> + mmc1 = &sdhci;
> + mmc2 = &sdio;
> + serial2 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial2:1500000n8";
> + };
> +
> + hdmi0-con {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi0_con_in: endpoint {
> + remote-endpoint = <&hdmi0_out_con>;
> + };
> + };
> + };
> +
> + hdmi1-con {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi1_con_in: endpoint {
> + remote-endpoint = <&hdmi1_out_con>;
> + };
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + status = "okay";
Which DTSI disabled it?
> +
> + power_led: power-led {
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_STATUS;
> + gpios = <&pca9554 0 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + status_led: status-led {
> + color = <LED_COLOR_ID_RED>;
> + function = LED_FUNCTION_STATUS;
> + gpios = <&pca9554 1 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "none";
> + };
> + };
> +
> + pcie20_avdd0v85: regulator-pcie20-avdd0v85 {
Unused, drop. Don't add useless/non-controllable supplies without
consumers. They bring no benefits, except more review, slower kernel,
more code to maintain.
> + compatible = "regulator-fixed";
> + regulator-name = "pcie20_avdd0v85";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <850000>;
> + vin-supply = <&vdd_0v85_s0>;
> + };
> +
> + pcie20_avdd1v8: regulator-pcie20-avdd1v8 {
No users
> + compatible = "regulator-fixed";
> + regulator-name = "pcie20_avdd1v8";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&avcc_1v8_s0>;
> + };
> +
> + pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
Is any of this real?
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd0v75";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <750000>;
> + regulator-max-microvolt = <750000>;
> + vin-supply = <&vdd_0v75_s0>;
> + };
> +
> + pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "pcie30_avdd1v8";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&avcc_1v8_s0>;
> + };
> +
> + sata_vcc_5v0: regulator-sata-vcc-5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "sata_vcc_5v0";
> + startup-delay-us = <5000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc12v_dcin>;
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&hym8563>;
> + clock-names = "ext_clock";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdio_reset_wifi>;
> + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
> + status = "okay";
> + };
> +
> + vcc0_4v0: vcc4v0_sys: regulator-vcc0-4v0 {
Odd sorting. And still not used!
> + compatible = "regulator-fixed";
> + regulator-name = "vcc0_4v0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <4000000>;
> + regulator-max-microvolt = <4000000>;
> + vin-supply = <&vcc12v_dcin>;
> + };
> +
> + vcc12v_dcin: regulator-vcc12v-dcin {
Also not used
> + compatible = "regulator-fixed";
> + regulator-name = "vcc12v_dcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + vcc3v3_io_expander: regulator-vcc3v3-io-expander {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_io_expander";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vcc3v3_pcie20_sata30: regulator-vcc3v3-pcie20-sata30 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_pcie20_sata30";
> + regulator-boot-on;
> + regulator-always-on;
> + enable-active-high;
> + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
> + regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> + vin-supply = <&vcc12v_dcin>;
> + };
...
> +
> +&i2c0 {
> + pinctrl-0 = <&i2c0m2_xfer>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + vdd_cpu_big0_s0: regulator@42 {
> + compatible = "rockchip,rk8602";
> + fcs,suspend-voltage-selector = <1>;
> + reg = <0x42>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1050000>;
> + regulator-min-microvolt = <550000>;
> + regulator-name = "vdd_cpu_big0_s0";
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_cpu_big1_s0: regulator@43 {
> + compatible = "rockchip,rk8603", "rockchip,rk8602";
> + fcs,suspend-voltage-selector = <1>;
> + reg = <0x43>;
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-max-microvolt = <1050000>;
> + regulator-min-microvolt = <550000>;
> + regulator-name = "vdd_cpu_big1_s0";
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + hym8563: rtc@51 {
> + compatible = "haoyu,hym8563";
> + reg = <0x51>;
> + #clock-cells = <0>;
> + clock-output-names = "hym8563";
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&rtc_int>;
> + wakeup-source;
> + status = "okay";
Why is this enabled but regulator above is not? What logic drivers this?
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1m2_xfer>;
> + status = "okay";
> +
> + vdd_npu_s0: regulator@42 {
> + compatible = "rockchip,rk8602";
> + reg = <0x42>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_npu_s0";
> + regulator-boot-on;
> + regulator-enable-ramp-delay = <500>;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +};
> +
> +&i2c6 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6m0_xfer>;
> + status = "okay";
> +
> + pca9554: gpio@24 {
> + compatible = "nxp,pca9554";
> + #gpio-cells = <2>;
> + gpio-controller;
> + reg = <0x24>;
> + vcc-supply = <&vcc3v3_io_expander>;
> + status = "okay";
Who disabled it?
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] KVM: arm64: nv: Skip vCPUs without a pseudo-TLB in invalidate_vncr_va()
From: Hyunwoo Kim @ 2026-06-07 8:43 UTC (permalink / raw)
To: maz, oupton, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will
Cc: linux-arm-kernel, kvmarm, imv4bel
vncr_tlb is not allocated before a vCPU runs for the first time, so
vcpu->arch.vncr_tlb is NULL for a vCPU that has been created but not yet
run. Code that iterates over every vCPU's pseudo-TLB must skip those.
invalidate_vncr_va() iterates over the vCPUs with kvm_for_each_vcpu() and
dereferences vt->valid without checking whether vncr_tlb is NULL.
While iterating, skip vCPUs whose pseudo-TLB has not been allocated.
Fixes: 4ffa72ad8f37 ("KVM: arm64: nv: Add S1 TLB invalidation primitive for VNCR_EL2")
Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
---
arch/arm64/kvm/nested.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 6f7bc9a9992e..063e079d1d1a 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -969,6 +969,10 @@ static void invalidate_vncr_va(struct kvm *kvm,
struct vncr_tlb *vt = vcpu->arch.vncr_tlb;
u64 va_start, va_end, va_size;
+ /* Skip vCPUs whose pseudo-TLB hasn't been allocated yet */
+ if (!vt)
+ continue;
+
if (!vt->valid)
continue;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 2/2] dt-bindings: arm: rockchip: add Vicharak Axon board
From: Krzysztof Kozlowski @ 2026-06-07 8:42 UTC (permalink / raw)
To: Hrushiraj Gandhi
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260601132529.139172-3-hrushirajg23@gmail.com>
On Mon, Jun 01, 2026 at 06:55:29PM +0530, Hrushiraj Gandhi wrote:
> Add the device tree binding for the Vicharak Axon single-board
> computer based on the Rockchip RK3588 SoC, and add the vicharak
> vendor prefix to the vendor-prefixes list.
>
> Signed-off-by: Hrushiraj Gandhi <hrushirajg23@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 2 files changed, 7 insertions(+)
Please organize the patch documenting the compatible (DT bindings)
before the patch using that compatible.
See also: https://elixir.bootlin.com/linux/v6.14-rc6/source/Documentation/devicetree/bindings/submitting-patches.rst#L46
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH bpf-next] arm64: mm: Complete the PTE store in ptep_try_set()
From: bot+bpf-ci @ 2026-06-07 8:38 UTC (permalink / raw)
To: tj, catalin.marinas, will, ast
Cc: david, arighi, memxor, akpm, rppt, andrii, daniel, martin.lau,
eddyz87, yonghong.song, emil, void, changwoo, linux-arm-kernel,
linux-mm, bpf, linux-kernel, ast, andrii, daniel, martin.lau,
eddyz87, yonghong.song, clm, ihor.solodrai
In-Reply-To: <088f52fd25860ca961449d53f91b214a@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 1949 bytes --]
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 3ce0f2a6cab6..dc8525431273 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -1838,7 +1838,11 @@ static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte)
> {
> pteval_t old = 0;
>
> - return try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte));
> + if (!try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte)))
> + return false;
> +
> + __set_pte_complete(new_pte);
An earlier posting of this drew a question on the mailing list about
__set_pte_complete() deferring the barriers in some contexts:
https://lore.kernel.org/all/20260607081229.12BC21F00893@smtp.kernel.org/
The concern is that __set_pte_complete() delegates to
queue_pte_barriers(), which only sets TIF_LAZY_MMU_PENDING and defers the
dsb when is_lazy_mmu_mode_active() is true.
The scenario raised is a synchronous BPF arena fault (for example via a
kprobe, where in_interrupt() is false) interrupting a task that is inside a
lazy MMU block such as zap_pte_range(). There is_lazy_mmu_mode_active()
would be true, so the dsb is deferred, and the fault handler could return
before the memory system observes the new PTE. The faulting instruction
would then retry and fault again.
Can this path actually loop, or is the deferred barrier guaranteed to be
flushed before the faulting instruction is retried?
Note this deferral mechanism is the same one used by the existing
__set_pte() path that this change deliberately mirrors, and the comment
above came from an automated review rather than a human, so the scenario
has not been confirmed.
> + return true;
> }
> #define ptep_try_set ptep_try_set
---
AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md
CI run summary: https://github.com/kernel-patches/bpf/actions/runs/27087148382
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: arm: sunxi: Add NetCube Systems OpenNMC (dobermann)
From: Krzysztof Kozlowski @ 2026-06-07 8:25 UTC (permalink / raw)
To: Lukas Schmid
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Maxime Ripard, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-riscv
In-Reply-To: <20260606205452.2386930-2-lukas.schmid@netcube.li>
On Sat, Jun 06, 2026 at 10:54:41PM +0200, Lukas Schmid wrote:
> The OpenNMC is an open replacement for APC SmartSlot management cards
> based on the Nagami System-on-Module.
>
> Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li>
> ---
> Documentation/devicetree/bindings/arm/sunxi.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH bpf-next] arm64: mm: Complete the PTE store in ptep_try_set()
From: Tejun Heo @ 2026-06-07 7:59 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Alexei Starovoitov
Cc: David Hildenbrand, Andrea Righi, Kumar Kartikeya Dwivedi,
Andrew Morton, Mike Rapoport, Andrii Nakryiko, Daniel Borkmann,
Martin KaFai Lau, Eduard Zingerman, Yonghong Song,
Emil Tsalapatis, David Vernet, Changwoo Min, linux-arm-kernel,
linux-mm, bpf, linux-kernel
In-Reply-To: <aiRFcz78QTZdIHHB@arm.com>
ptep_try_set() installs the new entry with try_cmpxchg() but, unlike
__set_pte(), never calls __set_pte_complete(). On arm64, installing a valid
kernel PTE requires barriers afterward so a subsequent access observes it.
Without them the access can fault instead of reaching the freshly installed
page.
Call __set_pte_complete() after a successful cmpxchg, mirroring
__set_pte().
Fixes: 258df8fce42f ("mm: Add ptep_try_set() for lockless empty-slot installs")
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/all/aiRFcz78QTZdIHHB@arm.com/
Signed-off-by: Tejun Heo <tj@kernel.org>
---
arch/arm64/include/asm/pgtable.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 3ce0f2a6cab6..dc8525431273 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -1838,7 +1838,11 @@ static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte)
{
pteval_t old = 0;
- return try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte));
+ if (!try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte)))
+ return false;
+
+ __set_pte_complete(new_pte);
+ return true;
}
#define ptep_try_set ptep_try_set
--
2.51.1
^ permalink raw reply related
* Re: [PATCH v3 0/2] KVM: arm64: Sanitise host vCPU fields copied in flush_hyp_vcpu()
From: Fuad Tabba @ 2026-06-07 7:05 UTC (permalink / raw)
To: Hyunwoo Kim
Cc: maz, oupton, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will, linux-arm-kernel, kvmarm, stable
In-Reply-To: <20260606175614.83273-1-imv4bel@gmail.com>
On Sat, 6 Jun 2026 at 18:57, Hyunwoo Kim <imv4bel@gmail.com> wrote:
>
> flush_hyp_vcpu() copies the host vCPU context and vGIC state into the
> hyp's private vCPU on every run. This series sanitises two fields that
> it currently copies verbatim (host -> EL2): __hyp_running_vcpu is
> cleared in the guest context, and used_lrs is bounded by the number of
> implemented list registers.
From my side I think you've addressed Marc's feedback. For the latest series:
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Cheers,
/fuad
>
> Changes in v3:
> - 2/2: replicate kvm_vgic_global_state.nr_lr into hyp_gicv3_nr_lr
> once at init (guarded by gicv3_cpuif), instead of reading
> ICH_VTR_EL2 on every entry behind a gicv3_cpuif gate. (Marc)
> - v2: https://lore.kernel.org/all/20260604151210.1304051-1-imv4bel@gmail.com/
>
> Changes in v2:
> - split into two patches, one per field, per review.
> - v1: https://lore.kernel.org/all/aiFe-CXo-XVTFz1g@v4bel/
>
> Hyunwoo Kim (2):
> KVM: arm64: Clear __hyp_running_vcpu when flushing the pKVM hyp vCPU
> KVM: arm64: Bound used_lrs when flushing the pKVM hyp vCPU
>
> arch/arm64/include/asm/kvm_hyp.h | 1 +
> arch/arm64/kvm/arm.c | 2 ++
> arch/arm64/kvm/hyp/nvhe/hyp-main.c | 12 ++++++++++++
> 3 files changed, 15 insertions(+)
>
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH] drm/sun4i: fix refcount leak in sun4i_backend_init_sat()
From: Christophe JAILLET @ 2026-06-07 6:32 UTC (permalink / raw)
To: Wentao Liang, wens, maarten.lankhorst, mripard, tzimmermann,
airlied, simona, jernej.skrabec, samuel
Cc: dri-devel, linux-arm-kernel, linux-sunxi, linux-kernel, stable
In-Reply-To: <20260607030950.83636-1-vulab@iscas.ac.cn>
Le 07/06/2026 à 05:09, Wentao Liang a écrit :
> When sun4i_backend_init_sat() calls reset_control_deassert() it
> increments the deassert_count of the reset controller, and must
> pair that with a reset_control_assert() call to decrement it.
> In the error path where clk_prepare_enable() fails, the function
> returns immediately without calling reset_control_assert(), leaking
> the reference count. Other error paths, like the devm_clk_get()
> failure, correctly jump to the err_assert_reset label which performs
> the missing assert.
>
> Fix the leak by using the existing err_assert_reset label in the
> clk_prepare_enable error path instead of returning directly.
>
> Cc: stable@vger.kernel.org
> Fixes: 440d2c7b127a ("drm/sun4i: backend: Handle the SAT")
> Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
> ---
> drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
> index bc35dad53b07..c9ec5fc26f7e 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_backend.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
> @@ -686,7 +686,7 @@ static int sun4i_backend_init_sat(struct device *dev) {
> ret = clk_prepare_enable(backend->sat_clk);
> if (ret) {
> dev_err(dev, "Couldn't enable the SAT clock\n");
> - return ret;
> + goto err_assert_reset;
> }
>
> return 0;
Hi,
another way to fix it and simplify the code at the same time would be to
use devm_reset_control_get_exclusive_deasserted() and
devm_clk_get_enabled().
just my 2c,
CJ
^ permalink raw reply
* [PATCH v2] nvme-apple: Prevent shared tags across queues on Apple A11
From: Nick Chan @ 2026-06-07 6:10 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Neal Gompa, Keith Busch, Jens Axboe,
Christoph Hellwig, Sagi Grimberg
Cc: asahi, linux-arm-kernel, linux-nvme, linux-kernel, stable,
Nick Chan
On Apple A11, tags of pending commands must be unique across the admin
and IO queues, else the firmware crashes with
"duplicate tag error for tag N", with N being the tag.
Apply the existing workaround for M1 of reserving two tags for the admin
queue to A11.
Cc: stable@vger.kernel.org
Fixes: 04d8ecf37b5e ("nvme: apple: Add Apple A11 support")
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
Changes in v2:
- Complete rewrite to use the existing workaround for M1.
- Link to v1: https://lore.kernel.org/r/20260606-prevent-tag-collision-t8015-v1-0-93ccf4eca550@gmail.com
---
drivers/nvme/host/apple.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/nvme/host/apple.c b/drivers/nvme/host/apple.c
index c692fc73babf..da6e983e2005 100644
--- a/drivers/nvme/host/apple.c
+++ b/drivers/nvme/host/apple.c
@@ -225,7 +225,7 @@ static unsigned int apple_nvme_queue_depth(struct apple_nvme_queue *q)
{
struct apple_nvme *anv = queue_to_apple_nvme(q);
- if (q->is_adminq && anv->hw->has_lsq_nvmmu)
+ if (q->is_adminq)
return APPLE_NVME_AQ_DEPTH;
return anv->hw->max_queue_depth;
@@ -303,7 +303,7 @@ static void apple_nvme_submit_cmd_t8015(struct apple_nvme_queue *q,
memcpy((void *)q->sqes + (q->sq_tail << APPLE_NVME_IOSQES),
cmd, sizeof(*cmd));
- if (++q->sq_tail == anv->hw->max_queue_depth)
+ if (++q->sq_tail == apple_nvme_queue_depth(q))
q->sq_tail = 0;
writel(q->sq_tail, q->sq_db);
@@ -1139,10 +1139,7 @@ static void apple_nvme_reset_work(struct work_struct *work)
}
/* Setup the admin queue */
- if (anv->hw->has_lsq_nvmmu)
- aqa = APPLE_NVME_AQ_DEPTH - 1;
- else
- aqa = anv->hw->max_queue_depth - 1;
+ aqa = APPLE_NVME_AQ_DEPTH - 1;
aqa |= aqa << 16;
writel(aqa, anv->mmio_nvme + NVME_REG_AQA);
writeq(anv->adminq.sq_dma_addr, anv->mmio_nvme + NVME_REG_ASQ);
@@ -1325,8 +1322,7 @@ static int apple_nvme_alloc_tagsets(struct apple_nvme *anv)
* both queues. The admin queue gets the first APPLE_NVME_AQ_DEPTH which
* must be marked as reserved in the IO queue.
*/
- if (anv->hw->has_lsq_nvmmu)
- anv->tagset.reserved_tags = APPLE_NVME_AQ_DEPTH;
+ anv->tagset.reserved_tags = APPLE_NVME_AQ_DEPTH;
anv->tagset.queue_depth = anv->hw->max_queue_depth - 1;
anv->tagset.timeout = NVME_IO_TIMEOUT;
anv->tagset.numa_node = NUMA_NO_NODE;
---
base-commit: e43ffb69e0438cddd72aaa30898b4dc446f664f8
change-id: 20260606-prevent-tag-collision-t8015-1c8adb3234de
Best regards,
--
Nick Chan <towinchenmi@gmail.com>
^ permalink raw reply related
* Re: [PATCH v1] ARM: OMAP2+: Fix OF node reference leaks in omap_hwmod
From: Andreas Kemnade @ 2026-06-07 5:52 UTC (permalink / raw)
To: Yuho Choi
Cc: Paul Walmsley, Aaro Koskinen, Kevin Hilman, Roger Quadros,
Tony Lindgren, Russell King, linux-omap, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260504164711.2854116-1-dbgh9129@gmail.com>
On Mon, 4 May 2026 12:47:11 -0400
Yuho Choi <dbgh9129@gmail.com> wrote:
> The OF helpers that return device nodes acquire references that must be
> released by the caller.
>
> _init() leaks the "ocp" bus node returned by of_find_node_by_name() on
> all paths after lookup, and also leaks the child returned by
> of_get_next_child() when parsing module flags. Route the post-lookup
> returns through a common cleanup path and release the child after use.
>
> omap_hwmod_setup_earlycon_flags() leaks the /chosen node and the UART
> node resolved from stdout-path. Track them separately and drop both
> references after use.
>
> Fixes: 1aa8f0cb19e5 ("ARM: OMAP2+: Remove unused legacy code for interconnects")
> Fixes: 4f2122473363 ("ARM: OMAP2+: Check also the first dts child for hwmod flags")
> Fixes: 8dd6666f4937 ("ARM: OMAP2+: omap_hwmod: Add support for earlycon")
> Signed-off-by: Yuho Choi <dbgh9129@gmail.com>
Reviewed-by: Andreas Kemnade <andreas@kemnade.info>
^ permalink raw reply
* [PATCH] arm_mpam: Fix MPAMCFG_MBW_PBM register setting
From: Fenghua Yu @ 2026-06-07 5:09 UTC (permalink / raw)
To: Ben Horgan, James Morse, Reinette Chatre, Catalin Marinas,
Gavin Shan, Shaopeng Tan, Jesse Chick
Cc: linux-kernel, linux-arm-kernel, Fenghua Yu, Matt Ochs
MPAMCFG_MBW_PBM is written from cfg if cfg has the MBW partition feature.
It is reset when cfg does not have the MBW partition feature.
But the register handling is reversed. This may cause an incorrect
register setting. For example, during an MPAM reset, reset_cfg is
empty (no MBW partition feature set), and cfg->mbw_pbm is 0. Instead of
resetting MPAMCFG_MBW_PBM to all 1's, the current logic will set it to
cfg->mbw_pbm, which is 0.
Fix the issue by swapping the if/else branches.
Fixes: a1cb6577f575 ("arm_mpam: Reset when feature configuration bit unset")
Reported-by: Matt Ochs <mochs@nvidia.com>
Signed-off-by: Fenghua Yu <fenghuay@nvidia.com>
---
drivers/resctrl/mpam_devices.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index 4b93e89c2678..d8b0383cee92 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1570,9 +1570,9 @@ static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid,
if (mpam_has_feature(mpam_feat_mbw_part, rprops)) {
if (mpam_has_feature(mpam_feat_mbw_part, cfg))
- mpam_reset_msc_bitmap(msc, MPAMCFG_MBW_PBM, rprops->mbw_pbm_bits);
- else
mpam_write_partsel_reg(msc, MBW_PBM, cfg->mbw_pbm);
+ else
+ mpam_reset_msc_bitmap(msc, MPAMCFG_MBW_PBM, rprops->mbw_pbm_bits);
}
if (mpam_has_feature(mpam_feat_mbw_min, rprops)) {
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2] media: bcm2835-unicam: Fix log status runtime access
From: Jai Luthra @ 2026-06-07 3:42 UTC (permalink / raw)
To: Broadcom internal kernel review list, Dave Stevenson,
Eugen Hristev, Florian Fainelli, Hans Verkuil,
Jean-Michel Hautbois, Laurent Pinchart, Mauro Carvalho Chehab,
Raspberry Pi Kernel Maintenance, Ray Jui, Sakari Ailus,
Scott Branden
Cc: Naushir Patuck, linux-media, linux-rpi-kernel, linux-arm-kernel,
linux-kernel, Eugen Hristev
In-Reply-To: <20260522-bcmpipm-v2-1-a3da66cbc9f0@kernel.org>
Quoting Eugen Hristev (2026-05-22 20:58:50)
> When requesting log status, the block might be powered off, but registers
> are being read.
> Avoid reading the registers if the device is not resumed, thus also avoid
> powering up the device just for log status.
>
> Fixes: 392cd78d495f ("media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface")
> Signed-off-by: Eugen Hristev <ehristev@kernel.org>
Reviewed-by: Jai Luthra <jai.luthra@ideasonboard.com>
> ---
> Changes in v2:
> - changed to use pm_runtime_get_if_active()
> - add corresponding put()
> - Link to v1: https://patch.msgid.link/20260521-bcmpipm-v1-1-3eba88d88045@kernel.org
>
> To: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> To: Florian Fainelli <florian.fainelli@broadcom.com>
> To: Ray Jui <rjui@broadcom.com>
> To: Scott Branden <sbranden@broadcom.com>
> To: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
> To: Sakari Ailus <sakari.ailus@linux.intel.com>
> To: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> To: Hans Verkuil <hverkuil@kernel.org>
> To: Naushir Patuck <naush@raspberrypi.com>
> Cc: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Cc: linux-media@vger.kernel.org
> Cc: linux-rpi-kernel@lists.infradead.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
[snip]
Thanks,
Jai
^ permalink raw reply
* Re: [PATCH v2] media: bcm2835-unicam: Fix log status runtime access
From: Jai Luthra @ 2026-06-07 3:41 UTC (permalink / raw)
To: Eugen Hristev, Sakari Ailus
Cc: Jean-Michel Hautbois, Raspberry Pi Kernel Maintenance,
Mauro Carvalho Chehab, Florian Fainelli,
Broadcom internal kernel review list, Ray Jui, Scott Branden,
Dave Stevenson, Hans Verkuil, Laurent Pinchart, Naushir Patuck,
linux-media, linux-rpi-kernel, linux-arm-kernel, linux-kernel
In-Reply-To: <ahyh0ZlwlZqr7VNa@kekkonen.localdomain>
Hi Sakari, Eugen,
Quoting Sakari Ailus (2026-06-01 02:32:09)
> Hi Eugen, others,
>
> On Fri, May 29, 2026 at 06:06:42PM +0300, Eugen Hristev wrote:
> > On 5/29/26 08:12, Jean-Michel Hautbois wrote:
> > > Hi Eugen,
> > >
> > > Le 22/05/2026 à 17:28, Eugen Hristev a écrit :
> > >> When requesting log status, the block might be powered off, but registers
> > >> are being read.
> > >> Avoid reading the registers if the device is not resumed, thus also avoid
> > >> powering up the device just for log status.
> > >>
> > >> Fixes: 392cd78d495f ("media: bcm2835-unicam: Add support for CCP2/CSI2 camera interface")
> > >> Signed-off-by: Eugen Hristev <ehristev@kernel.org>
> > >> ---
> > >> Changes in v2:
> > >> - changed to use pm_runtime_get_if_active()
> > >> - add corresponding put()
> > >> - Link to v1: https://patch.msgid.link/20260521-bcmpipm-v1-1-3eba88d88045@kernel.org
> > >>
> > >> To: Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
> > >> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> > >> To: Florian Fainelli <florian.fainelli@broadcom.com>
> > >> To: Ray Jui <rjui@broadcom.com>
> > >> To: Scott Branden <sbranden@broadcom.com>
> > >> To: Broadcom internal kernel review list <bcm-kernel-feedback-list@broadcom.com>
> > >> To: Sakari Ailus <sakari.ailus@linux.intel.com>
> > >> To: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> > >> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > >> To: Hans Verkuil <hverkuil@kernel.org>
> > >> To: Naushir Patuck <naush@raspberrypi.com>
> > >> Cc: Dave Stevenson <dave.stevenson@raspberrypi.com>
> > >> Cc: linux-media@vger.kernel.org
> > >> Cc: linux-rpi-kernel@lists.infradead.org
> > >> Cc: linux-arm-kernel@lists.infradead.org
> > >> Cc: linux-kernel@vger.kernel.org
> > >> ---
> > >> drivers/media/platform/broadcom/bcm2835-unicam.c | 9 +++++++++
> > >> 1 file changed, 9 insertions(+)
> > >>
> > >> diff --git a/drivers/media/platform/broadcom/bcm2835-unicam.c b/drivers/media/platform/broadcom/bcm2835-unicam.c
> > >> index 8d28ba0b59a3..93815b8ab930 100644
> > >> --- a/drivers/media/platform/broadcom/bcm2835-unicam.c
> > >> +++ b/drivers/media/platform/broadcom/bcm2835-unicam.c
> > >> @@ -2052,6 +2052,13 @@ static int unicam_log_status(struct file *file, void *fh)
> > >> node->fmt.fmt.pix.width, node->fmt.fmt.pix.height);
> > >> dev_info(unicam->dev, "V4L2 format: %08x\n",
> > >> node->fmt.fmt.pix.pixelformat);
> > >> +
> > >> + if (!pm_runtime_get_if_active(unicam->dev)) {
> > >
> > > Well, if I am picky I would say that pm_runtime_get_if_active() can
> > > return -EINVAL if runtime PM is disabled for the device. It should then
> > > be tested against '<= 0' ?
> > >
> > > I suppose this should not happen really often, as very few drivers
> > > actually test this case...
> >
> > I saw that. Some do. This driver enables runtime pm in probe though. So
> > I guess it cannot happen, unless runtime pm would not selected in kernel
> > config, but the driver depends on PM.
>
> Runtime PM can be disabled for a device via sysfs.
>
I tried this on my board, and you can only do:
echo on > /sys/class/<...>/control
Which leads to RPM count to always stay 1 regardless of get/put.
So if the driver enables RPM and never disables it unless it's removed,
there's no way from userspace to make this function return -EINVAL.
> >
> > Ultimately I guess it's up to Sakari or Hans to decide whether it's
> > worth checking for error code, but I picked the simpler path (and
> > considering <depends on PM> in Kconfig) .
>
> pm_runtime_put() musn't be called if there was an error as it decrements
> usage_count unconditionally.
>
> The vast majority of sensor drivers test for non-zero only and no-one has
> complained. They should be fixed though...
>
This driver has an explicit "depends on PM", but even for other sensor
drivers, the only case pm_runtime_get_if_active can return -EINVAL is when
CONFIG_PM=n, where pm_runtime_put is also stubbed out to return -ENOSYS..
So there is nothing to fix in sesnor drivers which do:
if (!pm_runtime_get_if_active(&client->dev))
return 0;
/* write registers */
/* unconditional put */
pm_runtime_put(&client->dev)
Thanks,
Jai
> > >
> > > With or without this small change:
> > > Reviewed-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
> > >
> > > Thanks,
> > > JM
> > >
> > >> + dev_info(unicam->dev,
> > >> + "Live data N/A due to device inactive\n");
> > >> + return 0;
> > >> + }
> > >> +
> > >> reg = unicam_reg_read(unicam, UNICAM_IPIPE);
> > >> dev_info(unicam->dev, "Unpacking/packing: %u / %u\n",
> > >> unicam_get_field(reg, UNICAM_PUM_MASK),
> > >> @@ -2065,6 +2072,8 @@ static int unicam_log_status(struct file *file, void *fh)
> > >> dev_info(unicam->dev, "Write pointer: %08x\n",
> > >> unicam_reg_read(unicam, UNICAM_IBWP));
> > >>
> > >> + pm_runtime_put(unicam->dev);
> > >> +
> > >> return 0;
> > >> }
> > >>
> > >>
> > >> ---
> > >> base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
> > >> change-id: 20260521-bcmpipm-6c578e73239c
> > >>
> > >> Best regards,
>
> --
> Regards,
>
> Sakari Ailus
>
^ permalink raw reply
* [PATCH] drm/sun4i: fix refcount leak in sun4i_backend_init_sat()
From: Wentao Liang @ 2026-06-07 3:09 UTC (permalink / raw)
To: wens, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
jernej.skrabec, samuel
Cc: dri-devel, linux-arm-kernel, linux-sunxi, linux-kernel,
Wentao Liang, stable
When sun4i_backend_init_sat() calls reset_control_deassert() it
increments the deassert_count of the reset controller, and must
pair that with a reset_control_assert() call to decrement it.
In the error path where clk_prepare_enable() fails, the function
returns immediately without calling reset_control_assert(), leaking
the reference count. Other error paths, like the devm_clk_get()
failure, correctly jump to the err_assert_reset label which performs
the missing assert.
Fix the leak by using the existing err_assert_reset label in the
clk_prepare_enable error path instead of returning directly.
Cc: stable@vger.kernel.org
Fixes: 440d2c7b127a ("drm/sun4i: backend: Handle the SAT")
Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index bc35dad53b07..c9ec5fc26f7e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -686,7 +686,7 @@ static int sun4i_backend_init_sat(struct device *dev) {
ret = clk_prepare_enable(backend->sat_clk);
if (ret) {
dev_err(dev, "Couldn't enable the SAT clock\n");
- return ret;
+ goto err_assert_reset;
}
return 0;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 1/3] dt-bindings: net: add Realtek r8169 family PCIe Ethernet
From: Ricardo Pardini @ 2026-06-07 1:03 UTC (permalink / raw)
To: Heiner Kallweit, nic_swsd, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-rockchip
In-Reply-To: <667f64e0-2b3e-41bf-9c97-3562696d3af7@gmail.com>
On 06/06/2026 22:50, Heiner Kallweit wrote:
> On 06.06.2026 07:03, Ricardo Pardini wrote:
>> On 05/06/2026 17:48, Heiner Kallweit wrote:
>>> On 05.06.2026 13:49, Ricardo Pardini via B4 Relay wrote:
>>>> From: Ricardo Pardini <ricardo@pardini.net>
>>>>
>>>> Add a binding for fixed/soldered Realtek PCIe Ethernet controllers
>>>> driven by the r8169 driver (RTL8125/8126/8127/8168 and variants).
>>>>
>>>> The "pciVVVV,DDDD" compatibles are the Open Firmware PCI Bus Binding
>>>> spelling, auto-derived from PCI-SIG vendor/device IDs, but they still
>>>> need a binding when used in a board DT - analogous to "usbVVVV,PPPP"
>>>> compatibles documented in their own bindings (e.g. microchip,lan95xx)
>>>> so board DTs attaching properties (fixed MAC, nvmem cell, ...) to
>>>> these PCI function nodes can be validated.
>>>
>>> The of node seems to be created by of_pci_make_dev_node(). But this
>>> function is called for bridges only in pci_bus_add_device().
>>> So where is the node created in your case? Did you test node creation?
>>
>> Seems to me of_pci_make_dev_node() is not at play here - that's the DT-synthesis path. For nodes already present in DT, the of_node is bound earlier, during pci_setup_device() -> pci_set_of_node() -> of_pci_find_child_device() via the 5-cell reg.
>>
> I see, thanks. If the matching is done based on the reg property, then I just wonder
> if and where the compatible string is used. Or would the logic also work with a
> random compatible string?
Thanks, Heiner. It seems the compatible is not involved in the kernel
runtime matching at all (and u-boot simply patches DT via the ethernetN
alias).
I guess DT-wise, specifying compatible (although not strictly required)
makes sense since DT describes the hardware; "there's an RTL8125 at
0x410000" sounds better than "there's a PCIe device that needs a MAC
address at 0x410000", and having the binding opens up usages of
non-generic properties, although that would be future-looking.
At this stage I've to ask the devicetree folks: should I simply drop the
compatible from the DT patches (and the whole binding)? dtbs_check
passes without it, and it also avoids the checkpatch.pl
vendor-prefix-undocumented warning. There's precedent: at least on some
Apple Silicon (2022, t600x-j375) and NVIDIA (2019, tegra210-p3450-0000).
On Rockchip there's quite a few (10?) boards using the same RTL chip we
might want to describe.
> [...]
>>> This list reflects just some of the PCI id's handled by r8169.
>>> Any specific reason for this exact selection?
>> I went for "chips likely to be soldered down on an SBC", but that was indeed speculative.
>>
>> I guess I should trim to pci10ec,8125, which is all this series describes? (further IDs can be added by the patches that introduce boards using them)
>>
> Yes, I'd prefer this approach. Considering that RTL8168 has been supported for
> about 20yrs now, your use case seems to be exotic. Otherwise I would have
> such a patch much earlier.
The Tegra Jetson Nano has an RTL8111 described in DT for this exact use
case (without compatible) for about 7 years now -- I just couldn't find
it until now.
I'll wait for people to chime in, and later send a v4 either dropping
the binding, or trimming it to only the 8125. Sashiko seems to have nice
suggestions [1] on the YAML too, in case we decide to keep the binding.
--
Regards,
Ricardo
[1]
https://sashiko.dev/#/patchset/20260605-rk3588-dts-rtl-eth-describe-dt-alias-v3-0-8a8857b39daf%40pardini.net
^ permalink raw reply
* [PATCH 17/18] pinctrl: airoha: prepare for en7523 adding
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
en7523 a bit differs from an7581/an7583. It has different register
offsets and slightly different bitfield masks.
Let's adapt common header and existing drivers for the future addition
of en7523.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/airoha-common.h | 42 ++++++--
drivers/pinctrl/airoha/pinctrl-an7581.c | 138 ++++++++++++------------
drivers/pinctrl/airoha/pinctrl-an7583.c | 132 +++++++++++------------
3 files changed, 167 insertions(+), 145 deletions(-)
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index 611194725757..f10cc7d20d15 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -56,7 +56,8 @@
}
/* MUX */
-#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define AN7581_REG_GPIO_2ND_I2C_MODE 0x0214
+#define EN7523_REG_GPIO_2ND_I2C_MODE 0x0210
#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14)
#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
#define GPIO_I2S_MODE_MASK BIT(12)
@@ -73,7 +74,8 @@
#define GSW_TOD_1PPS_MODE_MASK BIT(1)
#define GPIO_2ND_I2C_MODE_MASK BIT(0)
-#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define AN7581_REG_GPIO_SPI_CS1_MODE 0x0218
+#define EN7523_REG_GPIO_SPI_CS1_MODE 0x0214
#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
@@ -91,7 +93,8 @@
#define GPIO_SPI_CS2_MODE_MASK BIT(1)
#define GPIO_SPI_CS1_MODE_MASK BIT(0)
-#define REG_GPIO_PON_MODE 0x021c
+#define AN7581_REG_GPIO_PON_MODE 0x021c
+#define EN7523_REG_GPIO_PON_MODE 0x0218
#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
#define GPIO_PCIE_RESET2_MASK BIT(12)
@@ -108,11 +111,14 @@
#define GPIO_EMMC_MODE_MASK BIT(1)
#define GPIO_PON_MODE_MASK BIT(0)
-#define REG_NPU_UART_EN 0x0224
+#define AN7581_REG_NPU_UART_EN 0x0224
+#define EN7523_REG_NPU_UART_EN 0x0220
#define JTAG_UDI_EN_MASK BIT(4)
#define JTAG_DFD_EN_MASK BIT(3)
+#define NPU_UART_EN_MASK BIT(2)
-#define REG_FORCE_GPIO_EN 0x0228
+#define AN7581_REG_FORCE_GPIO_EN 0x0228
+#define EN7523_REG_FORCE_GPIO_EN 0x0224
#define FORCE_GPIO_EN(n) BIT(n)
/* LED MAP */
@@ -142,6 +148,10 @@
#define SPI_MOSI_E2_MASK BIT(13)
#define SPI_CLK_E2_MASK BIT(12)
#define SPI_CS0_E2_MASK BIT(11)
+#define EN7523_SPI_MISO_E2_MASK BIT(13)
+#define EN7523_SPI_MOSI_E2_MASK BIT(12)
+#define EN7523_SPI_CLK_E2_MASK BIT(11)
+#define EN7523_SPI_CS0_E2_MASK BIT(10)
#define PCIE2_RESET_E2_MASK BIT(10)
#define PCIE1_RESET_E2_MASK BIT(9)
#define PCIE0_RESET_E2_MASK BIT(8)
@@ -159,6 +169,10 @@
#define SPI_MOSI_E4_MASK BIT(13)
#define SPI_CLK_E4_MASK BIT(12)
#define SPI_CS0_E4_MASK BIT(11)
+#define EN7523_SPI_MISO_E4_MASK BIT(13)
+#define EN7523_SPI_MOSI_E4_MASK BIT(12)
+#define EN7523_SPI_CLK_E4_MASK BIT(11)
+#define EN7523_SPI_CS0_E4_MASK BIT(10)
#define PCIE2_RESET_E4_MASK BIT(10)
#define PCIE1_RESET_E4_MASK BIT(9)
#define PCIE0_RESET_E4_MASK BIT(8)
@@ -181,6 +195,10 @@
#define SPI_MOSI_PU_MASK BIT(13)
#define SPI_CLK_PU_MASK BIT(12)
#define SPI_CS0_PU_MASK BIT(11)
+#define EN7523_SPI_MISO_PU_MASK BIT(13)
+#define EN7523_SPI_MOSI_PU_MASK BIT(12)
+#define EN7523_SPI_CLK_PU_MASK BIT(11)
+#define EN7523_SPI_CS0_PU_MASK BIT(10)
#define PCIE2_RESET_PU_MASK BIT(10)
#define PCIE1_RESET_PU_MASK BIT(9)
#define PCIE0_RESET_PU_MASK BIT(8)
@@ -198,6 +216,10 @@
#define SPI_MOSI_PD_MASK BIT(13)
#define SPI_CLK_PD_MASK BIT(12)
#define SPI_CS0_PD_MASK BIT(11)
+#define EN7523_SPI_MISO_PD_MASK BIT(13)
+#define EN7523_SPI_MOSI_PD_MASK BIT(12)
+#define EN7523_SPI_CLK_PD_MASK BIT(11)
+#define EN7523_SPI_CS0_PD_MASK BIT(10)
#define PCIE2_RESET_PD_MASK BIT(10)
#define PCIE1_RESET_PD_MASK BIT(9)
#define PCIE0_RESET_PD_MASK BIT(8)
@@ -322,12 +344,12 @@
.regmap_size = 1, \
} \
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+#define AIROHA_PINCTRL_PHY_LED0(variant, gpio, mux_val, map_mask, map_val) \
{ \
.name = (gpio), \
.regmap[0] = { \
AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
+ variant##_REG_GPIO_2ND_I2C_MODE, \
(mux_val), \
(mux_val), \
}, \
@@ -340,12 +362,12 @@
.regmap_size = 2, \
}
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+#define AIROHA_PINCTRL_PHY_LED1(variant, gpio, mux_val, map_mask, map_val) \
{ \
.name = (gpio), \
.regmap[0] = { \
AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
+ variant##_REG_GPIO_2ND_I2C_MODE, \
(mux_val), \
(mux_val), \
}, \
@@ -449,7 +471,7 @@ enum airoha_pinctrl_confs_type {
AIROHA_PINCTRL_CONFS_DRIVE_E4,
AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
- AIROHA_PINCTRL_CONFS_MAX,
+ AIROHA_PINCTRL_CONFS_MAX
};
struct airoha_pinctrl {
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 56c452e278f5..838c7ae62e3f 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -303,7 +303,7 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
.name = "pon",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PON_MODE_MASK,
GPIO_PON_MODE_MASK
},
@@ -316,7 +316,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "pon_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
PON_TOD_1PPS_MODE_MASK,
PON_TOD_1PPS_MODE_MASK
},
@@ -325,7 +325,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "gsw_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GSW_TOD_1PPS_MODE_MASK,
GSW_TOD_1PPS_MODE_MASK
},
@@ -338,7 +338,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
.name = "sipo",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
GPIO_SIPO_MODE_MASK
},
@@ -347,7 +347,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
.name = "sipo_rclk",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
},
@@ -360,13 +360,13 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
.name = "mdio",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GPIO_MDC_IO_MASTER_MODE_MODE,
GPIO_MDC_IO_MASTER_MODE_MODE
},
.regmap[1] = {
AIROHA_FUNC_MUX,
- REG_FORCE_GPIO_EN,
+ AN7581_REG_FORCE_GPIO_EN,
FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
},
@@ -379,7 +379,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART2_MODE_MASK,
GPIO_UART2_MODE_MASK
},
@@ -388,7 +388,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart2_cts_rts",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
},
@@ -397,7 +397,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "hsuart",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
GPIO_HSUART_MODE_MASK
},
@@ -407,7 +407,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "hsuart_cts_rts",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
},
@@ -416,7 +416,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART4_MODE_MASK,
GPIO_UART4_MODE_MASK
},
@@ -425,7 +425,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart5",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART5_MODE_MASK,
GPIO_UART5_MODE_MASK
},
@@ -438,7 +438,7 @@ static const struct airoha_pinctrl_func_group i2c_func_group[] = {
.name = "i2c1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GPIO_2ND_I2C_MODE_MASK,
GPIO_2ND_I2C_MODE_MASK
},
@@ -451,7 +451,7 @@ static const struct airoha_pinctrl_func_group jtag_func_group[] = {
.name = "jtag_udi",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
+ AN7581_REG_NPU_UART_EN,
JTAG_UDI_EN_MASK,
JTAG_UDI_EN_MASK
},
@@ -460,7 +460,7 @@ static const struct airoha_pinctrl_func_group jtag_func_group[] = {
.name = "jtag_dfd",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
+ AN7581_REG_NPU_UART_EN,
JTAG_DFD_EN_MASK,
JTAG_DFD_EN_MASK
},
@@ -473,7 +473,7 @@ static const struct airoha_pinctrl_func_group pcm_func_group[] = {
.name = "pcm1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM1_MODE_MASK,
GPIO_PCM1_MODE_MASK
},
@@ -482,7 +482,7 @@ static const struct airoha_pinctrl_func_group pcm_func_group[] = {
.name = "pcm2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM2_MODE_MASK,
GPIO_PCM2_MODE_MASK
},
@@ -495,7 +495,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_quad",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_QUAD_MODE_MASK,
GPIO_SPI_QUAD_MODE_MASK
},
@@ -504,7 +504,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS1_MODE_MASK,
GPIO_SPI_CS1_MODE_MASK
},
@@ -513,7 +513,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS2_MODE_MASK,
GPIO_SPI_CS2_MODE_MASK
},
@@ -522,7 +522,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs3",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS3_MODE_MASK,
GPIO_SPI_CS3_MODE_MASK
},
@@ -531,7 +531,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS4_MODE_MASK,
GPIO_SPI_CS4_MODE_MASK
},
@@ -544,7 +544,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_MODE_MASK,
GPIO_PCM_SPI_MODE_MASK
},
@@ -553,7 +553,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_int",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_INT_MODE_MASK,
GPIO_PCM_INT_MODE_MASK
},
@@ -562,7 +562,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_rst",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_RESET_MODE_MASK,
GPIO_PCM_RESET_MODE_MASK
},
@@ -571,7 +571,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS1_MODE_MASK,
GPIO_PCM_SPI_CS1_MODE_MASK
},
@@ -580,7 +580,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs2_p128",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS2_MODE_P128_MASK,
GPIO_PCM_SPI_CS2_MODE_P128_MASK
},
@@ -589,7 +589,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs2_p156",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS2_MODE_P156_MASK,
GPIO_PCM_SPI_CS2_MODE_P156_MASK
},
@@ -598,7 +598,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs3",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS3_MODE_MASK,
GPIO_PCM_SPI_CS3_MODE_MASK
},
@@ -607,7 +607,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS4_MODE_MASK,
GPIO_PCM_SPI_CS4_MODE_MASK
},
@@ -620,7 +620,7 @@ static const struct airoha_pinctrl_func_group i2s_func_group[] = {
.name = "i2s",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GPIO_I2S_MODE_MASK,
GPIO_I2S_MODE_MASK
},
@@ -633,7 +633,7 @@ static const struct airoha_pinctrl_func_group emmc_func_group[] = {
.name = "emmc",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_EMMC_MODE_MASK,
GPIO_EMMC_MODE_MASK
},
@@ -646,7 +646,7 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
.name = "pnand",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PARALLEL_NAND_MODE_MASK,
GPIO_PARALLEL_NAND_MODE_MASK
},
@@ -659,7 +659,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
.name = "pcie_reset0",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PCIE_RESET0_MASK,
GPIO_PCIE_RESET0_MASK
},
@@ -668,7 +668,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
.name = "pcie_reset1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PCIE_RESET1_MASK,
GPIO_PCIE_RESET1_MASK
},
@@ -677,7 +677,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
.name = "pcie_reset2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PCIE_RESET2_MASK,
GPIO_PCIE_RESET2_MASK
},
@@ -732,90 +732,90 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
};
static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio34", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio35", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio42", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio43", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio44", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio45", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio46", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 4675cdf7727d..c47aca9f1077 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -284,7 +284,7 @@ static const struct airoha_pinctrl_func_group pon_func_group[] = {
.name = "pon",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PON_MODE_MASK,
GPIO_PON_MODE_MASK
},
@@ -297,7 +297,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "pon_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
PON_TOD_1PPS_MODE_MASK,
PON_TOD_1PPS_MODE_MASK
},
@@ -306,7 +306,7 @@ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
.name = "gsw_tod_1pps",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GSW_TOD_1PPS_MODE_MASK,
GSW_TOD_1PPS_MODE_MASK
},
@@ -319,7 +319,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
.name = "sipo",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
GPIO_SIPO_MODE_MASK
},
@@ -328,7 +328,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
.name = "sipo_rclk",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
},
@@ -341,13 +341,13 @@ static const struct airoha_pinctrl_func_group mdio_func_group[] = {
.name = "mdio",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_SGMII_MDIO_MODE_MASK,
GPIO_SGMII_MDIO_MODE_MASK
},
.regmap[1] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_MDC_IO_MASTER_MODE_MODE,
GPIO_MDC_IO_MASTER_MODE_MODE
},
@@ -360,7 +360,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART2_MODE_MASK,
GPIO_UART2_MODE_MASK
},
@@ -369,7 +369,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart2_cts_rts",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
},
@@ -378,7 +378,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "hsuart",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
GPIO_HSUART_MODE_MASK
},
@@ -388,7 +388,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "hsuart_cts_rts",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
},
@@ -397,7 +397,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART4_MODE_MASK,
GPIO_UART4_MODE_MASK
},
@@ -406,7 +406,7 @@ static const struct airoha_pinctrl_func_group uart_func_group[] = {
.name = "uart5",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_UART5_MODE_MASK,
GPIO_UART5_MODE_MASK
},
@@ -419,7 +419,7 @@ static const struct airoha_pinctrl_func_group i2c_func_group[] = {
.name = "i2c1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_2ND_I2C_MODE,
+ AN7581_REG_GPIO_2ND_I2C_MODE,
GPIO_2ND_I2C_MODE_MASK,
GPIO_2ND_I2C_MODE_MASK
},
@@ -432,7 +432,7 @@ static const struct airoha_pinctrl_func_group jtag_func_group[] = {
.name = "jtag_udi",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
+ AN7581_REG_NPU_UART_EN,
JTAG_UDI_EN_MASK,
JTAG_UDI_EN_MASK
},
@@ -441,7 +441,7 @@ static const struct airoha_pinctrl_func_group jtag_func_group[] = {
.name = "jtag_dfd",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_NPU_UART_EN,
+ AN7581_REG_NPU_UART_EN,
JTAG_DFD_EN_MASK,
JTAG_DFD_EN_MASK
},
@@ -454,7 +454,7 @@ static const struct airoha_pinctrl_func_group pcm_func_group[] = {
.name = "pcm1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM1_MODE_MASK,
GPIO_PCM1_MODE_MASK
},
@@ -463,7 +463,7 @@ static const struct airoha_pinctrl_func_group pcm_func_group[] = {
.name = "pcm2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM2_MODE_MASK,
GPIO_PCM2_MODE_MASK
},
@@ -476,7 +476,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_quad",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_QUAD_MODE_MASK,
GPIO_SPI_QUAD_MODE_MASK
},
@@ -485,7 +485,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS1_MODE_MASK,
GPIO_SPI_CS1_MODE_MASK
},
@@ -494,7 +494,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS2_MODE_MASK,
GPIO_SPI_CS2_MODE_MASK
},
@@ -503,7 +503,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs3",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS3_MODE_MASK,
GPIO_SPI_CS3_MODE_MASK
},
@@ -512,7 +512,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
.name = "spi_cs4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_SPI_CS4_MODE_MASK,
GPIO_SPI_CS4_MODE_MASK
},
@@ -525,7 +525,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_MODE_MASK,
GPIO_PCM_SPI_MODE_MASK
},
@@ -534,7 +534,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_int",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_INT_MODE_MASK,
GPIO_PCM_INT_MODE_MASK
},
@@ -543,7 +543,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_rst",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_RESET_MODE_MASK,
GPIO_PCM_RESET_MODE_MASK
},
@@ -552,7 +552,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS1_MODE_MASK,
GPIO_PCM_SPI_CS1_MODE_MASK
},
@@ -561,7 +561,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs2",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
},
@@ -570,7 +570,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs3",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS3_MODE_MASK,
GPIO_PCM_SPI_CS3_MODE_MASK
},
@@ -579,7 +579,7 @@ static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
.name = "pcm_spi_cs4",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_SPI_CS1_MODE,
+ AN7581_REG_GPIO_SPI_CS1_MODE,
GPIO_PCM_SPI_CS4_MODE_MASK,
GPIO_PCM_SPI_CS4_MODE_MASK
},
@@ -592,7 +592,7 @@ static const struct airoha_pinctrl_func_group emmc_func_group[] = {
.name = "emmc",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_EMMC_MODE_MASK,
GPIO_EMMC_MODE_MASK
},
@@ -605,7 +605,7 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
.name = "pnand",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PARALLEL_NAND_MODE_MASK,
GPIO_PARALLEL_NAND_MODE_MASK
},
@@ -618,7 +618,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
.name = "pcie_reset0",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PCIE_RESET0_MASK,
GPIO_PCIE_RESET0_MASK
},
@@ -627,7 +627,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
.name = "pcie_reset1",
.regmap[0] = {
AIROHA_FUNC_MUX,
- REG_GPIO_PON_MODE,
+ AN7581_REG_GPIO_PON_MODE,
GPIO_PCIE_RESET1_MASK,
GPIO_PCIE_RESET1_MASK
},
@@ -684,90 +684,90 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
};
static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
- AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio2", GPIO_LAN1_LED0_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio3", GPIO_LAN2_LED0_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED0(AN7581, "gpio4", GPIO_LAN3_LED0_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
- AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio9", GPIO_LAN1_LED1_MODE_MASK,
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio10", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
- AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1(AN7581, "gpio11", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
--
2.53.0
^ permalink raw reply related
* [PATCH 18/18] pinctrl: airoha: add support of en7523 SoC
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
This patch adds support of Airoha en7523 SoC pin controller.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/Kconfig | 6 +
drivers/pinctrl/airoha/Makefile | 1 +
drivers/pinctrl/airoha/pinctrl-en7523.c | 850 ++++++++++++++++++++++++
3 files changed, 857 insertions(+)
create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
index 08038a5b11c6..159b4496f64a 100644
--- a/drivers/pinctrl/airoha/Kconfig
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -15,6 +15,7 @@ config PINCTRL_AIROHA
select REGMAP_MMIO
imply PINCTRL_AIROHA_AN7581
imply PINCTRL_AIROHA_AN7583
+ imply PINCTRL_AIROHA_EN7523
help
Say yes here to support pin controller and gpio driver
on Airoha SoC.
@@ -29,4 +30,9 @@ config PINCTRL_AIROHA_AN7583
depends on ARM64 || COMPILE_TEST
depends on PINCTRL_AIROHA
+config PINCTRL_AIROHA_EN7523
+ tristate "EN7523 pinctrl"
+ depends on ARM || COMPILE_TEST
+ depends on PINCTRL_AIROHA
+
endmenu
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
index eac0f376b590..68ef023b7725 100644
--- a/drivers/pinctrl/airoha/Makefile
+++ b/drivers/pinctrl/airoha/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o
obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o
+obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o
diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c
new file mode 100644
index 000000000000..b77792c44dfc
--- /dev/null
+++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
@@ -0,0 +1,850 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>
+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+ */
+#include "airoha-common.h"
+
+static struct pinctrl_pin_desc pinctrl_pins[] = {
+ PINCTRL_PIN(2, "i2c_sda"),
+ PINCTRL_PIN(3, "i2c_scl"),
+ PINCTRL_PIN(4, "spi_cs0"),
+ PINCTRL_PIN(5, "spi_clk"),
+ PINCTRL_PIN(6, "spi_mosi"),
+ PINCTRL_PIN(7, "spi_miso"),
+ PINCTRL_PIN(8, "uart1_txd"),
+ PINCTRL_PIN(9, "uart1_rxd"),
+ PINCTRL_PIN(12, "gpio0"),
+ PINCTRL_PIN(13, "gpio1"),
+ PINCTRL_PIN(14, "gpio2"),
+ PINCTRL_PIN(15, "gpio3"),
+ PINCTRL_PIN(16, "gpio4"),
+ PINCTRL_PIN(17, "gpio5"),
+ PINCTRL_PIN(18, "gpio6"),
+ PINCTRL_PIN(19, "gpio7"),
+ PINCTRL_PIN(20, "gpio8"),
+ PINCTRL_PIN(21, "gpio9"),
+ PINCTRL_PIN(22, "gpio10"),
+ PINCTRL_PIN(23, "gpio11"),
+ PINCTRL_PIN(24, "gpio12"),
+ PINCTRL_PIN(25, "gpio13"),
+ PINCTRL_PIN(26, "gpio14"),
+ PINCTRL_PIN(27, "gpio15"),
+ PINCTRL_PIN(28, "gpio16"),
+ PINCTRL_PIN(29, "gpio17"),
+ PINCTRL_PIN(30, "gpio18"),
+ PINCTRL_PIN(31, "gpio19"),
+ PINCTRL_PIN(32, "gpio20"),
+ PINCTRL_PIN(33, "gpio21"),
+ PINCTRL_PIN(34, "gpio22"),
+ PINCTRL_PIN(35, "gpio23"),
+ PINCTRL_PIN(36, "gpio24"),
+ PINCTRL_PIN(37, "gpio25"),
+ PINCTRL_PIN(38, "gpio26"),
+ PINCTRL_PIN(39, "gpio27"),
+ PINCTRL_PIN(40, "pcie_reset0"),
+ PINCTRL_PIN(41, "pcie_reset1"),
+};
+
+static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 };
+static const int pon_tod_1pps_pins[] = { 21 };
+static const int gsw_tod_1pps_pins[] = { 21 };
+static const int sipo_pins[] = { 13, 38 };
+static const int sipo_rclk_pins[] = { 13, 30, 38 };
+static const int mdio_pins[] = { 20, 21 };
+static const int uart2_pins[] = { 20, 21 };
+static const int npu_uart_pins[] = { 13, 38 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 };
+static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 };
+static const int i2s_pins[] = { 16, 17, 18, 19 };
+static const int pcm1_pins[] = { 24, 25, 26, 27 };
+static const int pcm2_pins[] = { 16, 17, 18, 19 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_quad_pins[] = { 14, 15 };
+static const int spi_cs1_pins[] = { 21 };
+static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 };
+static const int pcm_spi_int_pins[] = { 15 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 22 };
+static const int pcm_spi_cs2_pins[] = { 39 };
+static const int pcm_spi_cs3_pins[] = { 20 };
+static const int pcm_spi_cs4_pins[] = { 23 };
+static const int gpio0_pins[] = { 12 };
+static const int gpio1_pins[] = { 13 };
+static const int gpio2_pins[] = { 14 };
+static const int gpio3_pins[] = { 15 };
+static const int gpio4_pins[] = { 16 };
+static const int gpio5_pins[] = { 17 };
+static const int gpio6_pins[] = { 18 };
+static const int gpio7_pins[] = { 19 };
+static const int gpio8_pins[] = { 20 };
+static const int gpio9_pins[] = { 21 };
+static const int gpio10_pins[] = { 22 };
+static const int gpio11_pins[] = { 23 };
+static const int gpio12_pins[] = { 24 };
+static const int gpio13_pins[] = { 25 };
+static const int gpio14_pins[] = { 26 };
+static const int gpio15_pins[] = { 27 };
+static const int gpio16_pins[] = { 28 };
+static const int gpio17_pins[] = { 29 };
+static const int gpio18_pins[] = { 30 };
+static const int gpio19_pins[] = { 31 };
+static const int gpio20_pins[] = { 32 };
+static const int gpio21_pins[] = { 33 };
+static const int gpio22_pins[] = { 34 };
+static const int gpio23_pins[] = { 35 };
+static const int gpio24_pins[] = { 36 };
+static const int gpio25_pins[] = { 37 };
+static const int gpio26_pins[] = { 38 };
+static const int gpio27_pins[] = { 39 };
+static const int pcie_reset0_pins[] = { 40 };
+static const int pcie_reset1_pins[] = { 41 };
+
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+};
+
+static const char *const pon_groups[] = { "pon" };
+static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
+static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+static const char *const mdio_groups[] = { "mdio" };
+
+static const char *const uart_groups[] = { "uart2", "npu_uart" };
+static const char *const i2c_groups[] = { "i2c1" };
+static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+static const char *const pcm_spi_groups[] = {
+ "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
+ "pcm_spi_cs2", "pcm_spi_cs3", "pcm_spi_cs4"
+};
+
+static const char *const i2s_groups[] = { "i2s" };
+static const char *const pcie_reset_groups[] = {
+ "pcie_reset0", "pcie_reset1"
+};
+
+static const char *const pwm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
+ "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
+ "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27"
+};
+
+static const char *const phy1_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy2_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy3_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy4_led0_groups[] = {
+ "gpio22", "gpio23", "gpio24", "gpio25"
+};
+static const char *const phy1_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy2_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy3_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+static const char *const phy4_led1_groups[] = {
+ "gpio7", "gpio6", "gpio5", "gpio4"
+};
+
+static const struct airoha_pinctrl_func_group pon_func_group[] = {
+ {
+ .name = "pon",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_PON_MODE_MASK,
+ GPIO_PON_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+ {
+ .name = "pon_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_2ND_I2C_MODE,
+ PON_TOD_1PPS_MODE_MASK,
+ PON_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "gsw_tod_1pps",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_2ND_I2C_MODE,
+ GSW_TOD_1PPS_MODE_MASK,
+ GSW_TOD_1PPS_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+ {
+ .name = "sipo",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "sipo_rclk",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+ GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+ {
+ .name = "mdio",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_SGMII_MDIO_MODE_MASK,
+ GPIO_SGMII_MDIO_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group uart_func_group[] = {
+ {
+ .name = "uart2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_UART2_MODE_MASK,
+ GPIO_UART2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "npu_uart",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_NPU_UART_EN,
+ NPU_UART_EN_MASK,
+ NPU_UART_EN_MASK
+ },
+ .regmap_size = 1,
+ }
+};
+
+static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+ {
+ .name = "i2c1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_2ND_I2C_MODE,
+ GPIO_2ND_I2C_MODE_MASK,
+ GPIO_2ND_I2C_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+ {
+ .name = "jtag_udi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_NPU_UART_EN,
+ JTAG_UDI_EN_MASK,
+ JTAG_UDI_EN_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "jtag_dfd",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_NPU_UART_EN,
+ JTAG_DFD_EN_MASK,
+ JTAG_DFD_EN_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+ {
+ .name = "pcm1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM1_MODE_MASK,
+ GPIO_PCM1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM2_MODE_MASK,
+ GPIO_PCM2_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group spi_func_group[] = {
+ {
+ .name = "spi_quad",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_QUAD_MODE_MASK,
+ GPIO_SPI_QUAD_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS1_MODE_MASK,
+ GPIO_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS2_MODE_MASK,
+ GPIO_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS3_MODE_MASK,
+ GPIO_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_SPI_CS4_MODE_MASK,
+ GPIO_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+ {
+ .name = "pcm_spi",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_MODE_MASK,
+ GPIO_PCM_SPI_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_int",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_INT_MODE_MASK,
+ GPIO_PCM_INT_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_rst",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_RESET_MODE_MASK,
+ GPIO_PCM_RESET_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS1_MODE_MASK,
+ GPIO_PCM_SPI_CS1_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs2",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+ AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs3",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS3_MODE_MASK,
+ GPIO_PCM_SPI_CS3_MODE_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcm_spi_cs4",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_SPI_CS1_MODE,
+ GPIO_PCM_SPI_CS4_MODE_MASK,
+ GPIO_PCM_SPI_CS4_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+ {
+ .name = "i2s",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_2ND_I2C_MODE,
+ GPIO_I2S_MODE_MASK,
+ GPIO_I2S_MODE_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+ {
+ .name = "pcie_reset0",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET0_MASK,
+ GPIO_PCIE_RESET0_MASK
+ },
+ .regmap_size = 1,
+ }, {
+ .name = "pcie_reset1",
+ .regmap[0] = {
+ AIROHA_FUNC_MUX,
+ EN7523_REG_GPIO_PON_MODE,
+ GPIO_PCIE_RESET1_MASK,
+ GPIO_PCIE_RESET1_MASK
+ },
+ .regmap_size = 1,
+ },
+};
+
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+ AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+ AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio22", GPIO_LAN0_LED0_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio23", GPIO_LAN1_LED0_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio24", GPIO_LAN2_LED0_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED0(EN7523, "gpio25", GPIO_LAN3_LED0_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+};
+
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+};
+
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+};
+
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio7", GPIO_LAN0_LED1_MODE_MASK,
+ LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio6", GPIO_LAN1_LED1_MODE_MASK,
+ LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio5", GPIO_LAN2_LED1_MODE_MASK,
+ LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+ AIROHA_PINCTRL_PHY_LED1(EN7523, "gpio4", GPIO_LAN3_LED1_MODE_MASK,
+ LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+};
+
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+ PINCTRL_FUNC_DESC("pon", pon),
+ PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+ PINCTRL_FUNC_DESC("sipo", sipo),
+ PINCTRL_FUNC_DESC("mdio", mdio),
+ PINCTRL_FUNC_DESC("uart", uart),
+ PINCTRL_FUNC_DESC("i2c", i2c),
+ PINCTRL_FUNC_DESC("jtag", jtag),
+ PINCTRL_FUNC_DESC("pcm", pcm),
+ PINCTRL_FUNC_DESC("spi", spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+ PINCTRL_FUNC_DESC("i2s", i2s),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+ PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)),
+ PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)),
+ PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)),
+ PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)),
+ PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)),
+ PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)),
+ PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)),
+ PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)),
+ PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)),
+ PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)),
+ PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)),
+ PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)),
+ PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)),
+ PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)),
+ PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)),
+ PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)),
+ PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)),
+ PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)),
+ PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)),
+ PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)),
+ PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)),
+ PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)),
+ PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)),
+ PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)),
+ PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)),
+ PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)),
+ PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)),
+ PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)),
+ PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)),
+ PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)),
+};
+
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
+ PINCTRL_CONF_DESC(40, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+ PINCTRL_CONF_DESC(41, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+};
+
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+ .confs_info = {
+ [AIROHA_PINCTRL_CONFS_PULLUP] = {
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+ },
+ [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
+ },
+ },
+};
+
+static const struct of_device_id airoha_pinctrl_of_match[] = {
+ { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+
+static struct platform_driver airoha_pinctrl_driver = {
+ .probe = airoha_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-airoha-en7523",
+ .of_match_table = airoha_pinctrl_of_match,
+ },
+};
+module_platform_driver(airoha_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>");
+MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>");
+MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC");
--
2.53.0
^ permalink raw reply related
* [PATCH 16/18] pinctrl: airoha: an7583: remove an7583 prefix from variable names
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7583 specific code in the pinctrl-an7583 kernel module,
so 'an75831_' prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7583.c | 482 ++++++++++++------------
1 file changed, 241 insertions(+), 241 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c
index 5b5e766abd45..4675cdf7727d 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
@@ -7,7 +7,7 @@
#include "airoha-common.h"
-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(2, "gpio0"),
PINCTRL_PIN(3, "gpio1"),
PINCTRL_PIN(4, "gpio2"),
@@ -63,170 +63,170 @@ static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
PINCTRL_PIN(54, "mdio_0"),
};
-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
-static const int an7583_pon_tod_1pps_pins[] = { 32 };
-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
-static const int an7583_sipo_pins[] = { 34, 35 };
-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
-static const int an7583_mdio_pins[] = { 43, 44 };
-static const int an7583_uart2_pins[] = { 34, 35 };
-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
-static const int an7583_hsuart_pins[] = { 30, 31 };
-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
-static const int an7583_npu_uart_pins[] = { 7, 8 };
-static const int an7583_uart4_pins[] = { 7, 8 };
-static const int an7583_uart5_pins[] = { 23, 24 };
-static const int an7583_i2c0_pins[] = { 41, 42 };
-static const int an7583_i2c1_pins[] = { 43, 44 };
-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-static const int an7583_spi_quad_pins[] = { 25, 26 };
-static const int an7583_spi_cs1_pins[] = { 27 };
-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-static const int an7583_pcm_spi_rst_pins[] = { 14 };
-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
-static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
-static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
-static const int an7583_gpio0_pins[] = { 2 };
-static const int an7583_gpio1_pins[] = { 3 };
-static const int an7583_gpio2_pins[] = { 4 };
-static const int an7583_gpio3_pins[] = { 5 };
-static const int an7583_gpio4_pins[] = { 6 };
-static const int an7583_gpio5_pins[] = { 7 };
-static const int an7583_gpio6_pins[] = { 8 };
-static const int an7583_gpio7_pins[] = { 9 };
-static const int an7583_gpio8_pins[] = { 10 };
-static const int an7583_gpio9_pins[] = { 11 };
-static const int an7583_gpio10_pins[] = { 12 };
-static const int an7583_gpio11_pins[] = { 13 };
-static const int an7583_gpio12_pins[] = { 14 };
-static const int an7583_gpio13_pins[] = { 15 };
-static const int an7583_gpio14_pins[] = { 16 };
-static const int an7583_gpio15_pins[] = { 17 };
-static const int an7583_gpio16_pins[] = { 18 };
-static const int an7583_gpio17_pins[] = { 19 };
-static const int an7583_gpio18_pins[] = { 20 };
-static const int an7583_gpio19_pins[] = { 21 };
-static const int an7583_gpio20_pins[] = { 22 };
-static const int an7583_gpio21_pins[] = { 23 };
-static const int an7583_gpio22_pins[] = { 24 };
-static const int an7583_gpio23_pins[] = { 25 };
-static const int an7583_gpio24_pins[] = { 26 };
-static const int an7583_gpio25_pins[] = { 27 };
-static const int an7583_gpio26_pins[] = { 28 };
-static const int an7583_gpio27_pins[] = { 29 };
-static const int an7583_gpio28_pins[] = { 30 };
-static const int an7583_gpio29_pins[] = { 31 };
-static const int an7583_gpio30_pins[] = { 32 };
-static const int an7583_gpio31_pins[] = { 33 };
-static const int an7583_gpio32_pins[] = { 34 };
-static const int an7583_gpio33_pins[] = { 35 };
-static const int an7583_gpio34_pins[] = { 36 };
-static const int an7583_gpio35_pins[] = { 37 };
-static const int an7583_gpio36_pins[] = { 38 };
-static const int an7583_gpio37_pins[] = { 39 };
-static const int an7583_gpio38_pins[] = { 40 };
-static const int an7583_gpio39_pins[] = { 41 };
-static const int an7583_gpio40_pins[] = { 42 };
-static const int an7583_gpio41_pins[] = { 43 };
-static const int an7583_gpio42_pins[] = { 44 };
-static const int an7583_gpio43_pins[] = { 45 };
-static const int an7583_gpio44_pins[] = { 46 };
-static const int an7583_gpio45_pins[] = { 47 };
-static const int an7583_gpio46_pins[] = { 48 };
-static const int an7583_gpio47_pins[] = { 49 };
-static const int an7583_gpio48_pins[] = { 50 };
-static const int an7583_pcie_reset0_pins[] = { 51 };
-static const int an7583_pcie_reset1_pins[] = { 52 };
+static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+static const int pon_tod_1pps_pins[] = { 32 };
+static const int gsw_tod_1pps_pins[] = { 32 };
+static const int sipo_pins[] = { 34, 35 };
+static const int sipo_rclk_pins[] = { 34, 35, 33 };
+static const int mdio_pins[] = { 43, 44 };
+static const int uart2_pins[] = { 34, 35 };
+static const int uart2_cts_rts_pins[] = { 32, 33 };
+static const int hsuart_pins[] = { 30, 31 };
+static const int hsuart_cts_rts_pins[] = { 28, 29 };
+static const int npu_uart_pins[] = { 7, 8 };
+static const int uart4_pins[] = { 7, 8 };
+static const int uart5_pins[] = { 23, 24 };
+static const int i2c0_pins[] = { 41, 42 };
+static const int i2c1_pins[] = { 43, 44 };
+static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+static const int pcm1_pins[] = { 10, 11, 12, 13, 14 };
+static const int pcm2_pins[] = { 28, 29, 30, 31, 24 };
+static const int spi_pins[] = { 28, 29, 30, 31 };
+static const int spi_quad_pins[] = { 25, 26 };
+static const int spi_cs1_pins[] = { 27 };
+static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+static const int pcm_spi_rst_pins[] = { 14 };
+static const int pcm_spi_cs1_pins[] = { 24 };
+static const int emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
+static const int pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
+static const int gpio0_pins[] = { 2 };
+static const int gpio1_pins[] = { 3 };
+static const int gpio2_pins[] = { 4 };
+static const int gpio3_pins[] = { 5 };
+static const int gpio4_pins[] = { 6 };
+static const int gpio5_pins[] = { 7 };
+static const int gpio6_pins[] = { 8 };
+static const int gpio7_pins[] = { 9 };
+static const int gpio8_pins[] = { 10 };
+static const int gpio9_pins[] = { 11 };
+static const int gpio10_pins[] = { 12 };
+static const int gpio11_pins[] = { 13 };
+static const int gpio12_pins[] = { 14 };
+static const int gpio13_pins[] = { 15 };
+static const int gpio14_pins[] = { 16 };
+static const int gpio15_pins[] = { 17 };
+static const int gpio16_pins[] = { 18 };
+static const int gpio17_pins[] = { 19 };
+static const int gpio18_pins[] = { 20 };
+static const int gpio19_pins[] = { 21 };
+static const int gpio20_pins[] = { 22 };
+static const int gpio21_pins[] = { 23 };
+static const int gpio22_pins[] = { 24 };
+static const int gpio23_pins[] = { 25 };
+static const int gpio24_pins[] = { 26 };
+static const int gpio25_pins[] = { 27 };
+static const int gpio26_pins[] = { 28 };
+static const int gpio27_pins[] = { 29 };
+static const int gpio28_pins[] = { 30 };
+static const int gpio29_pins[] = { 31 };
+static const int gpio30_pins[] = { 32 };
+static const int gpio31_pins[] = { 33 };
+static const int gpio32_pins[] = { 34 };
+static const int gpio33_pins[] = { 35 };
+static const int gpio34_pins[] = { 36 };
+static const int gpio35_pins[] = { 37 };
+static const int gpio36_pins[] = { 38 };
+static const int gpio37_pins[] = { 39 };
+static const int gpio38_pins[] = { 40 };
+static const int gpio39_pins[] = { 41 };
+static const int gpio40_pins[] = { 42 };
+static const int gpio41_pins[] = { 43 };
+static const int gpio42_pins[] = { 44 };
+static const int gpio43_pins[] = { 45 };
+static const int gpio44_pins[] = { 46 };
+static const int gpio45_pins[] = { 47 };
+static const int gpio46_pins[] = { 48 };
+static const int gpio47_pins[] = { 49 };
+static const int gpio48_pins[] = { 50 };
+static const int pcie_reset0_pins[] = { 51 };
+static const int pcie_reset1_pins[] = { 52 };
-static const struct pingroup an7583_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", an7583_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", an7583_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", an7583_mdio),
- PINCTRL_PIN_GROUP("uart2", an7583_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
- PINCTRL_PIN_GROUP("uart4", an7583_uart4),
- PINCTRL_PIN_GROUP("uart5", an7583_uart5),
- PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
- PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
- PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
- PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
- PINCTRL_PIN_GROUP("spi", an7583_spi),
- PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("emmc", an7583_emmc),
- PINCTRL_PIN_GROUP("pnand", an7583_pnand),
- PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
- PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
- PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
- PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
- PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
- PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
- PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
- PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
- PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
- PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
- PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
- PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
- PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
- PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
- PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
- PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
- PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
- PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
- PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
- PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
- PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
- PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
- PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
- PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
- PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
- PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
- PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
- PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
- PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
- PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
- PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
- PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
- PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
- PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
- PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
- PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
- PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
- PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
- PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
- PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
- PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
- PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
- PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
- PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
- PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
- PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
- PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
- PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
- PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
- PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("npu_uart", npu_uart),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("gpio47", gpio47),
+ PINCTRL_PIN_GROUP("gpio48", gpio48),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
};
static const char *const pon_groups[] = { "pon" };
static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
-static const char *const an7583_mdio_groups[] = { "mdio" };
+static const char *const mdio_groups[] = { "mdio" };
static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
"hsuart_cts_rts", "uart4",
"uart5" };
@@ -234,49 +234,49 @@ static const char *const i2c_groups[] = { "i2c1" };
static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
static const char *const pcm_groups[] = { "pcm1", "pcm2" };
static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
- "pcm_spi_rst", "pcm_spi_cs1" };
+static const char *const pcm_spi_groups[] = { "pcm_spi",
+ "pcm_spi_rst", "pcm_spi_cs1" };
static const char *const emmc_groups[] = { "emmc" };
static const char *const pnand_groups[] = { "pnand" };
-static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
-static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
- "gpio2", "gpio3",
- "gpio4", "gpio5",
- "gpio6", "gpio7",
- "gpio8", "gpio9",
- "gpio10", "gpio11",
- "gpio12", "gpio13",
- "gpio14", "gpio15",
- "gpio16", "gpio17",
- "gpio18", "gpio19",
- "gpio20", "gpio21",
- "gpio22", "gpio23",
- "gpio24", "gpio25",
- "gpio26", "gpio27",
- "gpio28", "gpio29",
- "gpio30", "gpio31",
- "gpio36", "gpio37",
- "gpio38", "gpio39",
- "gpio40", "gpio41",
- "gpio42", "gpio43",
- "gpio44", "gpio45",
- "gpio46", "gpio47",
- "gpio48" };
-static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
+static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
+static const char *const pwm_groups[] = { "gpio0", "gpio1",
+ "gpio2", "gpio3",
+ "gpio4", "gpio5",
+ "gpio6", "gpio7",
+ "gpio8", "gpio9",
+ "gpio10", "gpio11",
+ "gpio12", "gpio13",
+ "gpio14", "gpio15",
+ "gpio16", "gpio17",
+ "gpio18", "gpio19",
+ "gpio20", "gpio21",
+ "gpio22", "gpio23",
+ "gpio24", "gpio25",
+ "gpio26", "gpio27",
+ "gpio28", "gpio29",
+ "gpio30", "gpio31",
+ "gpio36", "gpio37",
+ "gpio38", "gpio39",
+ "gpio40", "gpio41",
+ "gpio42", "gpio43",
+ "gpio44", "gpio45",
+ "gpio46", "gpio47",
+ "gpio48" };
+static const char *const phy1_led0_groups[] = { "gpio1", "gpio2",
"gpio3", "gpio4" };
-static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
+static const char *const phy2_led0_groups[] = { "gpio1", "gpio2",
"gpio3", "gpio4" };
-static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
+static const char *const phy3_led0_groups[] = { "gpio1", "gpio2",
"gpio3", "gpio4" };
-static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
+static const char *const phy4_led0_groups[] = { "gpio1", "gpio2",
"gpio3", "gpio4" };
-static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
+static const char *const phy1_led1_groups[] = { "gpio8", "gpio9",
"gpio10", "gpio11" };
-static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
+static const char *const phy2_led1_groups[] = { "gpio8", "gpio9",
"gpio10", "gpio11" };
-static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
+static const char *const phy3_led1_groups[] = { "gpio8", "gpio9",
"gpio10", "gpio11" };
-static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
+static const char *const phy4_led1_groups[] = { "gpio8", "gpio9",
"gpio10", "gpio11" };
static const struct airoha_pinctrl_func_group pon_func_group[] = {
@@ -336,7 +336,7 @@ static const struct airoha_pinctrl_func_group sipo_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+static const struct airoha_pinctrl_func_group mdio_func_group[] = {
{
.name = "mdio",
.regmap[0] = {
@@ -520,7 +520,7 @@ static const struct airoha_pinctrl_func_group spi_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
{
.name = "pcm_spi",
.regmap[0] = {
@@ -613,7 +613,7 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
{
.name = "pcie_reset0",
.regmap[0] = {
@@ -635,7 +635,7 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
},
};
-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
@@ -683,7 +683,7 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -694,7 +694,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -705,7 +705,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -716,7 +716,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
@@ -727,7 +727,7 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -738,7 +738,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -749,7 +749,7 @@ static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
};
-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -760,7 +760,7 @@ static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
};
-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
@@ -771,32 +771,32 @@ static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
- PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+ PINCTRL_FUNC_DESC("mdio", mdio),
PINCTRL_FUNC_DESC("uart", uart),
PINCTRL_FUNC_DESC("i2c", i2c),
PINCTRL_FUNC_DESC("jtag", jtag),
PINCTRL_FUNC_DESC("pcm", pcm),
PINCTRL_FUNC_DESC("spi", spi),
- PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+ PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
PINCTRL_FUNC_DESC("emmc", emmc),
PINCTRL_FUNC_DESC("pnand", pnand),
- PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
- PINCTRL_FUNC_DESC("pwm", an7583_pwm),
- PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
- PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
- PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
- PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
- PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
- PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
- PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
- PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+ PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+ PINCTRL_FUNC_DESC("pwm", pwm),
+ PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+ PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+ PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+ PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+ PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+ PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+ PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+ PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
@@ -852,7 +852,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
@@ -908,7 +908,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
@@ -964,7 +964,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
@@ -1020,44 +1020,44 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
};
-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
- .pins = an7583_pinctrl_pins,
- .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
- .grps = an7583_pinctrl_groups,
- .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
- .funcs = an7583_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = an7583_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = an7583_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = an7583_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = an7583_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = an7583_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+ { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH 15/18] pinctrl: airoha: an7581: remove en7581 prefix from variable names
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
We have only an7581 specific code in the pinctrl-an7581 kernel module,
so 'en7581_' prefix is not necessary anymore. Remove it.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/pinctrl-an7581.c | 384 ++++++++++++------------
1 file changed, 192 insertions(+), 192 deletions(-)
diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c
index 22feb5e04388..56c452e278f5 100644
--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
+++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
@@ -7,7 +7,7 @@
#include "airoha-common.h"
-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+static struct pinctrl_pin_desc pinctrl_pins[] = {
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
PINCTRL_PIN(2, "i2c_scl"),
@@ -68,174 +68,174 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(63, "pcie_reset2"),
};
-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
-static const int en7581_pon_tod_1pps_pins[] = { 46 };
-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
-static const int en7581_sipo_pins[] = { 16, 17 };
-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
-static const int en7581_mdio_pins[] = { 14, 15 };
-static const int en7581_uart2_pins[] = { 48, 55 };
-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
-static const int en7581_hsuart_pins[] = { 28, 29 };
-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
-static const int en7581_uart4_pins[] = { 38, 39 };
-static const int en7581_uart5_pins[] = { 18, 19 };
-static const int en7581_i2c0_pins[] = { 2, 3 };
-static const int en7581_i2c1_pins[] = { 14, 15 };
-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
-static const int en7581_spi_quad_pins[] = { 32, 33 };
-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
-static const int en7581_spi_cs1_pins[] = { 34 };
-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
-static const int en7581_pcm_spi_int_pins[] = { 14 };
-static const int en7581_pcm_spi_rst_pins[] = { 15 };
-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
-static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
-static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
-static const int en7581_gpio0_pins[] = { 13 };
-static const int en7581_gpio1_pins[] = { 14 };
-static const int en7581_gpio2_pins[] = { 15 };
-static const int en7581_gpio3_pins[] = { 16 };
-static const int en7581_gpio4_pins[] = { 17 };
-static const int en7581_gpio5_pins[] = { 18 };
-static const int en7581_gpio6_pins[] = { 19 };
-static const int en7581_gpio7_pins[] = { 20 };
-static const int en7581_gpio8_pins[] = { 21 };
-static const int en7581_gpio9_pins[] = { 22 };
-static const int en7581_gpio10_pins[] = { 23 };
-static const int en7581_gpio11_pins[] = { 24 };
-static const int en7581_gpio12_pins[] = { 25 };
-static const int en7581_gpio13_pins[] = { 26 };
-static const int en7581_gpio14_pins[] = { 27 };
-static const int en7581_gpio15_pins[] = { 28 };
-static const int en7581_gpio16_pins[] = { 29 };
-static const int en7581_gpio17_pins[] = { 30 };
-static const int en7581_gpio18_pins[] = { 31 };
-static const int en7581_gpio19_pins[] = { 32 };
-static const int en7581_gpio20_pins[] = { 33 };
-static const int en7581_gpio21_pins[] = { 34 };
-static const int en7581_gpio22_pins[] = { 35 };
-static const int en7581_gpio23_pins[] = { 36 };
-static const int en7581_gpio24_pins[] = { 37 };
-static const int en7581_gpio25_pins[] = { 38 };
-static const int en7581_gpio26_pins[] = { 39 };
-static const int en7581_gpio27_pins[] = { 40 };
-static const int en7581_gpio28_pins[] = { 41 };
-static const int en7581_gpio29_pins[] = { 42 };
-static const int en7581_gpio30_pins[] = { 43 };
-static const int en7581_gpio31_pins[] = { 44 };
-static const int en7581_gpio32_pins[] = { 45 };
-static const int en7581_gpio33_pins[] = { 46 };
-static const int en7581_gpio34_pins[] = { 47 };
-static const int en7581_gpio35_pins[] = { 48 };
-static const int en7581_gpio36_pins[] = { 49 };
-static const int en7581_gpio37_pins[] = { 50 };
-static const int en7581_gpio38_pins[] = { 51 };
-static const int en7581_gpio39_pins[] = { 52 };
-static const int en7581_gpio40_pins[] = { 53 };
-static const int en7581_gpio41_pins[] = { 54 };
-static const int en7581_gpio42_pins[] = { 55 };
-static const int en7581_gpio43_pins[] = { 56 };
-static const int en7581_gpio44_pins[] = { 57 };
-static const int en7581_gpio45_pins[] = { 58 };
-static const int en7581_gpio46_pins[] = { 59 };
-static const int en7581_pcie_reset0_pins[] = { 61 };
-static const int en7581_pcie_reset1_pins[] = { 62 };
-static const int en7581_pcie_reset2_pins[] = { 63 };
+static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+static const int pon_tod_1pps_pins[] = { 46 };
+static const int gsw_tod_1pps_pins[] = { 46 };
+static const int sipo_pins[] = { 16, 17 };
+static const int sipo_rclk_pins[] = { 16, 17, 43 };
+static const int mdio_pins[] = { 14, 15 };
+static const int uart2_pins[] = { 48, 55 };
+static const int uart2_cts_rts_pins[] = { 46, 47 };
+static const int hsuart_pins[] = { 28, 29 };
+static const int hsuart_cts_rts_pins[] = { 26, 27 };
+static const int uart4_pins[] = { 38, 39 };
+static const int uart5_pins[] = { 18, 19 };
+static const int i2c0_pins[] = { 2, 3 };
+static const int i2c1_pins[] = { 14, 15 };
+static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+static const int i2s_pins[] = { 26, 27, 28, 29 };
+static const int pcm1_pins[] = { 22, 23, 24, 25 };
+static const int pcm2_pins[] = { 18, 19, 20, 21 };
+static const int spi_quad_pins[] = { 32, 33 };
+static const int spi_pins[] = { 4, 5, 6, 7 };
+static const int spi_cs1_pins[] = { 34 };
+static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+static const int pcm_spi_int_pins[] = { 14 };
+static const int pcm_spi_rst_pins[] = { 15 };
+static const int pcm_spi_cs1_pins[] = { 43 };
+static const int pcm_spi_cs2_pins[] = { 40 };
+static const int pcm_spi_cs2_p128_pins[] = { 40 };
+static const int pcm_spi_cs2_p156_pins[] = { 40 };
+static const int pcm_spi_cs3_pins[] = { 41 };
+static const int pcm_spi_cs4_pins[] = { 42 };
+static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
+static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
+static const int gpio0_pins[] = { 13 };
+static const int gpio1_pins[] = { 14 };
+static const int gpio2_pins[] = { 15 };
+static const int gpio3_pins[] = { 16 };
+static const int gpio4_pins[] = { 17 };
+static const int gpio5_pins[] = { 18 };
+static const int gpio6_pins[] = { 19 };
+static const int gpio7_pins[] = { 20 };
+static const int gpio8_pins[] = { 21 };
+static const int gpio9_pins[] = { 22 };
+static const int gpio10_pins[] = { 23 };
+static const int gpio11_pins[] = { 24 };
+static const int gpio12_pins[] = { 25 };
+static const int gpio13_pins[] = { 26 };
+static const int gpio14_pins[] = { 27 };
+static const int gpio15_pins[] = { 28 };
+static const int gpio16_pins[] = { 29 };
+static const int gpio17_pins[] = { 30 };
+static const int gpio18_pins[] = { 31 };
+static const int gpio19_pins[] = { 32 };
+static const int gpio20_pins[] = { 33 };
+static const int gpio21_pins[] = { 34 };
+static const int gpio22_pins[] = { 35 };
+static const int gpio23_pins[] = { 36 };
+static const int gpio24_pins[] = { 37 };
+static const int gpio25_pins[] = { 38 };
+static const int gpio26_pins[] = { 39 };
+static const int gpio27_pins[] = { 40 };
+static const int gpio28_pins[] = { 41 };
+static const int gpio29_pins[] = { 42 };
+static const int gpio30_pins[] = { 43 };
+static const int gpio31_pins[] = { 44 };
+static const int gpio32_pins[] = { 45 };
+static const int gpio33_pins[] = { 46 };
+static const int gpio34_pins[] = { 47 };
+static const int gpio35_pins[] = { 48 };
+static const int gpio36_pins[] = { 49 };
+static const int gpio37_pins[] = { 50 };
+static const int gpio38_pins[] = { 51 };
+static const int gpio39_pins[] = { 52 };
+static const int gpio40_pins[] = { 53 };
+static const int gpio41_pins[] = { 54 };
+static const int gpio42_pins[] = { 55 };
+static const int gpio43_pins[] = { 56 };
+static const int gpio44_pins[] = { 57 };
+static const int gpio45_pins[] = { 58 };
+static const int gpio46_pins[] = { 59 };
+static const int pcie_reset0_pins[] = { 61 };
+static const int pcie_reset1_pins[] = { 62 };
+static const int pcie_reset2_pins[] = { 63 };
-static const struct pingroup en7581_pinctrl_groups[] = {
- PINCTRL_PIN_GROUP("pon", en7581_pon),
- PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
- PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
- PINCTRL_PIN_GROUP("sipo", en7581_sipo),
- PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
- PINCTRL_PIN_GROUP("mdio", en7581_mdio),
- PINCTRL_PIN_GROUP("uart2", en7581_uart2),
- PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
- PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
- PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
- PINCTRL_PIN_GROUP("uart4", en7581_uart4),
- PINCTRL_PIN_GROUP("uart5", en7581_uart5),
- PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
- PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
- PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
- PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
- PINCTRL_PIN_GROUP("i2s", en7581_i2s),
- PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
- PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
- PINCTRL_PIN_GROUP("spi", en7581_spi),
- PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
- PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
- PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
- PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
- PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
- PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
- PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
- PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
- PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
- PINCTRL_PIN_GROUP("emmc", en7581_emmc),
- PINCTRL_PIN_GROUP("pnand", en7581_pnand),
- PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
- PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
- PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
- PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
- PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
- PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
- PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
- PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
- PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
- PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
- PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
- PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
- PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
- PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
- PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
- PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
- PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
- PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
- PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
- PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
- PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
- PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
- PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
- PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
- PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
- PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
- PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
- PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
- PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
- PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
- PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
- PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
- PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
- PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
- PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
- PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
- PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
- PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
- PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
- PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
- PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
- PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
- PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
- PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
- PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
- PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
- PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
- PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
- PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
- PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+static const struct pingroup pinctrl_groups[] = {
+ PINCTRL_PIN_GROUP("pon", pon),
+ PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+ PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+ PINCTRL_PIN_GROUP("sipo", sipo),
+ PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
+ PINCTRL_PIN_GROUP("mdio", mdio),
+ PINCTRL_PIN_GROUP("uart2", uart2),
+ PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
+ PINCTRL_PIN_GROUP("hsuart", hsuart),
+ PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
+ PINCTRL_PIN_GROUP("uart4", uart4),
+ PINCTRL_PIN_GROUP("uart5", uart5),
+ PINCTRL_PIN_GROUP("i2c0", i2c0),
+ PINCTRL_PIN_GROUP("i2c1", i2c1),
+ PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
+ PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
+ PINCTRL_PIN_GROUP("i2s", i2s),
+ PINCTRL_PIN_GROUP("pcm1", pcm1),
+ PINCTRL_PIN_GROUP("pcm2", pcm2),
+ PINCTRL_PIN_GROUP("spi", spi),
+ PINCTRL_PIN_GROUP("spi_quad", spi_quad),
+ PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
+ PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
+ PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
+ PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
+ PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
+ PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
+ PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
+ PINCTRL_PIN_GROUP("emmc", emmc),
+ PINCTRL_PIN_GROUP("pnand", pnand),
+ PINCTRL_PIN_GROUP("gpio0", gpio0),
+ PINCTRL_PIN_GROUP("gpio1", gpio1),
+ PINCTRL_PIN_GROUP("gpio2", gpio2),
+ PINCTRL_PIN_GROUP("gpio3", gpio3),
+ PINCTRL_PIN_GROUP("gpio4", gpio4),
+ PINCTRL_PIN_GROUP("gpio5", gpio5),
+ PINCTRL_PIN_GROUP("gpio6", gpio6),
+ PINCTRL_PIN_GROUP("gpio7", gpio7),
+ PINCTRL_PIN_GROUP("gpio8", gpio8),
+ PINCTRL_PIN_GROUP("gpio9", gpio9),
+ PINCTRL_PIN_GROUP("gpio10", gpio10),
+ PINCTRL_PIN_GROUP("gpio11", gpio11),
+ PINCTRL_PIN_GROUP("gpio12", gpio12),
+ PINCTRL_PIN_GROUP("gpio13", gpio13),
+ PINCTRL_PIN_GROUP("gpio14", gpio14),
+ PINCTRL_PIN_GROUP("gpio15", gpio15),
+ PINCTRL_PIN_GROUP("gpio16", gpio16),
+ PINCTRL_PIN_GROUP("gpio17", gpio17),
+ PINCTRL_PIN_GROUP("gpio18", gpio18),
+ PINCTRL_PIN_GROUP("gpio19", gpio19),
+ PINCTRL_PIN_GROUP("gpio20", gpio20),
+ PINCTRL_PIN_GROUP("gpio21", gpio21),
+ PINCTRL_PIN_GROUP("gpio22", gpio22),
+ PINCTRL_PIN_GROUP("gpio23", gpio23),
+ PINCTRL_PIN_GROUP("gpio24", gpio24),
+ PINCTRL_PIN_GROUP("gpio25", gpio25),
+ PINCTRL_PIN_GROUP("gpio26", gpio26),
+ PINCTRL_PIN_GROUP("gpio27", gpio27),
+ PINCTRL_PIN_GROUP("gpio28", gpio28),
+ PINCTRL_PIN_GROUP("gpio29", gpio29),
+ PINCTRL_PIN_GROUP("gpio30", gpio30),
+ PINCTRL_PIN_GROUP("gpio31", gpio31),
+ PINCTRL_PIN_GROUP("gpio32", gpio32),
+ PINCTRL_PIN_GROUP("gpio33", gpio33),
+ PINCTRL_PIN_GROUP("gpio34", gpio34),
+ PINCTRL_PIN_GROUP("gpio35", gpio35),
+ PINCTRL_PIN_GROUP("gpio36", gpio36),
+ PINCTRL_PIN_GROUP("gpio37", gpio37),
+ PINCTRL_PIN_GROUP("gpio38", gpio38),
+ PINCTRL_PIN_GROUP("gpio39", gpio39),
+ PINCTRL_PIN_GROUP("gpio40", gpio40),
+ PINCTRL_PIN_GROUP("gpio41", gpio41),
+ PINCTRL_PIN_GROUP("gpio42", gpio42),
+ PINCTRL_PIN_GROUP("gpio43", gpio43),
+ PINCTRL_PIN_GROUP("gpio44", gpio44),
+ PINCTRL_PIN_GROUP("gpio45", gpio45),
+ PINCTRL_PIN_GROUP("gpio46", gpio46),
+ PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
+ PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+ PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2),
};
static const char *const pon_groups[] = { "pon" };
@@ -819,7 +819,7 @@ static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
};
-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+static const struct airoha_pinctrl_func pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("pon", pon),
PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
PINCTRL_FUNC_DESC("sipo", sipo),
@@ -845,7 +845,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
@@ -906,7 +906,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
@@ -967,7 +967,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
@@ -1028,7 +1028,7 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
@@ -1089,45 +1089,45 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
};
-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
};
-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
- .pins = en7581_pinctrl_pins,
- .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
- .grps = en7581_pinctrl_groups,
- .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
- .funcs = en7581_pinctrl_funcs,
- .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+ .pins = pinctrl_pins,
+ .num_pins = ARRAY_SIZE(pinctrl_pins),
+ .grps = pinctrl_groups,
+ .num_grps = ARRAY_SIZE(pinctrl_groups),
+ .funcs = pinctrl_funcs,
+ .num_funcs = ARRAY_SIZE(pinctrl_funcs),
.confs_info = {
[AIROHA_PINCTRL_CONFS_PULLUP] = {
- .confs = en7581_pinctrl_pullup_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+ .confs = pinctrl_pullup_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
},
[AIROHA_PINCTRL_CONFS_PULLDOWN] = {
- .confs = en7581_pinctrl_pulldown_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+ .confs = pinctrl_pulldown_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
- .confs = en7581_pinctrl_drive_e2_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+ .confs = pinctrl_drive_e2_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
},
[AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
- .confs = en7581_pinctrl_drive_e4_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+ .confs = pinctrl_drive_e4_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
},
[AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
- .confs = en7581_pinctrl_pcie_rst_od_conf,
- .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+ .confs = pinctrl_pcie_rst_od_conf,
+ .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
},
},
};
static const struct of_device_id airoha_pinctrl_of_match[] = {
- { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+ { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
--
2.53.0
^ permalink raw reply related
* [PATCH 13/18] pinctrl: airoha: move common definitions to the separate header
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
Let's move the definitions and declarations of structures required for
Airoha SoC-specific pinctrl drivers to a common header. Later we'll have
several SoC-specific drivers, so this step is necessary.
No functional changes.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/airoha/airoha-common.h | 479 ++++++++++++++++++++++++
drivers/pinctrl/airoha/pinctrl-airoha.c | 464 +----------------------
2 files changed, 480 insertions(+), 463 deletions(-)
create mode 100644 drivers/pinctrl/airoha/airoha-common.h
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
new file mode 100644
index 000000000000..3d70002213bd
--- /dev/null
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -0,0 +1,479 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ * Author: Markus Gothe <markus.gothe@genexis.eu>
+ */
+
+#ifndef __AIROHA_COMMON_HEADER__
+#define __AIROHA_COMMON_HEADER__
+
+#include <linux/types.h>
+#include <linux/gpio/driver.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+#define PINCTRL_PIN_GROUP(id, table) \
+ PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
+
+#define PINCTRL_FUNC_DESC(id, table) \
+ { \
+ .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
+ ARRAY_SIZE(table##_groups)),\
+ .groups = table##_func_group, \
+ .group_size = ARRAY_SIZE(table##_func_group), \
+ }
+
+#define PINCTRL_CONF_DESC(p, offset, mask) \
+ { \
+ .pin = p, \
+ .reg = { offset, mask }, \
+ }
+
+/* MUX */
+#define REG_GPIO_2ND_I2C_MODE 0x0214
+#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14)
+#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
+#define GPIO_I2S_MODE_MASK BIT(12)
+#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
+#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
+#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
+#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
+#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
+#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
+#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
+#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
+#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
+#define PON_TOD_1PPS_MODE_MASK BIT(2)
+#define GSW_TOD_1PPS_MODE_MASK BIT(1)
+#define GPIO_2ND_I2C_MODE_MASK BIT(0)
+
+#define REG_GPIO_SPI_CS1_MODE 0x0218
+#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
+#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
+#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
+#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
+#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
+#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
+#define GPIO_PCM_SPI_MODE_MASK BIT(16)
+#define GPIO_PCM2_MODE_MASK BIT(13)
+#define GPIO_PCM1_MODE_MASK BIT(12)
+#define GPIO_PCM_INT_MODE_MASK BIT(9)
+#define GPIO_PCM_RESET_MODE_MASK BIT(8)
+#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
+#define GPIO_SPI_CS4_MODE_MASK BIT(3)
+#define GPIO_SPI_CS3_MODE_MASK BIT(2)
+#define GPIO_SPI_CS2_MODE_MASK BIT(1)
+#define GPIO_SPI_CS1_MODE_MASK BIT(0)
+
+#define REG_GPIO_PON_MODE 0x021c
+#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
+#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
+#define GPIO_PCIE_RESET2_MASK BIT(12)
+#define SIPO_RCLK_MODE_MASK BIT(11)
+#define GPIO_PCIE_RESET1_MASK BIT(10)
+#define GPIO_PCIE_RESET0_MASK BIT(9)
+#define GPIO_UART5_MODE_MASK BIT(8)
+#define GPIO_UART4_MODE_MASK BIT(7)
+#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
+#define GPIO_HSUART_MODE_MASK BIT(5)
+#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
+#define GPIO_UART2_MODE_MASK BIT(3)
+#define GPIO_SIPO_MODE_MASK BIT(2)
+#define GPIO_EMMC_MODE_MASK BIT(1)
+#define GPIO_PON_MODE_MASK BIT(0)
+
+#define REG_NPU_UART_EN 0x0224
+#define JTAG_UDI_EN_MASK BIT(4)
+#define JTAG_DFD_EN_MASK BIT(3)
+
+#define REG_FORCE_GPIO_EN 0x0228
+#define FORCE_GPIO_EN(n) BIT(n)
+
+/* LED MAP */
+#define REG_LAN_LED0_MAPPING 0x027c
+#define REG_LAN_LED1_MAPPING 0x0280
+
+#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
+#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+
+#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
+#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+
+#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
+#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+
+#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
+#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+
+#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
+#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+
+/* CONF */
+#define REG_I2C_SDA_E2 0x001c
+#define AN7583_I2C1_SCL_E2_MASK BIT(16)
+#define AN7583_I2C1_SDA_E2_MASK BIT(15)
+#define SPI_MISO_E2_MASK BIT(14)
+#define SPI_MOSI_E2_MASK BIT(13)
+#define SPI_CLK_E2_MASK BIT(12)
+#define SPI_CS0_E2_MASK BIT(11)
+#define PCIE2_RESET_E2_MASK BIT(10)
+#define PCIE1_RESET_E2_MASK BIT(9)
+#define PCIE0_RESET_E2_MASK BIT(8)
+#define AN7583_MDIO_0_E2_MASK BIT(5)
+#define AN7583_MDC_0_E2_MASK BIT(4)
+#define UART1_RXD_E2_MASK BIT(3)
+#define UART1_TXD_E2_MASK BIT(2)
+#define I2C_SCL_E2_MASK BIT(1)
+#define I2C_SDA_E2_MASK BIT(0)
+
+#define REG_I2C_SDA_E4 0x0020
+#define AN7583_I2C1_SCL_E4_MASK BIT(16)
+#define AN7583_I2C1_SDA_E4_MASK BIT(15)
+#define SPI_MISO_E4_MASK BIT(14)
+#define SPI_MOSI_E4_MASK BIT(13)
+#define SPI_CLK_E4_MASK BIT(12)
+#define SPI_CS0_E4_MASK BIT(11)
+#define PCIE2_RESET_E4_MASK BIT(10)
+#define PCIE1_RESET_E4_MASK BIT(9)
+#define PCIE0_RESET_E4_MASK BIT(8)
+#define AN7583_MDIO_0_E4_MASK BIT(5)
+#define AN7583_MDC_0_E4_MASK BIT(4)
+#define UART1_RXD_E4_MASK BIT(3)
+#define UART1_TXD_E4_MASK BIT(2)
+#define I2C_SCL_E4_MASK BIT(1)
+#define I2C_SDA_E4_MASK BIT(0)
+
+#define REG_GPIO_L_E2 0x0024
+#define REG_GPIO_L_E4 0x0028
+#define REG_GPIO_H_E2 0x002c
+#define REG_GPIO_H_E4 0x0030
+
+#define REG_I2C_SDA_PU 0x0044
+#define AN7583_I2C1_SCL_PU_MASK BIT(16)
+#define AN7583_I2C1_SDA_PU_MASK BIT(15)
+#define SPI_MISO_PU_MASK BIT(14)
+#define SPI_MOSI_PU_MASK BIT(13)
+#define SPI_CLK_PU_MASK BIT(12)
+#define SPI_CS0_PU_MASK BIT(11)
+#define PCIE2_RESET_PU_MASK BIT(10)
+#define PCIE1_RESET_PU_MASK BIT(9)
+#define PCIE0_RESET_PU_MASK BIT(8)
+#define AN7583_MDIO_0_PU_MASK BIT(5)
+#define AN7583_MDC_0_PU_MASK BIT(4)
+#define UART1_RXD_PU_MASK BIT(3)
+#define UART1_TXD_PU_MASK BIT(2)
+#define I2C_SCL_PU_MASK BIT(1)
+#define I2C_SDA_PU_MASK BIT(0)
+
+#define REG_I2C_SDA_PD 0x0048
+#define AN7583_I2C1_SDA_PD_MASK BIT(16)
+#define AN7583_I2C1_SCL_PD_MASK BIT(15)
+#define SPI_MISO_PD_MASK BIT(14)
+#define SPI_MOSI_PD_MASK BIT(13)
+#define SPI_CLK_PD_MASK BIT(12)
+#define SPI_CS0_PD_MASK BIT(11)
+#define PCIE2_RESET_PD_MASK BIT(10)
+#define PCIE1_RESET_PD_MASK BIT(9)
+#define PCIE0_RESET_PD_MASK BIT(8)
+#define AN7583_MDIO_0_PD_MASK BIT(5)
+#define AN7583_MDC_0_PD_MASK BIT(4)
+#define UART1_RXD_PD_MASK BIT(3)
+#define UART1_TXD_PD_MASK BIT(2)
+#define I2C_SCL_PD_MASK BIT(1)
+#define I2C_SDA_PD_MASK BIT(0)
+
+#define REG_GPIO_L_PU 0x004c
+#define REG_GPIO_L_PD 0x0050
+#define REG_GPIO_H_PU 0x0054
+#define REG_GPIO_H_PD 0x0058
+
+#define REG_PCIE_RESET_OD 0x018c
+#define PCIE2_RESET_OD_MASK BIT(2)
+#define PCIE1_RESET_OD_MASK BIT(1)
+#define PCIE0_RESET_OD_MASK BIT(0)
+
+/* GPIOs */
+#define REG_GPIO_CTRL 0x0000
+#define REG_GPIO_DATA 0x0004
+#define REG_GPIO_INT 0x0008
+#define REG_GPIO_INT_EDGE 0x000c
+#define REG_GPIO_INT_LEVEL 0x0010
+#define REG_GPIO_OE 0x0014
+#define REG_GPIO_CTRL1 0x0020
+#define REG_GPIO_CTRL2 0x0060
+#define REG_GPIO_CTRL3 0x0064
+
+/* PWM MODE CONF */
+#define REG_GPIO_FLASH_MODE_CFG 0x0034
+#define GPIO15_FLASH_MODE_CFG BIT(15)
+#define GPIO14_FLASH_MODE_CFG BIT(14)
+#define GPIO13_FLASH_MODE_CFG BIT(13)
+#define GPIO12_FLASH_MODE_CFG BIT(12)
+#define GPIO11_FLASH_MODE_CFG BIT(11)
+#define GPIO10_FLASH_MODE_CFG BIT(10)
+#define GPIO9_FLASH_MODE_CFG BIT(9)
+#define GPIO8_FLASH_MODE_CFG BIT(8)
+#define GPIO7_FLASH_MODE_CFG BIT(7)
+#define GPIO6_FLASH_MODE_CFG BIT(6)
+#define GPIO5_FLASH_MODE_CFG BIT(5)
+#define GPIO4_FLASH_MODE_CFG BIT(4)
+#define GPIO3_FLASH_MODE_CFG BIT(3)
+#define GPIO2_FLASH_MODE_CFG BIT(2)
+#define GPIO1_FLASH_MODE_CFG BIT(1)
+#define GPIO0_FLASH_MODE_CFG BIT(0)
+
+/* PWM MODE CONF EXT */
+#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
+#define GPIO51_FLASH_MODE_CFG BIT(31)
+#define GPIO50_FLASH_MODE_CFG BIT(30)
+#define GPIO49_FLASH_MODE_CFG BIT(29)
+#define GPIO48_FLASH_MODE_CFG BIT(28)
+#define GPIO47_FLASH_MODE_CFG BIT(27)
+#define GPIO46_FLASH_MODE_CFG BIT(26)
+#define GPIO45_FLASH_MODE_CFG BIT(25)
+#define GPIO44_FLASH_MODE_CFG BIT(24)
+#define GPIO43_FLASH_MODE_CFG BIT(23)
+#define GPIO42_FLASH_MODE_CFG BIT(22)
+#define GPIO41_FLASH_MODE_CFG BIT(21)
+#define GPIO40_FLASH_MODE_CFG BIT(20)
+#define GPIO39_FLASH_MODE_CFG BIT(19)
+#define GPIO38_FLASH_MODE_CFG BIT(18)
+#define GPIO37_FLASH_MODE_CFG BIT(17)
+#define GPIO36_FLASH_MODE_CFG BIT(16)
+#define GPIO31_FLASH_MODE_CFG BIT(15)
+#define GPIO30_FLASH_MODE_CFG BIT(14)
+#define GPIO29_FLASH_MODE_CFG BIT(13)
+#define GPIO28_FLASH_MODE_CFG BIT(12)
+#define GPIO27_FLASH_MODE_CFG BIT(11)
+#define GPIO26_FLASH_MODE_CFG BIT(10)
+#define GPIO25_FLASH_MODE_CFG BIT(9)
+#define GPIO24_FLASH_MODE_CFG BIT(8)
+#define GPIO23_FLASH_MODE_CFG BIT(7)
+#define GPIO22_FLASH_MODE_CFG BIT(6)
+#define GPIO21_FLASH_MODE_CFG BIT(5)
+#define GPIO20_FLASH_MODE_CFG BIT(4)
+#define GPIO19_FLASH_MODE_CFG BIT(3)
+#define GPIO18_FLASH_MODE_CFG BIT(2)
+#define GPIO17_FLASH_MODE_CFG BIT(1)
+#define GPIO16_FLASH_MODE_CFG BIT(0)
+
+#define REG_GPIO_DATA1 0x0070
+#define REG_GPIO_OE1 0x0078
+#define REG_GPIO_INT1 0x007c
+#define REG_GPIO_INT_EDGE1 0x0080
+#define REG_GPIO_INT_EDGE2 0x0084
+#define REG_GPIO_INT_EDGE3 0x0088
+#define REG_GPIO_INT_LEVEL1 0x008c
+#define REG_GPIO_INT_LEVEL2 0x0090
+#define REG_GPIO_INT_LEVEL3 0x0094
+
+#define AIROHA_NUM_PINS 64
+#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2)
+#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4)
+
+/* PWM */
+#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_MUX, \
+ REG_GPIO_FLASH_MODE_CFG, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ } \
+
+#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_PWM_EXT_MUX, \
+ REG_GPIO_FLASH_MODE_CFG_EXT, \
+ (mux_val), \
+ (mux_val) \
+ }, \
+ .regmap_size = 1, \
+ } \
+
+#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED0_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
+ { \
+ .name = (gpio), \
+ .regmap[0] = { \
+ AIROHA_FUNC_MUX, \
+ REG_GPIO_2ND_I2C_MODE, \
+ (mux_val), \
+ (mux_val), \
+ }, \
+ .regmap[1] = { \
+ AIROHA_FUNC_MUX, \
+ REG_LAN_LED1_MAPPING, \
+ (map_mask), \
+ (map_val), \
+ }, \
+ .regmap_size = 2, \
+ }
+
+#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
+ airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
+ (pin), (val))
+#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
+ (pin), (val))
+#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
+ (pin), (val))
+#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
+ (pin), (val))
+#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
+ airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
+ (pin), (val))
+
+struct airoha_pinctrl_reg {
+ u32 offset;
+ u32 mask;
+};
+
+enum airoha_pinctrl_mux_func {
+ AIROHA_FUNC_MUX,
+ AIROHA_FUNC_PWM_MUX,
+ AIROHA_FUNC_PWM_EXT_MUX,
+};
+
+struct airoha_pinctrl_func_group {
+ const char *name;
+ struct {
+ enum airoha_pinctrl_mux_func mux;
+ u32 offset;
+ u32 mask;
+ u32 val;
+ } regmap[2];
+ int regmap_size;
+};
+
+struct airoha_pinctrl_func {
+ const struct pinfunction desc;
+ const struct airoha_pinctrl_func_group *groups;
+ u8 group_size;
+};
+
+struct airoha_pinctrl_conf {
+ u32 pin;
+ struct airoha_pinctrl_reg reg;
+};
+
+struct airoha_pinctrl_gpiochip {
+ struct gpio_chip chip;
+
+ /* gpio */
+ const u32 *data;
+ const u32 *dir;
+ const u32 *out;
+ /* irq */
+ const u32 *status;
+ const u32 *level;
+ const u32 *edge;
+
+ u32 irq_type[AIROHA_NUM_PINS];
+};
+
+struct airoha_pinctrl_confs_info {
+ const struct airoha_pinctrl_conf *confs;
+ unsigned int num_confs;
+};
+
+enum airoha_pinctrl_confs_type {
+ AIROHA_PINCTRL_CONFS_PULLUP,
+ AIROHA_PINCTRL_CONFS_PULLDOWN,
+ AIROHA_PINCTRL_CONFS_DRIVE_E2,
+ AIROHA_PINCTRL_CONFS_DRIVE_E4,
+ AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
+
+ AIROHA_PINCTRL_CONFS_MAX,
+};
+
+struct airoha_pinctrl {
+ struct pinctrl_dev *ctrl;
+
+ struct pinctrl_desc desc;
+ const struct pingroup *grps;
+ const struct airoha_pinctrl_func *funcs;
+ const struct airoha_pinctrl_confs_info *confs_info;
+
+ struct regmap *chip_scu;
+ struct regmap *regmap;
+
+ struct airoha_pinctrl_gpiochip gpiochip;
+};
+
+struct airoha_pinctrl_match_data {
+ const struct pinctrl_pin_desc *pins;
+ const unsigned int num_pins;
+ const struct pingroup *grps;
+ const unsigned int num_grps;
+ const struct airoha_pinctrl_func *funcs;
+ const unsigned int num_funcs;
+ const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+};
+
+#endif
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index bf5ebb31e635..0b4bbcf08ec9 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -5,290 +5,7 @@
* Author: Markus Gothe <markus.gothe@genexis.eu>
*/
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/bitfield.h>
-#include <linux/bits.h>
-#include <linux/cleanup.h>
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "../core.h"
-#include "../pinconf.h"
-#include "../pinmux.h"
-
-#define PINCTRL_PIN_GROUP(id, table) \
- PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
-
-#define PINCTRL_FUNC_DESC(id, table) \
- { \
- .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
- ARRAY_SIZE(table##_groups)),\
- .groups = table##_func_group, \
- .group_size = ARRAY_SIZE(table##_func_group), \
- }
-
-#define PINCTRL_CONF_DESC(p, offset, mask) \
- { \
- .pin = p, \
- .reg = { offset, mask }, \
- }
-
-/* MUX */
-#define REG_GPIO_2ND_I2C_MODE 0x0214
-#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14)
-#define GPIO_I2C_MASTER_MODE_MODE BIT(13)
-#define GPIO_I2S_MODE_MASK BIT(12)
-#define GPIO_I2C_SLAVE_MODE_MODE BIT(11)
-#define GPIO_LAN3_LED1_MODE_MASK BIT(10)
-#define GPIO_LAN3_LED0_MODE_MASK BIT(9)
-#define GPIO_LAN2_LED1_MODE_MASK BIT(8)
-#define GPIO_LAN2_LED0_MODE_MASK BIT(7)
-#define GPIO_LAN1_LED1_MODE_MASK BIT(6)
-#define GPIO_LAN1_LED0_MODE_MASK BIT(5)
-#define GPIO_LAN0_LED1_MODE_MASK BIT(4)
-#define GPIO_LAN0_LED0_MODE_MASK BIT(3)
-#define PON_TOD_1PPS_MODE_MASK BIT(2)
-#define GSW_TOD_1PPS_MODE_MASK BIT(1)
-#define GPIO_2ND_I2C_MODE_MASK BIT(0)
-
-#define REG_GPIO_SPI_CS1_MODE 0x0218
-#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21)
-#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
-#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
-#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
-#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
-#define GPIO_PCM_SPI_MODE_MASK BIT(16)
-#define GPIO_PCM2_MODE_MASK BIT(13)
-#define GPIO_PCM1_MODE_MASK BIT(12)
-#define GPIO_PCM_INT_MODE_MASK BIT(9)
-#define GPIO_PCM_RESET_MODE_MASK BIT(8)
-#define GPIO_SPI_QUAD_MODE_MASK BIT(4)
-#define GPIO_SPI_CS4_MODE_MASK BIT(3)
-#define GPIO_SPI_CS3_MODE_MASK BIT(2)
-#define GPIO_SPI_CS2_MODE_MASK BIT(1)
-#define GPIO_SPI_CS1_MODE_MASK BIT(0)
-
-#define REG_GPIO_PON_MODE 0x021c
-#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14)
-#define GPIO_SGMII_MDIO_MODE_MASK BIT(13)
-#define GPIO_PCIE_RESET2_MASK BIT(12)
-#define SIPO_RCLK_MODE_MASK BIT(11)
-#define GPIO_PCIE_RESET1_MASK BIT(10)
-#define GPIO_PCIE_RESET0_MASK BIT(9)
-#define GPIO_UART5_MODE_MASK BIT(8)
-#define GPIO_UART4_MODE_MASK BIT(7)
-#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6)
-#define GPIO_HSUART_MODE_MASK BIT(5)
-#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4)
-#define GPIO_UART2_MODE_MASK BIT(3)
-#define GPIO_SIPO_MODE_MASK BIT(2)
-#define GPIO_EMMC_MODE_MASK BIT(1)
-#define GPIO_PON_MODE_MASK BIT(0)
-
-#define REG_NPU_UART_EN 0x0224
-#define JTAG_UDI_EN_MASK BIT(4)
-#define JTAG_DFD_EN_MASK BIT(3)
-
-#define REG_FORCE_GPIO_EN 0x0228
-#define FORCE_GPIO_EN(n) BIT(n)
-
-/* LED MAP */
-#define REG_LAN_LED0_MAPPING 0x027c
-#define REG_LAN_LED1_MAPPING 0x0280
-
-#define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
-#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
-
-#define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
-#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
-
-#define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
-#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
-
-#define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
-#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
-
-#define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
-#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
-
-/* CONF */
-#define REG_I2C_SDA_E2 0x001c
-#define AN7583_I2C1_SCL_E2_MASK BIT(16)
-#define AN7583_I2C1_SDA_E2_MASK BIT(15)
-#define SPI_MISO_E2_MASK BIT(14)
-#define SPI_MOSI_E2_MASK BIT(13)
-#define SPI_CLK_E2_MASK BIT(12)
-#define SPI_CS0_E2_MASK BIT(11)
-#define PCIE2_RESET_E2_MASK BIT(10)
-#define PCIE1_RESET_E2_MASK BIT(9)
-#define PCIE0_RESET_E2_MASK BIT(8)
-#define AN7583_MDIO_0_E2_MASK BIT(5)
-#define AN7583_MDC_0_E2_MASK BIT(4)
-#define UART1_RXD_E2_MASK BIT(3)
-#define UART1_TXD_E2_MASK BIT(2)
-#define I2C_SCL_E2_MASK BIT(1)
-#define I2C_SDA_E2_MASK BIT(0)
-
-#define REG_I2C_SDA_E4 0x0020
-#define AN7583_I2C1_SCL_E4_MASK BIT(16)
-#define AN7583_I2C1_SDA_E4_MASK BIT(15)
-#define SPI_MISO_E4_MASK BIT(14)
-#define SPI_MOSI_E4_MASK BIT(13)
-#define SPI_CLK_E4_MASK BIT(12)
-#define SPI_CS0_E4_MASK BIT(11)
-#define PCIE2_RESET_E4_MASK BIT(10)
-#define PCIE1_RESET_E4_MASK BIT(9)
-#define PCIE0_RESET_E4_MASK BIT(8)
-#define AN7583_MDIO_0_E4_MASK BIT(5)
-#define AN7583_MDC_0_E4_MASK BIT(4)
-#define UART1_RXD_E4_MASK BIT(3)
-#define UART1_TXD_E4_MASK BIT(2)
-#define I2C_SCL_E4_MASK BIT(1)
-#define I2C_SDA_E4_MASK BIT(0)
-
-#define REG_GPIO_L_E2 0x0024
-#define REG_GPIO_L_E4 0x0028
-#define REG_GPIO_H_E2 0x002c
-#define REG_GPIO_H_E4 0x0030
-
-#define REG_I2C_SDA_PU 0x0044
-#define AN7583_I2C1_SCL_PU_MASK BIT(16)
-#define AN7583_I2C1_SDA_PU_MASK BIT(15)
-#define SPI_MISO_PU_MASK BIT(14)
-#define SPI_MOSI_PU_MASK BIT(13)
-#define SPI_CLK_PU_MASK BIT(12)
-#define SPI_CS0_PU_MASK BIT(11)
-#define PCIE2_RESET_PU_MASK BIT(10)
-#define PCIE1_RESET_PU_MASK BIT(9)
-#define PCIE0_RESET_PU_MASK BIT(8)
-#define AN7583_MDIO_0_PU_MASK BIT(5)
-#define AN7583_MDC_0_PU_MASK BIT(4)
-#define UART1_RXD_PU_MASK BIT(3)
-#define UART1_TXD_PU_MASK BIT(2)
-#define I2C_SCL_PU_MASK BIT(1)
-#define I2C_SDA_PU_MASK BIT(0)
-
-#define REG_I2C_SDA_PD 0x0048
-#define AN7583_I2C1_SDA_PD_MASK BIT(16)
-#define AN7583_I2C1_SCL_PD_MASK BIT(15)
-#define SPI_MISO_PD_MASK BIT(14)
-#define SPI_MOSI_PD_MASK BIT(13)
-#define SPI_CLK_PD_MASK BIT(12)
-#define SPI_CS0_PD_MASK BIT(11)
-#define PCIE2_RESET_PD_MASK BIT(10)
-#define PCIE1_RESET_PD_MASK BIT(9)
-#define PCIE0_RESET_PD_MASK BIT(8)
-#define AN7583_MDIO_0_PD_MASK BIT(5)
-#define AN7583_MDC_0_PD_MASK BIT(4)
-#define UART1_RXD_PD_MASK BIT(3)
-#define UART1_TXD_PD_MASK BIT(2)
-#define I2C_SCL_PD_MASK BIT(1)
-#define I2C_SDA_PD_MASK BIT(0)
-
-#define REG_GPIO_L_PU 0x004c
-#define REG_GPIO_L_PD 0x0050
-#define REG_GPIO_H_PU 0x0054
-#define REG_GPIO_H_PD 0x0058
-
-#define REG_PCIE_RESET_OD 0x018c
-#define PCIE2_RESET_OD_MASK BIT(2)
-#define PCIE1_RESET_OD_MASK BIT(1)
-#define PCIE0_RESET_OD_MASK BIT(0)
-
-/* GPIOs */
-#define REG_GPIO_CTRL 0x0000
-#define REG_GPIO_DATA 0x0004
-#define REG_GPIO_INT 0x0008
-#define REG_GPIO_INT_EDGE 0x000c
-#define REG_GPIO_INT_LEVEL 0x0010
-#define REG_GPIO_OE 0x0014
-#define REG_GPIO_CTRL1 0x0020
-
-/* PWM MODE CONF */
-#define REG_GPIO_FLASH_MODE_CFG 0x0034
-#define GPIO15_FLASH_MODE_CFG BIT(15)
-#define GPIO14_FLASH_MODE_CFG BIT(14)
-#define GPIO13_FLASH_MODE_CFG BIT(13)
-#define GPIO12_FLASH_MODE_CFG BIT(12)
-#define GPIO11_FLASH_MODE_CFG BIT(11)
-#define GPIO10_FLASH_MODE_CFG BIT(10)
-#define GPIO9_FLASH_MODE_CFG BIT(9)
-#define GPIO8_FLASH_MODE_CFG BIT(8)
-#define GPIO7_FLASH_MODE_CFG BIT(7)
-#define GPIO6_FLASH_MODE_CFG BIT(6)
-#define GPIO5_FLASH_MODE_CFG BIT(5)
-#define GPIO4_FLASH_MODE_CFG BIT(4)
-#define GPIO3_FLASH_MODE_CFG BIT(3)
-#define GPIO2_FLASH_MODE_CFG BIT(2)
-#define GPIO1_FLASH_MODE_CFG BIT(1)
-#define GPIO0_FLASH_MODE_CFG BIT(0)
-
-#define REG_GPIO_CTRL2 0x0060
-#define REG_GPIO_CTRL3 0x0064
-
-/* PWM MODE CONF EXT */
-#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068
-#define GPIO51_FLASH_MODE_CFG BIT(31)
-#define GPIO50_FLASH_MODE_CFG BIT(30)
-#define GPIO49_FLASH_MODE_CFG BIT(29)
-#define GPIO48_FLASH_MODE_CFG BIT(28)
-#define GPIO47_FLASH_MODE_CFG BIT(27)
-#define GPIO46_FLASH_MODE_CFG BIT(26)
-#define GPIO45_FLASH_MODE_CFG BIT(25)
-#define GPIO44_FLASH_MODE_CFG BIT(24)
-#define GPIO43_FLASH_MODE_CFG BIT(23)
-#define GPIO42_FLASH_MODE_CFG BIT(22)
-#define GPIO41_FLASH_MODE_CFG BIT(21)
-#define GPIO40_FLASH_MODE_CFG BIT(20)
-#define GPIO39_FLASH_MODE_CFG BIT(19)
-#define GPIO38_FLASH_MODE_CFG BIT(18)
-#define GPIO37_FLASH_MODE_CFG BIT(17)
-#define GPIO36_FLASH_MODE_CFG BIT(16)
-#define GPIO31_FLASH_MODE_CFG BIT(15)
-#define GPIO30_FLASH_MODE_CFG BIT(14)
-#define GPIO29_FLASH_MODE_CFG BIT(13)
-#define GPIO28_FLASH_MODE_CFG BIT(12)
-#define GPIO27_FLASH_MODE_CFG BIT(11)
-#define GPIO26_FLASH_MODE_CFG BIT(10)
-#define GPIO25_FLASH_MODE_CFG BIT(9)
-#define GPIO24_FLASH_MODE_CFG BIT(8)
-#define GPIO23_FLASH_MODE_CFG BIT(7)
-#define GPIO22_FLASH_MODE_CFG BIT(6)
-#define GPIO21_FLASH_MODE_CFG BIT(5)
-#define GPIO20_FLASH_MODE_CFG BIT(4)
-#define GPIO19_FLASH_MODE_CFG BIT(3)
-#define GPIO18_FLASH_MODE_CFG BIT(2)
-#define GPIO17_FLASH_MODE_CFG BIT(1)
-#define GPIO16_FLASH_MODE_CFG BIT(0)
-
-#define REG_GPIO_DATA1 0x0070
-#define REG_GPIO_OE1 0x0078
-#define REG_GPIO_INT1 0x007c
-#define REG_GPIO_INT_EDGE1 0x0080
-#define REG_GPIO_INT_EDGE2 0x0084
-#define REG_GPIO_INT_EDGE3 0x0088
-#define REG_GPIO_INT_LEVEL1 0x008c
-#define REG_GPIO_INT_LEVEL2 0x0090
-#define REG_GPIO_INT_LEVEL3 0x0094
-
-#define AIROHA_NUM_PINS 64
-#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2)
-#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4)
+#include "airoha-common.h"
static const u32 gpio_data_regs[] = {
REG_GPIO_DATA,
@@ -326,93 +43,6 @@ static const u32 irq_edge_regs[] = {
REG_GPIO_INT_EDGE3
};
-struct airoha_pinctrl_reg {
- u32 offset;
- u32 mask;
-};
-
-enum airoha_pinctrl_mux_func {
- AIROHA_FUNC_MUX,
- AIROHA_FUNC_PWM_MUX,
- AIROHA_FUNC_PWM_EXT_MUX,
-};
-
-struct airoha_pinctrl_func_group {
- const char *name;
- struct {
- enum airoha_pinctrl_mux_func mux;
- u32 offset;
- u32 mask;
- u32 val;
- } regmap[2];
- int regmap_size;
-};
-
-struct airoha_pinctrl_func {
- const struct pinfunction desc;
- const struct airoha_pinctrl_func_group *groups;
- u8 group_size;
-};
-
-struct airoha_pinctrl_conf {
- u32 pin;
- struct airoha_pinctrl_reg reg;
-};
-
-struct airoha_pinctrl_gpiochip {
- struct gpio_chip chip;
-
- /* gpio */
- const u32 *data;
- const u32 *dir;
- const u32 *out;
- /* irq */
- const u32 *status;
- const u32 *level;
- const u32 *edge;
-
- u32 irq_type[AIROHA_NUM_PINS];
-};
-
-struct airoha_pinctrl_confs_info {
- const struct airoha_pinctrl_conf *confs;
- unsigned int num_confs;
-};
-
-enum airoha_pinctrl_confs_type {
- AIROHA_PINCTRL_CONFS_PULLUP,
- AIROHA_PINCTRL_CONFS_PULLDOWN,
- AIROHA_PINCTRL_CONFS_DRIVE_E2,
- AIROHA_PINCTRL_CONFS_DRIVE_E4,
- AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
-
- AIROHA_PINCTRL_CONFS_MAX,
-};
-
-struct airoha_pinctrl {
- struct pinctrl_dev *ctrl;
-
- struct pinctrl_desc desc;
- const struct pingroup *grps;
- const struct airoha_pinctrl_func *funcs;
- const struct airoha_pinctrl_confs_info *confs_info;
-
- struct regmap *chip_scu;
- struct regmap *regmap;
-
- struct airoha_pinctrl_gpiochip gpiochip;
-};
-
-struct airoha_pinctrl_match_data {
- const struct pinctrl_pin_desc *pins;
- const unsigned int num_pins;
- const struct pingroup *grps;
- const unsigned int num_grps;
- const struct airoha_pinctrl_func *funcs;
- const unsigned int num_funcs;
- const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
-};
-
static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
PINCTRL_PIN(0, "uart1_txd"),
PINCTRL_PIN(1, "uart1_rxd"),
@@ -1458,31 +1088,6 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
},
};
-/* PWM */
-#define AIROHA_PINCTRL_PWM(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_MUX, \
- REG_GPIO_FLASH_MODE_CFG, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_PWM_EXT_MUX, \
- REG_GPIO_FLASH_MODE_CFG_EXT, \
- (mux_val), \
- (mux_val) \
- }, \
- .regmap_size = 1, \
- } \
-
static const struct airoha_pinctrl_func_group pwm_func_group[] = {
AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
@@ -1577,42 +1182,6 @@ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
};
-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED0_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \
- { \
- .name = (gpio), \
- .regmap[0] = { \
- AIROHA_FUNC_MUX, \
- REG_GPIO_2ND_I2C_MODE, \
- (mux_val), \
- (mux_val), \
- }, \
- .regmap[1] = { \
- AIROHA_FUNC_MUX, \
- REG_LAN_LED1_MAPPING, \
- (map_mask), \
- (map_val), \
- }, \
- .regmap_size = 2, \
- }
-
static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
@@ -2679,37 +2248,6 @@ static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
return 0;
}
-#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
-#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
-#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
-#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
-#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
- airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
-#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
- (pin), (val))
-#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
- (pin), (val))
-#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
- (pin), (val))
-#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
- (pin), (val))
-#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
- airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
- (pin), (val))
-
static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
{
struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
--
2.53.0
^ permalink raw reply related
* [PATCH 12/18] pinctrl: airoha: move driver to separate directory
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
Preparation step. Later the driver will be split on several SoC
specific drivers and a common code. So it's better put them to
a separate directory.
No functional changes.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/airoha/Kconfig | 18 ++++++++++++++++++
drivers/pinctrl/airoha/Makefile | 4 ++++
.../{mediatek => airoha}/pinctrl-airoha.c | 0
drivers/pinctrl/mediatek/Kconfig | 18 +-----------------
drivers/pinctrl/mediatek/Makefile | 1 -
7 files changed, 25 insertions(+), 18 deletions(-)
create mode 100644 drivers/pinctrl/airoha/Kconfig
create mode 100644 drivers/pinctrl/airoha/Makefile
rename drivers/pinctrl/{mediatek => airoha}/pinctrl-airoha.c (100%)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 03f2e3ee065f..8b9b94ae9b33 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -678,6 +678,7 @@ config PINCTRL_RP1
Enable the gpio and pinctrl/mux driver for RaspberryPi RP1
multi function device.
+source "drivers/pinctrl/airoha/Kconfig"
source "drivers/pinctrl/actions/Kconfig"
source "drivers/pinctrl/aspeed/Kconfig"
source "drivers/pinctrl/bcm/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f7d5d5f76d0c..a61eecff0dad 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_PINCTRL_UPBOARD) += pinctrl-upboard.o
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
+obj-y += airoha/
obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-y += bcm/
diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig
new file mode 100644
index 000000000000..fd84a04cb428
--- /dev/null
+++ b/drivers/pinctrl/airoha/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# For ARMv8 SoCs
+config PINCTRL_AIROHA
+ tristate "Airoha AN7581/AN7583 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ depends on ARCH_AIROHA || COMPILE_TEST
+ select PINMUX
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select REGMAP_MMIO
+ help
+ Say yes here to support pin controller and gpio driver
+ on Airoha EN7581/AN7583 SoC.
diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile
new file mode 100644
index 000000000000..009800406f5e
--- /dev/null
+++ b/drivers/pinctrl/airoha/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
similarity index 100%
rename from drivers/pinctrl/mediatek/pinctrl-airoha.c
rename to drivers/pinctrl/airoha/pinctrl-airoha.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 4819617d9368..1fd09305c73f 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
menu "MediaTek pinctrl drivers"
- depends on ARCH_MEDIATEK || ARCH_AIROHA || RALINK || COMPILE_TEST
+ depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST
config EINT_MTK
tristate "MediaTek External Interrupt Support"
@@ -125,22 +125,6 @@ config PINCTRL_MT8127
default MACH_MT8127
select PINCTRL_MTK
-# For ARMv8 SoCs
-config PINCTRL_AIROHA
- tristate "Airoha EN7581 pin control"
- depends on OF
- depends on ARM64 || COMPILE_TEST
- select PINMUX
- select GENERIC_PINCONF
- select GENERIC_PINCTRL_GROUPS
- select GENERIC_PINMUX_FUNCTIONS
- select GPIOLIB
- select GPIOLIB_IRQCHIP
- select REGMAP_MMIO
- help
- Say yes here to support pin controller and gpio driver
- on Airoha EN7581 SoC.
-
config PINCTRL_MT2712
bool "MediaTek MT2712 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index ae765bd99965..6dc17b0c23f9 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -8,7 +8,6 @@ obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o
obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o
# SoC Drivers
-obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o
obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o
--
2.53.0
^ permalink raw reply related
* [PATCH 10/18] pinctrl: airoha: an7583: fix phy1_led1 pin function
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
phy1_led1 pin function wrongly refers to gpio1 instead of gpio11.
Fix it.
Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/mediatek/pinctrl-airoha.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index e66b608c4803..b73ab60d0065 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -1754,7 +1754,7 @@ static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
- AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK,
+ AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
};
--
2.53.0
^ permalink raw reply related
* [PATCH 11/18] pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function
From: Mikhail Kshevetskiy @ 2026-06-07 0:16 UTC (permalink / raw)
To: Linus Walleij, Sean Wang, Lorenzo Bianconi, Matthias Brugger,
AngeloGioacchino Del Regno, Christian Marangi,
Bartosz Golaszewski, Benjamin Larsson, linux-kernel, linux-gpio,
linux-mediatek, linux-arm-kernel, Matheus Sampaio Queiroga,
Markus Gothe
Cc: Mikhail Kshevetskiy
In-Reply-To: <20260607001654.1439480-1-mikhail.kshevetskiy@iopsys.eu>
pcm_spi_int, pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4 pin groups are not
defined, so pcm_spi function can't be applied to these groups.
Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
drivers/pinctrl/mediatek/pinctrl-airoha.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-airoha.c b/drivers/pinctrl/mediatek/pinctrl-airoha.c
index b73ab60d0065..bf5ebb31e635 100644
--- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
+++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
@@ -877,10 +877,8 @@ static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
"pcm_spi_cs2_p156",
"pcm_spi_cs2_p128",
"pcm_spi_cs3", "pcm_spi_cs4" };
-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
- "pcm_spi_rst", "pcm_spi_cs1",
- "pcm_spi_cs2", "pcm_spi_cs3",
- "pcm_spi_cs4" };
+static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
+ "pcm_spi_rst", "pcm_spi_cs1" };
static const char *const i2s_groups[] = { "i2s" };
static const char *const emmc_groups[] = { "emmc" };
static const char *const pnand_groups[] = { "pnand" };
--
2.53.0
^ permalink raw reply related
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