* Re: [PATCH v2 7/7] arm64: defconfig: Switch Qualcomm SDM845, SM8150 and SM8250 drivers to modules
From: Konrad Dybcio @ 2026-06-10 9:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-arm-kernel
In-Reply-To: <20260609-clk-qcom-defaults-v2-7-0c67c06dca11@oss.qualcomm.com>
On 6/9/26 5:32 PM, Krzysztof Kozlowski wrote:
> Display, GPU and video clock controllers on Qualcomm SDM845, SM8150 and
> SM8250 SoCs should not be built-in because they are not necessary for
> platform bring-up to shell or even mounting rootfs. Drop their explicit
> selection in defconfig, relying on defaults which makes them modules.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 5/7] clk: qcom: Add defaults for desired arm64 drivers
From: Konrad Dybcio @ 2026-06-10 9:07 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-arm-kernel
In-Reply-To: <20260609-clk-qcom-defaults-v2-5-0c67c06dca11@oss.qualcomm.com>
On 6/9/26 5:32 PM, Krzysztof Kozlowski wrote:
> Clock controller drivers are essential for booting up SoCs and are not
> really optional for a given platform. Kernel should not ask users
> choice of drivers when that choice is obvious and known to the
> developers that answer should be 'yes' or 'module'.
>
> Enable drivers for upstreamed or being upstreamed SoCs, which are not
> yed enabled in defconfig: Glymur, Hawi, Nord, MSM8976, MSM8998 (GPU CC),
> SC7180, SC8180X, SC8280XP, SC7280, SDM660, QDU1000, SM4450, SM7150,
> SM8150, SM8450, SM6125, SM6375. Note that main GCC clock controller
> drivers are usually already enabled for these.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
>
> Changes in v2:
> 1. Add defaults for: MSM_GCC_8976, MSM_GPUCC_8998, SDM_GCC_660,
> SDM_MMCC_660, SDM_GPUCC_660, HAWI
>
> 2. Drop the Konrad RB tag, considering above a significant change.
> ---
[...]
> tristate "SDM660 Global Clock Controller"
> depends on ARM64 || COMPILE_TEST
> select QCOM_GDSC
> + default m if ARCH_QCOM
Drop the 'm'
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/7] clk: qcom: Make important ARM64 drivers default
From: Konrad Dybcio @ 2026-06-10 9:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-arm-kernel
In-Reply-To: <20260609-clk-qcom-defaults-v2-3-0c67c06dca11@oss.qualcomm.com>
On 6/9/26 5:32 PM, Krzysztof Kozlowski wrote:
> Clock controller drivers are essential for booting up SoCs and are not
> really optional for a given platform. Kernel should not ask users
> choice of drivers when that choice is obvious and known to the
> developers that answer should be 'yes' or 'module'.
>
> Switch all Qualcomm clock controller drivers which are chosen in
> defconfig to respective default 'yes' or 'module'.
>
> This has no impact on ARM64 defconfig include/generated/autoconf.h,
> however changes few drivers for ARM 32-bit:
>
> 1. multi_v7_defconfig: Enable QCOM_CLK_RPMH as module, because SDX55
> (ARM 32-bit) uses it.
FWIW RPMHCC is a provider to GCC
I think TCSR_CC is also a good candidate for =y, as on platforms that
have it, it's necessary for USB/PCIe/UFS
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/7] KVM: arm64: Support FFA_NOTIFICATION_BIND in host handler
From: Vincent Donnefort @ 2026-06-10 9:03 UTC (permalink / raw)
To: Sebastian Ene
Cc: catalin.marinas, maz, oupton, will, joey.gouly, korneld, kvmarm,
linux-arm-kernel, linux-kernel, android-kvm, mrigendra.chaubey,
perlarsen, suzuki.poulose, yuzenghui
In-Reply-To: <20260608165549.1479409-4-sebastianene@google.com>
On Mon, Jun 08, 2026 at 04:55:45PM +0000, Sebastian Ene wrote:
> Verify the arguments of the FF-A notification bind call and forward the
> message to Trustzone.
>
> Signed-off-by: Sebastian Ene <sebastianene@google.com>
> ---
> arch/arm64/kvm/hyp/nvhe/ffa.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> index 91e89d889c44..eedb01955a45 100644
> --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> @@ -42,6 +42,8 @@
> */
> #define HOST_FFA_ID 0
>
> +#define FFA_NOTIF_SENDER_ENDP_MASK GENMASK(31, 16)
Could we move the MASK definitions form arm_ffa to include/linux/arm_ffa.h?
> +
> /*
> * A buffer to hold the maximum descriptor size we can see from the host,
> * which is required when the SPMD returns a fragmented FFA_MEM_RETRIEVE_RESP
> @@ -688,7 +690,6 @@ static bool ffa_call_supported(u64 func_id)
> case FFA_MEM_DONATE:
> case FFA_MEM_RETRIEVE_REQ:
> /* Optional notification interfaces added in FF-A 1.1 */
> - case FFA_NOTIFICATION_BIND:
> case FFA_NOTIFICATION_UNBIND:
> case FFA_NOTIFICATION_SET:
> case FFA_NOTIFICATION_GET:
> @@ -912,6 +913,32 @@ static void do_ffa_notif_bitmap_destroy(struct arm_smccc_1_2_regs *res,
> arm_smccc_1_2_smc(args, res);
> }
>
> +static void do_ffa_notif_bind(struct arm_smccc_1_2_regs *res,
> + struct kvm_cpu_context *ctxt)
> +{
> + DECLARE_REG(u32, endp_id, ctxt, 1);
> + DECLARE_REG(u32, flags, ctxt, 2);
> + struct arm_smccc_1_2_regs *args;
> +
> + if (ffa_check_unused_args_sbz(ctxt, 5)) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + if (FIELD_GET(FFA_NOTIF_SENDER_ENDP_MASK, endp_id) != HOST_FFA_ID) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + if (flags & GENMASK(31, 1)) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
if (flags > 1) ?
> +
> + args = (void *)&ctxt->regs.regs[0];
> + arm_smccc_1_2_smc(args, res);
And of course just like all the other functions, it should use
the hyp_ prefix.
> +}
> +
> bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> {
> struct arm_smccc_1_2_regs res;
> @@ -976,6 +1003,9 @@ bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> case FFA_NOTIFICATION_BITMAP_DESTROY:
> do_ffa_notif_bitmap_destroy(&res, host_ctxt);
> goto out_handled;
> + case FFA_NOTIFICATION_BIND:
> + do_ffa_notif_bind(&res, host_ctxt);
> + goto out_handled;
> }
>
> if (ffa_call_supported(func_id))
> --
> 2.54.0.1064.gd145956f57-goog
>
^ permalink raw reply
* Re: [PATCH v2 03/16] power: sequencing: Change CONFIG_POWER_SEQUENCING to bool
From: Chen-Yu Tsai @ 2026-06-10 9:00 UTC (permalink / raw)
To: Bartosz Golaszewski, Greg Kroah-Hartman, Andy Shevchenko,
Daniel Scally, Heikki Krogerus, Sakari Ailus, Rafael J. Wysocki,
Danilo Krummrich, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: Alan Stern, linux-acpi, driver-core, linux-pm, linux-usb,
devicetree, linux-mediatek, linux-arm-kernel, linux-kernel,
Manivannan Sadhasivam
In-Reply-To: <20260610084053.2059858-4-wenst@chromium.org>
On Wed, Jun 10, 2026 at 5:41 PM Chen-Yu Tsai <wenst@chromium.org> wrote:
>
> USB support, including the core and hub driver, is bool, no modules. To
> be able to use the power sequencing API in the USB core, the former must
> also be bool to avoid the latter being built as a module.
>
> Change CONFIG_POWER_SEQUENCING to bool.
As Sashiko pointed out, CONFIG_USB is tristate. I was looking at the
wrong symbol. Please ignore this patch.
ChenYu
^ permalink raw reply
* Re: [PATCH v2 2/7] clk: qcom: Restrict A7PLL and IPQ4019 GCC to ARM
From: Konrad Dybcio @ 2026-06-10 9:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-arm-kernel
In-Reply-To: <20260609-clk-qcom-defaults-v2-2-0c67c06dca11@oss.qualcomm.com>
On 6/9/26 5:32 PM, Krzysztof Kozlowski wrote:
> IPQ4019 is ARM 32-bit only SoC and QCOM_A7PLL is used only on SDX55 and
> SDX65, which are 32-bit as well.
>
> Do not allow building them for ARM64 to make built kernels smaller and
> user choices easier.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2 1/7] clk: qcom: Restrict IPQ5424, IPQ6018,IPQ9574, QCM2290 and others to ARM64
From: Konrad Dybcio @ 2026-06-10 8:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Konrad Dybcio
Cc: linux-arm-msm, linux-clk, linux-kernel, linux-arm-kernel,
Dmitry Baryshkov
In-Reply-To: <20260609-clk-qcom-defaults-v2-1-0c67c06dca11@oss.qualcomm.com>
On 6/9/26 5:32 PM, Krzysztof Kozlowski wrote:
> Some clock drivers for IPQ5424, IPQ9574, QCM2290, QDU1000 and SA8775
> already depend on ARM64. IPQ6018 is ARM64 only SoC (at least upstream)
> so should not be a choice for ARM 32-bit builds, to make kernels smaller
> and user choices easier.
>
> IPQ_CMN_PLL is used only by the SoCs already having clock controllers
> restricted to ARM64
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH v1 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
From: Stefano Radaelli @ 2026-06-10 8:58 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Maud Spierings, Alexander Stein, Ernest Van Hoecke,
Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1781024557.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add device tree support for the Variscite Sonata carrier board with the
DART-MX8M-MINI system on module.
The Sonata board includes
- uSD Card support
- USB ports and OTG
- Uart, SPI and I2C interfaces
- HDMI support
- GPIO Expanders
- RTC module
- TPM module
- CAN peripherals
Link: https://variscite.com/carrier-boards/sonata-board/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8mm-var-dart-sonata.dts | 517 ++++++++++++++++++
2 files changed, 518 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8ddaab127ab9..694c9aa32779 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
new file mode 100644
index 000000000000..93b0076987b8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Variscite Sonata carrier board for DART-MX8M-MINI
+ *
+ * Link: https://variscite.com/carrier-boards/sonata-board/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mm-var-dart.dtsi"
+
+/ {
+ model = "Variscite DART-MX8M-MINI on Sonata-Board";
+ compatible = "variscite,var-dart-mx8mm-sonata",
+ "variscite,var-dart-mx8mm",
+ "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-up {
+ label = "Up";
+ linux,code = <KEY_UP>;
+ gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-down {
+ label = "Down";
+ linux,code = <KEY_DOWN>;
+ gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-emmc {
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ label = "eMMC";
+ linux,default-trigger = "mmc2";
+ };
+ };
+
+ clk40m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "can_osc";
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vmmc_usdhc2>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
+ <&gpio1 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* Resistive touch controller */
+ ads7846: touchscreen@0 {
+ compatible = "ti,ads7846";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_restouch>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <1500000>;
+ pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ ti,x-min = /bits/ 16 <125>;
+ ti,x-max = /bits/ 16 <4008>;
+ ti,y-min = /bits/ 16 <282>;
+ ti,y-max = /bits/ 16 <3864>;
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+ ti,debounce-max = /bits/ 16 <10>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <1>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ ti,keep-vref-on;
+ wakeup-source;
+ };
+
+ can0: can@1 {
+ compatible = "microchip,mcp251xfd";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&clk40m>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+ðphy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pca9534: gpio@22 {
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /* RGB_SEL */
+ lvds-brg-enable-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rgb_sel";
+ };
+ };
+
+ /* Capacitive touch controller */
+ ft5x06_ts: touchscreen@38 {
+ compatible = "edt,edt-ft5206";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_captouch>;
+ reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ wakeup-source;
+ };
+
+ extcon_ptn5150: typec@3d {
+ compatible = "nxp,ptn5150";
+ reg = <0x3d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extcon>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pca6408_1: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca6408>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pca6408_2: gpio@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ st33ktpm2xi2c: tpm@2e {
+ compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+ reg = <0x2e>;
+ label = "tpm";
+ reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ clocks = <&pcie0_refclk>;
+ status = "okay";
+};
+
+&pcie0 {
+ reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+/* Console */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ wakeup-source;
+ status = "okay";
+};
+
+/* Header */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* Header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
+ >;
+ };
+
+ pinctrl_captouch: captouchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x13
+ >;
+ };
+
+ pinctrl_extcon: extcongrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ >;
+ };
+
+ pinctrl_gpio_leds: ledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
+ pinctrl_pca6408: pca6408grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6
+ >;
+ };
+
+ pinctrl_pwm: pwmgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
+ >;
+ };
+
+ pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1
+ >;
+ };
+
+ pinctrl_restouch: restouchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
+ >;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v1 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
From: Stefano Radaelli @ 2026-06-10 8:58 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Maud Spierings, Alexander Stein, Ernest Van Hoecke,
Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1781024557.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add device tree support for the Variscite DART-MX8MM system on module.
This SOM is designed to be used with various carrier boards.
The module includes:
- NXP i.MX8M Mini MPU processor
- Up to 4GB of LPDDR4 memory
- Up to 128GB of eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver
- Codec audio WM8904
- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.
Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
.../boot/dts/freescale/imx8mm-var-dart.dtsi | 559 ++++++++++++++++++
1 file changed, 559 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
new file mode 100644
index 000000000000..1b65e2829672
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for Variscite DART-MX8M-MINI
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Variscite DART-MX8M-MINI Module";
+ compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ reg_audio_supply: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8904-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth_phy>;
+ regulator-name = "eth_phy_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <20000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
+
+ reg_phy_vddio: regulator-phy-vddio {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ sound-wm8904 {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "wm8904-audio";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+ <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the SOM PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ phy-supply = <®_eth_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ vddio-supply = <®_phy_vddio>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ wm8904: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+ clock-names = "mclk";
+ AVDD-supply = <&ldo5_reg>;
+ CPVDD-supply = <&ldo5_reg>;
+ DBVDD-supply = <®_audio_supply>;
+ DCVDD-supply = <&ldo5_reg>;
+ MICVDD-supply = <&ldo5_reg>;
+ wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+ "soft", "music";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
+ * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
+ * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+ /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+ /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+ };
+};
+
+&mu {
+ status = "okay";
+};
+
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <1536000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+/* BT module */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth_iw61x: bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+/* WIFI */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec1_sleep: fec1sleepgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
+ MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
+ MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
+ MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
+ MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
+ MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
+ MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
+ MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
+ MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
+ MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
+ MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
+ MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
+ MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
+ MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140
+ >;
+ };
+
+ pinctrl_reg_eth_phy: regeth-phygrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1
+ >;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards
From: Stefano Radaelli @ 2026-06-10 8:58 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Maud Spierings, Alexander Stein, Ernest Van Hoecke,
Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1781024557.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add DT compatible strings for Variscite DART-MX8MM SoM and Variscite
development carrier Board.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 86876311ec59..c942d3d06469 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1064,6 +1064,12 @@ properties:
- const: solidrun,imx8mm-sr-som
- const: fsl,imx8mm
+ - description: Variscite DART-MX8MM based boards
+ items:
+ - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board
+ - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
--
2.47.3
^ permalink raw reply related
* [PATCH v1 0/3] Add support for Variscite DART-MX8M-MINI and Sonata board
From: Stefano Radaelli @ 2026-06-10 8:58 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Dario Binacchi,
Josua Mayer, Maud Spierings, Alexander Stein, Ernest Van Hoecke,
Francesco Dolcini, Hugo Villeneuve
This patch series adds support for the Variscite DART-MX8M-MINI
system on module and the Sonata carrier board.
The series includes:
- SOM device tree with on-module peripherals
- Sonata carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern
where the SOM dtsi contains only peripherals mounted on the module,
while carrier-specific interfaces are enabled in the board dts.
Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards
arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
.../devicetree/bindings/arm/fsl.yaml | 6 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8mm-var-dart-sonata.dts | 517 ++++++++++++++++
.../boot/dts/freescale/imx8mm-var-dart.dtsi | 559 ++++++++++++++++++
4 files changed, 1083 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
base-commit: 23a7098c710673ce8f245af317903ae46325a694
--
2.47.3
^ permalink raw reply
* Re: [PATCH v1 13/26] s390: Introduce read/write ARM sysreg instructions
From: Janosch Frank @ 2026-06-10 8:55 UTC (permalink / raw)
To: Steffen Eiden
Cc: kvm, kvmarm, linux-arm-kernel, linux-kernel, linux-s390,
Alexander Gordeev, Andreas Grapentin, Arnd Bergmann,
Catalin Marinas, Christian Borntraeger, Claudio Imbrenda,
David Hildenbrand, Friedrich Welter, Gautam Gala, Hariharan Mari,
Heiko Carstens, Hendrik Brueckner, Ilya Leoshkevich, Joey Gouly,
Marc Zyngier, Nico Boehr, Nina Schoetterl-Glausch, Oliver Upton,
Paolo Bonzini, Suzuki K Poulose, Sven Schnelle, Ulrich Weigand,
Vasily Gorbik, Will Deacon, Zenghui Yu
In-Reply-To: <20260610083054.151573-A-seiden@linux.ibm.com>
On 6/10/26 10:30, Steffen Eiden wrote:
> On Tue, Jun 09, 2026 at 05:04:10PM +0200, Janosch Frank wrote:
>> On 5/29/26 17:55, Steffen Eiden wrote:
>>> Introduce Extract Arm System Register and Store Arm System Register to
>>> enable s390 hosts to read and write system registers for arm64 guests.
>>> The new instructions use the new RIE_H instruction format. Add assembler
>>> macros to create instructions in RIE_H format manually. Add Support for
>>> disassembling the new instructions.
>>>
>>> Co-developed-by: Andreas Grapentin <gra@linux.ibm.com>
>>> Signed-off-by: Andreas Grapentin <gra@linux.ibm.com>
>>> Signed-off-by: Steffen Eiden <seiden@linux.ibm.com>
>>> ---
>>> arch/s390/include/asm/sae-asm.h | 48 +++++++++++++++++++++++++++
>>> arch/s390/include/asm/sae.h | 58 +++++++++++++++++++++++++++++++++
>>> arch/s390/kernel/dis.c | 1 +
>>> arch/s390/tools/opcodes.txt | 2 ++
>>> 4 files changed, 109 insertions(+)
>>> create mode 100644 arch/s390/include/asm/sae-asm.h
>>>
>
[...]
>>> + * sasr() - Set Arm System Register
>>> + * @arm_reg: ARM system register identifier; compile-time constant
>>> + * @val: Value to set
>>> + * @save_area: Pointer to SAE save area
>>> + * @flags: Operation flags; compile-time constant
>>> + *
>>> + * Sets an ARM system register value.
>>> + */
>>> +static __always_inline void sasr(unsigned int arm_reg, u64 val,
>>> + struct kvm_sae_save_area *save_area,
>>> + u64 flags)
>>
>> m4 is 4 bits in length, any reason why we use a u64 here?
>> Same for easr.
>>
>
> No real reason beside my preference of using u64 by default.
>
> Do you want me to change it to u8?
Yes, that makes the potential problem a bit smaller but also:
Since we go through our macro magic I'm not sure if the compiler would
complain about values over 4 bits. Did you check for that and if not
please do check now.
If it does not complain we need a compile time check. Well maybe we
should have one either way until the instruction format is available in
compilers just to be safe.
@Christian: Thoughts?
^ permalink raw reply
* Re: [PATCH v2 2/7] KVM: arm64: Support FFA_NOTIFICATION_BITMAP_DESTROY in host handler
From: Vincent Donnefort @ 2026-06-10 8:53 UTC (permalink / raw)
To: Sebastian Ene
Cc: catalin.marinas, maz, oupton, will, joey.gouly, korneld, kvmarm,
linux-arm-kernel, linux-kernel, android-kvm, mrigendra.chaubey,
perlarsen, suzuki.poulose, yuzenghui
In-Reply-To: <20260608165549.1479409-3-sebastianene@google.com>
On Mon, Jun 08, 2026 at 04:55:44PM +0000, Sebastian Ene wrote:
> Allow FF-A notification bitmap destruction messages to be forwarded to
> Trustzone from the host.
>
> Signed-off-by: Sebastian Ene <sebastianene@google.com>
> ---
> arch/arm64/kvm/hyp/nvhe/ffa.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> index c20d45191085..91e89d889c44 100644
> --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> @@ -688,7 +688,6 @@ static bool ffa_call_supported(u64 func_id)
> case FFA_MEM_DONATE:
> case FFA_MEM_RETRIEVE_REQ:
> /* Optional notification interfaces added in FF-A 1.1 */
> - case FFA_NOTIFICATION_BITMAP_DESTROY:
> case FFA_NOTIFICATION_BIND:
> case FFA_NOTIFICATION_UNBIND:
> case FFA_NOTIFICATION_SET:
> @@ -893,6 +892,26 @@ static void do_ffa_notif_bitmap_create(struct arm_smccc_1_2_regs *res,
> arm_smccc_1_2_smc(args, res);
> }
>
> +static void do_ffa_notif_bitmap_destroy(struct arm_smccc_1_2_regs *res,
> + struct kvm_cpu_context *ctxt)
> +{
> + DECLARE_REG(u32, vmid, ctxt, 1);
> + struct arm_smccc_1_2_regs *args;
> +
> + if (ffa_check_unused_args_sbz(ctxt, 2)) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + if (vmid != HOST_FFA_ID) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + args = (void *)&ctxt->regs.regs[0];
> + arm_smccc_1_2_smc(args, res);
> +}
Sounds exactly like do_ffa_notif_bitmap_create. Could we use a single one
"do_ffa_notif_bitmap" ?
> +
> bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> {
> struct arm_smccc_1_2_regs res;
> @@ -954,6 +973,9 @@ bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> case FFA_NOTIFICATION_BITMAP_CREATE:
> do_ffa_notif_bitmap_create(&res, host_ctxt);
> goto out_handled;
> + case FFA_NOTIFICATION_BITMAP_DESTROY:
> + do_ffa_notif_bitmap_destroy(&res, host_ctxt);
> + goto out_handled;
> }
>
> if (ffa_call_supported(func_id))
> --
> 2.54.0.1064.gd145956f57-goog
>
^ permalink raw reply
* [PATCH RFC v7 9/9] arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS DVFS
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
On Qualcomm Hamoa SoCs, the memlat governor and the mechanism for
controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control
Processor (CPUCP) and are exposed via the QCOM SCMI Generic Extension
protocol. Add the SCMI vendor protocol node required for the QCOM
SCMI Generic Extension protocol to probe get functional bus dvfs
on Hamoa/Purwa SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 4ba751a65142..abd3e4bb9372 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -338,6 +338,10 @@ scmi_dvfs: protocol@13 {
reg = <0x13>;
#power-domain-cells = <1>;
};
+
+ scmi_vendor: protocol@80 {
+ reg = <0x80>;
+ };
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 7/9] PM / devfreq: Introduce the QCOM SCMI Memlat devfreq driver
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra, Amir Vajid, Ramakrishna Gottimukkula
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
On Qualcomm Glymur, Mahua and X1E/X1P (Hamoa) SoCs, the memlat governor and
the mechanism to control the various caches and RAM is hosted on the CPU
Control Processor (CPUCP), and configuration and control of this governor
is exposed through the QCOM SCMI Generic Extension Protocol, addressed via
the "MEMLAT" algorithm string.
Introduce a devfreq SCMI client driver that uses the MEMLAT algorithm
string to detect memory-latency-bound workloads and control the
frequency/level of the memory buses (DDR, LLCC and DDR_QOS). Model each bus
as a devfreq device using the remote devfreq governor. This provides basic
insight into device operation via trans_stat and allows further tuning of
the remote governor's parameters from userspace.
Co-developed-by: Amir Vajid <amir.vajid@oss.qualcomm.com>
Signed-off-by: Amir Vajid <amir.vajid@oss.qualcomm.com>
Co-developed-by: Ramakrishna Gottimukkula <ramakrishna.gottimukkula@oss.qualcomm.com>
Signed-off-by: Ramakrishna Gottimukkula <ramakrishna.gottimukkula@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
drivers/devfreq/Kconfig | 13 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/scmi-qcom-memlat-cfg.h | 573 +++++++++++++++++++++++++++
drivers/devfreq/scmi-qcom-memlat-devfreq.c | 616 +++++++++++++++++++++++++++++
4 files changed, 1203 insertions(+)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 2caa87554914..98b5a50d3189 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -169,6 +169,19 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
This adds the DEVFREQ driver for the MBUS controller in some
Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
+config SCMI_QCOM_MEMLAT_DEVFREQ
+ tristate "Qualcomm Technologies Inc. SCMI client driver"
+ depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST
+ select DEVFREQ_GOV_REMOTE
+ help
+ This driver uses the MEMLAT (memory latency) algorithm string
+ hosted on QCOM SCMI Vendor Protocol to detect memory latency
+ workloads and control frequency/level of the various memory
+ buses (DDR/LLCC/DDR_QOS).
+
+ This driver defines/documents the parameter IDs used while configuring
+ the memory buses.
+
source "drivers/devfreq/event/Kconfig"
endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index cde57c8cda76..b11f94e2f485 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
+obj-$(CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ) += scmi-qcom-memlat-devfreq.o
# DEVFREQ Event Drivers
obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
diff --git a/drivers/devfreq/scmi-qcom-memlat-cfg.h b/drivers/devfreq/scmi-qcom-memlat-cfg.h
new file mode 100644
index 000000000000..1ab8b61ea271
--- /dev/null
+++ b/drivers/devfreq/scmi-qcom-memlat-cfg.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__
+#define __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__
+
+/*
+ * Memlat Effective Frequency Calculation Method
+ * CPUCP_EFFECTIVE_FREQ_METHOD_0 - Uses CPU Cycles and CONST Cycles to calculate
+ * CPUCP_EFFECTIVE_FREQ_METHOD_1 - Uses CPU Cycles and time period
+ */
+#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_0 0
+#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1 1
+
+#define EV_CPU_CYCLES 0
+#define EV_CNT_CYCLES 1
+#define EV_INST_RETIRED 2
+#define EV_STALL_BACKEND_MEM 3
+#define EV_L2_D_RFILL 5
+#define INVALID_IDX 0xff
+
+#define MEMLAT_ALGO_STR 0x4D454D4C4154ULL /* MEMLAT */
+
+struct scmi_qcom_map_table {
+ unsigned int cpu_freq;
+ unsigned int mem_freq;
+};
+
+struct scmi_qcom_opp_data {
+ unsigned long freq;
+ unsigned int level;
+};
+
+struct scmi_qcom_memory_range {
+ unsigned int min_freq;
+ unsigned int max_freq;
+};
+
+enum common_ev_idx {
+ INST_IDX,
+ CYC_IDX,
+ CONST_CYC_IDX,
+ FE_STALL_IDX,
+ BE_STALL_IDX,
+ NUM_COMMON_EVS
+};
+
+enum grp_ev_idx {
+ MISS_IDX,
+ WB_IDX,
+ ACC_IDX,
+ NUM_GRP_EVS
+};
+
+/*
+ * CPUCP firmware identifies memory groups by a small integer (the hw_type
+ * carried in node_msg / scalar_param_msg / map_param_msg / ev_map_msg). The
+ * encoding is shared between the cfg tables below and scmi_qcom_devfreq_get_cur_freq()
+ * which special-cases DDR_QOS as a level-based bus rather than a frequency-scaled one.
+ */
+enum scmi_qcom_memlat_hw_type {
+ MEMLAT_HW_DDR = 0,
+ MEMLAT_HW_LLCC = 1,
+ MEMLAT_HW_DDR_QOS_COMPUTE = 2,
+};
+
+struct scmi_qcom_monitor_cfg {
+ const struct scmi_qcom_map_table *table;
+ const char *name;
+ u32 be_stall_floor;
+ u32 cpu_mask;
+ u32 ipm_ceil;
+ int table_len;
+};
+
+struct scmi_qcom_memory_cfg {
+ const struct scmi_qcom_monitor_cfg *monitor_cfg;
+ const struct scmi_qcom_opp_data *mem_table;
+ struct scmi_qcom_memory_range memory_range;
+ const u32 *grp_ev;
+ const char *name;
+ u32 memory_type;
+ int monitor_cnt;
+ int num_opps;
+};
+
+struct scmi_qcom_memlat_cfg_data {
+ const struct scmi_qcom_memory_cfg *memory_cfg;
+ const u32 *common_ev;
+ u32 cpucp_freq_method;
+ u32 cpucp_sample_ms;
+ int memory_cnt;
+};
+
+static const u32 glymur_common_ev[NUM_COMMON_EVS] = {
+ [INST_IDX] = EV_INST_RETIRED,
+ [CYC_IDX] = EV_CPU_CYCLES,
+ [CONST_CYC_IDX] = EV_CNT_CYCLES,
+ [FE_STALL_IDX] = INVALID_IDX,
+ [BE_STALL_IDX] = EV_STALL_BACKEND_MEM,
+};
+
+static const u32 glymur_ddr_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const u32 glymur_llcc_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const u32 glymur_ddr_qos_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const u32 hamoa_common_ev[NUM_COMMON_EVS] = {
+ [INST_IDX] = EV_INST_RETIRED,
+ [CYC_IDX] = EV_CPU_CYCLES,
+ [CONST_CYC_IDX] = EV_CNT_CYCLES,
+ [FE_STALL_IDX] = INVALID_IDX,
+ [BE_STALL_IDX] = EV_STALL_BACKEND_MEM,
+};
+
+static const u32 hamoa_ddr_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const u32 hamoa_llcc_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const u32 hamoa_ddr_qos_grp_ev[NUM_GRP_EVS] = {
+ [MISS_IDX] = EV_L2_D_RFILL,
+ [WB_IDX] = INVALID_IDX,
+ [ACC_IDX] = INVALID_IDX,
+};
+
+static const struct scmi_qcom_opp_data glymur_llcc_table[] = {
+ { .freq = 315000000 },
+ { .freq = 479000000 },
+ { .freq = 545000000 },
+ { .freq = 725000000 },
+ { .freq = 840000000 },
+ { .freq = 959000000 },
+ { .freq = 1090000000 },
+ { .freq = 1211000000 },
+};
+
+static const struct scmi_qcom_opp_data hamoa_llcc_table[] = {
+ { .freq = 300000000 },
+ { .freq = 466000000 },
+ { .freq = 600000000 },
+ { .freq = 806000000 },
+ { .freq = 933000000 },
+ { .freq = 1066000000 },
+};
+
+static const struct scmi_qcom_opp_data glymur_ddr_table[] = {
+ { .freq = 200000000 },
+ { .freq = 547000000 },
+ { .freq = 1353000000 },
+ { .freq = 1555000000 },
+ { .freq = 1708000000 },
+ { .freq = 2092000000 },
+ { .freq = 2736000000 },
+ { .freq = 3187000000 },
+ { .freq = 3686000000 },
+ { .freq = 4224000000 },
+ { .freq = 4761000000 },
+};
+
+static const struct scmi_qcom_opp_data hamoa_ddr_table[] = {
+ { .freq = 200000000 },
+ { .freq = 547000000 },
+ { .freq = 768000000 },
+ { .freq = 1555000000 },
+ { .freq = 1708000000 },
+ { .freq = 2092000000 },
+ { .freq = 2736000000 },
+ { .freq = 3187000000 },
+ { .freq = 3686000000 },
+ { .freq = 4224000000 },
+};
+
+/*
+ * DDR_QOS is a level-based bus (0 = nominal, 1 = boost), not a
+ * frequency-scaled one. The OPP entries below use synthetic frequencies
+ * (1 / 100) purely as distinct devfreq keys so trans_stat can show
+ * level transitions. scmi_qcom_devfreq_get_cur_freq() maps the firmware
+ * level back to the matching key.
+ */
+static const struct scmi_qcom_opp_data glymur_ddr_qos_table[] = {
+ { .freq = 1, .level = 0 },
+ { .freq = 100, .level = 1 },
+};
+
+static const struct scmi_qcom_memory_cfg glymur_memory_cfg[] = {
+ {
+ .memory_type = MEMLAT_HW_DDR,
+ .name = "ddr",
+ .mem_table = glymur_ddr_table,
+ .num_opps = ARRAY_SIZE(glymur_ddr_table),
+ .grp_ev = glymur_ddr_grp_ev,
+ .monitor_cnt = 4,
+ .memory_range = { .min_freq = 547000, .max_freq = 4761000},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0x3f,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 8,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 960, .mem_freq = 547000 },
+ { .cpu_freq = 1133, .mem_freq = 1353000 },
+ { .cpu_freq = 1594, .mem_freq = 1555000 },
+ { .cpu_freq = 1920, .mem_freq = 1708000 },
+ { .cpu_freq = 2228, .mem_freq = 2736000 },
+ { .cpu_freq = 2362, .mem_freq = 3187000 },
+ { .cpu_freq = 2650, .mem_freq = 3686000 },
+ { .cpu_freq = 2938, .mem_freq = 4761000 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xfc0,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 8,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 356, .mem_freq = 547000 },
+ { .cpu_freq = 1018, .mem_freq = 1353000 },
+ { .cpu_freq = 1536, .mem_freq = 1555000 },
+ { .cpu_freq = 1748, .mem_freq = 1708000 },
+ { .cpu_freq = 2324, .mem_freq = 2736000 },
+ { .cpu_freq = 2496, .mem_freq = 3187000 },
+ { .cpu_freq = 2900, .mem_freq = 3686000 },
+ { .cpu_freq = 3514, .mem_freq = 4761000 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0x3f000,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 8,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 356, .mem_freq = 547000 },
+ { .cpu_freq = 1018, .mem_freq = 1353000 },
+ { .cpu_freq = 1536, .mem_freq = 1555000 },
+ { .cpu_freq = 1748, .mem_freq = 1708000 },
+ { .cpu_freq = 2324, .mem_freq = 2736000 },
+ { .cpu_freq = 2496, .mem_freq = 3187000 },
+ { .cpu_freq = 2900, .mem_freq = 3686000 },
+ { .cpu_freq = 3514, .mem_freq = 4761000 },
+ }
+ },
+ {
+ .name = "mon_3",
+ .cpu_mask = 0x3ffff,
+ .table_len = 4,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2823, .mem_freq = 547000 },
+ { .cpu_freq = 3034, .mem_freq = 1555000 },
+ { .cpu_freq = 3226, .mem_freq = 1708000 },
+ { .cpu_freq = 5012, .mem_freq = 2092000 },
+ }
+ },
+ },
+ },
+ {
+ .memory_type = MEMLAT_HW_LLCC,
+ .name = "llcc",
+ .mem_table = glymur_llcc_table,
+ .num_opps = ARRAY_SIZE(glymur_llcc_table),
+ .grp_ev = glymur_llcc_grp_ev,
+ .monitor_cnt = 3,
+ .memory_range = { .min_freq = 315000, .max_freq = 1211000},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0x3f,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 7,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 960, .mem_freq = 315000 },
+ { .cpu_freq = 1113, .mem_freq = 479000 },
+ { .cpu_freq = 1594, .mem_freq = 545000 },
+ { .cpu_freq = 1920, .mem_freq = 725000 },
+ { .cpu_freq = 2362, .mem_freq = 840000 },
+ { .cpu_freq = 2650, .mem_freq = 959000 },
+ { .cpu_freq = 2938, .mem_freq = 1211000 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xfc0,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 7,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 356, .mem_freq = 315000 },
+ { .cpu_freq = 1018, .mem_freq = 479000 },
+ { .cpu_freq = 1536, .mem_freq = 545000 },
+ { .cpu_freq = 1748, .mem_freq = 725000 },
+ { .cpu_freq = 2496, .mem_freq = 840000 },
+ { .cpu_freq = 2900, .mem_freq = 959000 },
+ { .cpu_freq = 3514, .mem_freq = 1211000 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0x3f000,
+ .ipm_ceil = 60000000,
+ .be_stall_floor = 1,
+ .table_len = 7,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 356, .mem_freq = 315000 },
+ { .cpu_freq = 1018, .mem_freq = 479000 },
+ { .cpu_freq = 1536, .mem_freq = 545000 },
+ { .cpu_freq = 1748, .mem_freq = 725000 },
+ { .cpu_freq = 2496, .mem_freq = 840000 },
+ { .cpu_freq = 2900, .mem_freq = 959000 },
+ { .cpu_freq = 3514, .mem_freq = 1211000 },
+ }
+ },
+ },
+ },
+ {
+ .memory_type = MEMLAT_HW_DDR_QOS_COMPUTE,
+ .name = "ddr-qos",
+ .monitor_cnt = 3,
+ .mem_table = glymur_ddr_qos_table,
+ .num_opps = ARRAY_SIZE(glymur_ddr_qos_table),
+ .grp_ev = glymur_ddr_qos_grp_ev,
+ .memory_range = { .min_freq = 0, .max_freq = 1},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0x3f,
+ .ipm_ceil = 80000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2362, .mem_freq = 0 },
+ { .cpu_freq = 2938, .mem_freq = 1 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xfc0,
+ .ipm_ceil = 80000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2496, .mem_freq = 0 },
+ { .cpu_freq = 3514, .mem_freq = 1 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0x3f000,
+ .ipm_ceil = 80000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2496, .mem_freq = 0 },
+ { .cpu_freq = 3514, .mem_freq = 1 },
+ }
+ },
+ },
+ },
+};
+
+static const struct scmi_qcom_memory_cfg hamoa_memory_cfg[] = {
+ {
+ .memory_type = MEMLAT_HW_DDR,
+ .name = "ddr",
+ .mem_table = hamoa_ddr_table,
+ .num_opps = ARRAY_SIZE(hamoa_ddr_table),
+ .grp_ev = hamoa_ddr_grp_ev,
+ .monitor_cnt = 4,
+ .memory_range = { .min_freq = 200000, .max_freq = 4224000},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0xf,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 547000 },
+ { .cpu_freq = 1440, .mem_freq = 768000 },
+ { .cpu_freq = 1671, .mem_freq = 1555000 },
+ { .cpu_freq = 2189, .mem_freq = 2092000 },
+ { .cpu_freq = 2516, .mem_freq = 3187000 },
+ { .cpu_freq = 3860, .mem_freq = 4224000 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xf0,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 547000 },
+ { .cpu_freq = 1440, .mem_freq = 768000 },
+ { .cpu_freq = 1671, .mem_freq = 1555000 },
+ { .cpu_freq = 2189, .mem_freq = 2092000 },
+ { .cpu_freq = 2516, .mem_freq = 3187000 },
+ { .cpu_freq = 3860, .mem_freq = 4224000 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0xf00,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 547000 },
+ { .cpu_freq = 1440, .mem_freq = 768000 },
+ { .cpu_freq = 1671, .mem_freq = 1555000 },
+ { .cpu_freq = 2189, .mem_freq = 2092000 },
+ { .cpu_freq = 2516, .mem_freq = 3187000 },
+ { .cpu_freq = 3860, .mem_freq = 4224000 },
+ }
+ },
+ {
+ .name = "mon_3",
+ .cpu_mask = 0xfff,
+ .table_len = 4,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 1440, .mem_freq = 547000 },
+ { .cpu_freq = 2189, .mem_freq = 768000 },
+ { .cpu_freq = 2516, .mem_freq = 1555000 },
+ { .cpu_freq = 3860, .mem_freq = 2092000 },
+ }
+ },
+ },
+ },
+ {
+ .memory_type = MEMLAT_HW_LLCC,
+ .name = "llcc",
+ .mem_table = hamoa_llcc_table,
+ .num_opps = ARRAY_SIZE(hamoa_llcc_table),
+ .grp_ev = hamoa_llcc_grp_ev,
+ .monitor_cnt = 3,
+ .memory_range = { .min_freq = 300000, .max_freq = 1066000},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0xf,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 300000 },
+ { .cpu_freq = 1440, .mem_freq = 466000 },
+ { .cpu_freq = 1671, .mem_freq = 600000 },
+ { .cpu_freq = 2189, .mem_freq = 806000 },
+ { .cpu_freq = 2516, .mem_freq = 933000 },
+ { .cpu_freq = 3860, .mem_freq = 1066000 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xf0,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 300000 },
+ { .cpu_freq = 1440, .mem_freq = 466000 },
+ { .cpu_freq = 1671, .mem_freq = 600000 },
+ { .cpu_freq = 2189, .mem_freq = 806000 },
+ { .cpu_freq = 2516, .mem_freq = 933000 },
+ { .cpu_freq = 3860, .mem_freq = 1066000 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0xf00,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 6,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 999, .mem_freq = 300000 },
+ { .cpu_freq = 1440, .mem_freq = 466000 },
+ { .cpu_freq = 1671, .mem_freq = 600000 },
+ { .cpu_freq = 2189, .mem_freq = 806000 },
+ { .cpu_freq = 2516, .mem_freq = 933000 },
+ { .cpu_freq = 3860, .mem_freq = 1066000 },
+ }
+ },
+ },
+ },
+ {
+ .memory_type = MEMLAT_HW_DDR_QOS_COMPUTE,
+ .name = "ddr-qos",
+ .monitor_cnt = 3,
+ .mem_table = glymur_ddr_qos_table,
+ .num_opps = ARRAY_SIZE(glymur_ddr_qos_table),
+ .grp_ev = hamoa_ddr_qos_grp_ev,
+ .memory_range = { .min_freq = 0, .max_freq = 1},
+ .monitor_cfg = (const struct scmi_qcom_monitor_cfg[]) {
+ {
+ .name = "mon_0",
+ .cpu_mask = 0xf,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2189, .mem_freq = 0 },
+ { .cpu_freq = 3860, .mem_freq = 1 },
+ }
+ },
+ {
+ .name = "mon_1",
+ .cpu_mask = 0xf0,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2189, .mem_freq = 0 },
+ { .cpu_freq = 3860, .mem_freq = 1 },
+ }
+ },
+ {
+ .name = "mon_2",
+ .cpu_mask = 0xf00,
+ .ipm_ceil = 20000000,
+ .be_stall_floor = 1,
+ .table_len = 2,
+ .table = (const struct scmi_qcom_map_table[]) {
+ { .cpu_freq = 2189, .mem_freq = 0 },
+ { .cpu_freq = 3860, .mem_freq = 1 },
+ }
+ },
+ },
+ },
+};
+
+static const struct scmi_qcom_memlat_cfg_data glymur_memlat_data = {
+ .memory_cfg = glymur_memory_cfg,
+ .common_ev = glymur_common_ev,
+ .cpucp_freq_method = CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1,
+ .cpucp_sample_ms = 4,
+ .memory_cnt = ARRAY_SIZE(glymur_memory_cfg),
+};
+
+static const struct scmi_qcom_memlat_cfg_data hamoa_memlat_data = {
+ .memory_cfg = hamoa_memory_cfg,
+ .common_ev = hamoa_common_ev,
+ .cpucp_freq_method = CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1,
+ .cpucp_sample_ms = 4,
+ .memory_cnt = ARRAY_SIZE(hamoa_memory_cfg),
+};
+
+#endif
diff --git a/drivers/devfreq/scmi-qcom-memlat-devfreq.c b/drivers/devfreq/scmi-qcom-memlat-devfreq.c
new file mode 100644
index 000000000000..99ae229acfdc
--- /dev/null
+++ b/drivers/devfreq/scmi-qcom-memlat-devfreq.c
@@ -0,0 +1,616 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/cpu.h>
+#include <linux/devfreq.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/scmi_protocol.h>
+#include <linux/scmi_qcom_protocol.h>
+#include <linux/units.h>
+
+#define MAX_NAME_LEN 20
+#define MAX_MAP_ENTRIES 10
+
+#include "scmi-qcom-memlat-cfg.h"
+
+/**
+ * enum scmi_memlat_protocol_cmd - parameter_ids supported by the "MEMLAT" algo_str hosted
+ * by the Qualcomm Generic Vendor Protocol on the SCMI controller.
+ *
+ * MEMLAT (Memory Latency) monitors the counters to detect memory latency bound workloads
+ * and scales the frequency/levels of the memory buses accordingly.
+ *
+ * @MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling functions for the memory bus.
+ * @MEMLAT_SET_MONITOR: configures the monitor to work on a specific memory bus.
+ * @MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the cpu frequency.
+ * @MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor the memory bus.
+ * @MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per monitor.
+ * @MEMLAT_BE_STALL_FLOOR: set the back-end stall floor per monitor.
+ * @MEMLAT_SAMPLE_MS: set the sampling period for all the monitors.
+ * @MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map.
+ * @MEMLAT_SET_MIN_FREQ: set the min frequency of the memory bus.
+ * @MEMLAT_SET_MAX_FREQ: set the max frequency of the memory bus.
+ * @MEMLAT_GET_CUR_FREQ: query the current frequency/level of the memory bus.
+ * @MEMLAT_START_TIMER: start all the monitors with the requested sampling period.
+ * @MEMLAT_STOP_TIMER: stop all the running monitors.
+ * @MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu frequency.
+ */
+enum scmi_memlat_protocol_cmd {
+ MEMLAT_SET_MEM_GROUP = 16,
+ MEMLAT_SET_MONITOR,
+ MEMLAT_SET_COMMON_EV_MAP,
+ MEMLAT_SET_GRP_EV_MAP,
+ MEMLAT_IPM_CEIL = 23,
+ MEMLAT_BE_STALL_FLOOR = 25,
+ MEMLAT_SAMPLE_MS = 31,
+ MEMLAT_MON_FREQ_MAP,
+ MEMLAT_SET_MIN_FREQ,
+ MEMLAT_SET_MAX_FREQ,
+ MEMLAT_GET_CUR_FREQ,
+ MEMLAT_START_TIMER = 36,
+ MEMLAT_STOP_TIMER,
+ MEMLAT_SET_EFFECTIVE_FREQ_METHOD = 39,
+};
+
+struct cpucp_map_table {
+ __le16 v1;
+ __le16 v2;
+};
+
+struct map_param_msg {
+ __le32 hw_type;
+ __le32 mon_idx;
+ __le32 nr_rows;
+ struct cpucp_map_table tbl[MAX_MAP_ENTRIES];
+} __packed;
+
+struct node_msg {
+ __le32 cpumask;
+ __le32 hw_type;
+ __le32 mon_type;
+ __le32 mon_idx;
+ char mon_name[MAX_NAME_LEN];
+};
+
+struct scalar_param_msg {
+ __le32 hw_type;
+ __le32 mon_idx;
+ __le32 val;
+};
+
+struct ev_map_msg {
+ __le32 num_evs;
+ __le32 hw_type;
+ __le32 cid[NUM_COMMON_EVS];
+};
+
+struct scmi_qcom_memlat_map {
+ unsigned int cpufreq_mhz;
+ unsigned int memfreq_khz;
+};
+
+struct scmi_qcom_monitor_info {
+ struct scmi_qcom_memlat_map *freq_map;
+ char name[MAX_NAME_LEN];
+ u32 mon_idx;
+ u32 mon_type;
+ u32 ipm_ceil;
+ u32 be_stall_floor;
+ u32 mask;
+ u32 freq_map_len;
+};
+
+struct scmi_qcom_memory_info {
+ struct scmi_qcom_monitor_info **monitor;
+ u32 hw_type;
+ int monitor_cnt;
+ u32 min_freq;
+ u32 max_freq;
+ struct devfreq_dev_profile profile;
+ struct devfreq *devfreq;
+ struct platform_device *pdev;
+ struct scmi_protocol_handle *ph;
+ const struct qcom_generic_ext_ops *ops;
+};
+
+struct scmi_qcom_memlat_info {
+ struct scmi_protocol_handle *ph;
+ const struct qcom_generic_ext_ops *ops;
+ const struct scmi_qcom_memlat_cfg_data *cfg_data;
+ struct scmi_qcom_memory_info **memory;
+ u32 cpucp_freq_method;
+ u32 cpucp_sample_ms;
+ int memory_cnt;
+};
+
+static int configure_cpucp_common_events(struct scmi_qcom_memlat_info *info,
+ const struct scmi_qcom_memlat_cfg_data *cfg_data)
+{
+ const struct qcom_generic_ext_ops *ops = info->ops;
+ struct ev_map_msg msg = {};
+ int i;
+
+ msg.num_evs = cpu_to_le32(NUM_COMMON_EVS);
+ /* Common events apply to all groups; INVALID_IDX flags "no specific group". */
+ msg.hw_type = cpu_to_le32(INVALID_IDX);
+ for (i = 0; i < NUM_COMMON_EVS; i++)
+ msg.cid[i] = cpu_to_le32(cfg_data->common_ev[i]);
+
+ return ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR,
+ MEMLAT_SET_COMMON_EV_MAP);
+}
+
+static int configure_cpucp_grp(struct device *dev, struct scmi_qcom_memlat_info *info,
+ const struct scmi_qcom_memlat_cfg_data *cfg_data,
+ int memory_index)
+{
+ const u32 *grp_ev = cfg_data->memory_cfg[memory_index].grp_ev;
+ struct scmi_qcom_memory_info *memory = info->memory[memory_index];
+ const struct qcom_generic_ext_ops *ops = info->ops;
+ struct ev_map_msg ev_msg = {};
+ struct node_msg msg = {};
+ int ret;
+ int i;
+
+ msg.cpumask = cpu_to_le32(*cpumask_bits(cpu_possible_mask));
+ msg.hw_type = cpu_to_le32(memory->hw_type);
+ msg.mon_type = 0;
+ msg.mon_idx = 0;
+ ret = ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEMLAT_SET_MEM_GROUP);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to configure mem type %d\n",
+ memory->hw_type);
+
+ ev_msg.num_evs = cpu_to_le32(NUM_GRP_EVS);
+ ev_msg.hw_type = cpu_to_le32(memory->hw_type);
+ for (i = 0; i < NUM_GRP_EVS; i++)
+ ev_msg.cid[i] = cpu_to_le32(grp_ev[i]);
+
+ ret = ops->set_param(info->ph, &ev_msg, sizeof(ev_msg), MEMLAT_ALGO_STR,
+ MEMLAT_SET_GRP_EV_MAP);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to configure event map for mem type %d\n",
+ memory->hw_type);
+
+ return ret;
+}
+
+static int configure_cpucp_mon(struct device *dev, struct scmi_qcom_memlat_info *info,
+ int memory_index, int monitor_index)
+{
+ const struct qcom_generic_ext_ops *ops = info->ops;
+ struct scmi_qcom_memory_info *memory = info->memory[memory_index];
+ struct scmi_qcom_monitor_info *monitor = memory->monitor[monitor_index];
+ struct scalar_param_msg scalar_msg = {};
+ struct map_param_msg map_msg = {};
+ struct node_msg msg = {};
+ int ret;
+ int i;
+
+ msg.cpumask = cpu_to_le32(monitor->mask);
+ msg.hw_type = cpu_to_le32(memory->hw_type);
+ msg.mon_type = cpu_to_le32(monitor->mon_type);
+ msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ strscpy(msg.mon_name, monitor->name, sizeof(msg.mon_name));
+ ret = ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEMLAT_SET_MONITOR);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to configure monitor %s\n",
+ monitor->name);
+
+ scalar_msg.hw_type = cpu_to_le32(memory->hw_type);
+ scalar_msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ scalar_msg.val = cpu_to_le32(monitor->ipm_ceil);
+ ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR,
+ MEMLAT_IPM_CEIL);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n",
+ monitor->name);
+
+ scalar_msg.hw_type = cpu_to_le32(memory->hw_type);
+ scalar_msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ scalar_msg.val = cpu_to_le32(monitor->be_stall_floor);
+ ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR,
+ MEMLAT_BE_STALL_FLOOR);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to set be_stall_floor for %s\n",
+ monitor->name);
+
+ map_msg.hw_type = cpu_to_le32(memory->hw_type);
+ map_msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ map_msg.nr_rows = cpu_to_le32(monitor->freq_map_len);
+ for (i = 0; i < monitor->freq_map_len; i++) {
+ map_msg.tbl[i].v1 = cpu_to_le16(monitor->freq_map[i].cpufreq_mhz);
+
+ /*
+ * Wire format v2 is u16 in MHz; convert from kHz. For DDR_QOS
+ * the table holds level indices (0 / 1) rather than real
+ * frequencies, so pass them through unchanged.
+ */
+ if (monitor->freq_map[i].memfreq_khz > 1)
+ map_msg.tbl[i].v2 = cpu_to_le16(monitor->freq_map[i].memfreq_khz / 1000);
+ else
+ map_msg.tbl[i].v2 = cpu_to_le16(monitor->freq_map[i].memfreq_khz);
+ }
+ ret = ops->set_param(info->ph, &map_msg, sizeof(map_msg), MEMLAT_ALGO_STR,
+ MEMLAT_MON_FREQ_MAP);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n",
+ monitor->name);
+
+ scalar_msg.hw_type = cpu_to_le32(memory->hw_type);
+ scalar_msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ scalar_msg.val = cpu_to_le32(memory->min_freq);
+ ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR,
+ MEMLAT_SET_MIN_FREQ);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to set min_freq for %s\n",
+ monitor->name);
+
+ scalar_msg.hw_type = cpu_to_le32(memory->hw_type);
+ scalar_msg.mon_idx = cpu_to_le32(monitor->mon_idx);
+ scalar_msg.val = cpu_to_le32(memory->max_freq);
+ ret = ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_ALGO_STR,
+ MEMLAT_SET_MAX_FREQ);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to set max_freq for %s\n", monitor->name);
+
+ return ret;
+}
+
+static int scmi_qcom_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+ struct scmi_qcom_memory_info *memory = dev_get_drvdata(dev);
+ const struct qcom_generic_ext_ops *ops = memory->ops;
+ struct scalar_param_msg scalar_msg = {};
+ u32 max_freq_khz = 0;
+ __le32 cur_freq;
+ int ret, i;
+
+ /*
+ * MEMLAT_GET_CUR_FREQ returns target_freq for a single (hw_type,
+ * mon_idx) tuple. The bus's actual voted frequency is the max across
+ * all configured monitors in the group, so query each one and pick
+ * the highest vote.
+ */
+ for (i = 0; i < memory->monitor_cnt; i++) {
+ scalar_msg.hw_type = cpu_to_le32(memory->hw_type);
+ scalar_msg.mon_idx = cpu_to_le32(memory->monitor[i]->mon_idx);
+ scalar_msg.val = 0;
+
+ ret = ops->get_param(memory->ph, &scalar_msg, sizeof(scalar_msg),
+ MEMLAT_ALGO_STR, MEMLAT_GET_CUR_FREQ,
+ sizeof(cur_freq));
+ if (ret < 0) {
+ dev_err(dev, "failed to get current frequency for %s\n",
+ memory->monitor[i]->name);
+ return ret;
+ }
+
+ /* qcom_scmi_common_xfer() returns the response into the same tx buffer. */
+ memcpy(&cur_freq, &scalar_msg, sizeof(cur_freq));
+ if (le32_to_cpu(cur_freq) > max_freq_khz)
+ max_freq_khz = le32_to_cpu(cur_freq);
+ }
+
+ /*
+ * Frequency-scaled buses (DDR/LLCC) report cur_freq in kHz; convert
+ * to Hz to match the devfreq OPP table units. Level-based buses
+ * (e.g. DDR_QOS_COMPUTE) configure max_freq == 1 because the firmware
+ * reports a 0/1 level rather than a frequency, and the matching
+ * synthetic OPP keys (1 / 100) live in glymur_ddr_qos_table.
+ */
+ if (memory->max_freq > 1)
+ *freq = max_freq_khz * 1000UL;
+ else
+ *freq = max_freq_khz ? 100 : 1;
+
+ return 0;
+}
+
+static void scmi_qcom_memlat_unwind(struct scmi_qcom_memlat_info *info, int count)
+{
+ for (int i = 0; i < count; i++) {
+ struct scmi_qcom_memory_info *memory = info->memory[i];
+
+ if (IS_ERR_OR_NULL(memory) || IS_ERR_OR_NULL(memory->pdev))
+ continue;
+
+ dev_pm_opp_remove_all_dynamic(&memory->pdev->dev);
+ platform_device_unregister(memory->pdev);
+ }
+}
+
+static int scmi_qcom_memlat_configure_events(struct scmi_device *sdev,
+ struct scmi_qcom_memlat_info *info)
+{
+ const struct qcom_generic_ext_ops *ops = info->ops;
+ struct scmi_protocol_handle *ph = info->ph;
+ __le32 sample_ms, freq_method;
+ int i, j, ret;
+
+ /* Configure common events ids */
+ ret = configure_cpucp_common_events(info, info->cfg_data);
+ if (ret < 0)
+ return dev_err_probe(&sdev->dev, ret, "failed to configure common events\n");
+
+ for (i = 0; i < info->memory_cnt; i++) {
+ /* Configure per group parameters */
+ ret = configure_cpucp_grp(&sdev->dev, info, info->cfg_data, i);
+ if (ret < 0)
+ return ret;
+
+ for (j = 0; j < info->memory[i]->monitor_cnt; j++) {
+ /* Configure per monitor parameters */
+ ret = configure_cpucp_mon(&sdev->dev, info, i, j);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ /* Set loop sampling time */
+ sample_ms = cpu_to_le32(info->cpucp_sample_ms);
+ ret = ops->set_param(ph, &sample_ms, sizeof(sample_ms),
+ MEMLAT_ALGO_STR, MEMLAT_SAMPLE_MS);
+ if (ret < 0)
+ return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n");
+
+ /* Set the effective cpu frequency calculation method */
+ freq_method = cpu_to_le32(info->cpucp_freq_method);
+ ret = ops->set_param(ph, &freq_method, sizeof(freq_method),
+ MEMLAT_ALGO_STR, MEMLAT_SET_EFFECTIVE_FREQ_METHOD);
+ if (ret < 0)
+ return dev_err_probe(&sdev->dev, ret,
+ "failed to set effective frequency calc method\n");
+
+ /* Start sampling and voting timer */
+ ret = ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TIMER);
+ if (ret < 0)
+ return dev_err_probe(&sdev->dev, ret, "failed to start memory group timer\n");
+
+ for (i = 0; i < info->memory_cnt; i++) {
+ struct scmi_qcom_memory_info *memory = info->memory[i];
+ struct platform_device *pdev = memory->pdev;
+ struct devfreq_dev_profile *profile = &memory->profile;
+
+ /* sampling time should be double the devfreq observing time */
+ profile->polling_ms = max(1U, info->cpucp_sample_ms / 2);
+ profile->get_cur_freq = scmi_qcom_devfreq_get_cur_freq;
+ profile->initial_freq = memory->min_freq > 1 ?
+ (memory->min_freq * 1000UL) : memory->min_freq;
+
+ platform_set_drvdata(pdev, memory);
+
+ memory->devfreq = devm_devfreq_add_device(&pdev->dev, profile,
+ DEVFREQ_GOV_REMOTE, NULL);
+ if (IS_ERR(memory->devfreq)) {
+ dev_err(&sdev->dev, "failed to add devfreq device\n");
+ /* Stop sampling and voting timer */
+ ret = ops->stop_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TIMER);
+ if (ret < 0)
+ dev_err_probe(&sdev->dev, ret,
+ "failed to stop memory group timer\n");
+ return PTR_ERR(memory->devfreq);
+ }
+ }
+
+ return 0;
+}
+
+static struct scmi_qcom_memlat_map *
+scmi_qcom_parse_memlat_map(struct device *dev, const struct scmi_qcom_monitor_cfg *mon_cfg)
+{
+ struct scmi_qcom_memlat_map *map_table;
+ const struct scmi_qcom_map_table *table;
+
+ if (mon_cfg->table_len > MAX_MAP_ENTRIES)
+ return ERR_PTR(-EINVAL);
+
+ map_table = devm_kcalloc(dev, mon_cfg->table_len, sizeof(*map_table),
+ GFP_KERNEL);
+ if (!map_table)
+ return ERR_PTR(-ENOMEM);
+
+ for (int i = 0; i < mon_cfg->table_len; i++) {
+ table = &mon_cfg->table[i];
+
+ map_table[i].cpufreq_mhz = table->cpu_freq;
+ map_table[i].memfreq_khz = table->mem_freq;
+ }
+
+ return map_table;
+}
+
+static const struct of_device_id scmi_qcom_memlat_configs[] = {
+ { .compatible = "qcom,glymur", .data = &glymur_memlat_data},
+ { .compatible = "qcom,mahua", .data = &glymur_memlat_data},
+ { .compatible = "qcom,x1e80100", .data = &hamoa_memlat_data},
+ { .compatible = "qcom,x1p42100", .data = &hamoa_memlat_data},
+ { }
+};
+
+static int scmi_qcom_memlat_parse_cfg(struct scmi_device *sdev, struct scmi_qcom_memlat_info *info)
+{
+ const struct scmi_qcom_memlat_cfg_data *cfg_data;
+ struct scmi_qcom_monitor_info *monitor;
+ struct scmi_qcom_memory_info *memory;
+ int ret, i, j;
+
+ cfg_data = of_machine_get_match_data(scmi_qcom_memlat_configs);
+ if (!cfg_data) {
+ /*
+ * The SCMI generic-ext protocol can bind on Qualcomm SoCs that
+ * do not ship CPUCP memlat. Bail out quietly in that case rather
+ * than printing an error on every such system.
+ */
+ dev_dbg(&sdev->dev, "no memlat config data for this platform\n");
+ return -ENODEV;
+ }
+
+ info->memory = devm_kcalloc(&sdev->dev, cfg_data->memory_cnt,
+ sizeof(*info->memory), GFP_KERNEL);
+ if (!info->memory)
+ return -ENOMEM;
+
+ for (i = 0; i < cfg_data->memory_cnt; i++) {
+ const struct scmi_qcom_memory_cfg *memory_cfg = &cfg_data->memory_cfg[i];
+ struct platform_device_info pdevinfo = { 0 };
+
+ pdevinfo.parent = &sdev->dev;
+ pdevinfo.name = memory_cfg->name;
+ pdevinfo.id = PLATFORM_DEVID_NONE;
+
+ memory = devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL);
+ if (!memory)
+ return -ENOMEM;
+
+ memory->ops = info->ops;
+ memory->ph = info->ph;
+ memory->hw_type = memory_cfg->memory_type;
+ memory->monitor_cnt = memory_cfg->monitor_cnt;
+ memory->min_freq = memory_cfg->memory_range.min_freq;
+ memory->max_freq = memory_cfg->memory_range.max_freq;
+
+ memory->pdev = platform_device_register_full(&pdevinfo);
+ if (IS_ERR(memory->pdev))
+ return dev_err_probe(&sdev->dev, PTR_ERR(memory->pdev),
+ "failed to register platform device\n");
+
+ info->memory[i] = memory;
+ /* Track progress so probe() can unwind on a later failure. */
+ info->memory_cnt = i + 1;
+
+ for (j = 0; j < memory_cfg->num_opps; j++) {
+ const struct scmi_qcom_opp_data *table = &memory_cfg->mem_table[j];
+ struct platform_device *pdev = memory->pdev;
+ struct dev_pm_opp_data data = {};
+
+ data.freq = table->freq;
+ data.level = table->level;
+
+ ret = dev_pm_opp_add_dynamic(&pdev->dev, &data);
+ if (ret)
+ return dev_err_probe(&sdev->dev, ret, "failed to add OPP\n");
+ }
+
+ memory->monitor = devm_kcalloc(&sdev->dev, memory_cfg->monitor_cnt,
+ sizeof(*memory->monitor), GFP_KERNEL);
+ if (!memory->monitor)
+ return -ENOMEM;
+
+ for (j = 0; j < memory_cfg->monitor_cnt; j++) {
+ const struct scmi_qcom_monitor_cfg *mon_cfg = &memory_cfg->monitor_cfg[j];
+
+ monitor = devm_kzalloc(&sdev->dev, sizeof(*monitor), GFP_KERNEL);
+ if (!monitor)
+ return -ENOMEM;
+
+ monitor->ipm_ceil = mon_cfg->ipm_ceil;
+ /* mon_type 0 = IPM-based latency monitor; 1 = stall-only (compute) */
+ monitor->mon_type = monitor->ipm_ceil ? 0 : 1;
+ monitor->be_stall_floor = mon_cfg->be_stall_floor;
+ monitor->mask = mon_cfg->cpu_mask;
+ monitor->freq_map_len = mon_cfg->table_len;
+
+ monitor->freq_map = scmi_qcom_parse_memlat_map(&sdev->dev, mon_cfg);
+ if (IS_ERR(monitor->freq_map))
+ return dev_err_probe(&sdev->dev, PTR_ERR(monitor->freq_map),
+ "failed to populate cpufreq-memfreq map\n");
+
+ strscpy(monitor->name, mon_cfg->name, sizeof(monitor->name));
+ monitor->mon_idx = j;
+ memory->monitor[j] = monitor;
+ }
+ }
+
+ info->cfg_data = cfg_data;
+ info->cpucp_freq_method = cfg_data->cpucp_freq_method;
+ info->cpucp_sample_ms = cfg_data->cpucp_sample_ms;
+
+ return 0;
+}
+
+static int scmi_qcom_devfreq_memlat_probe(struct scmi_device *sdev)
+{
+ const struct scmi_handle *handle = sdev->handle;
+ const struct qcom_generic_ext_ops *ops;
+ struct scmi_qcom_memlat_info *info;
+ struct scmi_protocol_handle *ph;
+ int ret;
+
+ if (!handle)
+ return -ENODEV;
+
+ info = devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph);
+ if (IS_ERR(ops))
+ return PTR_ERR(ops);
+
+ info->ops = ops;
+ info->ph = ph;
+
+ ret = scmi_qcom_memlat_parse_cfg(sdev, info);
+ if (ret) {
+ scmi_qcom_memlat_unwind(info, info->memory_cnt);
+ return ret;
+ }
+
+ ret = scmi_qcom_memlat_configure_events(sdev, info);
+ if (ret) {
+ scmi_qcom_memlat_unwind(info, info->memory_cnt);
+ return ret;
+ }
+
+ dev_set_drvdata(&sdev->dev, info);
+
+ return ret;
+}
+
+static void scmi_qcom_devfreq_memlat_remove(struct scmi_device *sdev)
+{
+ struct scmi_qcom_memlat_info *info = dev_get_drvdata(&sdev->dev);
+ struct scmi_protocol_handle *ph;
+ const struct qcom_generic_ext_ops *ops;
+ int ret;
+
+ if (!info)
+ return;
+
+ ph = info->ph;
+ ops = info->ops;
+
+ ret = ops->stop_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TIMER);
+ if (ret < 0)
+ dev_err(&sdev->dev, "failed to stop memory group timer\n");
+
+ scmi_qcom_memlat_unwind(info, info->memory_cnt);
+}
+
+static const struct scmi_device_id scmi_id_table[] = {
+ { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" },
+ { },
+};
+MODULE_DEVICE_TABLE(scmi, scmi_id_table);
+
+static struct scmi_driver scmi_qcom_devfreq_memlat_driver = {
+ .name = "scmi-qcom-devfreq-memlat",
+ .probe = scmi_qcom_devfreq_memlat_probe,
+ .remove = scmi_qcom_devfreq_memlat_remove,
+ .id_table = scmi_id_table,
+};
+module_scmi_driver(scmi_qcom_devfreq_memlat_driver);
+
+MODULE_AUTHOR("Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>");
+MODULE_DESCRIPTION("SCMI QCOM DEVFREQ MEMLAT driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 8/9] arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS DVFS
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
On Qualcomm Glymur SoCs, the memlat governor and the mechanism for
controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control
Processor (CPUCP). Add the CPUCP mailbox and SCMI nodes required for the
QCOM SCMI Generic Extension protocol to probe and get functional bus dvfs
on Glymur/Mahua SoCs.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 41 ++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e..c0edbfefc39a 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -396,6 +396,20 @@ scmi_perf: protocol@13 {
#power-domain-cells = <1>;
};
};
+
+ cpucp_scmi: scmi-1 {
+ compatible = "arm,scmi";
+ mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_vendor: protocol@80 {
+ reg = <0x80>;
+ };
+ };
};
clk_virt: interconnect-0 {
@@ -6919,6 +6933,13 @@ pdp0_mbox: mailbox@17610000 {
#mbox-cells = <1>;
};
+ cpucp_mbox: mailbox@17620000 {
+ compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0x0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
timer@17810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17810000 0x0 0x1000>;
@@ -7103,6 +7124,26 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ cpucp_sram: sram@18b4e000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x18b4e000 0x0 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x0 0x18b4e000 0x400>;
+
+ cpucp_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpucp_scp_lpri1: scp-sram-section@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
nsi_noc: interconnect@1d600000 {
compatible = "qcom,glymur-nsinoc";
reg = <0x0 0x1d600000 0x0 0x14080>;
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 6/9] PM / devfreq: Add a governor for tracking remote device frequencies
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
On SoCs where the governor and the mechanism to control the frequency
for devices like caches is hosted on the System Control Processor
(SCP), there exists a need to track the frequency changes in a
reliable way and provide ways to tweak parameters on the remote
governor.
Add a new "remote" devfreq governor that uses the track_remote
flag to expose the remote device's frequency to userspace via
trans_stat. The governor deliberately does not advertise the
DEVFREQ_GOV_ATTR_TARGET_FREQ attribute since the kernel cannot
set the frequency on a remote-managed device; reads of the
target_freq sysfs node therefore return -EINVAL.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
drivers/devfreq/Kconfig | 8 +++++
drivers/devfreq/Makefile | 1 +
drivers/devfreq/governor_remote.c | 73 +++++++++++++++++++++++++++++++++++++++
include/linux/devfreq.h | 1 +
4 files changed, 83 insertions(+)
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index c999c4a1e567..2caa87554914 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -56,6 +56,14 @@ config DEVFREQ_GOV_POWERSAVE
the DEVFREQ framework returns the lowest frequency available
at any time.
+config DEVFREQ_GOV_REMOTE
+ tristate "Remote"
+ help
+ A simple governor to track the frequency of devices whose
+ dvfs control lies outside the kernel. This governor acts
+ as an observer and provides for ways to track frequency and
+ set/get information related to the remote dvfs device.
+
config DEVFREQ_GOV_USERSPACE
tristate "Userspace"
help
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 404179d79a9d..cde57c8cda76 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PM_DEVFREQ_EVENT) += devfreq-event.o
obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) += governor_simpleondemand.o
obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
+obj-$(CONFIG_DEVFREQ_GOV_REMOTE) += governor_remote.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
diff --git a/drivers/devfreq/governor_remote.c b/drivers/devfreq/governor_remote.c
new file mode 100644
index 000000000000..df3819757e56
--- /dev/null
+++ b/drivers/devfreq/governor_remote.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-governor.h>
+
+static int devfreq_remote_track_func(struct devfreq *devfreq, unsigned long *freq)
+{
+ if (!devfreq->profile->get_cur_freq)
+ return -ENXIO;
+
+ return devfreq->profile->get_cur_freq(devfreq->dev.parent, freq);
+}
+
+static int devfreq_remote_track_handler(struct devfreq *devfreq, unsigned int event, void *data)
+{
+ switch (event) {
+ case DEVFREQ_GOV_START:
+ devfreq_monitor_start(devfreq);
+ break;
+
+ case DEVFREQ_GOV_STOP:
+ devfreq_monitor_stop(devfreq);
+ break;
+
+ case DEVFREQ_GOV_UPDATE_INTERVAL:
+ devfreq_update_interval(devfreq, (unsigned int *)data);
+ break;
+
+ case DEVFREQ_GOV_SUSPEND:
+ devfreq_monitor_suspend(devfreq);
+ break;
+
+ case DEVFREQ_GOV_RESUME:
+ devfreq_monitor_resume(devfreq);
+ break;
+ }
+
+ return 0;
+}
+
+static struct devfreq_governor devfreq_remote_track = {
+ .name = DEVFREQ_GOV_REMOTE,
+ .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL
+ | DEVFREQ_GOV_ATTR_TIMER,
+ .flags = DEVFREQ_GOV_FLAG_IMMUTABLE
+ | DEVFREQ_GOV_FLAG_TRACK_REMOTE,
+ .get_target_freq = devfreq_remote_track_func,
+ .event_handler = devfreq_remote_track_handler,
+};
+
+static int __init devfreq_remote_track_init(void)
+{
+ return devfreq_add_governor(&devfreq_remote_track);
+}
+subsys_initcall(devfreq_remote_track_init);
+
+static void __exit devfreq_remote_track_exit(void)
+{
+ int ret;
+
+ ret = devfreq_remove_governor(&devfreq_remote_track);
+ if (ret)
+ pr_err("%s: failed to remove governor %d\n", __func__, ret);
+}
+module_exit(devfreq_remote_track_exit);
+
+MODULE_DESCRIPTION("DEVFREQ Remote Tracking governor");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index dc1075dc3446..4d50cf230950 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -21,6 +21,7 @@
#define DEVFREQ_GOV_POWERSAVE "powersave"
#define DEVFREQ_GOV_USERSPACE "userspace"
#define DEVFREQ_GOV_PASSIVE "passive"
+#define DEVFREQ_GOV_REMOTE "remote"
/* DEVFREQ notifier interface */
#define DEVFREQ_TRANSITION_NOTIFIER (0)
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 5/9] PM / devfreq: Add new track_remote flag for governors
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Some devfreq governors need to track frequency changes performed on remote
devices rather than driving the frequency updates themselves. In such
cases, the device's frequency is already updated by an external entity and
devfreq only needs to keep its transition statistics and notifier
subscribers in sync.
Add a new DEVFREQ_GOV_FLAG_TRACK_REMOTE governor flag. When set,
devfreq_set_target() skips the profile->target() update sequence but still
emits the DEVFREQ_PRECHANGE/DEVFREQ_POSTCHANGE notification pair and the
devfreq_frequency trace event, so transition-notifier subscribers (passive
governor, devfreq cooling, etc.) and tracing observe the remote frequency
change exactly as they would on the normal path, and the transition
statistics are refreshed.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
drivers/devfreq/devfreq.c | 21 +++++++++++++++++++++
include/linux/devfreq-governor.h | 5 +++++
2 files changed, 26 insertions(+)
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 2f27a239e34a..71c6ced9e4e1 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -348,6 +348,26 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq,
unsigned long cur_freq;
int err = 0;
+ /*
+ * When a remote agent (e.g. firmware) owns the frequency, skip the
+ * local profile->target() call. Still emit the PRECHANGE/POSTCHANGE
+ * pair and the trace event so that transition-notifier subscribers
+ * (passive governor, devfreq cooling, etc.) and tracing observe the
+ * frequency change exactly as they would on the normal path.
+ */
+ if (devfreq->governor &&
+ IS_SUPPORTED_FLAG(devfreq->governor->flags, TRACK_REMOTE)) {
+ freqs.old = devfreq->previous_freq;
+ freqs.new = new_freq;
+ devfreq_notify_transition(devfreq, &freqs, DEVFREQ_PRECHANGE);
+
+ if (trace_devfreq_frequency_enabled() && new_freq != freqs.old)
+ trace_devfreq_frequency(devfreq, new_freq, freqs.old);
+
+ devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE);
+ goto update_status;
+ }
+
if (devfreq->profile->get_cur_freq)
devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq);
else
@@ -375,6 +395,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq,
freqs.new = new_freq;
devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE);
+update_status:
if (devfreq_update_status(devfreq, new_freq))
dev_warn(&devfreq->dev,
"Couldn't update frequency transition information.\n");
diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-governor.h
index 2853f571dfdf..e4f7b6cb07bc 100644
--- a/include/linux/devfreq-governor.h
+++ b/include/linux/devfreq-governor.h
@@ -33,9 +33,14 @@
* : This governor is never changeable to other governors.
* - DEVFREQ_GOV_FLAG_IRQ_DRIVEN
* : The devfreq won't schedule the work for this governor.
+ * - DEVFREQ_GOV_FLAG_TRACK_REMOTE
+ * : The governor only tracks frequency changes performed by a remote
+ * agent (e.g. firmware); devfreq skips the local profile->target()
+ * call and just keeps its statistics and notifiers in sync.
*/
#define DEVFREQ_GOV_FLAG_IMMUTABLE BIT(0)
#define DEVFREQ_GOV_FLAG_IRQ_DRIVEN BIT(1)
+#define DEVFREQ_GOV_FLAG_TRACK_REMOTE BIT(2)
/*
* Definition of governor attribute flags except for common sysfs attributes
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 4/9] PM / devfreq: Add new target_freq attribute flag for governors
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
The target_freq sysfs attribute exposes a governor's predicted next
target frequency. Not every devfreq governor has a meaningful value
to report there; some merely observe an externally-driven device.
Add a DEVFREQ_GOV_ATTR_TARGET_FREQ attribute flag that governors with
a meaningful target frequency must opt in to. Gate the existing
target_freq sysfs read on the flag and return -EINVAL when the active
governor does not advertise it.
Tag all in-tree governors that already populate previous_freq via
get_target_freq() so visible behaviour stays unchanged for in-tree
users. Out-of-tree governors that drive frequency updates and want
to keep target_freq readable need to set the new flag.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
Documentation/ABI/testing/sysfs-class-devfreq | 8 ++++++++
drivers/devfreq/devfreq.c | 6 ++++++
drivers/devfreq/governor_passive.c | 1 +
drivers/devfreq/governor_performance.c | 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
drivers/devfreq/hisi_uncore_freq.c | 1 +
drivers/devfreq/tegra30-devfreq.c | 3 ++-
include/linux/devfreq-governor.h | 3 +++
10 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-class-devfreq b/Documentation/ABI/testing/sysfs-class-devfreq
index df8ba88b9f6a..5be9940a5853 100644
--- a/Documentation/ABI/testing/sysfs-class-devfreq
+++ b/Documentation/ABI/testing/sysfs-class-devfreq
@@ -37,6 +37,14 @@ Description:
The /sys/class/devfreq/.../target_freq shows the next governor
predicted target frequency of the corresponding devfreq object.
+ Reading this attribute returns -EINVAL when the active
+ governor does not advertise DEVFREQ_GOV_ATTR_TARGET_FREQ.
+ All in-tree governors that drive frequency transitions tag
+ this attribute, so existing in-tree behaviour is unchanged.
+ Out-of-tree governors that previously relied on the
+ unconditional read of df->previous_freq must opt in by
+ setting DEVFREQ_GOV_ATTR_TARGET_FREQ in their attrs field.
+
What: /sys/class/devfreq/.../trans_stat
Date: October 2012
Contact: MyungJoo Ham <myungjoo.ham@samsung.com>
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index f08fc6966eae..2f27a239e34a 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -1530,6 +1530,12 @@ static ssize_t target_freq_show(struct device *dev,
{
struct devfreq *df = to_devfreq(dev);
+ guard(mutex)(&devfreq_list_lock);
+
+ if (!df->profile || !df->governor ||
+ !IS_SUPPORTED_ATTR(df->governor->attrs, TARGET_FREQ))
+ return -EINVAL;
+
return sprintf(buf, "%lu\n", df->previous_freq);
}
static DEVICE_ATTR_RO(target_freq);
diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c
index d7feecd900f1..b75e4bbee4b1 100644
--- a/drivers/devfreq/governor_passive.c
+++ b/drivers/devfreq/governor_passive.c
@@ -448,6 +448,7 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq,
static struct devfreq_governor devfreq_passive = {
.name = DEVFREQ_GOV_PASSIVE,
+ .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ,
.flags = DEVFREQ_GOV_FLAG_IMMUTABLE,
.get_target_freq = devfreq_passive_get_target_freq,
.event_handler = devfreq_passive_event_handler,
diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/governor_performance.c
index fdb22bf512cf..b9ec587f582c 100644
--- a/drivers/devfreq/governor_performance.c
+++ b/drivers/devfreq/governor_performance.c
@@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *devfreq,
static struct devfreq_governor devfreq_performance = {
.name = DEVFREQ_GOV_PERFORMANCE,
+ .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ,
.get_target_freq = devfreq_performance_func,
.event_handler = devfreq_performance_handler,
};
diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governor_powersave.c
index ee2d6ec8a512..69eab1d0a7fc 100644
--- a/drivers/devfreq/governor_powersave.c
+++ b/drivers/devfreq/governor_powersave.c
@@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devfreq,
static struct devfreq_governor devfreq_powersave = {
.name = DEVFREQ_GOV_POWERSAVE,
+ .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ,
.get_target_freq = devfreq_powersave_func,
.event_handler = devfreq_powersave_handler,
};
diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/governor_simpleondemand.c
index ac9c5e9e51a4..65ff9d912ef9 100644
--- a/drivers/devfreq/governor_simpleondemand.c
+++ b/drivers/devfreq/governor_simpleondemand.c
@@ -118,6 +118,7 @@ static int devfreq_simple_ondemand_handler(struct devfreq *devfreq,
static struct devfreq_governor devfreq_simple_ondemand = {
.name = DEVFREQ_GOV_SIMPLE_ONDEMAND,
.attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL
+ | DEVFREQ_GOV_ATTR_TARGET_FREQ
| DEVFREQ_GOV_ATTR_TIMER,
.get_target_freq = devfreq_simple_ondemand_func,
.event_handler = devfreq_simple_ondemand_handler,
diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governor_userspace.c
index 3906ebedbae8..d1b765a7b8e5 100644
--- a/drivers/devfreq/governor_userspace.c
+++ b/drivers/devfreq/governor_userspace.c
@@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *devfreq,
static struct devfreq_governor devfreq_userspace = {
.name = DEVFREQ_GOV_USERSPACE,
+ .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ,
.get_target_freq = devfreq_userspace_func,
.event_handler = devfreq_userspace_handler,
};
diff --git a/drivers/devfreq/hisi_uncore_freq.c b/drivers/devfreq/hisi_uncore_freq.c
index 4d00d813c8ac..0800116e3334 100644
--- a/drivers/devfreq/hisi_uncore_freq.c
+++ b/drivers/devfreq/hisi_uncore_freq.c
@@ -399,6 +399,7 @@ static struct devfreq_governor hisi_platform_governor = {
* Set interrupt_driven to skip the devfreq monitor mechanism, though
* this governor is not interrupt-driven.
*/
+ .attrs = DEVFREQ_GOV_ATTR_TARGET_FREQ,
.flags = DEVFREQ_GOV_FLAG_IRQ_DRIVEN,
.get_target_freq = hisi_platform_gov_func,
.event_handler = hisi_platform_gov_handler,
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index 401aac6a9f07..fcb278c4a74c 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -776,7 +776,8 @@ static int tegra_governor_event_handler(struct devfreq *devfreq,
static struct devfreq_governor tegra_devfreq_governor = {
.name = "tegra_actmon",
- .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL,
+ .attrs = DEVFREQ_GOV_ATTR_POLLING_INTERVAL
+ | DEVFREQ_GOV_ATTR_TARGET_FREQ,
.flags = DEVFREQ_GOV_FLAG_IMMUTABLE
| DEVFREQ_GOV_FLAG_IRQ_DRIVEN,
.get_target_freq = tegra_governor_get_target,
diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-governor.h
index dfdd0160a29f..2853f571dfdf 100644
--- a/include/linux/devfreq-governor.h
+++ b/include/linux/devfreq-governor.h
@@ -43,9 +43,12 @@
* : Indicate polling_interval sysfs attribute
* - DEVFREQ_GOV_ATTR_TIMER
* : Indicate timer sysfs attribute
+ * - DEVFREQ_GOV_ATTR_TARGET_FREQ
+ * : Indicate the target freq sysfs attribute
*/
#define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0)
#define DEVFREQ_GOV_ATTR_TIMER BIT(1)
+#define DEVFREQ_GOV_ATTR_TARGET_FREQ BIT(2)
/**
* struct devfreq_governor - Devfreq policy governor
--
2.34.1
^ permalink raw reply related
* [PATCH v8 05/10] clk: realtek: Add support for gate clock
From: Yu-Chun Lin @ 2026-06-10 8:08 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, p.zabel, cylee12,
afaerber, jyanchou
Cc: bmasney, devicetree, linux-clk, linux-kernel, linux-arm-kernel,
linux-realtek-soc, james.tai, cy.huang, stanley_chang,
eleanor.lin
In-Reply-To: <20260610080824.255063-1-eleanor.lin@realtek.com>
From: Cheng-Yu Lee <cylee12@realtek.com>
Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and
for standard regmap gate clocks.
Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled.
Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
Changes in v8:
- None
---
drivers/clk/realtek/Makefile | 2 +
drivers/clk/realtek/clk-regmap-gate.c | 70 +++++++++++++++++++++++++++
drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++
3 files changed, 137 insertions(+)
create mode 100644 drivers/clk/realtek/clk-regmap-gate.c
create mode 100644 drivers/clk/realtek/clk-regmap-gate.h
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
index a89ad77993e9..74375f8127ac 100644
--- a/drivers/clk/realtek/Makefile
+++ b/drivers/clk/realtek/Makefile
@@ -2,5 +2,7 @@
obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
clk-rtk-y += common.o
+
clk-rtk-y += clk-pll.o
+clk-rtk-y += clk-regmap-gate.o
clk-rtk-y += freq_table.o
diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c
new file mode 100644
index 000000000000..0db0057215e3
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-gate.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2017-2026 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/export.h>
+#include <linux/regmap.h>
+#include "clk-regmap-gate.h"
+
+static int clk_regmap_gate_enable(struct clk_hw *hw)
+{
+ struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw);
+ unsigned int mask;
+ unsigned int val;
+
+ mask = BIT(clkg->bit_idx);
+ val = BIT(clkg->bit_idx);
+
+ if (clkg->write_en) {
+ mask |= BIT(clkg->bit_idx + 1);
+ val |= BIT(clkg->bit_idx + 1);
+ }
+
+ return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val);
+}
+
+static void clk_regmap_gate_disable(struct clk_hw *hw)
+{
+ struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw);
+ unsigned int mask;
+ unsigned int val;
+
+ mask = BIT(clkg->bit_idx);
+ val = 0;
+
+ if (clkg->write_en) {
+ mask |= BIT(clkg->bit_idx + 1);
+ val |= BIT(clkg->bit_idx + 1);
+ }
+
+ regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val);
+}
+
+static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
+{
+ struct clk_regmap_gate *clkg = to_clk_regmap_gate(hw);
+ int ret;
+ u32 val;
+
+ ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val);
+ if (ret < 0)
+ return ret;
+
+ return !!(val & BIT(clkg->bit_idx));
+}
+
+const struct clk_ops rtk_clk_regmap_gate_ops = {
+ .enable = clk_regmap_gate_enable,
+ .disable = clk_regmap_gate_disable,
+ .is_enabled = clk_regmap_gate_is_enabled,
+};
+EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "REALTEK_CLK");
+
+const struct clk_ops rtk_clk_regmap_gate_ro_ops = {
+ .is_enabled = clk_regmap_gate_is_enabled,
+};
+EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "REALTEK_CLK");
diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h
new file mode 100644
index 000000000000..711e168071f6
--- /dev/null
+++ b/drivers/clk/realtek/clk-regmap-gate.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2017-2026 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H
+#define __CLK_REALTEK_CLK_REGMAP_GATE_H
+
+#include "common.h"
+
+struct clk_regmap_gate {
+ struct clk_regmap clkr;
+ int gate_ofs;
+ u8 bit_idx;
+ u32 write_en : 1;
+};
+
+#define __clk_regmap_gate_hw(_p) __clk_regmap_hw(&(_p)->clkr)
+
+#define __CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \
+ _write_en) \
+ struct clk_regmap_gate _name = { \
+ .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \
+ .gate_ofs = _ofs, \
+ .bit_idx = _bit_idx, \
+ .write_en = _write_en, \
+ }
+
+#define CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \
+ __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \
+ _bit_idx, _write_en)
+
+#define CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \
+ __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \
+ _ofs, _bit_idx, _write_en)
+
+#define __CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \
+ _write_en) \
+ struct clk_regmap_gate _name = { \
+ .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \
+ .gate_ofs = _ofs, \
+ .bit_idx = _bit_idx, \
+ .write_en = _write_en, \
+ }
+
+#define CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \
+ __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \
+ _bit_idx, _write_en)
+
+#define CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \
+ __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \
+ _ofs, _bit_idx, _write_en)
+
+static inline struct clk_regmap_gate *to_clk_regmap_gate(struct clk_hw *hw)
+{
+ struct clk_regmap *clkr = to_clk_regmap(hw);
+
+ return container_of(clkr, struct clk_regmap_gate, clkr);
+}
+
+extern const struct clk_ops rtk_clk_regmap_gate_ops;
+extern const struct clk_ops rtk_clk_regmap_gate_ro_ops;
+
+#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */
--
2.43.0
^ permalink raw reply related
* [PATCH RFC v7 3/9] firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra, Amir Vajid, Ramakrishna Gottimukkula
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
The QCOM SCMI Generic Extensions Protocol provides a generic way of
exposing a number of Qualcomm SoC specific features (like memory bus
scaling) through a mixture of pre-determined algorithm strings and
param_id pairs hosted on the SCMI controller.
Co-developed-by: Amir Vajid <amir.vajid@oss.qualcomm.com>
Signed-off-by: Amir Vajid <amir.vajid@oss.qualcomm.com>
Co-developed-by: Ramakrishna Gottimukkula <ramakrishna.gottimukkula@oss.qualcomm.com>
Signed-off-by: Ramakrishna Gottimukkula <ramakrishna.gottimukkula@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
drivers/firmware/arm_scmi/Kconfig | 1 +
drivers/firmware/arm_scmi/Makefile | 1 +
drivers/firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++
drivers/firmware/arm_scmi/vendors/qcom/Makefile | 2 +
.../arm_scmi/vendors/qcom/qcom-generic-ext.c | 153 +++++++++++++++++++++
include/linux/scmi_qcom_protocol.h | 37 +++++
6 files changed, 209 insertions(+)
diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig
index e3fb36825978..a52f4d1b8b2c 100644
--- a/drivers/firmware/arm_scmi/Kconfig
+++ b/drivers/firmware/arm_scmi/Kconfig
@@ -84,6 +84,7 @@ config ARM_SCMI_QUIRKS
source "drivers/firmware/arm_scmi/transports/Kconfig"
source "drivers/firmware/arm_scmi/vendors/imx/Kconfig"
+source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig"
endif #ARM_SCMI_PROTOCOL
diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile
index 780cd62b2f78..5a0e003c2477 100644
--- a/drivers/firmware/arm_scmi/Makefile
+++ b/drivers/firmware/arm_scmi/Makefile
@@ -13,6 +13,7 @@ scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y)
obj-$(CONFIG_ARM_SCMI_PROTOCOL) += transports/
obj-$(CONFIG_ARM_SCMI_PROTOCOL) += vendors/imx/
+obj-$(CONFIG_ARM_SCMI_PROTOCOL) += vendors/qcom/
obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-core.o
obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-module.o
diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig
new file mode 100644
index 000000000000..8aa0efd6a03d
--- /dev/null
+++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "ARM SCMI QCOM Vendor Protocols"
+
+config QCOM_SCMI_GENERIC_EXT
+ tristate "Qualcomm Technologies, Inc. SCMI Generic Vendor Protocol"
+ depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST && OF)
+ help
+ The QCOM SCMI vendor protocol provides a generic way of exposing
+ a number of Qualcomm SoC specific features (like memory bus scaling)
+ through a mixture of pre-determined algorithm strings and param_id
+ pairs hosted on the SCMI controller.
+
+ This driver defines/documents the message IDs used for this
+ communication and also exposes the operations used by the clients.
+endmenu
diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firmware/arm_scmi/vendors/qcom/Makefile
new file mode 100644
index 000000000000..6b98fabbebb8
--- /dev/null
+++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) += qcom-generic-ext.o
diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c
new file mode 100644
index 000000000000..77c07272c09d
--- /dev/null
+++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/module.h>
+#include <linux/scmi_qcom_protocol.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <linux/types.h>
+
+#include "../../common.h"
+
+/*
+ * This protocol is intended as a generic way of exposing a number of Qualcomm
+ * SoC specific features through a mixture of pre-determined algorithm string
+ * and param_id pairs hosted on the SCMI controller.
+ *
+ * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id set
+ * to Qualcomm and the supported version is set to 0x10000. The PROTOCOL_VERSION
+ * command returns version 1.0.
+ */
+
+/**
+ * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported by SCMI Qualcomm
+ * generic vendor protocol.
+ *
+ * @QCOM_SCMI_SET_PARAM: is used to set the parameter of a specific algo_str hosted on
+ * QCOM SCMI Vendor Protocol. The tx len depends on the algo_str used.
+ * @QCOM_SCMI_GET_PARAM: is used to get parameter information of a specific algo_str
+ * hosted on QCOM SCMI Vendor Protocol. The tx and rx len depends
+ * on the algo_str used.
+ * @QCOM_SCMI_START_ACTIVITY: is used to start the activity performed by the algo_str.
+ * @QCOM_SCMI_STOP_ACTIVITY: is used to stop a pre-existing activity performed by the algo_str.
+ */
+enum qcom_generic_ext_protocol_cmd {
+ QCOM_SCMI_SET_PARAM = 0x10,
+ QCOM_SCMI_GET_PARAM = 0x11,
+ QCOM_SCMI_START_ACTIVITY = 0x12,
+ QCOM_SCMI_STOP_ACTIVITY = 0x13,
+};
+
+/**
+ * struct qcom_scmi_msg - represents the various parameters to be populated
+ * for using the QCOM SCMI Vendor Protocol
+ *
+ * @ext_id: reserved, must be zero
+ * @algo_low: lower 32 bits of the algo_str
+ * @algo_high: upper 32 bits of the algo_str
+ * @param_id: serves as token message id to the specific algo_str
+ * @buf: serves as the payload to the specified param_id and algo_str pair
+ */
+struct qcom_scmi_msg {
+ __le32 ext_id;
+ __le32 algo_low;
+ __le32 algo_high;
+ __le32 param_id;
+ __le32 buf[];
+};
+
+static int qcom_scmi_common_xfer(const struct scmi_protocol_handle *ph,
+ enum qcom_generic_ext_protocol_cmd cmd_id, void *buf,
+ size_t buf_len, u64 algo_str, u32 param_id, size_t rx_size)
+{
+ struct scmi_xfer *t;
+ struct qcom_scmi_msg *msg;
+ int ret;
+
+ /* Reject calls where rx_size exceeds buf_len. */
+ if (rx_size > buf_len)
+ return -EINVAL;
+
+ ret = ph->xops->xfer_get_init(ph, cmd_id, buf_len + sizeof(*msg), rx_size, &t);
+ if (ret)
+ return ret;
+
+ msg = t->tx.buf;
+ msg->ext_id = 0;
+ msg->algo_low = cpu_to_le32(lower_32_bits(algo_str));
+ msg->algo_high = cpu_to_le32(upper_32_bits(algo_str));
+ msg->param_id = cpu_to_le32(param_id);
+ memcpy(msg->buf, buf, buf_len);
+
+ ret = ph->xops->do_xfer(ph, t);
+ if (!ret && rx_size)
+ /*
+ * Response is returned into the caller's @buf, replacing the
+ * tx payload. Callers using the same on-stack struct for both
+ * directions must not rely on tx contents after this point.
+ */
+ memcpy(buf, t->rx.buf, t->rx.len);
+ ph->xops->xfer_put(ph, t);
+
+ return ret;
+}
+
+static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id)
+{
+ return qcom_scmi_common_xfer(ph, QCOM_SCMI_SET_PARAM, buf, buf_len, algo_str,
+ param_id, 0);
+}
+
+static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id, size_t rx_size)
+{
+ return qcom_scmi_common_xfer(ph, QCOM_SCMI_GET_PARAM, buf, buf_len, algo_str,
+ param_id, rx_size);
+}
+
+static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph, void *buf,
+ size_t buf_len, u64 algo_str, u32 param_id)
+{
+ return qcom_scmi_common_xfer(ph, QCOM_SCMI_START_ACTIVITY, buf, buf_len, algo_str,
+ param_id, 0);
+}
+
+static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, void *buf,
+ size_t buf_len, u64 algo_str, u32 param_id)
+{
+ return qcom_scmi_common_xfer(ph, QCOM_SCMI_STOP_ACTIVITY, buf, buf_len, algo_str,
+ param_id, 0);
+}
+
+static const struct qcom_generic_ext_ops qcom_proto_ops = {
+ .set_param = qcom_scmi_set_param,
+ .get_param = qcom_scmi_get_param,
+ .start_activity = qcom_scmi_start_activity,
+ .stop_activity = qcom_scmi_stop_activity,
+};
+
+static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handle *ph)
+{
+ dev_dbg(ph->dev, "QCOM Generic Vendor Version %d.%d\n",
+ PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version));
+
+ return 0;
+}
+
+static const struct scmi_protocol qcom_generic_ext = {
+ .id = SCMI_PROTOCOL_QCOM_GENERIC,
+ .owner = THIS_MODULE,
+ .instance_init = &qcom_generic_ext_protocol_init,
+ .ops = &qcom_proto_ops,
+ .vendor_id = "Qualcomm",
+ .supported_version = 0x10000,
+};
+module_scmi_protocol(qcom_generic_ext);
+
+MODULE_ALIAS("scmi-protocol-" __stringify(SCMI_PROTOCOL_QCOM_GENERIC) "-Qualcomm");
+MODULE_AUTHOR("Sibi Sankar <sibi.sankar@oss.qualcomm.com>");
+MODULE_DESCRIPTION("QCOM SCMI Generic Vendor Protocol");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_protocol.h
new file mode 100644
index 000000000000..41632ee7bbc7
--- /dev/null
+++ b/include/linux/scmi_qcom_protocol.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * SCMI Message Protocol driver QCOM extension header
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H
+#define _LINUX_SCMI_QCOM_PROTOCOL_H
+
+#include <linux/types.h>
+
+#define SCMI_PROTOCOL_QCOM_GENERIC 0x80
+
+struct scmi_protocol_handle;
+
+/**
+ * struct qcom_generic_ext_ops - represents the various operations provided
+ * by QCOM Generic Vendor Protocol
+ *
+ * @set_param: set parameter specified by param_id and algo_str pair.
+ * @get_param: retrieve parameter specified by param_id and algo_str pair.
+ * @start_activity: initiate a specific activity defined by algo_str.
+ * @stop_activity: halt previously initiated activity defined by algo_str.
+ */
+struct qcom_generic_ext_ops {
+ int (*set_param)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id);
+ int (*get_param)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id, size_t rx_size);
+ int (*start_activity)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id);
+ int (*stop_activity)(const struct scmi_protocol_handle *ph, void *buf, size_t buf_len,
+ u64 algo_str, u32 param_id);
+};
+
+#endif /* _LINUX_SCMI_QCOM_PROTOCOL_H */
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 2/9] dt-bindings: firmware: arm,scmi: Add Qualcomm Generic Extension Protocol
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
Add the binding schema for the Qualcomm SCMI Generic Extension Protocol
which helps support Bus DVFS on Glymur/Mahua/Hamoa/Purwa SoCs.
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
.../devicetree/bindings/firmware/arm,scmi.yaml | 1 +
.../bindings/firmware/qcom,generic-scmi.yaml | 27 ++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
index d06cca9273c4..aedc57dd3b38 100644
--- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -24,6 +24,7 @@ description: |
anyOf:
- $ref: /schemas/firmware/nxp,imx95-scmi.yaml
+ - $ref: /schemas/firmware/qcom,generic-scmi.yaml
properties:
$nodename:
diff --git a/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml
new file mode 100644
index 000000000000..077653dc1cda
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/qcom,generic-scmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm System Control and Management Interface(SCMI) Vendor Protocols Extension
+
+maintainers:
+ - Sibi Sankar <sibi.sankar@oss.qualcomm.com>
+ - Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
+
+properties:
+ protocol@80:
+ description:
+ SCMI Qualcomm Generic Vendor Protocol which exposes a number of
+ Qualcomm SoC specific features (such as memory bus scaling) through
+ a mixture of pre-determined algorithm strings and param_id pairs
+ hosted on the SCMI controller.
+ $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node'
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ const: 0x80
+
+additionalProperties: true
--
2.34.1
^ permalink raw reply related
* [PATCH RFC v7 1/9] firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra
In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com>
From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Add QCOM System Control Management Interface (SCMI) Generic Vendor
Extensions Protocol documentation. It exposes Qualcomm SoC-specific
features through (algorithm string, param_id) pairs carried over a small
set of generic SET/GET/START/STOP commands, alongside the standard
PROTOCOL_VERSION / _ATTRIBUTES / _MESSAGE_ATTRIBUTES handshake required by
the Arm SCMI specification.
Document the protocol so that drivers targeting it have a stable reference
for command ids, payload layouts and status code semantics. The first
algorithm covered is MEMLAT (memory latency governor), including its
memory-group model (DDR, LLCC, DDR_QOS), event-map programming and per-
monitor frequency voting tables.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Co-developed-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
.../arm_scmi/vendors/qcom/qcom_generic.rst | 647 +++++++++++++++++++++
1 file changed, 647 insertions(+)
diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst
new file mode 100644
index 000000000000..ba0c64729790
--- /dev/null
+++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst
@@ -0,0 +1,647 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. include:: <isonum.txt>
+
+===============================================================================
+QCOM System Control and Management Interface(SCMI) Vendor Protocols Extension
+===============================================================================
+
+:Copyright: |copy| Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+:Author:
+ - Sibi Sankar <sibi.sankar@oss.qualcomm.com>
+ - Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
+
+SCMI_GENERIC: System Control and Management Interface QCOM Generic Vendor Protocol
+==================================================================================
+
+This protocol is intended as a generic way of exposing a number of Qualcomm
+SoC specific features through a mixture of pre-determined algorithm string and
+param_id pairs hosted on the SCMI controller. It implements an interface compliant
+with the Arm SCMI Specification with additional vendor specific commands as
+detailed below.
+
+Supported algorithm strings are documented in their own sections after the
+generic commands (currently: MEMLAT, see below).
+
+Commands:
+_________
+
+PROTOCOL_VERSION
+~~~~~~~~~~~~~~~~
+
+message_id: 0x0
+protocol_id: 0x80
+
++---------------+--------------------------------------------------------------+
+|Return values |
++---------------+--------------------------------------------------------------+
+|Name |Description |
++---------------+--------------------------------------------------------------+
+|int32 status |See ARM SCMI Specification for status code definitions. |
++---------------+--------------------------------------------------------------+
+|uint32 version |For this revision of the specification, this value must be |
+| |0x10000. |
++---------------+--------------------------------------------------------------+
+
+PROTOCOL_ATTRIBUTES
+~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x1
+protocol_id: 0x80
+
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |See ARM SCMI Specification for status code definitions. |
++------------------+-----------------------------------------------------------+
+|uint32 attributes |Bits[31:16] Reserved, must be set to 0. |
+| |Bits[15:8] Number of agents in the system. Must match the |
+| |value reported by the standard BASE protocol's |
+| |PROTOCOL_ATTRIBUTES response. |
+| |Bits[7:0] Number of algorithmic strings supported by the |
+| |system. Only "MEMLAT" is currently supported hence it |
+| |returns 1. |
++------------------+-----------------------------------------------------------+
+
+PROTOCOL_MESSAGE_ATTRIBUTES
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x2
+protocol_id: 0x80
+
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |See ARM SCMI Specification for status code definitions. |
++------------------+-----------------------------------------------------------+
+|uint32 attributes |For all message IDs the parameter has a value of 0. |
++------------------+-----------------------------------------------------------+
+
+QCOM_SCMI_SET_PARAM
+~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x10
+protocol_id: 0x80
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 ext_id |Reserved, must be zero. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_low |Lower 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_high |Upper 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 param_id |Serves as the token message id for the algorithm string |
+| |and is used to set various parameters supported by it. |
++------------------+-----------------------------------------------------------+
+|uint32 buf[] |Serves as the payload for the specified param_id and |
+| |algorithm string pair. The payload size depends on the |
+| |(algorithm string, param_id) pair; see the per-algorithm |
+| |sections below. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: if the param_id and buf[] is parsed successfully |
+| |by the chosen algorithm string. |
+| |NOT_SUPPORTED: if the algorithm string does not have any |
+| |matches. |
+| |INVALID_PARAMETERS: if the param_id and the buf[] passed |
+| |is rejected by the algorithm string. |
++------------------+-----------------------------------------------------------+
+
+QCOM_SCMI_GET_PARAM
+~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x11
+protocol_id: 0x80
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 ext_id |Reserved, must be zero. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_low |Lower 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_high |Upper 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 param_id |Serves as the token message id for the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 buf[] |Serves as the payload and store of value for the specified |
+| |param_id and algorithm string pair. The payload size |
+| |depends on the (algorithm string, param_id) pair; see the |
+| |per-algorithm sections below. The response payload is |
+| |returned in the same buffer, overwriting the request |
+| |contents on success. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: if the param_id and buf[] is parsed successfully |
+| |by the chosen algorithm string and the result is copied |
+| |into buf[]. |
+| |NOT_SUPPORTED: if the algorithm string does not have any |
+| |matches. |
+| |INVALID_PARAMETERS: if the param_id and the buf[] passed |
+| |is rejected by the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 buf[] |Holds the payload of the result of the query, returned in |
+| |the same buffer used to send the request. Size depends on |
+| |the (algorithm string, param_id) pair. |
++------------------+-----------------------------------------------------------+
+
+QCOM_SCMI_START_ACTIVITY
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x12
+protocol_id: 0x80
+
+The activity to be started is defined by the algorithm string; see the
+per-algorithm sections (e.g. MEMLAT_START_TIMER) for valid param_ids.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 ext_id |Reserved, must be zero. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_low |Lower 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_high |Upper 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 param_id |Serves as the token message id for the algorithm string |
+| |and is generally used to start the activity performed by |
+| |the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 buf[] |Serves as the payload for the specified param_id and |
+| |algorithm string pair. The payload size depends on the |
+| |(algorithm string, param_id) pair; see the per-algorithm |
+| |sections below. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: if the activity performed by the algorithm string |
+| |starts successfully, or if it was already running. |
+| |NOT_SUPPORTED: if the algorithm string does not have any |
+| |matches. |
++------------------+-----------------------------------------------------------+
+
+QCOM_SCMI_STOP_ACTIVITY
+~~~~~~~~~~~~~~~~~~~~~~~
+
+message_id: 0x13
+protocol_id: 0x80
+
+The activity to be stopped is defined by the algorithm string; see the
+per-algorithm sections (e.g. MEMLAT_STOP_TIMER) for valid param_ids.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 ext_id |Reserved, must be zero. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_low |Lower 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 algo_high |Upper 32-bit value of the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 param_id |Serves as the token message id for the algorithm string |
+| |and is generally used to stop the activity performed by |
+| |the algorithm string. |
++------------------+-----------------------------------------------------------+
+|uint32 buf[] |Serves as the payload for the specified param_id and |
+| |algorithm string pair. The payload size depends on the |
+| |(algorithm string, param_id) pair; see the per-algorithm |
+| |sections below. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: if the activity performed by the algorithm string |
+| |stops successfully, or if it was not running. |
+| |NOT_SUPPORTED: if the algorithm string does not have any |
+| |matches. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT: Memory Latency algorithm
+================================
+
+The MEMLAT algorithm string (0x4D454D4C4154, ASCII "MEMLAT") is hosted on
+the Qualcomm Generic Vendor Protocol and runs on the CPUCP firmware. The
+6-byte value is treated as a 64-bit algorithm string and split into two
+uint32 fields on the wire: algo_low carries its lower 32 bits and algo_high
+its upper 32 bits.
+It samples per-CPU performance counters at a configurable period, computes
+per memory-group statistics (Instructions-Per-Miss, back-end stall, etc.),
+and votes the resulting target frequency to the bus interconnect for DDR,
+LLCC and DDR_QOS. Userspace control of the algorithm is exposed via
+parameter IDs issued through QCOM_SCMI_SET_PARAM and QCOM_SCMI_GET_PARAM.
+
+The hw_type field carried in most payloads identifies the memory group:
+
++----------+--------------------------------------------------------------+
+|hw_type |Group |
++----------+--------------------------------------------------------------+
+|0 |DDR |
++----------+--------------------------------------------------------------+
+|1 |LLCC |
++----------+--------------------------------------------------------------+
+|2 |DDR_QOS |
++----------+--------------------------------------------------------------+
+
+All multi-byte fields below are little-endian, in line with the SCMI
+specification. mon_idx selects a monitor within the group (0-based, less
+than the firmware-supported maximum). All SET commands return the SCMI
+status word; on success it carries SUCCESS, on lookup failure
+INVALID_PARAMETERS, and on an unknown param_id NOT_SUPPORTED.
+
+Frequency units differ per command: MEMLAT_SET_MIN_FREQ and
+MEMLAT_SET_MAX_FREQ take kHz for DDR/LLCC, whereas MEMLAT_MON_FREQ_MAP
+expresses the resulting vote (v2) in MHz for DDR/LLCC. For DDR_QOS all of
+these carry a raw level index (0 / 1) rather than a frequency.
+
+MEMLAT_SET_MEM_GROUP
+~~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x10 (16)
+command: QCOM_SCMI_SET_PARAM
+
+Allocates a new memory group on the firmware side and binds it to the
+underlying interconnect path (DDR / LLCC / DDR_QOS).
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 cpumask |Bitmask of HW CPU IDs that contribute counters to this |
+| |group (limited to 32 CPUs). |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier (0 = DDR, 1 = LLCC, 2 = DDR_QOS). |
++------------------+-----------------------------------------------------------+
+|uint32 mon_type |Reserved for SET_MEM_GROUP (set to 0; populated only on |
+| |SET_MONITOR). |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Reserved for SET_MEM_GROUP (set to 0). |
++------------------+-----------------------------------------------------------+
+|char mon_name[20] |Reserved for SET_MEM_GROUP (zero-filled). |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: group allocated. |
+| |BUSY: no free memory group slot (the firmware-supported |
+| |maximum number of groups is already configured). |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_MONITOR
+~~~~~~~~~~~~~~~~~~
+
+param_id: 0x11 (17)
+command: QCOM_SCMI_SET_PARAM
+
+Adds a monitor (a CPU subset that votes within an already-configured
+group).
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 cpumask |Bitmask of HW CPU IDs assigned to this monitor (must be a |
+| |subset of the group's cpumask; limited to 32 CPUs). |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier the monitor belongs to. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_type |0 = IPM-based latency monitor, 1 = compute (stall-only) |
+| |monitor. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Index of the monitor within the group. |
++------------------+-----------------------------------------------------------+
+|char mon_name[20] |Human-readable monitor name (NUL-terminated, used in |
+| |firmware log lines). |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: monitor created. |
+| |NOT_FOUND: hw_type does not match any configured group, or |
+| |the firmware-supported maximum number of monitors already |
+| |exist for the group. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_COMMON_EV_MAP
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x12 (18)
+command: QCOM_SCMI_SET_PARAM
+
+Configures the common counter IDs (instructions, cycles, stall, etc.)
+that the firmware reads on every sample for every CPU.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 num_evs |Number of valid entries in cid[]. |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Set to 0xFF (sentinel for the common-events case). |
++------------------+-----------------------------------------------------------+
+|uint8 cid[] |Array of CPUCP counter IDs indexed by INST/CYC/CONST_CYC/ |
+| |FE_STALL/BE_STALL. 0xFF marks an unused slot. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if num_evs exceeds the |
+| |firmware-supported maximum. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_GRP_EV_MAP
+~~~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x13 (19)
+command: QCOM_SCMI_SET_PARAM
+
+Configures the per-group event IDs (cache miss / writeback / access)
+used by the IPM and write-back computations for the selected hw_type.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 num_evs |Number of valid entries in cid[]. |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint8 cid[] |Array of CPUCP counter IDs indexed by MISS/WB/ACC. 0xFF |
+| |marks an unused slot. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type is unknown or |
+| |num_evs exceeds the firmware-supported maximum. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_IPM_CEIL
+~~~~~~~~~~~~~~~
+
+param_id: 0x17 (23)
+command: QCOM_SCMI_SET_PARAM
+
+Sets the IPM (Instructions-Per-Miss) ceiling for a monitor. CPUs whose
+IPM falls at or below this ceiling are considered memory-bound and
+contribute their cpufreq into the monitor's voting pool.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|uint32 val |IPM ceiling (instructions per cache miss). |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) does |
+| |not match a registered monitor. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_BE_STALL_FLOOR
+~~~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x19 (25)
+command: QCOM_SCMI_SET_PARAM
+
+Sets the back-end stall floor (in milli-percent: 100000 = 100%) for a
+monitor. CPUs whose back-end stall is at or above this floor are
+eligible to contribute their cpufreq even if their IPM is above the
+ceiling.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|uint32 val |Back-end stall floor in milli-percent (0..100000). |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) does |
+| |not match a registered monitor. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SAMPLE_MS
+~~~~~~~~~~~~~~~~
+
+param_id: 0x1F (31)
+command: QCOM_SCMI_SET_PARAM
+
+Sets the sampling period (in milliseconds) used by the firmware update
+loop.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 sample_ms |Sampling period in milliseconds. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_MON_FREQ_MAP
+~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x20 (32)
+command: QCOM_SCMI_SET_PARAM
+
+Programs the cpufreq to memfreq voting table for a single monitor.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|uint32 nr_rows |Number of valid rows in tbl[] (must not exceed the |
+| |firmware-supported maximum). |
++------------------+-----------------------------------------------------------+
+|struct { |Per-row mapping. v1 is the cpufreq trigger in MHz; v2 is |
+| uint16 v1; |the resulting memfreq vote (MHz for DDR/LLCC, a level |
+| uint16 v2; |index 0/1 for DDR_QOS). |
+|} tbl[] | |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) is |
+| |unknown / OUT_OF_RANGE if nr_rows exceeds the |
+| |firmware-supported maximum. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_MIN_FREQ
+~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x21 (33)
+command: QCOM_SCMI_SET_PARAM
+
+Clamps a monitor's vote to a minimum value. Units are kHz for DDR/LLCC and
+raw level index for DDR_QOS.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|uint32 val |Minimum frequency: kHz for DDR/LLCC, level for DDR_QOS. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) does |
+| |not match a registered monitor. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_MAX_FREQ
+~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x22 (34)
+command: QCOM_SCMI_SET_PARAM
+
+Clamps a monitor's vote to a maximum value. Units identical to
+MEMLAT_SET_MIN_FREQ.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|uint32 val |Maximum frequency: kHz for DDR/LLCC, level for DDR_QOS. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) does |
+| |not match a registered monitor. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_GET_CUR_FREQ
+~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x23 (35)
+command: QCOM_SCMI_GET_PARAM
+
+Reads the current target frequency that the firmware is voting for the
+selected (hw_type, mon_idx) tuple. The response payload is returned in
+the same buffer used to send the request, overwriting it on success.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|uint32 hw_type |Memory group identifier. |
++------------------+-----------------------------------------------------------+
+|uint32 mon_idx |Monitor index within the group. |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) does |
+| |not match a registered monitor. |
++------------------+-----------------------------------------------------------+
+|uint32 cur_freq |Current target frequency in kHz for DDR/LLCC; raw level |
+| |(0/1) for DDR_QOS. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_START_TIMER
+~~~~~~~~~~~~~~~~~~
+
+param_id: 0x24 (36)
+command: QCOM_SCMI_START_ACTIVITY
+
+Starts the firmware sampling and voting loop at the configured
+sample_ms interval. Has no payload beyond the QCOM_SCMI_START_ACTIVITY
+header.
+
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: timer started (or was already running). |
+| |GENERIC_ERROR: events not yet initialized |
+| |(MEMLAT_SET_GRP_EV_MAP not called for any group). |
+| |NOT_SUPPORTED: invalid param_id under START_ACTIVITY. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_STOP_TIMER
+~~~~~~~~~~~~~~~~~
+
+param_id: 0x25 (37)
+command: QCOM_SCMI_STOP_ACTIVITY
+
+Suspends the firmware sampling and voting loop. Has no payload beyond
+the QCOM_SCMI_STOP_ACTIVITY header. The configured monitors and freq
+maps are retained, so a subsequent MEMLAT_START_TIMER resumes voting
+without re-programming.
+
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS: timer stopped (or was already stopped). |
+| |NOT_SUPPORTED: invalid param_id under STOP_ACTIVITY. |
++------------------+-----------------------------------------------------------+
+
+MEMLAT_SET_EFFECTIVE_FREQ_METHOD
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+param_id: 0x27 (39)
+command: QCOM_SCMI_SET_PARAM
+
+Selects the algorithm used to derive the per-CPU effective frequency
+from the cycle counters.
+
++------------------+-----------------------------------------------------------+
+|Parameters |
++------------------+-----------------------------------------------------------+
+|Name |Description |
++------------------+-----------------------------------------------------------+
+|int32 method |0: const-cycles method (CPU cycles / const-cycles, scaled |
+| |by the cluster's max frequency). |
+| |1: legacy method (CPU cycles / sampling-window time). |
++------------------+-----------------------------------------------------------+
+|Return values |
++------------------+-----------------------------------------------------------+
+|int32 status |SUCCESS / INVALID_PARAMETERS if method is not 0 or 1. |
++------------------+-----------------------------------------------------------+
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 1/7] KVM: arm64: Support FFA_NOTIFICATION_BITMAP_CREATE in host handler
From: Vincent Donnefort @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sebastian Ene
Cc: catalin.marinas, maz, oupton, will, joey.gouly, korneld, kvmarm,
linux-arm-kernel, linux-kernel, android-kvm, mrigendra.chaubey,
perlarsen, suzuki.poulose, yuzenghui
In-Reply-To: <20260608165549.1479409-2-sebastianene@google.com>
Hi Seb,
On Mon, Jun 08, 2026 at 04:55:43PM +0000, Sebastian Ene wrote:
> Allow FF-A notification bitmap creation messages to be forwarded to
> Trustzone from the host and introduce a helper to check for SBZ
> register fields.
>
> Signed-off-by: Sebastian Ene <sebastianene@google.com>
> ---
> arch/arm64/kvm/hyp/nvhe/ffa.c | 36 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> index 1af722771178..c20d45191085 100644
> --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> @@ -71,6 +71,18 @@ static u32 hyp_ffa_version;
> static bool has_version_negotiated;
> static hyp_spinlock_t version_lock;
>
> +static bool ffa_check_unused_args_sbz(struct kvm_cpu_context *ctxt, int first_reg)
> +{
> + int reg;
> +
> + for (reg = first_reg; reg < 17; reg++) {
The upper limit should probably be something like ARRAY_SIZE(ctx->regs.regs) - first_reg?
> + if (cpu_reg(ctxt, reg))
> + return true;
> + }
> +
> + return false;
> +}
> +
> static void ffa_to_smccc_error(struct arm_smccc_1_2_regs *res, u64 ffa_errno)
> {
> *res = (struct arm_smccc_1_2_regs) {
> @@ -676,7 +688,6 @@ static bool ffa_call_supported(u64 func_id)
> case FFA_MEM_DONATE:
> case FFA_MEM_RETRIEVE_REQ:
> /* Optional notification interfaces added in FF-A 1.1 */
> - case FFA_NOTIFICATION_BITMAP_CREATE:
> case FFA_NOTIFICATION_BITMAP_DESTROY:
> case FFA_NOTIFICATION_BIND:
> case FFA_NOTIFICATION_UNBIND:
> @@ -862,6 +873,26 @@ static void do_ffa_part_get(struct arm_smccc_1_2_regs *res,
> hyp_spin_unlock(&host_buffers.lock);
> }
>
> +static void do_ffa_notif_bitmap_create(struct arm_smccc_1_2_regs *res,
> + struct kvm_cpu_context *ctxt)
> +{
> + DECLARE_REG(u32, vmid, ctxt, 1);
> + struct arm_smccc_1_2_regs *args;
> +
> + if (ffa_check_unused_args_sbz(ctxt, 3)) {
Is that expected we start at 3 but only read 0 and 1?
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + if (vmid != HOST_FFA_ID) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + return;
> + }
> +
> + args = (void *)&ctxt->regs.regs[0];
> + arm_smccc_1_2_smc(args, res);
Should be hyp_smccc_1_2_smc()
> +}
> +
> bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> {
> struct arm_smccc_1_2_regs res;
> @@ -920,6 +951,9 @@ bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> case FFA_PARTITION_INFO_GET:
> do_ffa_part_get(&res, host_ctxt);
> goto out_handled;
> + case FFA_NOTIFICATION_BITMAP_CREATE:
> + do_ffa_notif_bitmap_create(&res, host_ctxt);
> + goto out_handled;
> }
>
> if (ffa_call_supported(func_id))
> --
> 2.54.0.1064.gd145956f57-goog
>
^ permalink raw reply
* [PATCH RFC v7 0/9] firmware: arm_scmi: vendors: Qualcomm Generic Vendor Extensions
From: Pragnesh Papaniya @ 2026-06-10 8:51 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio
Cc: Pragnesh Papaniya, Rajendra Nayak, Pankaj Patil, linux-arm-msm,
linux-kernel, arm-scmi, linux-arm-kernel, devicetree, linux-pm,
linux-tegra, Amir Vajid, Ramakrishna Gottimukkula
The QCOM SCMI vendor protocol provides a generic way of exposing a number of
Qualcomm SoC specific features (like memory bus scaling) through a mixture of
pre-determined algorithm strings and param_id pairs hosted on the SCMI
controller. On Qualcomm Glymur and Hamoa SoCs, the memlat governor and the
mechanism to control the various caches and RAM is hosted on the CPU Control
Processor (CPUCP) and the method to tweak and start the governor is exposed
through the QCOM SCMI Generic Extension Protocol.
This series introduces the devfreq SCMI client driver that uses the MEMLAT
algorithm string hosted on the QCOM SCMI Generic Extension Protocol to detect
memory latency workloads and control frequency/level of the various memory
buses (DDR/LLCC/DDR_QOS). DDR/LLCC/DDR_QOS are modelled as devfreq devices
using the remote devfreq governor. This provides basic insight into device
operation via trans_stat and lets userspace further tweak the parameters of
the remote governor.
trans_stat data for DDR/LLCC/DDR_QOS is now available with this series:
From : To
315000000 479000000 545000000 725000000 840000000 959000000 1090000000 1211000000 time(ms)
315000000: 0 3 6 6 6 7 0 30 143956
479000000: 2 0 7 1 1 1 0 3 356
545000000: 7 6 0 5 5 0 0 10 1200
725000000: 3 0 5 0 6 1 0 6 2172
840000000: 8 2 3 2 0 4 0 12 1188
959000000: 3 0 1 2 2 0 0 13 272
1090000000: 0 0 0 0 0 0 0 0 0
1211000000: 35 4 11 5 11 8 0 0 21684
Total transition : 253
QCOM SCMI Generic Vendor protocol background:
A lot of the vendor protocol numbers used internally were for
debug/internal development purposes that were either highly SoC-specific
or had to be disabled because some features were fused out during
production. This led to a large number of vendor protocol numbers being
quickly consumed and never released. Using a single generic vendor
protocol with functionality abstracted behind algorithm strings gives us
the flexibility of letting such functionality exist during initial
development/debugging while still being able to expose mature features
(like MEMLAT) once they have stabilised. The param_ids are expected to
act as ABI for algorithm strings like MEMLAT.
Thanks in advance for taking time to review the series.
Changes in v7:
- Minor bug fixes and documentation improvements based on review feedback.
- Significantly expand the QCOM Generic Vendor Protocol documentation
with a dedicated MEMLAT section covering all param_ids, payloads and
return values [Sudeep, Cristian].
- Move per-SoC event IDs and hardware type identifiers from the driver
into the platform configuration header.
- Poll devfreq at twice the CPUCP sampling rate so every firmware voting
cycle is reliably observed [Lukasz].
- Add a devicetree binding schema for the Qualcomm SCMI vendor
protocol@80 node.
- Link to v6: https://lore.kernel.org/r/20260507062237.78051-1-sibi.sankar@oss.qualcomm.com
Changes in v6:
- Combining vendor protocol and the client and moving it
back into RFC mode.
- Introduce target_freq attr flag and TRACK_REMOTE devfreq
governor flag.
- Add basic remote devfreq governor to give users data like
transtat [Dmitry]
- Drop the current design that relies on manual parsing of
device tree data and move those into SoC specific structs
- Add Glymur/Mahua/Hamoa/Purwa support in the same series.
- Link to v5: https://lore.kernel.org/lkml/20241115011515.1313447-1-quic_sibis@quicinc.com/
Changes in v5:
- Splitting the series into vendor protocol and memlat client.
- Also the move the memlat client implementation back to RFC
due to multiple opens.
- Use common xfer helper to avoid code duplication [Dmitry]
- Update enum documentation without duplicate enum info [Dmitry]
- Update the protol attributes doc with more information. [Cristian]
- Link to v4: https://lore.kernel.org/lkml/20241007061023.1978380-1-quic_sibis@quicinc.com/
Changes in v4:
- Restructure the bindings to mimic IMX [Christian]
- Add documentation for the qcom generic vendor protocol [Christian/Sudeep]
- Pick up Rb tag and fixup/re-order elements of the vendor ops [Christian]
- Follow naming convention and folder structure used by IMX
- Add missing enum in the vendor protocol and fix documentation [Konrad]
- Add missing enum in the scmi memlat driver and fix documentation [Konrad]
- Add checks for max memory and monitor [Shivnandan]
- Fix typo from START_TIMER -> STOP_TIMER [Shivnandan]
- Make populate_physical_mask func to void [Shivnandan]
- Remove unecessary zero set [Shivnandan]
- Use __free(device node) in init_cpufreq-memfreqmap [Christian/Konrad]
- Use sdev->dev.of_node directly [Christian]
- use return dev_err_probe in multiple places [Christian]
- Link to v3: https://lore.kernel.org/lkml/20240702191440.2161623-1-quic_sibis@quicinc.com/
Changes in v3:
- Drop container dvfs memlat container node. [Rob]
- Move scmi-memlat.yaml to protocol level given that a lot of vendors might end up
- using the same protocol number. [Rob]
- Replace qcom,cpulist with the standard "cpus" property. [Rob]
- Fix up compute-type/ipm-ceil required. [Rob]
- Make driver changes to the accommodate bindings changes. [Rob]
- Minor fixups in subjects/coverletter.
- Minor style fixes in dts.
- Link to v2: https://lore.kernel.org/lkml/20240612183031.219906-1-quic_sibis@quicinc.com/
Changes in v2:
- Add missing bindings for the protocol. [Konrad/Dmitry]
- Use alternate bindings. [Dmitry/Konrad]
- Rebase on top of Cristian's "SCMI multiple vendor protocol support" series. [Cristian]
- Add more documentation wherever possible. [Sudeep]
- Replace pr_err/info with it's dev equivalents.
- Mixed tabs and initialization cleanups in the memlat driver. [Konrad]
- Commit message update for the memlat driver. [Dmitry]
- Cleanups/Fixes suggested for the client driver. [Dmitry/Konrad/Cristian]
- Use opp-tables instead of memfreq-tbl. [Dmitry/Konrad]
- Detect physical cpu to deal with variants with reduced cpu count.
- Add support for DDR_QOS mem_type.
- Link to v1: https://lore.kernel.org/lkml/20240117173458.2312669-1-quic_sibis@quicinc.com/
Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
---
Pragnesh Papaniya (1):
dt-bindings: firmware: arm,scmi: Add Qualcomm Generic Extension Protocol
Sibi Sankar (8):
firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation
firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions
PM / devfreq: Add new target_freq attribute flag for governors
PM / devfreq: Add new track_remote flag for governors
PM / devfreq: Add a governor for tracking remote device frequencies
PM / devfreq: Introduce the QCOM SCMI Memlat devfreq driver
arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS DVFS
arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS DVFS
Documentation/ABI/testing/sysfs-class-devfreq | 8 +
.../devicetree/bindings/firmware/arm,scmi.yaml | 1 +
.../bindings/firmware/qcom,generic-scmi.yaml | 27 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 41 ++
arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 +
drivers/devfreq/Kconfig | 21 +
drivers/devfreq/Makefile | 2 +
drivers/devfreq/devfreq.c | 27 +
drivers/devfreq/governor_passive.c | 1 +
drivers/devfreq/governor_performance.c | 1 +
drivers/devfreq/governor_powersave.c | 1 +
drivers/devfreq/governor_remote.c | 73 +++
drivers/devfreq/governor_simpleondemand.c | 1 +
drivers/devfreq/governor_userspace.c | 1 +
drivers/devfreq/hisi_uncore_freq.c | 1 +
drivers/devfreq/scmi-qcom-memlat-cfg.h | 573 ++++++++++++++++++
drivers/devfreq/scmi-qcom-memlat-devfreq.c | 616 ++++++++++++++++++++
drivers/devfreq/tegra30-devfreq.c | 3 +-
drivers/firmware/arm_scmi/Kconfig | 1 +
drivers/firmware/arm_scmi/Makefile | 1 +
drivers/firmware/arm_scmi/vendors/qcom/Kconfig | 15 +
drivers/firmware/arm_scmi/vendors/qcom/Makefile | 2 +
.../arm_scmi/vendors/qcom/qcom-generic-ext.c | 153 +++++
.../arm_scmi/vendors/qcom/qcom_generic.rst | 647 +++++++++++++++++++++
include/linux/devfreq-governor.h | 8 +
include/linux/devfreq.h | 1 +
include/linux/scmi_qcom_protocol.h | 37 ++
27 files changed, 2266 insertions(+), 1 deletion(-)
---
base-commit: 49e02880ec0a8c378e811bc9d85da188d7c6204c
change-id: 20260610-rfc_v7_scmi_memlat-3d3d0c0896d4
Best regards,
--
Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com>
^ permalink raw reply
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