* RE: [PATCH 5/7] soc: aspeed: Add eSPI flash channel support
From: YH Chung @ 2026-06-29 8:10 UTC (permalink / raw)
To: Markus Elfring, linux-aspeed@lists.ozlabs.org,
openbmc@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, Andrew Jeffery, Conor Dooley,
Joel Stanley, Krzysztof Kozlowski, Philipp Zabel, Rob Herring,
Ryan Chen
Cc: LKML, Maciej Lawniczak
In-Reply-To: <e78c2122-d10b-41ce-af94-45f573306c43@web.de>
Hi Markus,
> > +++ b/drivers/soc/aspeed/espi/aspeed-espi-comm.h
> > @@ -0,0 +1,62 @@
> …
> > +/*
> > + * eSPI cycle type encoding
> > + *
> > + * Section 5.1 Cycle Types and Packet Format,
> > + * Intel eSPI Interface Base Specification, Rev 1.0, Jan. 2016.
> > + */
> > +#define ESPI_FLASH_READ 0x00
> > +#define ESPI_FLASH_WRITE 0x01
> > +#define ESPI_FLASH_ERASE 0x02
> …
>
> How do you think about to use an enumeration for such data?
> https://en.wikipedia.org/wiki/Enumerated_type#C_and_syntactically_similar_lan
> guages
Thanks for the feedback. Yes, these values are related cycle type encodings,
so using an enum makes sense. I will update them, as well as other
specification-defined encodings, to enums in the next revision, while still
using fixed-width types such as `u8` for the actual packet/register fields.
Thanks,
Yun-Hsuan
^ permalink raw reply
* RE: [PATCH] misc: xilinx_sdfec: validate LDPC code register offsets
From: Cvetic, Dragan @ 2026-06-29 8:14 UTC (permalink / raw)
To: Yousef Alhouseen, Kiernan, Derek
Cc: Arnd Bergmann, Greg Kroah-Hartman, Simek, Michal,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20260624190812.3075-1-alhouseenyousef@gmail.com>
AMD General
> -----Original Message-----
> From: Yousef Alhouseen <alhouseenyousef@gmail.com>
> Sent: Wednesday 24 June 2026 20:08
> To: Kiernan, Derek <derek.kiernan@amd.com>; Cvetic, Dragan
> <dragan.cvetic@amd.com>
> Cc: Arnd Bergmann <arnd@arndb.de>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Simek, Michal <michal.simek@amd.com>;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Yousef
> Alhouseen <alhouseenyousef@gmail.com>
> Subject: [PATCH] misc: xilinx_sdfec: validate LDPC code register offsets
>
> The LDPC code register helpers check the target MMIO address after adding
> code_id * XSDFEC_LDPC_REG_JUMP to the register base. code_id is supplied
> through the ioctl path, so the multiplication and addition can wrap before
> the bounds check.
>
> Validate the code_id against the register window size before computing
> the final address, then write using the checked address.
>
> Signed-off-by: Yousef Alhouseen <alhouseenyousef@gmail.com>
> ---
> drivers/misc/xilinx_sdfec.c | 72 +++++++++++++++++--------------------
> 1 file changed, 32 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c
> index 3135ba3a5..63f0eb2bd 100644
> --- a/drivers/misc/xilinx_sdfec.c
> +++ b/drivers/misc/xilinx_sdfec.c
> @@ -456,10 +456,23 @@ static int xsdfec_get_turbo(struct xsdfec_dev
> *xsdfec, void __user *arg)
> return err;
> }
>
> +static int xsdfec_ldpc_reg_addr(struct xsdfec_dev *xsdfec, u32 base, u32
> high,
> + u32 offset, u32 *addr)
> +{
> + if (offset > (high - base) / XSDFEC_LDPC_REG_JUMP) {
If someone accidentally passes swapped high, base constants in the future, this underflows because they're unsigned.
Check if (high-base) >=0
> + dev_dbg(xsdfec->dev, "Writing outside of LDPC register
> space");
> + return -EINVAL;
> + }
> +
> + *addr = base + offset * XSDFEC_LDPC_REG_JUMP;
> + return 0;
> +}
> +
> static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32
> psize,
> u32 offset)
> {
> u32 wdata;
> + u32 addr;
>
> if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX || psize ==
> 0 ||
> (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0))
> {
> @@ -476,17 +489,11 @@ static int xsdfec_reg0_write(struct xsdfec_dev
> *xsdfec, u32 n, u32 k, u32 psize,
> k = k << XSDFEC_REG0_K_LSB;
> wdata = k | n;
>
> - if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset *
> XSDFEC_LDPC_REG_JUMP) >
> - XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
> - dev_dbg(xsdfec->dev, "Writing outside of LDPC reg0 space
> 0x%x",
> - XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP));
> + if (xsdfec_ldpc_reg_addr(xsdfec,
> XSDFEC_LDPC_CODE_REG0_ADDR_BASE,
> + XSDFEC_LDPC_CODE_REG0_ADDR_HIGH,
> offset,
> + &addr))
Put debug message, previous code had debug message.
> return -EINVAL;
> - }
> - xsdfec_regwrite(xsdfec,
> - XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP),
> - wdata);
> + xsdfec_regwrite(xsdfec, addr, wdata);
> return 0;
> }
>
> @@ -494,6 +501,7 @@ static int xsdfec_reg1_write(struct xsdfec_dev
> *xsdfec, u32 psize,
> u32 no_packing, u32 nm, u32 offset)
> {
> u32 wdata;
> + u32 addr;
>
> if (psize < XSDFEC_REG1_PSIZE_MIN || psize >
> XSDFEC_REG1_PSIZE_MAX) {
> dev_dbg(xsdfec->dev, "Psize is not in range");
> @@ -510,17 +518,11 @@ static int xsdfec_reg1_write(struct xsdfec_dev
> *xsdfec, u32 psize,
> nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;
>
> wdata = nm | no_packing | psize;
> - if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset *
> XSDFEC_LDPC_REG_JUMP) >
> - XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
> - dev_dbg(xsdfec->dev, "Writing outside of LDPC reg1 space
> 0x%x",
> - XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP));
> + if (xsdfec_ldpc_reg_addr(xsdfec,
> XSDFEC_LDPC_CODE_REG1_ADDR_BASE,
> + XSDFEC_LDPC_CODE_REG1_ADDR_HIGH,
> offset,
> + &addr))
Put debug message, previous code had debug message.
> return -EINVAL;
> - }
> - xsdfec_regwrite(xsdfec,
> - XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP),
> - wdata);
> + xsdfec_regwrite(xsdfec, addr, wdata);
> return 0;
> }
>
> @@ -529,6 +531,7 @@ static int xsdfec_reg2_write(struct xsdfec_dev
> *xsdfec, u32 nlayers, u32 nmqc,
> u32 max_schedule, u32 offset)
> {
> u32 wdata;
> + u32 addr;
>
> if (nlayers < XSDFEC_REG2_NLAYERS_MIN ||
> nlayers > XSDFEC_REG2_NLAYERS_MAX) {
> @@ -563,17 +566,11 @@ static int xsdfec_reg2_write(struct xsdfec_dev
> *xsdfec, u32 nlayers, u32 nmqc,
> wdata = (max_schedule | no_final_parity | special_qc | norm_type |
> nmqc | nlayers);
>
> - if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset *
> XSDFEC_LDPC_REG_JUMP) >
> - XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
> - dev_dbg(xsdfec->dev, "Writing outside of LDPC reg2 space
> 0x%x",
> - XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP));
> + if (xsdfec_ldpc_reg_addr(xsdfec,
> XSDFEC_LDPC_CODE_REG2_ADDR_BASE,
> + XSDFEC_LDPC_CODE_REG2_ADDR_HIGH,
> offset,
> + &addr))
Put debug message, previous code had debug message.
> return -EINVAL;
> - }
> - xsdfec_regwrite(xsdfec,
> - XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP),
> - wdata);
> + xsdfec_regwrite(xsdfec, addr, wdata);
> return 0;
> }
>
> @@ -581,20 +578,15 @@ static int xsdfec_reg3_write(struct xsdfec_dev
> *xsdfec, u8 sc_off, u8 la_off,
> u16 qc_off, u32 offset)
> {
> u32 wdata;
> + u32 addr;
>
> wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
> (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
> - if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset *
> XSDFEC_LDPC_REG_JUMP) >
> - XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
> - dev_dbg(xsdfec->dev, "Writing outside of LDPC reg3 space
> 0x%x",
> - XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP));
> + if (xsdfec_ldpc_reg_addr(xsdfec,
> XSDFEC_LDPC_CODE_REG3_ADDR_BASE,
> + XSDFEC_LDPC_CODE_REG3_ADDR_HIGH,
> offset,
> + &addr))
Put debug message, previous code had debug message.
> return -EINVAL;
> - }
> - xsdfec_regwrite(xsdfec,
> - XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
> - (offset * XSDFEC_LDPC_REG_JUMP),
> - wdata);
> + xsdfec_regwrite(xsdfec, addr, wdata);
> return 0;
> }
>
> --
> 2.54.0
Dragan
Regards
^ permalink raw reply
* RE: [PATCH 5/7] soc: aspeed: Add eSPI flash channel support
From: YH Chung @ 2026-06-29 8:15 UTC (permalink / raw)
To: Markus Elfring, linux-aspeed@lists.ozlabs.org,
openbmc@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, Andrew Jeffery, Conor Dooley,
Joel Stanley, Krzysztof Kozlowski, Philipp Zabel, Rob Herring,
Ryan Chen
Cc: LKML, Maciej Lawniczak
In-Reply-To: <3ab543eb-ca09-4d75-b75c-b8a4c71b2173@web.de>
Hi Markus,
> > +++ b/drivers/soc/aspeed/espi/aspeed-espi.c
> …
> > +static void aspeed_espi_flash_rx_work(struct work_struct *work) {
> > + struct aspeed_espi_flash *flash = container_of(work, struct
> aspeed_espi_flash, rx_work);
> > + struct aspeed_espi *espi = container_of(flash, struct aspeed_espi,
> > +flash);
> > +
> > + mutex_lock(&flash->tx_mtx);
> > + aspeed_espi_flash_handle_lun(espi);
> > + mutex_unlock(&flash->tx_mtx);
> > +}
> …
>
> Under which circumstances would you become interested to apply a statement
> like “guard(mutex)(&flash->tx_mtx);”?
> https://elixir.bootlin.com/linux/v7.1.1/source/include/linux/mutex.h#L253
>
Thanks for the suggestion. I agree that guard(mutex) is helpful when a locked
section has multiple exit paths. Since this worker currently has a single
simple path, I would prefer to keep the explicit mutex_lock()/mutex_unlock()
pair for readability. I can switch to guard(mutex) if you think it would be
better in this case.
Thanks,
Yun Hsuan
^ permalink raw reply
* Re: [PATCH v4 00/31] Introduce SCMI Telemetry FS support
From: Christian Brauner @ 2026-06-29 8:22 UTC (permalink / raw)
To: David Hildenbrand (Arm)
Cc: Cristian Marussi, Christian Brauner, linux-kernel,
linux-arm-kernel, arm-scmi, linux-fsdevel, linux-doc,
sudeep.holla, james.quinlan, f.fainelli, vincent.guittot,
etienne.carriere, peng.fan, michal.simek, d-gole, jic23,
elif.topuz, lukasz.luba, philip.radford, souvik.chakravarty,
leitao, kas, puranjay, usama.arif, kernel-team
In-Reply-To: <eba18827-5ef5-464c-90f0-2444a996acac@kernel.org>
> > Thanks a lot, David !
>
> Let's hope for some guidance regarding the FS side soon.
>
> But yeah, avoiding the in-kernel FS sounds completely reasonable at this point.
Afaiu, David wanted me to add a few comments on the viability of a
character device for this.
I think you usually have at least the following options:
(1) character device
(2) notification pipe
(3) netlink
(4) well-known AF_UNIX socket
You then need to consider your constraints. David added a few:
(i) root can set properties (enable/disable events)
(ii) non-root can only retrieve properties/events
I assume you mean real root, i.e., root on the host system or more
specifically anyone with CAP_SYS_ADMIN or some other relevant
capability.
This is a rather simple model and gets a lot of head-scratching out of
the way.
But root could also mean "root in a users namespace" which makes this
more complicated as it effectively means that an unprivileged container
would be enable/disable events. This makes sense if there's a subset of
events that naturally lends itself to be charged to a container and that
the container might have a genuine use for.
This touches on another design question which decides how complicated
the whole implementation is going to be: What consumer-producer
relationship does this need?
The process subscribing to the telemetry stream might have exclusive
access. IOW, once you have subscribed to the telemetry stream the
connect is busy and no new subscribers are allowed. This is a very
simple model ofc which has advantages.
On the other end you have the uevent model. Uevents are broadcast to all
subscribers who have a uevent netlink socket open (glossing over some
namespacing details that are irrelevant here).
You need to figure out what you really need here. The choice of
transport also has quality of life implications.
(1):
A character device is somewhat simple but it means it's all inherently
tied to devtmpfs and namespacing it retroactively is not possible. If
you ever want to namespace it, i.e., delegate it to unprivileged
sandboxes, userspace needs to bind-mount the character device into the
container at container startup or have a mechanism to inject said
character devices later via the new mount api. It's all possible I'm
just pointing out that you're tied to a rather rigid kernel object. But
I think in general it is ok.
(2):
A while ago David Howells extended pipes with the concept of a
watchqueue. A watchqueue is just a pipe with some special properties. It
can be created by passing O_NOTIFICATION to pipe(2) "meticulously
undocumented" as Jon would say...) into which the kernel splices small,
fixed-format notification records:
int fds[2];
pipe2(fds, O_NOTIFICATION_PIPE);
ioctl(fds[0], IOC_WATCH_QUEUE_SET_SIZE, nr_notes); /* preallocate, 1..512 */
ioctl(fds[0], IOC_WATCH_QUEUE_SET_FILTER, &filter); /* optional */
keyctl(KEYCTL_WATCH_KEY, KEY_SPEC_SESSION_KEYRING, fds[0], 0x01); /* subscribe a source */
If the ring is full or no free note exists, the record is dropped and
PIPE_BUF_FLAG_LOSS is set on the last buffer. So consumers always learn
that they missed something — but not what.
IOC_WATCH_QUEUE_SET_FILTER takes struct watch_notification_filter with
up to 16 watch_notification_type_filter entries. With a filter installed
the default is reject and only the type bit + subtype bit + info match
let a record through. Passing NULL removes all filters (everything
passes).
Kinda like a ringbuffer might be something to consider.
O_NOTIFICATION_PIPE works from all contexts (hence the preallocation).
(3):
No.
(4):
A while ago I added the "coredump socket" to the kernel. Basically,
userspace listens on a well-known AF_UNIX socket address (in this case
configured via /proc/sys/kernel/core_pattern). The kernel connects to it
and sends the coredump data via this socket (with some protocol
negotiation at the beginning).
If you really want to transform the data stream you're receiving into a
FUSE filesystem I think any of the referenced methods is compatible with
that. You just refresh the various files when new events come in and
otherwise show the data that you already have.
In other words, if you allow multiple consumers the following scenario
may happen: Consumer A consumes event E_1 and consumer B consumes E_2,
consumer A now gets E_3. If consumer A is what funnels the data into a
filesystem then consumer A misses data. That might be fine or might not
be.
^ permalink raw reply
* [PATCH v26 1/7] Documentation/firmware: add imx/se to other_interfaces
From: pankaj.gupta @ 2026-06-29 12:21 UTC (permalink / raw)
To: Jonathan Corbet, Shuah Khan, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Pankaj Gupta
Cc: linux-doc, linux-kernel, devicetree, imx, linux-arm-kernel
In-Reply-To: <20260629-imx-se-if-v26-0-146446285744@nxp.com>
From: Pankaj Gupta <pankaj.gupta@nxp.com>
Documents i.MX SoC's Service layer and C_DEV driver for selected SoC(s)
that contains the NXP hardware IP(s) for Secure Enclaves(se) like:
- NXP EdgeLock Enclave on i.MX93 & i.MX8ULP
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../driver-api/firmware/other_interfaces.rst | 133 +++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/Documentation/driver-api/firmware/other_interfaces.rst b/Documentation/driver-api/firmware/other_interfaces.rst
index 06ac89adaafb..6c6fa9a0ba1d 100644
--- a/Documentation/driver-api/firmware/other_interfaces.rst
+++ b/Documentation/driver-api/firmware/other_interfaces.rst
@@ -49,3 +49,136 @@ of the requests on to a secure monitor (EL3).
.. kernel-doc:: drivers/firmware/stratix10-svc.c
:export:
+
+NXP Secure Enclave Firmware Interface
+=====================================
+
+Introduction
+------------
+The NXP's i.MX HW IP like EdgeLock Enclave, V2X etc., creates an embedded secure
+enclave within the SoC boundary to enable features like:
+
+- Hardware Security Module (HSM)
+- Security Hardware Extension (SHE)
+- Vehicular to Anything (V2X)
+
+Each of the above features is enabled through dedicated NXP H/W IP on the SoC.
+On a single SoC, multiple hardware IP (or can say more than one secure enclave)
+can exist.
+
+NXP SoCs enabled with the such secure enclaves(SEs) IPs are:
+i.MX93, i.MX8ULP
+
+To communicate with one or more co-existing SE(s) on SoC, there is/are dedicated
+messaging units(MU) per SE. Each co-existing SE can have one or multiple exclusive
+MUs, dedicated to itself. None of the MU is shared between two SEs. Communication
+of the MU is realized using the mailbox driver. Each secure enclave can cater to
+multiple clients by virtue of these exclusive MUs. Also, they can distinguish
+transactions originating from these clients based on the MU used and core security
+state. The communication between the clients and secure enclaves is in the form of
+a command/response mechanism. Each client could expose a specific set of secure enclave
+features to the higher layers, based on the commands supported by that client. For
+example, the secure enclave could simultaneously support an OPTEE TA and Linux
+middleware as clients. Each of these clients can expose a specific set of secure
+enclave features based on the command set supported by them.
+
+NXP Secure Enclave(SE) Interface
+--------------------------------
+MU(s) is/are not shared between SE(s). But for an SoC like i.MX95 which has
+multiple SE(s) like HSM, V2X-HSM, V2X-SHE, all the SE(s) and their interfaces 'se-if'
+that is/are dedicated to a particular SE will be enumerated and provisioned using the
+single compatible node("fsl,imx95-se").
+
+Each 'se-if' comprises two layers:
+
+- (C_DEV Layer) User-Space software-access interface.
+- (Service Layer) OS-level software-access interface.
+
+::
+
+ +--------------------------------------------+
+ | Character Device(C_DEV) |
+ | |
+ | +---------+ +---------+ +---------+ |
+ | | misc #1 | | misc #2 | ... | misc #n | |
+ | | dev | | dev | | dev | |
+ | +---------+ +---------+ +---------+ |
+ | +-------------------------+ |
+ | | Misc. Dev Synchr. Logic | |
+ | +-------------------------+ |
+ | |
+ +--------------------------------------------+
+
+ +--------------------------------------------+
+ | Service Layer |
+ | |
+ | +-----------------------------+ |
+ | | Message Serialization Logic | |
+ | +-----------------------------+ |
+ | +---------------+ |
+ | | imx-mailbox | |
+ | | mailbox.c | |
+ | +---------------+ |
+ | |
+ +--------------------------------------------+
+
+- service layer:
+ This layer is responsible for ensuring the communication protocol that is defined
+ for communication with firmware.
+
+ FW Communication protocol ensures two things:
+
+ - Serializing the messages to be sent over an MU.
+ - FW can handle one command message at a time.
+
+- c_dev:
+ This layer offers character device contexts, created as '/dev/<se>_mux_chx'.
+ Using these multiple device contexts that are multiplexed over a single MU,
+ userspace application(s) can call fops like write/read to send the command message,
+ and read back the command response message to/from Firmware.
+ fops like read & write use the above defined service layer API(s) to communicate with
+ Firmware.
+
+ Misc-device(/dev/<se>_mux_chn) synchronization protocol::
+
+ Non-Secure + Secure
+ |
+ |
+ +-----------+ +-------------+ |
+ | se_ctrl.c +<---->+imx-mailbox.c| |
+ | | | mailbox.c +<-->+------+ +------+
+ +-----+-----+ +-------------+ | MU X +<-->+ ELE |
+ | +------+ +------+
+ +----------------+ |
+ | | |
+ v v |
+ logical logical |
+ receiver waiter |
+ + + |
+ | | |
+ | | |
+ | +----+------+ |
+ | | | |
+ | | | |
+ device_ctx device_ctx device_ctx |
+ |
+ User 0 User 1 User Y |
+ +------+ +------+ +------+ |
+ |misc.c| |misc.c| |misc.c| |
+ kernel space +------+ +------+ +------+ |
+ |
+ +---------------------------------------------------- |
+ | | | |
+ userspace /dev/ele_muXch0 | | |
+ /dev/ele_muXch1 | |
+ /dev/ele_muXchY |
+ |
+
+When a user sends a command to the firmware, it registers its device_ctx
+as waiter of a response from firmware.
+
+Enclave's Firmware owns the storage management over a Linux filesystem.
+For this c_dev provisions a dedicated slave device called "receiver".
+
+.. kernel-doc:: drivers/firmware/imx/se_ctrl.c
+ :export:
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v15 1/9] drm/bridge: Implement generic USB Type-C DP HPD bridge
From: Xu Yang @ 2026-06-29 8:26 UTC (permalink / raw)
To: Chaoyi Chen
Cc: Heikki Krogerus, Chaoyi Chen, Greg Kroah-Hartman,
Dmitry Baryshkov, Peter Chen, Luca Ceresoli, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang, Andy Yan,
Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker, linux-usb,
devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel
In-Reply-To: <56c6abb8-c127-449f-9368-12f94620c2bc@rock-chips.com>
On Mon, Jun 29, 2026 at 09:29:08AM +0800, Chaoyi Chen wrote:
> Hello Xu Yang,
>
> On 6/26/2026 7:15 PM, Xu Yang wrote:
> > On Wed, Mar 04, 2026 at 05:41:44PM +0800, Chaoyi Chen wrote:
> >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> >>
> >> The HPD function of Type-C DP is implemented through
> >> drm_connector_oob_hotplug_event(). For embedded DP, it is required
> >> that the DRM connector fwnode corresponds to the Type-C port fwnode.
> >>
> >> To describe the relationship between the DP controller and the Type-C
> >> port device, we usually using drm_bridge to build a bridge chain.
> >>
> >> Now several USB-C controller drivers have already implemented the DP
> >> HPD bridge function provided by aux-hpd-bridge.c, it will build a DP
> >> HPD bridge on USB-C connector port device.
> >>
> >> But this requires the USB-C controller driver to manually register the
> >> HPD bridge. If the driver does not implement this feature, the bridge
> >> will not be create.
> >>
> >> So this patch implements a generic DP HPD bridge based on
> >> aux-hpd-bridge.c. It will monitor Type-C bus events, and when a
> >> Type-C port device containing the DP svid is registered, it will
> >> create an HPD bridge for it without the need for the USB-C controller
> >> driver to implement it.
> >>
> >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> >> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> >> ---
> >>
> >> (no changes since v14)
> >>
> >> Changes in v13:
> >> - Only register drm dp hpd bridge for typec port altmode device.
> >>
> >> (no changes since v12)
> >>
> >> Changes in v11:
> >> - Switch to using typec bus notifiers.
> >>
> >> (no changes since v10)
> >>
> >> Changes in v9:
> >> - Remove the exposed DRM_AUX_HPD_BRIDGE option, and select
> >> DRM_AUX_HPD_TYPEC_BRIDGE when it is available.
> >> - Add more commit comment about problem background.
> >>
> >> Changes in v8:
> >> - Merge generic DP HPD bridge into one module.
> >> ---
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 10 ++++
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> .../gpu/drm/bridge/aux-hpd-typec-dp-bridge.c | 49 +++++++++++++++++++
> >> 3 files changed, 60 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/aux-hpd-typec-dp-bridge.c
> >>
> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> >> index a250afd8d662..559487aa09a9 100644
> >> --- a/drivers/gpu/drm/bridge/Kconfig
> >> +++ b/drivers/gpu/drm/bridge/Kconfig
> >> @@ -30,6 +30,16 @@ config DRM_AUX_HPD_BRIDGE
> >> Simple bridge that terminates the bridge chain and provides HPD
> >> support.
> >>
> >> +if DRM_AUX_HPD_BRIDGE
> >> +config DRM_AUX_HPD_TYPEC_BRIDGE
> >> + tristate
> >> + depends on TYPEC || !TYPEC
> >> + default TYPEC
> >> + help
> >> + Simple bridge that terminates the bridge chain and provides HPD
> >> + support. It build bridge on each USB-C connector device node.
> >> +endif
> >> +
> >
> > Should CONFIG_TYPEC_DP_ALTMODE select this one? Otherwise, we need to do it
> > manually.
> >
> > $ grep -nr --include=Kconfig "select DRM_AUX_HPD_BRIDGE" .
> > ./drivers/soc/qcom/Kconfig:118: select DRM_AUX_HPD_BRIDGE
> > ./drivers/usb/typec/ucsi/Kconfig:88: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/ucsi/Kconfig:99: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/tcpm/Kconfig:62: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/tcpm/Kconfig:85: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> >
>
> That's a fair point. But based on the previous discussion, Heikki
> point out that configurations in the TYPEC subsystem should not
> select configurations from DRM.
I have just reviewed your previous patchsets but I did't find such opinion from
Heikki. Otherwise, why are tcpm.c/ucsi.c already allowed to add the above select
condition in their configs?
I think Heikki means that the DRM_AUX_HPD_BRIDGE shouldn't been selected at the
top level of Type-C subsystem. Because not all Type-C devices support the DP function.
As a generic Type-C DP HPD bridge, displayport.c will likely need to use it in
the future. Therefore, allowing displayport.c to select DRM_AUX_HPD_BRIDGE makes sense.
According to my testing, it's impossible to build this driver in unless TYPEC_FUSB302
or a relevant CONFIG is built in to select DRM_AUX_HPD_BRIDGE, or the defconfig is modified.
Thanks,
Xu Yang
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: arm: rockchip: Add Graperain G3568 series
From: Coia Prant @ 2026-06-29 8:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Dragan Simic, Jonas Karlman, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
In-Reply-To: <20260629-fabulous-muskrat-of-romance-cd1bef@quoll>
On Mon, Jun 29, 2026 at 03:12:XXPM +0800, Krzysztof Kozlowski wrote:
> On Sun, Jun 28, 2026 at 06:57:56AM +0800, Coia Prant wrote:
> > This documents Graperain G3568 v2 which is a development board based on RK3568 SoC.
>
> "Document"
>
> Please do not use "This commit/patch/change", but imperative mood. See
> longer explanation here:
> https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94
Thank you for pointing this out. I have revised the commit message to
use imperative mood and split the overlong line to stay within 75
characters.
> > This series also have an SBC series with the suffix "box".
> >
> > This board is development board series, not SBC series.
>
> Remember to also address Sashiko review.
Okay.
> > Link: ...
> > Signed-off-by: ...
> > ---
> > ...
> > +
>
> Looks like you just added bunch of format-patch and check-patch
> warnings...
I have re‑run checkpatch on the entire series and fixed all trailing
whitespace and other formatting issues. The patch set should now be
clean (except for a hardware‑list line in the third patch which I kept
intact for readability).
Apologies for the oversight – it was late night work.
I will send a v2 with all fixes shortly.
Best,
Coia
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins
From: Michal Simek @ 2026-06-29 8:33 UTC (permalink / raw)
To: linux-kernel, monstr, git
Cc: mikko.rapeli, Conor Dooley, Krzysztof Kozlowski, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/ZYNQ ARCHITECTURE
In-Reply-To: <e01c8e60e1d9ed68c347f1a3741f89149109d8b7.1780496388.git.michal.simek@amd.com>
On 6/3/26 16:19, Michal Simek wrote:
> Since commit 9c105255108b ("pinctrl: pinconf-generic: perform basic
> checks on pincfg properties"), the generic pinconf parser logs an error
> when a pin configuration node specifies more than one bias mode.
> Several ZynqMP boards described SDIO card-detect and write-protect pins
> with both bias-high-impedance and bias-pull-up, which triggers at
> pinctrl probe:
>
> generic pinconfig core: /firmware/zynqmp-firmware/pinctrl/.../conf-cd:
> cannot have multiple bias configurations
>
> On ZynqMP, bias-high-impedance enables tri-state while bias-pull-up
> enables the internal pull resistor; these are mutually exclusive bias
> settings and only pull-up is needed for CD/WP inputs. Drop the redundant
> bias-high-impedance property and keep bias-pull-up.
>
> Reported-by: Mikko Rapeli (Linaro) <mikko.rapeli@linaro.org>
> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221586
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 -
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 -
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ----
> arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 2 --
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 1 -
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 --
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 -
> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 1 -
> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 --
> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 -
> 10 files changed, 16 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index 923a70d750bf..44834bf1c19c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -374,7 +374,6 @@ conf {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 563e750b0e08..49732de5fa4b 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -365,7 +365,6 @@ conf {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> index 6aff22d43361..f57987dad50f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
> @@ -270,7 +270,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio0_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -283,7 +282,6 @@ mux-wp {
>
> conf-wp {
> groups = "sdio0_wp_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -310,7 +308,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -323,7 +320,6 @@ mux-wp {
>
> conf-wp {
> groups = "sdio1_wp_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> index 53aa3dca1dca..737d445dc16b 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
> @@ -270,7 +270,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio0_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -283,7 +282,6 @@ mux-wp {
>
> conf-wp {
> groups = "sdio0_wp_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> index 4ec8a400494e..41f312a82bb4 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -320,7 +320,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio0_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> index e172a30e7b21..a5bc521ab679 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -896,7 +896,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -909,7 +908,6 @@ mux-wp {
>
> conf-wp {
> groups = "sdio1_wp_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> index fe8f151ed706..32509083e54f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
> @@ -359,7 +359,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> index 3ee8ab224722..96699be8430f 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
> @@ -371,7 +371,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index 7f6c87d4d77e..52441e5c8739 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -895,7 +895,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> @@ -908,7 +907,6 @@ mux-wp {
>
> conf-wp {
> groups = "sdio1_wp_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> index 428b5558fbba..b34e4c93d249 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
> @@ -750,7 +750,6 @@ mux-cd {
>
> conf-cd {
> groups = "sdio1_cd_0_grp";
> - bias-high-impedance;
> bias-pull-up;
> slew-rate = <SLEW_RATE_SLOW>;
> power-source = <IO_STANDARD_LVCMOS18>;
Applied.
M
^ permalink raw reply
* Re: [PATCH] ARM: enable interrupts when arm_notify_die() is handling user mode errors
From: Xie Yuanbin @ 2026-06-29 8:31 UTC (permalink / raw)
To: bigeasy, linux, rmk+kernel
Cc: arnd, clrkwllms, liaohua4, lilinjie8, linusw, linux-arm-kernel,
linux-kernel, linux-rt-devel, rostedt, xieyuanbin1
In-Reply-To: <20260629075726.McX9yWi1@linutronix.de>
On Mon, 29 Jun 2026 09:57:26 +0200, Sebastian Andrzej Siewior wrote:
> In oops_enter() not only interrupts are disabled but also the emergency
> mode of the console is enabled. That means all console output is written
> via the atomic_write interface to the console as it the output happens.
> At this point, your real-time guarantees are gone. There is no need to
> worry about anything here since everything is lost.
>
> Restricting it to user context is reasonable: Here you kill the task and
> need enabled interrupts in order to send the signal.
> For kernel threads it is not needed because the "printing" happens with
> disabled interrupts anyway and without any buffering. Should this event
> not end with panic() then it will kill the kernel thread and enable
> interrupts before doing so.
Thanks. So, can I take it that you agree with the first one?
On Thu, 25 Jun 2026 20:26:12 +0800, Xie Yuanbin wrote:
> ```c
> if (!inf->fn(addr, ifsr | FSR_LNX_PF, regs))
> return;
>
> if (likely(user_mode(regs)))
> local_irq_enable();
>
> pr_alert("8<--- cut here ---\n");
> ```
> or
> ```c
> if (!inf->fn(addr, ifsr | FSR_LNX_PF, regs))
> return;
>
> if (likely(interrupts_enabled(regs)))
> local_irq_enable();
>
> pr_alert("8<--- cut here ---\n");
> ```
^ permalink raw reply
* RE: [External Mail] Re: [PATCH v3 2/7] net: wwan: t9xx: Add control plane transaction layer
From: Wu. JackBB (GSM) @ 2026-06-29 7:26 UTC (permalink / raw)
To: Andrew Lunn
Cc: Loic Poulain, Sergey Ryazanov, Johannes Berg, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Wen-Zhi Huang, Shi-Wei Yeh, Minano Tseng, Matthias Brugger,
AngeloGioacchino Del Regno, Simon Horman, Jonathan Corbet,
Shuah Khan, linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org
In-Reply-To: <2a90ae6b-2b6d-4340-b557-915252cc3488@lunn.ch>
Hi Andrew,
> > +static int __init mtk_common_drv_init(void)
> > +{
> > + return 0;
> > +}
> > +module_init(mtk_common_drv_init);
> > +
> > +static void __exit mtk_common_drv_exit(void)
> > +{
> > +}
> > +module_exit(mtk_common_drv_exit);
>
> Since these don't do anything, they should not be needed.
Will move module_init/module_exit to the patch that first adds
content to them in v4.
> > + SET_HW_BITS(hw_bits, chs, MHCCIF_RC2EP_EVT_DEVICE_RESET,
> > + DEV_EVT_H2D_DEVICE_RESET);
> > +
> > + return LE32_TO_U32(cpu_to_le32(hw_bits));
>
> Please don't add white space like this. I assume a previous patch
> added this code, so move this to that patch.
Will remove the extra blank line in v4.
> > - devm_kfree(dev, mdev);
> > + mtk_dev_free(mdev);
>
> Why are you removing devm_ calls?
mtk_dev_alloc/mtk_dev_free are paired wrappers so the caller
doesn't need to know the underlying allocation mechanism.
The devm_kfree is still called inside mtk_dev_free.
Thanks.
Jack Wu.
^ permalink raw reply
* Re: [PATCH v6 1/9] media: mc-entity: Store parsed V4L2 fwnode endpoint in media_pad
From: Laurent Pinchart @ 2026-06-29 8:45 UTC (permalink / raw)
To: Sakari Ailus
Cc: Frank Li, Hans Verkuil, Mauro Carvalho Chehab, Michael Riesch,
Martin Kepplinger-Novakovic, Rui Miguel Silva, Purism Kernel Team,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-media, linux-kernel,
imx, Guoniu Zhou, devicetree, linux-arm-kernel
In-Reply-To: <akGD3ZjW6GPHHI3D@kekkonen.localdomain>
On Sun, Jun 28, 2026 at 11:28:13PM +0300, Sakari Ailus wrote:
> On Wed, Jun 24, 2026 at 04:37:48PM -0400, Frank.Li@oss.nxp.com wrote:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > Each media pad is associated with a firmware node endpoint. Capture the
> > parsed V4L2 fwnode endpoint information in struct media_pad so it can be
> > reused by consumers.
> >
> > This avoids reparsing firmware node endpoint data every time the endpoint
> > configuration is needed, reduces duplicate code, and provides a common
> > place to store endpoint properties associated with a pad.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > Assume 1 to 1 map between dt's endpoint to medie pad.
> > Change in v6
> > - new patch
> > ---
> > include/media/media-entity.h | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/media/media-entity.h b/include/media/media-entity.h
> > index d9b72cd87d524..4a3785cd9f370 100644
> > --- a/include/media/media-entity.h
> > +++ b/include/media/media-entity.h
> > @@ -20,6 +20,8 @@
> > #include <linux/minmax.h>
> > #include <linux/types.h>
> >
> > +#include <media/v4l2-fwnode.h>
>
> We have dependencies from V4L2 to MC but not the other way around as MC is
> (or was?) intended for wider use then just V4L2. I'm thus more than a bit
> hesitant adding any references to V4L2 in MC.
>
> I wonder what Hans and Laurent think.
I agree. Furthermore, this will significantly increase the size of the
media_pad structure, for all pads. That's not a good design.
> > +
> > /* Enums used internally at the media controller to represent graphs */
> >
> > /**
> > @@ -230,6 +232,7 @@ enum media_pad_signal_type {
> > * @flags: Pad flags, as defined in
> > * :ref:`include/uapi/linux/media.h <media_header>`
> > * (seek for ``MEDIA_PAD_FL_*``)
> > + * @vep: associated fwnode endpoint information
> > * @pipe: Pipeline this pad belongs to. Use media_entity_pipeline() to
> > * access this field.
> > */
> > @@ -240,7 +243,7 @@ struct media_pad {
> > u16 num_links;
> > enum media_pad_signal_type sig_type;
> > unsigned long flags;
> > -
> > + struct v4l2_fwnode_endpoint vep;
> > /*
> > * The fields below are private, and should only be accessed via
> > * appropriate functions.
> >
>
> --
> Regards,
>
> Sakari Ailus
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v6 3/9] media: subdev: Add media_async_register_subdev() helper
From: Laurent Pinchart @ 2026-06-29 8:46 UTC (permalink / raw)
To: Frank.Li
Cc: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch, Frank Li,
Martin Kepplinger-Novakovic, Rui Miguel Silva, Purism Kernel Team,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-media, linux-kernel,
imx, Guoniu Zhou, devicetree, linux-arm-kernel
In-Reply-To: <20260624-imx8qxp_pcam-v6-3-4b3f45920d2f@nxp.com>
On Wed, Jun 24, 2026 at 04:37:50PM -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Add media_async_register_subdev(), a helper to register a V4L2 sub-device
> with the asynchronous sub-device framework.
For the reason stated by Sakari in patch 1/9 (dependency from MC to
V4L2), I don't think a "media_async_register_subdev()" function is a
good idea.
> The helper assumes a 1:1 mapping between firmware endpoints and media pads.
> During registration it parses the firmware graph, creates media pads for
> all endpoints, and registers common asynchronous notifiers for sink
> endpoints. These notifiers automatically create media links when the
> corresponding remote source devices become available.
>
> The set_pad_by_ep() callback allows drivers to determine the media pad
> associated with a firmware endpoint and identify whether the endpoint
> represents a sink pad.
>
> By centralizing firmware graph parsing, media pad creation, notifier
> registration, and link creation, this helper reduces duplicated code and
> simplifies error handling in V4L2 sub-device drivers.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change in v6
> - new patch
> ---
> drivers/media/v4l2-core/v4l2-fwnode.c | 155 ++++++++++++++++++++++++++++++++++
> include/media/v4l2-async.h | 39 +++++++++
> 2 files changed, 194 insertions(+)
>
> diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
> index 62a3a452f7884..169059654478f 100644
> --- a/drivers/media/v4l2-core/v4l2-fwnode.c
> +++ b/drivers/media/v4l2-core/v4l2-fwnode.c
> @@ -26,6 +26,7 @@
>
> #include <media/v4l2-async.h>
> #include <media/v4l2-fwnode.h>
> +#include <media/v4l2-mc.h>
> #include <media/v4l2-subdev.h>
>
> #include "v4l2-subdev-priv.h"
> @@ -1302,6 +1303,160 @@ int __v4l2_async_register_subdev_sensor(struct v4l2_subdev *sd, struct module *m
> }
> EXPORT_SYMBOL_GPL(__v4l2_async_register_subdev_sensor);
>
> +static int v4l2_common_notifier_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *sd,
> + struct v4l2_async_connection *asd)
> +{
> + struct media_pad *pad = NULL;
> + int ret;
> +
> + if (asd->match.type != V4L2_ASYNC_MATCH_TYPE_FWNODE)
> + return -EINVAL;
> +
> + if (!asd->match.fwnode)
> + return -EINVAL;
> +
> + struct fwnode_handle *remote __free(fwnode_handle) =
> + fwnode_graph_get_remote_endpoint(asd->match.fwnode);
> +
> + for (int i = 0; i < notifier->sd->entity.num_pads; i++) {
> + if (notifier->sd->entity.pads[i].vep.base.local_fwnode == remote) {
> + pad = ¬ifier->sd->entity.pads[i];
> + break;
> + }
> + }
> +
> + if (!pad) {
> + dev_err(notifier->sd->dev, "failed to find sink pad\n");
> + return -EINVAL;
> + }
> +
> + ret = v4l2_create_fwnode_links_to_pad(sd, pad, MEDIA_LNK_FL_ENABLED);
> + if (ret) {
> + dev_err(sd->dev, "failed to link source pad\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct v4l2_async_notifier_operations v4l2_common_notifier_ops = {
> + .bound = v4l2_common_notifier_bound,
> +};
> +
> +static int
> +v4l2_async_nf_parse_fwnode(struct device *dev, struct media_pad *pads,
> + struct v4l2_async_notifier *notifier)
> +{
> + struct v4l2_subdev *sd = notifier->sd;
> + struct v4l2_async_connection *asd;
> + struct media_pad *pad;
> + int ret;
> +
> + if (!sd->internal_ops->set_pad_by_ep)
> + return dev_err_probe(dev, -EINVAL,
> + "Missed valiate_endpoint() callback\n");
> + pad = pads;
> +
> + fwnode_graph_for_each_endpoint_scoped(dev_fwnode(dev), ep) {
> + u32 flags;
> +
> + ret = v4l2_fwnode_endpoint_parse(ep, &pad->vep);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to parse endpoint\n");
> +
> + ret = sd->internal_ops->set_pad_by_ep(sd, pad);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Can support endponit\n");
> +
> + flags = pad->flags;
> +
> + pad++;
> +
> + if (flags & MEDIA_PAD_FL_SOURCE)
> + continue; /* Bypass source port */
> +
> + notifier->ops = &v4l2_common_notifier_ops;
> +
> + asd = v4l2_async_nf_add_fwnode_remote(notifier, ep,
> + struct v4l2_async_connection);
> + if (IS_ERR(asd))
> + return dev_err_probe(dev, PTR_ERR(asd),
> + "failed to add notifier\n");
> + }
> +
> + return 0;
> +}
> +
> +void media_async_subdev_cleanup(struct v4l2_subdev *sd)
> +{
> + v4l2_async_unregister_subdev(sd);
> + v4l2_subdev_cleanup(sd);
> + media_entity_cleanup(&sd->entity);
> + v4l2_async_nf_unregister(sd->subdev_notifier);
> + v4l2_async_nf_cleanup(sd->subdev_notifier);
> + kfree(sd->entity.pads);
> +}
> +EXPORT_SYMBOL_GPL(media_async_subdev_cleanup);
> +
> +int __media_async_register_subdev(struct v4l2_subdev *sd, struct module *module)
> +{
> + struct device *dev = sd->dev;
> + u32 ep_count;
> + int ret;
> +
> + if (WARN_ON(!sd->dev))
> + return -ENODEV;
> +
> + struct v4l2_async_notifier *notifier __free(kfree) = kzalloc_obj(*notifier);
> + if (!notifier)
> + return -ENOMEM;
> +
> + v4l2_async_subdev_nf_init(notifier, sd);
> +
> + ep_count = fwnode_graph_get_endpoint_count(dev_fwnode(dev), 0);
> + if (!ep_count)
> + return dev_err_probe(dev, -EINVAL, "No connected endpoints\n");
> +
> + struct media_pad *pads __free(kfree) = kzalloc_objs(struct media_pad, ep_count);
> + if (!pads)
> + return -ENOMEM;
> +
> + ret = v4l2_async_nf_parse_fwnode(dev, pads, notifier);
> + if (ret < 0)
> + return ret;
> +
> + ret = media_entity_pads_init(&sd->entity, ep_count, pads);
> + if (ret)
> + goto out_cleanup;
> +
> + ret = v4l2_async_nf_register(notifier);
> + if (ret < 0)
> + goto out_cleanup;
> +
> + ret = v4l2_subdev_init_finalize(sd);
> + if (ret)
> + goto out_unregister;
> +
> + ret = __v4l2_async_register_subdev(sd, module);
> + if (ret < 0)
> + goto out_unregister;
> +
> + sd->subdev_notifier = no_free_ptr(notifier);
> + retain_and_null_ptr(pads);
> +
> + return 0;
> +
> +out_unregister:
> + v4l2_async_nf_unregister(notifier);
> +
> +out_cleanup:
> + v4l2_async_nf_cleanup(notifier);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(__media_async_register_subdev);
> +
> MODULE_DESCRIPTION("V4L2 fwnode binding parsing library");
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
> diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h
> index 54a2d9620ed5b..ca41820f776c5 100644
> --- a/include/media/v4l2-async.h
> +++ b/include/media/v4l2-async.h
> @@ -345,4 +345,43 @@ __v4l2_async_register_subdev_sensor(struct v4l2_subdev *sd, struct module *modul
> * @sd: pointer to &struct v4l2_subdev
> */
> void v4l2_async_unregister_subdev(struct v4l2_subdev *sd);
> +
> +enum v4l2_subdev_1to1_pads {
> + V4L2_SUBDEV_1TO1_PADS_SINK,
> + V4L2_SUBDEV_1TO1_PADS_SOURCE,
> + V4L2_SUBDEV_1TO1_PADS_TOTAL,
> +};
> +
> +/**
> + * media_async_register_subdev - registers a sub-device to the asynchronous
> + * sub-device framework and parse set up common
> + * related devices
> + *
> + * @sd: pointer to struct &v4l2_subdev
> + *
> + * Register a V4L2 sub-device with the asynchronous sub-device framework.
> + * In addition to v4l2_async_register_subdev(), this function parses the
> + * firmware graph, creates media pads for the endpoints, and registers common
> + * notifiers to create media links between connected devices.
> + *
> + * This function also init media_pads.
> + *
> + * The sub-device is unregistered and cleanup by media_async_subdev_cleanup()
> + *
> + * While registered, the subdev module is marked as in-use.
> + *
> + * An error is returned if the module is no longer loaded on any attempts
> + * to register it.
> + */
> +#define media_async_register_subdev(sd_1to1) \
> + __media_async_register_subdev(sd_1to1, THIS_MODULE)
> +
> +int __media_async_register_subdev(struct v4l2_subdev *sd_1to1, struct module *module);
> +
> +/**
> + * media_async_subdev_cleanup - unregistered and cleanup subdev and media pads
> + * @sd_1to1: pointer to struct &v4l2_subdev_1to1
> + */
> +void media_async_subdev_cleanup(struct v4l2_subdev *sd_1to1);
> +
> #endif
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v3 4/8] arm64: dts: qcom: shikra: Add Adreno SMMU node
From: Konrad Dybcio @ 2026-06-29 8:46 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Imran Shaik,
Komal Bajaj
In-Reply-To: <20260628-shikra-gpu-v3-4-9b28a3b167e1@oss.qualcomm.com>
On 6/28/26 8:23 PM, Akhil P Oommen wrote:
> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> Add the Adreno GPU IOMMU (adreno_smmu) node for the Shikra SoC.
>
> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Drop the sign-offs that don't apply (presumably applied as part
of shuffling around the handlers of the patch in the in-flight
tree OR missing c-d-b)
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH rc v6 3/7] iommu/arm-smmu-v3: Do not enable EVTQ/PRIQ interrupts in kdump kernel
From: Pranjal Shrivastava @ 2026-06-29 8:48 UTC (permalink / raw)
To: Nicolin Chen
Cc: will, robin.murphy, jgg, joro, kees, baolu.lu, kevin.tian,
miko.lenczewski, smostafa, linux-arm-kernel, iommu, linux-kernel,
stable, jamien
In-Reply-To: <e643786d849d274c1d8dcfc03795f572aef812bd.1779265413.git.nicolinc@nvidia.com>
On Wed, May 20, 2026 at 10:03:20AM -0700, Nicolin Chen wrote:
> In kdump cases, the crashed kernel's CDs and page tables can be corrupted,
> which could trigger event spamming. Also, we cannot serve page requests.
>
> Skip the IRQ setup for EVTQ/PRIQ in arm_smmu_setup_irqs().
>
> Skip their IRQ handler registration in unique-IRQ and combined-IRQ cases.
>
> Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel")
> Cc: stable@vger.kernel.org # v6.12+
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 58 ++++++++++++++-------
> 1 file changed, 39 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 2d7eb42449eaf..e00b28e36f9c4 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -2464,7 +2464,11 @@ static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev)
>
> static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)
> {
> - arm_smmu_gerror_handler(irq, dev);
> + irqreturn_t ret = arm_smmu_gerror_handler(irq, dev);
> +
> + /* In kdump, EVTQ/PRIQ are disabled and there is no thread to wake */
> + if (is_kdump_kernel())
> + return ret;
> return IRQ_WAKE_THREAD;
> }
>
> @@ -4963,6 +4967,21 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
> arm_smmu_setup_msis(smmu);
>
> /* Request interrupt lines */
> + irq = smmu->gerr_irq;
> + if (irq) {
> + ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
> + 0, "arm-smmu-v3-gerror", smmu);
> + if (ret < 0)
> + dev_warn(smmu->dev, "failed to enable gerror irq\n");
> + } else {
> + dev_warn(smmu->dev,
> + "no gerr irq - errors will not be reported!\n");
> + }
> +
> + /* No EVTQ/PRIQ interrupts in kdump -- queues are disabled */
> + if (is_kdump_kernel())
> + return;
> +
> irq = smmu->evtq.q.irq;
> if (irq) {
> ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
> @@ -4975,16 +4994,6 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
> dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n");
> }
>
> - irq = smmu->gerr_irq;
> - if (irq) {
> - ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
> - 0, "arm-smmu-v3-gerror", smmu);
> - if (ret < 0)
> - dev_warn(smmu->dev, "failed to enable gerror irq\n");
> - } else {
> - dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n");
> - }
> -
> if (smmu->features & ARM_SMMU_FEAT_PRI) {
> irq = smmu->priq.q.irq;
> if (irq) {
> @@ -5005,7 +5014,7 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
> static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
> {
> int ret, irq;
> - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
> + u32 irqen_flags = IRQ_CTRL_GERROR_IRQEN;
>
> /* Disable IRQs first */
> ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
> @@ -5020,19 +5029,30 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
> /*
> * Cavium ThunderX2 implementation doesn't support unique irq
> * lines. Use a single irq line for all the SMMUv3 interrupts.
> + *
> + * In kdump, EVTQ/PRIQ are disabled, so no threaded handling.
> */
> - ret = devm_request_threaded_irq(smmu->dev, irq,
> - arm_smmu_combined_irq_handler,
> - arm_smmu_combined_irq_thread,
> - IRQF_ONESHOT,
> - "arm-smmu-v3-combined-irq", smmu);
> + if (is_kdump_kernel())
> + ret = devm_request_irq(smmu->dev, irq,
> + arm_smmu_combined_irq_handler, 0,
> + "arm-smmu-v3-combined-irq",
> + smmu);
This `if` isn't needed, we can continue using devm_request_threaded_irq,
if you look at the doc for devm_request_threaded_irq [1] it says:
/**
* devm_request_threaded_irq - allocate an interrupt line for a managed device with error logging
* @dev: Device to request interrupt for
* @irq: Interrupt line to allocate
* @handler: Function to be called when the interrupt occurs
* @thread_fn: Function to be called in a threaded interrupt context. NULL
* for devices which handle everything in @handler
* @irqflags: Interrupt type flags
* @devname: An ascii name for the claiming device, dev_name(dev) if NULL
* @dev_id: A cookie passed back to the handler function
[...]
*/
So, we can pass handler() here while leaving the thread_fn == NULL:
ret = devm_request_threaded_irq(smmu->dev, irq,
arm_smmu_combined_irq_handler,
is_kdump_kernel() ? NULL : arm_smmu_combined_irq_thread,
IRQF_ONESHOT,
"arm-smmu-v3-combined-irq", smmu);
(In fact that's exactly what devm_request_irq does under the hood [2])
Additionally, the arm_smmu_combined_irq_handler() returns
IRQ_WAKE_THREAD unconditionally, which causes us to hit the warn_on[3] in
__handle_irq_event_percpu.
Hence, we'd need to refactor the arm_smmu_combined_irq_handler() to
return IRQ_HANDLED / _NONE if is_kdump_kernel().
> + else
> + ret = devm_request_threaded_irq(
> + smmu->dev, irq, arm_smmu_combined_irq_handler,
> + arm_smmu_combined_irq_thread, IRQF_ONESHOT,
> + "arm-smmu-v3-combined-irq", smmu);
> if (ret < 0)
> dev_warn(smmu->dev, "failed to enable combined irq\n");
> } else
> arm_smmu_setup_unique_irqs(smmu);
>
> - if (smmu->features & ARM_SMMU_FEAT_PRI)
> - irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
> + /* No EVTQ/PRIQ IRQ generation in kdump -- queues are disabled */
> + if (!is_kdump_kernel()) {
> + irqen_flags |= IRQ_CTRL_EVTQ_IRQEN;
> + if (smmu->features & ARM_SMMU_FEAT_PRI)
> + irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
> + }
>
> /* Enable interrupt generation on the SMMU */
> ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
> --
> 2.43.0
>
Thanks,
Praan
[1] https://elixir.bootlin.com/linux/v7.1.1/source/kernel/irq/devres.c#L75
[2] https://elixir.bootlin.com/linux/v7.1.1/source/include/linux/interrupt.h#L218
[3] https://elixir.bootlin.com/linux/v7.1.1/source/kernel/irq/handle.c#L225
^ permalink raw reply
* Re: [5/7] soc: aspeed: Add eSPI flash channel support
From: Markus Elfring @ 2026-06-29 8:50 UTC (permalink / raw)
To: YH Chung, linux-aspeed, openbmc, linux-arm-kernel, devicetree,
Andrew Jeffery, Conor Dooley, Joel Stanley, Krzysztof Kozlowski,
Philipp Zabel, Rob Herring, Ryan Chen
Cc: LKML, Maciej Lawniczak
In-Reply-To: <KL1PR0601MB4276C2C831B257898AAB363190E82@KL1PR0601MB4276.apcprd06.prod.outlook.com>
…
>>> +++ b/drivers/soc/aspeed/espi/aspeed-espi.c
>> …
>>> +static void aspeed_espi_flash_rx_work(struct work_struct *work) {
…
> Thanks for the suggestion. I agree that guard(mutex) is helpful when a locked
> section has multiple exit paths. Since this worker currently has a single
> simple path, I would prefer to keep the explicit mutex_lock()/mutex_unlock()
> pair for readability. I can switch to guard(mutex) if you think it would be
> better in this case.
I hope that development interests can increase more also for the application of
scope-based resource management.
Regards,
Markus
^ permalink raw reply
* Re: [PATCH v3 5/8] arm64: dts: qcom: shikra: Add A704 GPU support
From: Konrad Dybcio @ 2026-06-29 8:53 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu,
Aditya Sherawat
In-Reply-To: <20260628-shikra-gpu-v3-5-9b28a3b167e1@oss.qualcomm.com>
On 6/28/26 8:23 PM, Akhil P Oommen wrote:
> From: Aditya Sherawat <asherawa@qti.qualcomm.com>
>
> Add the A704 GPU and GMU wrapper nodes with register maps, clocks,
> interconnects, IOMMU, OPP table and the zap-shader region.
>
> Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v7 1/7] optee: ffa: Add NULL check in optee_ffa_lend_protmem
From: Jens Wiklander @ 2026-06-29 8:53 UTC (permalink / raw)
To: Sebastian Ene
Cc: catalin.marinas, oupton, sudeep.holla, will, joey.gouly, kvmarm,
linux-arm-kernel, linux-kernel, android-kvm, maz,
mrigendra.chaubey, op-tee, perlarsen, seiden, smostafa,
sumit.garg, suzuki.poulose, vdonnefort, yuzenghui, Sumit Garg
In-Reply-To: <20260617145130.3729015-2-sebastianene@google.com>
Hi,
On Wed, Jun 17, 2026 at 4:51 PM Sebastian Ene <sebastianene@google.com> wrote:
>
> From: Mostafa Saleh <smostafa@google.com>
>
> From: Mostafa Saleh <smostafa@google.com>
>
> Sashiko (locally) reports a possible null dereference under memory
> pressure due to the lack of validation of the allocated pointer.
>
> Fix that by adding the missing check.
>
> Fixes: 2b78d79cdf96 ("optee: FF-A: dynamic protected memory allocation")
> Signed-off-by: Mostafa Saleh <smostafa@google.com>
> Signed-off-by: Sebastian Ene <sebastianene@google.com>
> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
> ---
> drivers/tee/optee/ffa_abi.c | 3 +++
> 1 file changed, 3 insertions(+)
I'm picking up this isolated patch from the patchset.
Cheers,
Jens
^ permalink raw reply
* RE: [External Mail] Re: [PATCH v3 1/7] net: wwan: t9xx: Add PCIe core
From: Wu. JackBB (GSM) @ 2026-06-29 7:05 UTC (permalink / raw)
To: Andrew Lunn
Cc: Loic Poulain, Sergey Ryazanov, Johannes Berg, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Wen-Zhi Huang, Shi-Wei Yeh, Minano Tseng, Matthias Brugger,
AngeloGioacchino Del Regno, Simon Horman, Jonathan Corbet,
Shuah Khan, linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org
In-Reply-To: <b6ee3440-385f-4567-993d-c10db6f10b97@lunn.ch>
Hi Andrew,
> > +#else /* !CONFIG_ACPI */
> > + dev_err((mdev)->dev, "Unsupported, CONFIG ACPI hasn't been set to 'y'\n");
>
> Why not just have the Kconfig depend on ACPI?
Will add "depends on ACPI" and remove the #ifdef blocks in v4.
> > + if (ret) {
> > + dev_err((mdev)->dev, "Failed to register mhccif_irq callback\n");
>
> Why the () around mdev?
Will remove the unnecessary parentheses from all occurrences in v4.
Thanks.
^ permalink raw reply
* [PATCH 1/2] arm64: dts: ti: k3-am642-tqma64xxl: add ospi0 vcc-supply
From: Nora Schiffer @ 2026-06-29 8:55 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
devicetree, linux-kernel, linux, Alexander Feilke, Nora Schiffer
From: Alexander Feilke <Alexander.Feilke@ew.tq-group.com>
Add missing vcc-supply to ospi0 flash.
Signed-off-by: Alexander Feilke <Alexander.Feilke@ew.tq-group.com>
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
index dde19d0784e31..fe4cb49934bef 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
@@ -106,6 +106,7 @@ flash@0 {
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <84000000>;
+ vcc-supply = <®_1v8>;
bootph-all;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v8 01/13] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present()
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In-Reply-To: <20260629090007.1718746-1-yeoreum.yun@arm.com>
According to Embedded Trace Macrocell Architecture Specification
ETMv4.0 to ETM4.6 [0], TRCSSPCICR<n> is present only if all of
the following are true:
- TRCIDR4.NUMSSCC > n.
- TRCIDR4.NUMPC > 0b0000.
- TRCSSCSR<n>.PC == 0b1.
Comment for etm4x_sspcicrn_present() is align with the specification.
However, the check should use drvdata->nr_pe_cmp to check TRCIDR4.NUMPC
not nr_pe.
Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Fixes: f6a18f354c58 ("coresight: etm4x: Handle access to TRCSSPCICRn")
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 14bb31bd6a0b..1e3b0344dc00 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -93,7 +93,7 @@ static int etm4_probe_cpu(unsigned int cpu);
static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
{
return (n < drvdata->nr_ss_cmp) &&
- drvdata->nr_pe &&
+ drvdata->nr_pe_cmp &&
(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
}
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related
* [PATCH v8 00/13] fix several inconsistencies with sysfs configuration in etmX
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
The current ETMx configuration via sysfs can lead to the following
inconsistencies:
- If a configuration is modified via sysfs while a perf session is
active, the running configuration may differ between before
a sched-out and after a subsequent sched-in.
- If a perf session and sysfs session tries to enable concurrently,
configuration from configfs could be corrupted (etm4).
- There is chance to corrupt drvdata->config if perf session tries
to enabled among handling cscfg_csdev_disable_active_config()
in etm4_disable_sysfs() (etm4).
To resolve these inconsistencies, the configuration should be separated into:
- active_config, which is applied configuration for the current session
- config, which stores the settings configured via sysfs.
and apply configuration from configfs after taking a mode.
Also, This patch set includes some small fixes:
- missing trace id release in etm4x.
- underflow issue for nrseqstate.
- wrong check in etm4x_sspcicrn_present().
- missing call of cscfg_csdev_disable_active_config()
This patch based on coresight tree's next
Patch History
=============
from v7 to v8:
- accept @Leo Yan' suggestion to handle error.
- small minor fixes following @Suzuki' suggestion.
- https://lore.kernel.org/all/20260519154812.254884-1-yeoreum.yun@arm.com/
from v6 to v7:
- rebase on coresight/next
- add ETM_MAX_SEQ_TRANSITIONS define
- remove redundant patch relavent cpu-hotplug as coresight-pm patch
merged.
- https://lore.kernel.org/all/20260422132203.977549-1-yeoreum.yun@arm.com/
from v5 to v6:
- fix missing of calling cscfg_csdev_disable_active_config()
- add rb & fixes tags.
- add ss_status field in etm4x_drvdata to expose STATUS and PENDING bits.
- https://lore.kernel.org/all/20260415165528.3369607-1-yeoreum.yun@arm.com/
from v4 to v5:
- add rb-tag.
- fix underflow issue for nrseqstate.
- fix wrong check in etm4_sspcicrn_present().
- remove redundant fields on etmv4_save_state.
- rename caps->ss_status to ss_cmp.
- fix wrong location of etm4_release_trace_id.
- https://lore.kernel.org/all/20260413142003.3549310-1-yeoreum.yun@arm.com/
from v3 to v4:
- change etm_drvdata->spinlock type to raw_spin_lock_t
- remove redundant call etmX_enable_hw() with starting_cpu() callsback.
- fix missing trace id release.
- add missing docs.
- https://lore.kernel.org/all/20260412175506.412301-1-yeoreum.yun@arm.com/
from v2 to v3:
- fix build error for etm3x.
- fix checkpatch warning.
- https://lore.kernel.org/all/20260410074310.2693385-1-yeoreum.yun@arm.com/
from v1 to v2
- rebased to v7.0-rc7.
- introduce etmX_caps structure to save etmX's capabilities.
- remove ss_status from etmv4_config.
- modify active_config after taking a mode (perf/sysfs).
- https://lore.kernel.org/all/20260317181705.2456271-1-yeoreum.yun@arm.com/
Yeoreum Yun (13):
coresight: etm4x: fix wrong check of etm4x_sspcicrn_present()
coresight: etm4x: fix underflow for usage of (nrseqstate - 1)
coresight: etm4x: introduce struct etm4_caps
coresight: etm4x: exclude ss_status from drvdata->config
coresight: etm4x: remove s_ex_level from config
coresight: etm4x: remove redundant fields in etmv4_save_state
coresight: etm4x: fix leaked trace id
coresight: etm4x: fix inconsistencies with sysfs configuration
coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf
enable
coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t
coresight: etm3x: introduce struct etm_caps
coresight: etm3x: fix inconsistencies with sysfs configuration
coresight: etm3x: remove redundant cpu online check on
etm_enable_sysfs()
drivers/hwtracing/coresight/coresight-etm.h | 46 +-
.../coresight/coresight-etm3x-core.c | 96 ++--
.../coresight/coresight-etm3x-sysfs.c | 159 +++---
.../hwtracing/coresight/coresight-etm4x-cfg.c | 5 +-
.../coresight/coresight-etm4x-core.c | 454 ++++++++++--------
.../coresight/coresight-etm4x-sysfs.c | 204 ++++----
drivers/hwtracing/coresight/coresight-etm4x.h | 202 ++++----
7 files changed, 639 insertions(+), 527 deletions(-)
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply
* [PATCH v8 02/13] coresight: etm4x: fix underflow for usage of (nrseqstate - 1)
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In-Reply-To: <20260629090007.1718746-1-yeoreum.yun@arm.com>
According to IHI006H Embedded Trace Macrocell Architecture
Specification[0], TRCSEQEVR<n> is implemented only when
TRCIDR5.NUMSEQSTATE is 0b100, in which case n ranges from 0 to 2;
otherwise, TRCIDR5.NUMSEQSTATE is 0b000.
IOW, the number of usage in the initialisation or setting
TRCSEQEVR<n> with drvdata->nrseqstate - 1 in the loop could make
underflow issue when TRCIDR5.NUMSEQSTATE is 0b000.
Therefore, introduce nr_seq_ctrls field and untie it from nrseqstate.
As part of this introduce ETM_MAX_SEQ_TRANSITIONS macro and
apply nr_seq_ctrls and above macro to TRCSEQEVR<n> relevant fields setup.
Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver")
Suggested-by: Leo Yan <leo.yan@arm.com>
Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++---
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++++--
drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++++--
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index c302072b293a..e1a59b434505 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
/* sequencer state control registers */
idx = (offset & GENMASK(3, 0)) / 4;
- if (idx < ETM_MAX_SEQ_STATES) {
+ if (idx < ETM_MAX_SEQ_TRANSITIONS) {
reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
err = 0;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 1e3b0344dc00..1884960cfe6f 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -542,7 +542,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
if (drvdata->nr_pe_cmp)
etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+
+ for (i = 0; i < drvdata->nr_seq_ctrls; i++)
etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
if (drvdata->nrseqstate) {
etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
@@ -1508,6 +1509,8 @@ static void etm4_init_arch_data(void *info)
drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
/* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
+ if (drvdata->nrseqstate)
+ drvdata->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS;
/* NUMCNTR, bits[30:28] number of counters available for tracing */
drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
@@ -1896,7 +1899,7 @@ static int etm4_cpu_save(struct coresight_device *csdev)
if (drvdata->nr_pe_cmp)
state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ for (i = 0; i < drvdata->nr_seq_ctrls; i++)
state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
if (drvdata->nrseqstate) {
@@ -2009,7 +2012,7 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
if (drvdata->nr_pe_cmp)
etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
- for (i = 0; i < drvdata->nrseqstate - 1; i++)
+ for (i = 0; i < drvdata->nr_seq_ctrls; i++)
etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
if (drvdata->nrseqstate) {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index e9eeea6240d5..cc6cdd3ae29d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -223,7 +223,7 @@ static ssize_t reset_store(struct device *dev,
config->vipcssctlr = 0x0;
/* Disable seq events */
- for (i = 0; i < drvdata->nrseqstate-1; i++)
+ for (i = 0; i < drvdata->nr_seq_ctrls; i++)
config->seq_ctrl[i] = 0x0;
config->seq_rst = 0x0;
config->seq_state = 0x0;
@@ -1395,9 +1395,11 @@ static ssize_t seq_idx_store(struct device *dev,
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etmv4_config *config = &drvdata->config;
+ if (!drvdata->nr_seq_ctrls)
+ return -ENOTSUPP;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
- if (val >= drvdata->nrseqstate - 1)
+ if (val >= drvdata->nr_seq_ctrls)
return -EINVAL;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 89d81ce4e04e..84db8b97c98a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
#define ETM_MAX_NR_PE 8
#define ETMv4_MAX_CNTR 4
#define ETM_MAX_SEQ_STATES 4
+#define ETM_MAX_SEQ_TRANSITIONS 3
#define ETM_MAX_EXT_INP_SEL 4
#define ETM_MAX_EXT_INP 256
#define ETM_MAX_EXT_OUT 4
@@ -877,7 +878,7 @@ struct etmv4_config {
u32 vipcssctlr;
u8 seq_idx;
u8 syncfreq;
- u32 seq_ctrl[ETM_MAX_SEQ_STATES];
+ u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS];
u32 seq_rst;
u32 seq_state;
u8 cntr_idx;
@@ -928,7 +929,7 @@ struct etmv4_save_state {
u32 trcvissctlr;
u32 trcvipcssctlr;
- u32 trcseqevr[ETM_MAX_SEQ_STATES];
+ u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS];
u32 trcseqrstevr;
u32 trcseqstr;
u32 trcextinselr;
@@ -981,6 +982,7 @@ struct etmv4_save_state {
* @numcidc: Number of contextID comparators.
* @numvmidc: Number of VMID comparators.
* @nrseqstate: The number of sequencer states that are implemented.
+ * @nr_seq_ctrls: The number of sequence state transition control registers.
* @nr_event: Indicates how many events the trace unit support.
* @nr_resource:The number of resource selection pairs available for tracing.
* @nr_ss_cmp: Number of single-shot comparator controls that are available.
@@ -1046,6 +1048,7 @@ struct etmv4_drvdata {
u8 numextinsel;
u8 numvmidc;
u8 nrseqstate;
+ u8 nr_seq_ctrls;
u8 nr_event;
u8 nr_resource;
u8 nr_ss_cmp;
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related
* [PATCH v8 05/13] coresight: etm4x: remove s_ex_level from config
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In-Reply-To: <20260629090007.1718746-1-yeoreum.yun@arm.com>
s_ex_level is a hardware capability rather than a configurable parameter.
As such, it should not be stored in the configuration structure.
Remove s_ex_level from the config structure and pass etm4_caps to the
functions that need to access this capability.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
.../coresight/coresight-etm4x-core.c | 58 +++++++++++--------
.../coresight/coresight-etm4x-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 5 +-
3 files changed, 38 insertions(+), 27 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 8fc593bc7041..faa00dcd03a7 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -66,10 +66,12 @@ MODULE_PARM_DESC(pm_save_enable,
"Save/restore state on power down: 1 = never, 2 = self-hosted. MMIO and DT only.");
static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
-static void etm4_set_default_config(struct etmv4_config *config);
+static void etm4_set_default_config(struct etmv4_config *config,
+ const struct etmv4_caps *caps);
static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
struct perf_event *event);
-static u64 etm4_get_access_type(struct etmv4_config *config);
+static u64 etm4_get_access_type(struct etmv4_config *config,
+ const struct etmv4_caps *caps);
static enum cpuhp_state hp_online;
@@ -784,7 +786,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
config->mode |= ETM_MODE_EXCL_GUEST;
/* Always start from the default config */
- etm4_set_default_config(config);
+ etm4_set_default_config(config, caps);
/* Configure filters specified on the perf cmd line, if any. */
ret = etm4_set_event_filters(drvdata, event);
@@ -1445,7 +1447,6 @@ static void etm4_init_arch_data(void *info)
/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
caps->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
- drvdata->config.s_ex_level = caps->s_ex_level;
/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
caps->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
/*
@@ -1530,19 +1531,22 @@ static void etm4_init_arch_data(void *info)
cpu_detect_trace_filtering(drvdata);
}
-static u32 etm4_get_victlr_access_type(struct etmv4_config *config)
+static u32 etm4_get_victlr_access_type(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
- return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
+ return etm4_get_access_type(config, caps) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
}
/* Set ELx trace filter access in the TRCVICTLR register */
-static void etm4_set_victlr_access(struct etmv4_config *config)
+static void etm4_set_victlr_access(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
- config->vinst_ctrl |= etm4_get_victlr_access_type(config);
+ config->vinst_ctrl |= etm4_get_victlr_access_type(config, caps);
}
-static void etm4_set_default_config(struct etmv4_config *config)
+static void etm4_set_default_config(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
/* disable all events tracing */
config->eventctrl0 = 0x0;
@@ -1561,7 +1565,7 @@ static void etm4_set_default_config(struct etmv4_config *config)
config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
/* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
- etm4_set_victlr_access(config);
+ etm4_set_victlr_access(config, caps);
}
static u64 etm4_get_ns_access_type(struct etmv4_config *config)
@@ -1593,21 +1597,24 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
* This must be shifted to the corresponding register field
* for usage.
*/
-static u64 etm4_get_access_type(struct etmv4_config *config)
+static u64 etm4_get_access_type(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
/* All Secure exception levels are excluded from the trace */
- return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
+ return etm4_get_ns_access_type(config) | (u64)caps->s_ex_level;
}
-static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
+static u64 etm4_get_comparator_access_type(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
- return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
+ return etm4_get_access_type(config, caps) << TRCACATR_EXLEVEL_SHIFT;
}
static void etm4_set_comparator_filter(struct etmv4_config *config,
+ const struct etmv4_caps *caps,
u64 start, u64 stop, int comparator)
{
- u64 access_type = etm4_get_comparator_access_type(config);
+ u64 access_type = etm4_get_comparator_access_type(config, caps);
/* First half of default address comparator */
config->addr_val[comparator] = start;
@@ -1638,11 +1645,12 @@ static void etm4_set_comparator_filter(struct etmv4_config *config,
}
static void etm4_set_start_stop_filter(struct etmv4_config *config,
+ const struct etmv4_caps *caps,
u64 address, int comparator,
enum etm_addr_type type)
{
int shift;
- u64 access_type = etm4_get_comparator_access_type(config);
+ u64 access_type = etm4_get_comparator_access_type(config, caps);
/* Configure the comparator */
config->addr_val[comparator] = address;
@@ -1674,7 +1682,8 @@ static void etm4_set_default_filter(struct etmv4_config *config)
config->vissctlr = 0x0;
}
-static void etm4_set_default(struct etmv4_config *config)
+static void etm4_set_default(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
if (WARN_ON_ONCE(!config))
return;
@@ -1686,7 +1695,7 @@ static void etm4_set_default(struct etmv4_config *config)
* full instruction trace - with a default filter for trace all
* achieved by having no filtering.
*/
- etm4_set_default_config(config);
+ etm4_set_default_config(config, caps);
etm4_set_default_filter(config);
}
@@ -1734,6 +1743,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
{
int i, comparator, ret = 0;
u64 address;
+ const struct etmv4_caps *caps = &drvdata->caps;
struct etmv4_config *config = &drvdata->config;
struct etm_filters *filters = event->hw.addr_filters;
@@ -1763,7 +1773,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
switch (type) {
case ETM_ADDR_TYPE_RANGE:
- etm4_set_comparator_filter(config,
+ etm4_set_comparator_filter(config, caps,
filter->start_addr,
filter->stop_addr,
comparator);
@@ -1784,7 +1794,7 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
filter->stop_addr);
/* Configure comparator */
- etm4_set_start_stop_filter(config, address,
+ etm4_set_start_stop_filter(config, caps, address,
comparator, type);
/*
@@ -1820,7 +1830,8 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
return ret;
}
-void etm4_config_trace_mode(struct etmv4_config *config)
+void etm4_config_trace_mode(struct etmv4_config *config,
+ const struct etmv4_caps *caps)
{
u32 mode;
@@ -1834,7 +1845,7 @@ void etm4_config_trace_mode(struct etmv4_config *config)
if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
return;
- etm4_set_victlr_access(config);
+ etm4_set_victlr_access(config, caps);
}
static int etm4_online_cpu(unsigned int cpu)
@@ -2146,6 +2157,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
struct coresight_platform_data *pdata = NULL;
struct device *dev = init_arg->dev;
struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
+ const struct etmv4_caps *caps = &drvdata->caps;
struct coresight_desc desc = { 0 };
u8 major, minor;
char *type_name;
@@ -2175,7 +2187,7 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
if (!desc.name)
return -ENOMEM;
- etm4_set_default(&drvdata->config);
+ etm4_set_default(&drvdata->config, caps);
if (etm4x_always_pm_save(dev, init_arg->csa))
pm_save = true;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index ac290f446c51..fa4a271d4191 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -443,7 +443,7 @@ static ssize_t mode_store(struct device *dev,
config->vinst_ctrl &= ~TRCVICTLR_TRCERR;
if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
- etm4_config_trace_mode(config);
+ etm4_config_trace_mode(config, caps);
raw_spin_unlock(&drvdata->spinlock);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 86fd0cad703e..43f878dc8748 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -955,7 +955,6 @@ struct etmv4_caps {
* @vmid_mask0: VM ID comparator mask for comparator 0-3.
* @vmid_mask1: VM ID comparator mask for comparator 4-7.
* @ext_inp: External input selection.
- * @s_ex_level: Secure ELs where tracing is supported.
*/
struct etmv4_config {
u64 mode;
@@ -998,7 +997,6 @@ struct etmv4_config {
u32 vmid_mask0;
u32 vmid_mask1;
u32 ext_inp;
- u8 s_ex_level;
};
/**
@@ -1119,7 +1117,8 @@ enum etm_addr_ctxtype {
};
extern const struct attribute_group *coresight_etmv4_groups[];
-void etm4_config_trace_mode(struct etmv4_config *config);
+void etm4_config_trace_mode(struct etmv4_config *config,
+ const struct etmv4_caps *caps);
u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related
* [PATCH v8 06/13] coresight: etm4x: remove redundant fields in etmv4_save_state
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In-Reply-To: <20260629090007.1718746-1-yeoreum.yun@arm.com>
Some of fields are redundant in etmv4_save_state and never used:
ss_status => trcsscsr
seq_state => trcseqstr
cntr_val => trccntvr
vinst_ctrl => trcvictlr
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 43f878dc8748..c0f7da17a186 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -1046,11 +1046,6 @@ struct etmv4_save_state {
u32 trcclaimset;
- u32 cntr_val[ETMv4_MAX_CNTR];
- u32 seq_state;
- u32 vinst_ctrl;
- u32 ss_status[ETM_MAX_SS_CMP];
-
u32 trcpdcr;
};
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related
* [PATCH v8 04/13] coresight: etm4x: exclude ss_status from drvdata->config
From: Yeoreum Yun @ 2026-06-29 8:59 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, mike.leach, james.clark, alexander.shishkin,
leo.yan, jie.gan, Yeoreum Yun
In-Reply-To: <20260629090007.1718746-1-yeoreum.yun@arm.com>
The purpose of TRCSSCSRn register is to show status of
the corresponding Single-shot Comparator Control and input supports.
That means writable field's purpose for reset or restore from idle status
not for configuration.
Therefore, exclude ss_status from drvdata->config and move it to drvdata.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 1 -
.../hwtracing/coresight/coresight-etm4x-core.c | 15 ++++++++-------
.../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++-
4 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index e1a59b434505..9b4947d75fde 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
off_mask = (offset & GENMASK(11, 5));
do {
CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask);
- CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask);
CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask);
} while (0);
} else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) {
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 3ef4543a4f15..8fc593bc7041 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -95,7 +95,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
const struct etmv4_caps *caps = &drvdata->caps;
return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp &&
- (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
+ (drvdata->ss_status[n] & TRCSSCSRn_PC);
}
u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
@@ -570,11 +570,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
for (i = 0; i < caps->nr_ss_cmp; i++) {
- /* always clear status bit on restart if using single-shot */
+ /* always clear status and pending bits on restart if using single-shot */
if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
- config->ss_status[i] &= ~TRCSSCSRn_STATUS;
+ drvdata->ss_status[i] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
- etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
+ etm4x_relaxed_write32(csa, drvdata->ss_status[i], TRCSSCSRn(i));
if (etm4x_sspcicrn_present(drvdata, i))
etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
}
@@ -1063,7 +1063,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata)
/* read the status of the single shot comparators */
for (i = 0; i < caps->nr_ss_cmp; i++) {
- config->ss_status[i] =
+ drvdata->ss_status[i] =
etm4x_relaxed_read32(csa, TRCSSCSRn(i));
}
@@ -1496,8 +1496,9 @@ static void etm4_init_arch_data(void *info)
*/
caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
for (i = 0; i < caps->nr_ss_cmp; i++) {
- drvdata->config.ss_status[i] =
- etm4x_relaxed_read32(csa, TRCSSCSRn(i));
+ drvdata->ss_status[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i));
+ drvdata->ss_status[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV |
+ TRCSSCSRn_DA | TRCSSCSRn_INST);
}
/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 2d8a8f64a038..ac290f446c51 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1829,8 +1829,8 @@ static ssize_t sshot_ctrl_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
+ /* must clear bit 31 and 30 in related status register on programming */
+ drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
raw_spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1844,7 +1844,7 @@ static ssize_t sshot_status_show(struct device *dev,
struct etmv4_config *config = &drvdata->config;
raw_spin_lock(&drvdata->spinlock);
- val = config->ss_status[config->ss_idx];
+ val = drvdata->ss_status[config->ss_idx];
raw_spin_unlock(&drvdata->spinlock);
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
}
@@ -1879,8 +1879,8 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,
raw_spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val);
- /* must clear bit 31 in related status register on programming */
- config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
+ /* must clear bit 31 and 30 in related status register on programming */
+ drvdata->ss_status[idx] &= ~(TRCSSCSRn_STATUS | TRCSSCSRn_PENDING);
raw_spin_unlock(&drvdata->spinlock);
return size;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index c0748110d7af..86fd0cad703e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -213,6 +213,7 @@
#define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
#define TRCSSCSRn_STATUS BIT(31)
+#define TRCSSCSRn_PENDING BIT(30)
#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
@@ -730,6 +731,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
#define ETM_DEFAULT_ADDR_COMP 0
#define TRCSSCSRn_PC BIT(3)
+#define TRCSSCSRn_DV BIT(2)
+#define TRCSSCSRn_DA BIT(1)
+#define TRCSSCSRn_INST BIT(0)
/* PowerDown Control Register bits */
#define TRCPDCR_PU BIT(3)
@@ -980,7 +984,6 @@ struct etmv4_config {
u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */
u8 ss_idx;
u32 ss_ctrl[ETM_MAX_SS_CMP];
- u32 ss_status[ETM_MAX_SS_CMP];
u32 ss_pe_cmp[ETM_MAX_SS_CMP];
u8 addr_idx;
u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
@@ -1075,6 +1078,7 @@ struct etmv4_save_state {
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
* @paused: Indicates if the trace unit is paused.
+ * @ss_status: The status of the corresponding single-shot comparator.
* @arch_features: Bitmap of arch features of etmv4 devices.
*/
struct etmv4_drvdata {
@@ -1094,6 +1098,7 @@ struct etmv4_drvdata {
u64 trfcr;
struct etmv4_config config;
struct etmv4_save_state *save_state;
+ u32 ss_status[ETM_MAX_SS_CMP];
DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
};
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}
^ permalink raw reply related
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