* Re: [PATCH 2/3] can: rockchip: add RK3588 CAN-FD support
From: Heiko Stübner @ 2026-07-01 16:02 UTC (permalink / raw)
To: Marc Kleine-Budde, 💫.220
Cc: linux-can, mailhol, kernel, robh, krzk+dt, conor+dt, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <tencent_AF88C27E354DFF34B132BC0906236A01A408@qq.com>
Am Mittwoch, 1. Juli 2026, 14:29:22 Mitteleuropäische Sommerzeit schrieb 💫.220:
> Hi Heiko, Marc,
>
> thanks for the review.
>
> > please use a real name, not an alias.
>
> I will use my real name in future revisions.
>
> > Funnily enough, we seem to have worked on the same topic
> > at the same time :-)
> >
> > https://lore.kernel.org/lkml/20260630164336.3444550-1-heiko@sntech.de/
>
> I missed Heiko's series before sending mine, sorry for the noise.
> (But it really is a very interesting coincidence.)
> Since the series overlap, I am happy to base further work on Heiko's
> series, or to let Heiko fold the RK3588 RX_FIFO_CNT bitfield change into
> his v2 if that is preferred.
I don't think we need two people working on this and you did the better
investigation into the differences, so you should get the credit :-)
So I guess my preference would be to:
- pick up the erratum 6 into your patch
- add my haikou patch to the series - that way we also get a user
- handle Krzysztof's comment from
https://lore.kernel.org/linux-rockchip/20260701-sensible-cryptic-ocelot-58035b@quoll/
as both our bindings have the same structure, so I guess it should be
oneOf:
- enum:
rockchip,rk3568v2-canfd
rockchip,rk3588v2-canfd
- items:
- const: rockchip,rk3568v3-canfd
- const: rockchip,rk3568v2-canfd
And submit that as v2.
> For RX_FIFO_CNT, I found the bitfield difference by reading Rockchip's
> vendor kernel 6.1 driver and comparing the CAN support for RK3568 and
> RK3588. The vendor driver uses different RX FIFO count bitfields for the
> two SoCs, and my testing on RK3588v2 also indicates that bits 7:5 are
> needed. I can add a short note about this in the commit message or
> code comment.
It's already in the commit message, so that should be fine
> One more question about RKCANFD_QUIRK_CANFD_BROKEN: in my RK3588v2 test
> setup the two known CAN-FD trigger frames did not cause an Error
> Interrupt or Error-Warning. I also ran a 12 hour CAN-FD stress test with
> can0/can1 directly connected, 200 MHz CAN clock, 500 kbit/s nominal
> bitrate and 1 Mbit/s data bitrate. That test included periodic
> transmission of the two CANFD_BROKEN frames, variable DLC CAN-FD frames,
> CAN-FD+BRS+EFF load, and a canfdtest run with 19,417,129 frames without
> data mismatch.
>
> Would it make sense to leave RKCANFD_QUIRK_CANFD_BROKEN disabled for
> RK3588v2, or have you seen this issue on RK3588 as well?
I was more going by the fact that even Rockchip removed every mention of
the -FD from all documentation, so was assuming it still being broken as
before. But if it actually works, then personally I'm more than fine with
enabling CAN-FD :-D .
I guess Marc might have more insight where the FD issue triggered on
the RK3568.
Heiko
^ permalink raw reply
* [PATCH 0/1] describe GPIO and EIRQ resources in SIUL2 pinctrl node for S32G2/S32G3 SoCs
From: Khristine Andreea Barbulescu @ 2026-07-01 11:51 UTC (permalink / raw)
To: Bartosz Golaszewski, Chester Lin, Matthias Brugger,
Ghennadi Procopciuc, Frank Li, Sascha Hauer, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
This patch describes the GPIO and EIRQ resources in the SIUL2 pinctrl
node for the S32G2 and S32G3 SoCs.
The rest of the changes from the series - the device tree bindings and
the pinctrl driver changes adding GPIO support - have been applied to
the pin control tree. This patch contains the remaining device tree changes.
Khristine Andreea Barbulescu (1):
arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl
node
arch/arm64/boot/dts/freescale/s32g2.dtsi | 21 ++++++++++++++++++++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 21 ++++++++++++++++++++-
2 files changed, 40 insertions(+), 2 deletions(-)
--
2.34.1
^ permalink raw reply
* Re: [PATCH v3 1/3] KVM: arm64: skip pKVM cache flushes for non cacheable mappings
From: Leonardo Bras @ 2026-07-01 16:05 UTC (permalink / raw)
To: Bradley Morgan
Cc: Leonardo Bras, Marc Zyngier, Oliver Upton, Fuad Tabba, Joey Gouly,
Steffen Eiden, Suzuki K Poulose, Zenghui Yu, Catalin Marinas,
Will Deacon, Quentin Perret, Vincent Donnefort, Gavin Shan,
Alexandru Elisei, linux-arm-kernel, kvmarm, linux-kernel
In-Reply-To: <20260624160028.15591-2-include@grrlz.net>
On Wed, Jun 24, 2026 at 04:00:26PM +0000, Bradley Morgan wrote:
> pKVM keeps its own mapping list for stage 2 operations. Its flush path
> uses that list directly, so it lost the PTE attribute check done by the
> generic stage 2 walker.
>
> Record whether a mapping is cacheable and skip cache maintenance for
> mappings that are not cacheable.
>
> Fixes: e912efed485a ("KVM: arm64: Introduce the EL1 pKVM MMU")
> Signed-off-by: Bradley Morgan <include@grrlz.net>
> ---
> arch/arm64/kvm/pkvm.c | 51 ++++++++++++++++++++++++++++++++++---------
> 1 file changed, 41 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c
> index 428723b1b0f5..ca6e823028c2 100644
> --- a/arch/arm64/kvm/pkvm.c
> +++ b/arch/arm64/kvm/pkvm.c
> @@ -302,9 +302,32 @@ static u64 __pkvm_mapping_start(struct pkvm_mapping *m)
> return m->gfn * PAGE_SIZE;
> }
>
> +#define PKVM_MAPPING_NR_PAGES_MASK GENMASK_ULL(47, 0)
> +#define PKVM_MAPPING_CACHEABLE BIT_ULL(48)
Out of curiosity here, why do you choose to use bit 48 here instead of,
let's say, bit 63?
(I know it makes absolutely no difference to inner working here, as there
should probably not be 2^48 pages in one mapping.)
Thanks!
Leo
> +
> +static u64 pkvm_mapping_nr_pages(struct pkvm_mapping *m)
> +{
> + return m->nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
> +}
> +
> +static bool pkvm_mapping_is_cacheable(struct pkvm_mapping *m)
> +{
> + return m->nr_pages & PKVM_MAPPING_CACHEABLE;
> +}
> +
> +static void pkvm_mapping_set_nr_pages(struct pkvm_mapping *m, u64 nr_pages,
> + bool cacheable)
> +{
> + WARN_ON_ONCE(nr_pages & ~PKVM_MAPPING_NR_PAGES_MASK);
> +
> + m->nr_pages = nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
> + if (cacheable)
> + m->nr_pages |= PKVM_MAPPING_CACHEABLE;
> +}
> +
> static u64 __pkvm_mapping_end(struct pkvm_mapping *m)
> {
> - return (m->gfn + m->nr_pages) * PAGE_SIZE - 1;
> + return (m->gfn + pkvm_mapping_nr_pages(m)) * PAGE_SIZE - 1;
> }
>
> INTERVAL_TREE_DEFINE(struct pkvm_mapping, node, u64, __subtree_last,
> @@ -350,7 +373,7 @@ static int __pkvm_pgtable_stage2_reclaim(struct kvm_pgtable *pgt, u64 start, u64
> continue;
>
> page = pfn_to_page(mapping->pfn);
> - WARN_ON_ONCE(mapping->nr_pages != 1);
> + WARN_ON_ONCE(pkvm_mapping_nr_pages(mapping) != 1);
> unpin_user_pages_dirty_lock(&page, 1, true);
> account_locked_vm(kvm->mm, 1, false);
> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
> @@ -369,7 +392,7 @@ static int __pkvm_pgtable_stage2_unshare(struct kvm_pgtable *pgt, u64 start, u64
>
> for_each_mapping_in_range_safe(pgt, start, end, mapping) {
> ret = kvm_call_hyp_nvhe(__pkvm_host_unshare_guest, handle, mapping->gfn,
> - mapping->nr_pages);
> + pkvm_mapping_nr_pages(mapping));
> if (WARN_ON(ret))
> return ret;
> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
> @@ -448,7 +471,7 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
> * permission faults are handled in the relax_perms() path.
> */
> if (mapping) {
> - if (size == (mapping->nr_pages * PAGE_SIZE))
> + if (size == (pkvm_mapping_nr_pages(mapping) * PAGE_SIZE))
> return -EAGAIN;
>
> /*
> @@ -472,7 +495,9 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
> swap(mapping, cache->mapping);
> mapping->gfn = gfn;
> mapping->pfn = pfn;
> - mapping->nr_pages = size / PAGE_SIZE;
> + pkvm_mapping_set_nr_pages(mapping, size / PAGE_SIZE,
> + !(prot & (KVM_PGTABLE_PROT_DEVICE |
> + KVM_PGTABLE_PROT_NORMAL_NC)));
> pkvm_mapping_insert(mapping, &pgt->pkvm_mappings);
>
> return ret;
> @@ -503,7 +528,7 @@ int pkvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size)
> lockdep_assert_held(&kvm->mmu_lock);
> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
> ret = kvm_call_hyp_nvhe(__pkvm_host_wrprotect_guest, handle, mapping->gfn,
> - mapping->nr_pages);
> + pkvm_mapping_nr_pages(mapping));
> if (WARN_ON(ret))
> break;
> }
> @@ -517,9 +542,13 @@ int pkvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size)
> struct pkvm_mapping *mapping;
>
> lockdep_assert_held(&kvm->mmu_lock);
> - for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
> + for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
> + if (!pkvm_mapping_is_cacheable(mapping))
> + continue;
> +
> __clean_dcache_guest_page(pfn_to_kaddr(mapping->pfn),
> - PAGE_SIZE * mapping->nr_pages);
> + PAGE_SIZE * pkvm_mapping_nr_pages(mapping));
> + }
>
> return 0;
> }
> @@ -536,8 +565,10 @@ bool pkvm_pgtable_stage2_test_clear_young(struct kvm_pgtable *pgt, u64 addr, u64
>
> lockdep_assert_held(&kvm->mmu_lock);
> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
> - young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest, handle, mapping->gfn,
> - mapping->nr_pages, mkold);
> + young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest,
> + handle, mapping->gfn,
> + pkvm_mapping_nr_pages(mapping),
> + mkold);
>
> return young;
> }
> --
> 2.53.0
>
^ permalink raw reply
* Re: [PATCH RFC 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM
From: Enzo Adriano @ 2026-07-01 16:07 UTC (permalink / raw)
To: Junhui Liu
Cc: Michael Turquette, Stephen Boyd, Brian Masney, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Andre Przywara, Jerome Brunet,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Richard Cochran, linux-clk, devicetree, linux-arm-kernel,
linux-sunxi, linux-kernel, linux-riscv, netdev
In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech>
Hi Junhui,
Thanks for the A733 CCU/PRCM RFC v1. I've been reading through the
series and the review feedback, including the NSI clock/reset handling,
the binding naming and ordering comments, the SDM macro cleanup, and the
question around modeled but otherwise-unused clocks such as the GIC clock.
I do not see a v2 on the list yet, so I wanted to check in: are you still
planning to take this series forward? No rush at all, and I am happy to
leave it entirely with you if so.
If you have moved on to other things, I would be glad to help carry the
series forward and address the review comments, keeping your authorship
and prior work intact. I have A733 hardware here and can help test the
changes.
Either way, please let me know what works best for you.
Thanks,
Enzo
^ permalink raw reply
* Re: (subset) [PATCH v5 0/2] media: nxp: imx8-isi: Add virtual channel and frame descriptor support
From: Frank Li @ 2026-07-01 16:09 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Laurent Pinchart, Mauro Carvalho Chehab, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Guoniu Zhou, Frank Li,
Aisheng Dong, linux-media, imx, linux-arm-kernel, linux-kernel,
Guoniu Zhou
In-Reply-To: <akU3hNb_9IkwGLK2@SMW015318>
On Wed, Jul 01, 2026 at 10:51:32AM -0500, Frank Li wrote:
> On Tue, Jun 30, 2026 at 11:20:53PM +0100, Bryan O'Donoghue wrote:
> > On 30/06/2026 17:20, Frank Li wrote:
> > > On Mon, Jun 29, 2026 at 11:23:02PM +0300, Laurent Pinchart wrote:
> > > > On Mon, Jun 29, 2026 at 03:42:31PM -0400, Frank.Li@oss.nxp.com wrote:
> > > > > From: Frank Li <Frank.Li@nxp.com>
> > > > >
> > > > >
> > > > > On Thu, 21 May 2026 17:10:03 +0800, Guoniu Zhou wrote:
> > > > > > This patch series enhances the i.MX ISI driver's with virtual channel
> > > > > > support and adds frame descriptor capabilities to the crossbar subdevice.
> > > > >
> > > > > Applied, thanks!
> > > > >
> > > > > [1/2] media: imx8-isi: crossbar: Add get_frame_desc operation
> > > > > commit: 3e15a3510908c990ee352aa206d5f9c23d4b216e
> > > >
> > > > Is this a mistake ? Patch 1/2 has no R-b tag, and you're not listed as
> > > > maintainer for this driver.
> > >
> > > Sorry, I missed checking Maintainer files, in media summit, agree on I pick
> > > imx's media drivers, but forget finalize the file\dir list. Can you help
> > > summery which files\dir I should take care?
> > >
> > > If you have concern about this patch, I can drop it.
> > >
> > > Frank
> > You should set yourself up here:
> > https://patchwork.linuxtv.org/project/linux-media/list/
>
> I just register it.
>
> "Registration successful!
>
> A confirmation email has been sent to frank.li@kernel.org. You'll need to visit the link provided in that email to confirm your registration."
>
> I have not recieved such confirm email. Anything wrong?
I just got it. But I am not in delegate list yet.
Frank
>
> Frank
>
>
> >
> > That way you can coordinate with other maintainers on which files get
> > reviewed by whom, see what the RB and ci status is.
> >
> > Its pretty essential.
> >
> > ---
> > bod
>
^ permalink raw reply
* [PATCH] futex: Optimise the size check get_futex_key()
From: Sebastian Andrzej Siewior @ 2026-07-01 16:17 UTC (permalink / raw)
To: K Prateek Nayak
Cc: Peter Zijlstra, Arnd Bergmann, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, x86, Catalin Marinas, Will Deacon,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Carstens,
Vasily Gorbik, Alexander Gordeev, Darren Hart, Davidlohr Bueso,
André Almeida, linux-arch, linux-kernel, Samuel Holland,
Charlie Jenkins, linux-arm-kernel, linux-riscv, linux-s390,
H. Peter Anvin, Thomas Huth, Sean Christopherson, Jisheng Zhang,
Alexandre Ghiti, Christian Borntraeger, Sven Schnelle
In-Reply-To: <38239f40-1673-469f-baa3-4a343d2aa4c3@amd.com>
The futex address must be naturally aligned and this is checked via
"address % size" where `address' is the supplied address and `size' is
the expected size of futex. It is guaranteed that `size' is power of two
but the compiler does not see it and creates here a `div' operation
(x86, arm, gcc-15).
We can take advantage of the pow2 property and rewrite it as
"address & (size-1)".
As per testing, the command
|perf bench futex hash -f 1 -b 16384 -t 1 -r 30
improved from
| [thread 0] futex: 0x5619f931f740 [ 7001583 ops/sec ]
to
| [thread 0] futex: 0x55da173e5740 [ 7376137 ops/sec ]
or by 5.3%
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
Could someone verify this, please? The 5% look a bit high. This is on
top of the series (but not worsen by the series).
kernel/futex/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/futex/core.c b/kernel/futex/core.c
index 179b26e9c9341..2b00ab510e7d2 100644
--- a/kernel/futex/core.c
+++ b/kernel/futex/core.c
@@ -520,7 +520,7 @@ int get_futex_key(u32 __user *uaddr, unsigned int flags, union futex_key *key,
* The futex address must be "naturally" aligned.
*/
key->both.offset = address % PAGE_SIZE;
- if (unlikely((address % size) != 0))
+ if (unlikely((address & (size-1)) != 0))
return -EINVAL;
address -= key->both.offset;
--
2.53.0
^ permalink raw reply related
* [PATCH v7 08/11] arm64: dts: ti: k3-am62p-ti-ipc-firmware: Move wkup reserved memory
From: Markus Schneider-Pargmann (TI) @ 2026-07-01 12:39 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Nathan Chancellor,
Nick Desaulniers, Bill Wendling, Justin Stitt, Judith Mendez,
Daniel Schultz, Andrew Davis, Siddharth Vadapalli, Paresh Bhagat,
Bryan Brattlof, Jai Luthra, Devarsh Thakkar, Beleswar Padhi,
Francesco Dolcini, Stefano Radaelli
Cc: Vishal Mahaveer, Kevin Hilman, Sebin Francis, Kendall Willis,
Akashdeep Kaur, linux-arm-kernel, devicetree, linux-kernel, llvm,
Hari Nagalla, Markus Schneider-Pargmann (TI)
In-Reply-To: <20260701-topic-am62a-ioddr-dt-v6-19-v7-0-e9db8b16821a@baylibre.com>
Move the reserved memory regions used for wkup_r5fss0_core0 to the
k3-am62p-ti-ipc-firmware.dtsi. These are all the same for the other
boards as well, so we can combine them here similar to what is already
done for the mcu_r5fss0_core0 memory regions.
Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
---
arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 12 ++++++++++++
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 12 ------------
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 12 ------------
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 12 ------------
4 files changed, 12 insertions(+), 36 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
index 5d7f701420e2d8308b637f3064c560e485ed85f2..f77651109564224408723b72baba93e39a82be07 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi
@@ -17,6 +17,18 @@ mcu_r5fss0_core0_memory_region: memory@9b900000 {
reg = <0x00 0x9b900000 0x00 0xf00000>;
no-map;
};
+
+ wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c800000 0x00 0x100000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: memory@9c900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c900000 0x00 0x01d08000>;
+ no-map;
+ };
};
&mailbox0_cluster0 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
index 8a5ff5c457579c7b1be7157d235fd4b4e5c6af11..49c78b6b8b2b43fe381c761823bbd93725f331aa 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
@@ -161,18 +161,6 @@ secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
no-map;
};
-
- wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c800000 0x00 0x100000>;
- no-map;
- };
-
- wkup_r5fss0_core0_memory_region: memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01d08000>;
- no-map;
- };
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index 16549fd7340a556798cf5a242746c219d3168d83..6444aa0c106197eb44088ec99d7c7dba7f8f854d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -49,18 +49,6 @@ reserved_memory: reserved-memory {
#size-cells = <2>;
ranges;
- wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c800000 0x00 0x100000>;
- no-map;
- };
-
- wkup_r5fss0_core0_memory_region: memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01d08000>;
- no-map;
- };
-
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
no-map;
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
index 1408c970f1942e8a720c9cf071b2f49eafa9db5e..76295e47eca9d6373a89430355330c9a4ac9be32 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -63,18 +63,6 @@ rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
no-map;
};
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c800000 0x00 0x00100000>;
- no-map;
- };
-
- wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01d08000>;
- no-map;
- };
-
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
no-map;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH 1/2] coresight: Fix clock refcount imbalance on platform remove
From: Leo Yan @ 2026-07-01 16:23 UTC (permalink / raw)
To: Jie Gan
Cc: Suzuki K Poulose, Mike Leach, James Clark, Alexander Shishkin,
Anshuman Khandual, Yeoreum Yun, Yuanfang Zhang, Maxime Coquelin,
Alexandre Torgue, Tingwei Zhang, coresight, linux-arm-kernel,
linux-kernel, linux-stm32
In-Reply-To: <20260701-fix-clock-refcount-unbalance-v1-1-321dc63c1f90@oss.qualcomm.com>
On Wed, Jul 01, 2026 at 02:05:02PM +0800, Jie Gan wrote:
> After probe, pm_runtime_put() allows the device to suspend and the
> runtime suspend callback disables the same clocks. During remove the
> device is left runtime suspended, so pm_runtime_disable() freezes it
> with the clocks already disabled. The devm cleanup that runs afterwards
> calls clk_disable_unprepare() a second time, underflowing the clock
> enable refcount.
Thanks for fixing the issue.
The problem is that if the device has already been runtime suspended and
its clock has been disabled, afterwards when remove the device, the devm
cleanup disables the clock again, resulting in clock count underflow.
> diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
> index 0abc11f0690c..4c5b94640e6a 100644
> --- a/drivers/hwtracing/coresight/coresight-funnel.c
> +++ b/drivers/hwtracing/coresight/coresight-funnel.c
> @@ -334,6 +334,7 @@ static void funnel_platform_remove(struct platform_device *pdev)
> return;
>
> funnel_remove(&pdev->dev);
> + pm_runtime_get_sync(&pdev->dev);
> pm_runtime_disable(&pdev->dev);
Let's use the funnel driver for the discussion. Once we agree on the
approach, we can apply the same change to the other CoreSight platform
drivers.
How about the following teardown?
static void funnel_platform_remove(struct platform_device *pdev)
{
struct funnel_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
+ int ret;
if (WARN_ON(!drvdata))
return;
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret < 0)
+ dev_warn(&pdev->dev, "failed to resume before remove: %d\n", ret);
+
funnel_remove(&pdev->dev);
+
pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+ pm_runtime_put_noidle(&pdev->dev);
}
The idea is to first resume the device with pm_runtime_get_sync(), then
perform the remove (which is safe if they need to access or clean up
hardware state), and finally clean up the runtime PM states. I mainly
referred to drivers/iio/adc/stm32-adc.c.
Thanks,
Leo
^ permalink raw reply
* Re: [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
From: Rob Herring (Arm) @ 2026-07-01 16:24 UTC (permalink / raw)
To: Louis-Alexis Eyraud
Cc: linux-kernel, Richard Cochran, Chun-Jie Chen, netdev,
AngeloGioacchino Del Regno, Brian Masney, Philipp Zabel,
devicetree, linux-arm-kernel, Stephen Boyd, linux-mediatek,
Krzysztof Kozlowski, kernel, Michael Turquette, Edward-JW Yang,
Matthias Brugger, Conor Dooley, linux-clk
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-2-2b048feea50a@collabora.com>
On Wed, 01 Jul 2026 15:11:07 +0200, Louis-Alexis Eyraud wrote:
> Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones
> to ease maintainability and have common files for several currently
> supported SoC or new future ones, that have the same kind of clock
> controller design.
>
> Note:
> The `#clock-cells` property is a required property for all compatibles
> declared in MT8188 clock and system clock dt-bindings but not in MT8186
> ones.
> To avoid ABI breakage, conditional blocks to check this requirement
> for MT8188 compatibles are added, rather than enforcing it for MT8186
> compatibles.
>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
> .../bindings/clock/mediatek,mt8186-clock.yaml | 82 ++++++++++++++++++-
> .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 20 ++++-
> .../bindings/clock/mediatek,mt8188-clock.yaml | 93 ----------------------
> .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 --------------
> 4 files changed, 100 insertions(+), 153 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml:62:1: [warning] too many blank lines (2 > 1) (empty-lines)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701-mt8189-clocks-system-base-v1-2-2b048feea50a@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* [PATCH v2 1/4] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 SoC
From: Louis-Alexis Eyraud @ 2026-07-01 16:35 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang
Cc: kernel, linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-mediatek, Krzysztof Kozlowski, Louis-Alexis Eyraud
In-Reply-To: <20260701-add-mediatek-genio-520-720-evk-v2-0-19d5da4ef984@collabora.com>
Add a compatible string for the MT8189 SoC.
The UART IPs in this chip are fully compatible with the one found in
MT6577 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
index 5bd8a8853ae0..3f0f4aea0a4c 100644
--- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml
@@ -47,6 +47,7 @@ properties:
- mediatek,mt8183-uart
- mediatek,mt8186-uart
- mediatek,mt8188-uart
+ - mediatek,mt8189-uart
- mediatek,mt8192-uart
- mediatek,mt8195-uart
- mediatek,mt8365-uart
--
2.54.0
^ permalink raw reply related
* [PATCH v2 0/4] Add support for the Mediatek Genio 520-EVK and 720-EVK boards
From: Louis-Alexis Eyraud @ 2026-07-01 16:35 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang
Cc: kernel, linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-mediatek, Krzysztof Kozlowski, Louis-Alexis Eyraud
This patch series adds the support for the Mediatek Genio 520-EVK (based
on MT8371 SoC) and Mediatek Genio 720-EVK (based on MT8391 SoC).
MT8371 and MT8391 SoC are less powerful variants of MT8189 SoC
with the following differences:
- Arm Cortex-A78 CPU core maximum frequency (2.2 Ghz for MT8371, 2.6
Ghz for MT8391, 3 Ghz for MT8189).
- Arm Mali G57 MC2 GPU core maximum frequency (880 Mhz for MT8371,
1.1 Ghz for MT8189 and MT8391)
- ISP engine number (1 for MT8371, 2 for MT8189 and MT8391)
MT8371 and MT8391 SoC hardware register maps are identical to MT8189.
The Genio 520/720-EVK boards have following features:
- MT8371 (or MT8391) SoC
- MT6365 PMIC
- MT6319 Buck IC
- MT6375 Charger IC
- 8GB LPDDR5 RAM
- 64GB eMMC 5.1
- 128GB UFS
- 20V DC Jack
- USB Type-C Power Adapter
- Micro SD card slot
- Push Button x 4 (Power, Reset, Download and Home Key)
- LED x 3 (System Power, Reset, DC-IN Power)
- USB Type-C Connector (USB 3.2) x 2
- USB Type-C Connector (USB 2.0) x 1
- 3.5mm Earphone Jack x 1 (with Microphone Input)
- 3.5mm Line Out Audio Jack x 1
- Analog Microphone x 1
- Digital Microphone x 2
- Gigabit Ethernet with RJ45 connector
- DP x 1 (Mode over USB Type-C)
- LVDS port x 1
- eDP port x 1
- UART x2 with serial-to-usb converters and USB Type-C connectors
- UART Port x 2 on Pin Header
- M.2 Slot x 2
- I2C Capacitive Touch Pad
- 4-Lane DSI x 1
- 4-Data Lane CSI x 2
- I2S Pin header
- 40-Pin 2.54mm Pin Header x 1
- CAN Bus x 1 (RS232 Connector)
The series adds two include files for mt8189 (mt8189.dtsi) and common
board definitions (mt8391-genio-common.dtsi) and a devicetree file for
each board.
In regard to the current MT8189 SoC upstream support and this series
provides the following basic hardware enablement for:
- CPU
- system and base clocks (including fhctl support)
- spmi and regulators
- power domain controller and all domains (excluding multimedia and
graphics related ones)
- UART 0/1/2/3 with DMA support
- eMMC and SD card
- watchdog
- timer
- efuse and socinfo
- auxadc
- PCIe controller and Wifi PCIe M.2 module
The series is based on linux-next next-20260630 tag, and the
following patch series are currently required:
- MT8189: Add support for system and base clock controllers [1]
- mt8189: Add pinmux macro header file [2]
- dt-bindings: timer: mediatek,timer: Add compatible for MT8189 [3]
- dt-bindings: mmc: mtk-sd: Document extra clocks for MT8189 [4]
- dt-bindings: mfd: mediatek,mt8195-scpsys: Add support for MT8189 SoC [5]
- dt-bindings: PCI: mediatek-gen3: Add support for MT8189 SoC [6]
- dt-bindings: phy: mediatek,tphy: Add support for MT8189 SoC [7]
- dt-bindings: dma: mediatek,uart-dma: add support for MT8189 SoC [8]
[1] https://lore.kernel.org/linux-mediatek/20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com/
[2] https://lore.kernel.org/linux-mediatek/20251205064357.13591-1-ot_cathy.xu@mediatek.com/
[3] https://lore.kernel.org/linux-mediatek/20250825033136.7705-1-zhanzhan.ge@mediatek.com/
[4] https://lore.kernel.org/linux-mediatek/20260701-mt8189-mmc-dt-bindings-fix-v1-1-e75f241a275b@collabora.com/
[5] https://lore.kernel.org/linux-mediatek/20260701-mt8189-dt-bindings-scpsys-v1-1-2c04f0fda1b7@collabora.com/
[6] https://lore.kernel.org/linux-mediatek/20260701-mt8189-dt-bindings-pcie-v1-1-7c7a65087654@collabora.com/
[7] https://lore.kernel.org/linux-mediatek/20260701-mt8189-dt-bindings-tphy-v1-1-5848a2be8303@collabora.com/
[8] https://lore.kernel.org/linux-mediatek/20260701-mt8189-dt-bindings-uart-dma-v1-1-c7106216a40d@collabora.com/
---
Changes in v2:
- Added Acked-by trailers in patchs 1 and 2
- Reworded patchs 2, 3 and 4 subjects to remove redundant parts
- Patch 3:
- Moved aliases from mt8189.dtsi to mt8391-genio-common.dtsi
- Renamed fixed-clock names in mt8189.dtsi
- Removed the multimedia and graphics related clock controller nodes
and aligned remaining clock-controller compatibles to match the
latest mt8189 clock series revision ([1])
- Added missing aud_adc_ext fixed clock (used as parent in
clk-mt8189-vlpckgen.c)
- Removed _clk suffix from all clock controller aliases
- Added UART DMA controller node and use
- Added PCIE host controller node and use
- Added MT8189 powerdomain controller node and SoC power domain
definitions (excluding the multimedia and graphics related ones)
- Added ARM DSU PMU support with fail status to handle its optional
support in firmware/bootloaders.
- Added extra clocks in MMC0 and MMC1 nodes, that are now required
with latest mt8189 clock series revisions ([1] and [4])
- Replaced mt6359.dtsi include by mt6365.dtsi and added the supply
definitions and compatible related to this PMIC
- Added the MT6319 PMIC supply definitions
- Added the MT6319 PMIC definitions and aliases with two different
USID and enabled the expected one in Genio 720-EVK devicetree to
fix this PMIC not being properly detected on Genio 520-EVK in v1.
- Added the needed definitions, pinctrl and regulator to enable wifi
module support
- Enabled the MT6319 PMIC with correct USID in Genio 520-EVK devicetree
in patch 4.
- Link to v1: https://lore.kernel.org/r/20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com
---
Louis-Alexis Eyraud (4):
dt-bindings: serial: mediatek,uart: Add compatible for MT8189 SoC
dt-bindings: arm: mediatek: add Mediatek Genio 520/720-EVK boards
arm64: dts: mediatek: add Genio 720-EVK board
arm64: dts: mediatek: add Genio 520-EVK board
.../devicetree/bindings/arm/mediatek.yaml | 10 +
.../devicetree/bindings/serial/mediatek,uart.yaml | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 2 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 920 +++++++++++++++++++++
.../boot/dts/mediatek/mt8371-genio-520-evk.dts | 32 +
.../boot/dts/mediatek/mt8391-genio-720-evk.dts | 27 +
.../boot/dts/mediatek/mt8391-genio-common.dtsi | 673 +++++++++++++++
7 files changed, 1665 insertions(+)
---
base-commit: ba7c57499e5999aeae8dd4f954eb2600589d80aa
change-id: 20251128-add-mediatek-genio-520-720-evk-06162377974d
prerequisite-message-id: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
prerequisite-patch-id: 7b1af194800ee6075aeb7933e2b55ac57e1dc5e2
prerequisite-patch-id: 875e450fd11593714ac2f5de93240c058d4b0a42
prerequisite-patch-id: b38381973e1d32c5ae8e04aba4673b7221dad2b1
prerequisite-patch-id: ed4aab90f897ed26c4cbf6f0a5be965c9e9cedd7
prerequisite-patch-id: 41ea05f49926cab03759da60e03b2d58fd524846
prerequisite-patch-id: c193828b36c6195aa6c21e8926e61bba4032ed9b
prerequisite-patch-id: 2c9894cd211e5676f43ebac4a722704c0e127190
prerequisite-patch-id: a29fd1f809b1ddc581847ba26638882e5ff127e7
prerequisite-patch-id: 6dffca2ee6a8762d22aece8a319499500ee271cc
prerequisite-patch-id: 587d2d91b66dcaa59488eece20931b76d8fbd655
prerequisite-patch-id: 28acddfadf1d24eb54ca107e2b4573a57113ded7
prerequisite-patch-id: 75658fbbf84ba98c996571253f4cdc0508552d5c
prerequisite-patch-id: 96cbb979a4b52485e5078472827a165d1d65b418
prerequisite-patch-id: e924638bcd10aabd9ef6c3c3a2eed6984f9dbac7
prerequisite-patch-id: 6bb480bbd14445cc515a890db212d5570f0824d4
prerequisite-message-id: <20251205064357.13591-1-ot_cathy.xu@mediatek.com>
prerequisite-patch-id: 7f2d960cde2f0e0a307721150e83b7b05b9a60d7
prerequisite-message-id: <20250825033136.7705-1-zhanzhan.ge@mediatek.com>
prerequisite-patch-id: 7aeee7d452186b3bc1c11722b7ddb7dfbae7d396
prerequisite-message-id: <20260701-mt8189-mmc-dt-bindings-fix-v1-1-e75f241a275b@collabora.com>
prerequisite-patch-id: 3f6f8e5a3005e7ee4a9f082da6842efaae560d4d
prerequisite-message-id: <20260701-mt8189-dt-bindings-scpsys-v1-1-2c04f0fda1b7@collabora.com>
prerequisite-patch-id: 8982f7b2776e6cae070c41a48076b5a02c97ef2a
prerequisite-message-id: <20260701-mt8189-dt-bindings-pcie-v1-1-7c7a65087654@collabora.com>
prerequisite-patch-id: 8b5cc41be174d3e0768fd43bff843208c0ec200b
prerequisite-message-id: <20260701-mt8189-dt-bindings-tphy-v1-1-5848a2be8303@collabora.com>
prerequisite-patch-id: da74129ef4f3ed94555df4f540f44bee2f5f05f9
prerequisite-message-id: <20260701-mt8189-dt-bindings-uart-dma-v1-1-c7106216a40d@collabora.com>
prerequisite-patch-id: c5894d7c4c71327f7855869cbd8686d0ea610f3e
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* [PATCH v2 2/4] dt-bindings: arm: mediatek: add Mediatek Genio 520/720-EVK boards
From: Louis-Alexis Eyraud @ 2026-07-01 16:35 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang
Cc: kernel, linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-mediatek, Krzysztof Kozlowski, Louis-Alexis Eyraud
In-Reply-To: <20260701-add-mediatek-genio-520-720-evk-v2-0-19d5da4ef984@collabora.com>
Add compatible strings for the Mediatek Genio 520-EVK (based on
MT8371 SoC) and Mediatek Genio 720-EVK (based on MT8391 SoC) boards.
MT8391 and MT8371 SoC are less powerful variants of MT8189 SoC,
with identical hardware register maps.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 382d0eb4d0af..1dd32219f68f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -443,6 +443,11 @@ properties:
- mediatek,mt8370-evk
- const: mediatek,mt8370
- const: mediatek,mt8188
+ - items:
+ - enum:
+ - mediatek,mt8371-evk
+ - const: mediatek,mt8371
+ - const: mediatek,mt8189
- items:
- enum:
- ezurio,mt8390-tungsten-smarc
@@ -450,6 +455,11 @@ properties:
- mediatek,mt8390-evk
- const: mediatek,mt8390
- const: mediatek,mt8188
+ - items:
+ - enum:
+ - mediatek,mt8391-evk
+ - const: mediatek,mt8391
+ - const: mediatek,mt8189
- items:
- enum:
- kontron,3-5-sbc-i1200
--
2.54.0
^ permalink raw reply related
* [PATCH v2 4/4] arm64: dts: mediatek: add Genio 520-EVK board
From: Louis-Alexis Eyraud @ 2026-07-01 16:35 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang
Cc: kernel, linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260701-add-mediatek-genio-520-720-evk-v2-0-19d5da4ef984@collabora.com>
Add devicetree for the basic hardware enablement of the Genio 520-EVK
board, based on MT8371 SoC.
MT8371 SoC is a variant of MT8189 SoC with the following differences:
- Arm Cortex-A78 CPU core maximum frequency (2.2 Ghz for MT8371, 3 Ghz
for MT8189).
- Arm Mali G57 MC2 GPU core maximum frequency (880 Mhz for MT8371, 1.1
Ghz for MT8189)
- one ISP engine instead of two
MT8371 hardware register maps are identical to MT8189.
The Genio 520-EVK has following features:
- MT8371 SoC
- MT6365 PMIC
- MT6319 Buck IC
- MT6375 Charger IC
- 8GB LPDDR5 RAM
- 64GB eMMC 5.1
- 128GB UFS
- 20V DC Jack
- USB Type-C Power Adapter
- Micro SD card slot
- Push Button x 4 (Power, Reset, Download and Home Key)
- LED x 3 (System Power, Reset, DC-IN Power)
- USB Type-C Connector (USB 3.2) x 2
- USB Type-C Connector (USB 2.0) x 1
- 3.5mm Earphone Jack x 1 (with Microphone Input)
- 3.5mm Line Out Audio Jack x 1
- Analog Microphone x 1
- Digital Microphone x 2
- Gigabit Ethernet with RJ45 connector
- DP x 1 (Mode over USB Type-C)
- LVDS port x 1
- eDP port x 1
- UART x2 with serial-to-usb converters and USB Type-C connectors
- UART Port x 2 on Pin Header
- M.2 Slot x 2
- I2C Capacitive Touch Pad
- 4-Lane DSI x 1
- 4-Data Lane CSI x 2
- I2S Pin header
- 40-Pin 2.54mm Pin Header x 1
- CAN Bus x 1 (RS232 Connector)
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
.../boot/dts/mediatek/mt8371-genio-520-evk.dts | 32 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 5c75ea1ef09a..e6a8109ffbaa 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -168,6 +168,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8371-genio-520-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts b/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts
new file mode 100644
index 000000000000..b4fd343bc08a
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+/dts-v1/;
+
+#include "mt8189.dtsi"
+#include "mt8391-genio-common.dtsi"
+
+/*
+ * MT8371 SoC is a variant of the MT8189 with only one ISP engine
+ * and lower maximum frequency on the big cores and on the Mali GPU.
+ */
+
+/ {
+ model = "MediaTek Genio 520 EVK";
+ compatible = "mediatek,mt8371-evk", "mediatek,mt8371",
+ "mediatek,mt8189";
+};
+
+&cpu6 {
+ cpu-supply = <&mt6319_sid6_vbuck1>;
+};
+
+&cpu7 {
+ cpu-supply = <&mt6319_sid6_vbuck1>;
+};
+
+&mt6319_sid6 {
+ status = "okay";
+};
--
2.54.0
^ permalink raw reply related
* [PATCH v2 3/4] arm64: dts: mediatek: add Genio 720-EVK board
From: Louis-Alexis Eyraud @ 2026-07-01 16:35 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Sean Wang
Cc: kernel, linux-kernel, linux-serial, devicetree, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260701-add-mediatek-genio-520-720-evk-v2-0-19d5da4ef984@collabora.com>
Add support for MediaTek MT8189 SoC and its variants, and a devicetree
for the basic hardware enablement of the Genio 720-EVK board, based on
MT8391 SoC.
MT8391 SoC is a variant of MT8189 SoC with a difference for the Arm
Cortex-A78 CPU core maximum frequency (2.6 Ghz for MT8391, 3 Ghz for
MT8189). MT8391 hardware register maps are identical to MT8189.
The Genio 720-EVK board has following features:
- MT8391 SoC
- MT6365 PMIC
- MT6319 Buck IC
- MT6375 Charger IC
- 8GB LPDDR5 RAM
- 64GB eMMC 5.1
- 128GB UFS
- 20V DC Jack
- USB Type-C Power Adapter
- Micro SD card slot
- Push Button x 4 (Power, Reset, Download and Home Key)
- LED x 3 (System Power, Reset, DC-IN Power)
- USB Type-C Connector (USB 3.2) x 2
- USB Type-C Connector (USB 2.0) x 1
- 3.5mm Earphone Jack x 1 (with Microphone Input)
- 3.5mm Line Out Audio Jack x 1
- Analog Microphone x 1
- Digital Microphone x 2
- Gigabit Ethernet with RJ45 connector
- DP x 1 (Mode over USB Type-C)
- LVDS port x 1
- eDP port x 1
- UART x2 with serial-to-usb converters and USB Type-C connectors
- UART Port x 2 on Pin Header
- M.2 Slot x 2
- I2C Capacitive Touch Pad
- 4-Lane DSI x 1
- 4-Data Lane CSI x 2
- I2S Pin header
- 40-Pin 2.54mm Pin Header x 1
- CAN Bus x 1 (RS232 Connector)
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 920 +++++++++++++++++++++
.../boot/dts/mediatek/mt8391-genio-720-evk.dts | 27 +
.../boot/dts/mediatek/mt8391-genio-common.dtsi | 673 +++++++++++++++
4 files changed, 1621 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index a86fb313b1a9..5c75ea1ef09a 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8391-genio-720-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..272b1b34c953
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,920 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ *
+ * Copyright (c) 2025 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mediatek,mt8189-power.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk32k: clock-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "clk32k";
+ };
+
+ clk13m: clock-13m {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&clk26m>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: clock-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clock-520m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <520000000>;
+ clock-output-names = "ulposc";
+ };
+
+ clock-vow-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "vowpll";
+ };
+
+ clock-auxadc-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "aud_adc_ext";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+
+ core6 {
+ cpu = <&cpu6>;
+ };
+
+ core7 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <25>;
+ exit-latency-us = <57>;
+ min-residency-us = <5700>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <35>;
+ exit-latency-us = <82>;
+ min-residency-us = <1890>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ status = "fail";
+ };
+
+ fhctl: fhctl@1000ce00 {
+ compatible = "mediatek,mt8189-fhctl";
+ clocks = <&apmixedsys CLK_APMIXED_APUPLL>,
+ <&apmixedsys CLK_APMIXED_APUPLL2>,
+ <&apmixedsys CLK_APMIXED_ARMPLL_LL>,
+ <&apmixedsys CLK_APMIXED_ARMPLL_BL>,
+ <&apmixedsys CLK_APMIXED_CCIPLL>,
+ <&apmixedsys CLK_APMIXED_EMIPLL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>,
+ <&apmixedsys CLK_APMIXED_MFGPLL>,
+ <&apmixedsys CLK_APMIXED_MMPLL>,
+ <&apmixedsys CLK_APMIXED_MSDCPLL>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>,
+ <&apmixedsys CLK_APMIXED_UFSPLL>;
+ reg = <0 0x1000ce00 0 0x200>;
+ status = "okay";
+ };
+
+ memory: memory@40000000 {
+ device_type = "memory";
+ /* This memory size is filled in by the bootloader */
+ reg = <0 0x40000000 0 0>;
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ performance: performance-controller@108d78 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x00108d78 0 0x120>, <0 0x00108e98 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ apdma: dma-controller@11300b00 {
+ compatible = "mediatek,mt8189-uart-dma", "mediatek,mt6985-uart-dma";
+ reg = <0 0x11300b00 0 0x80>,
+ <0 0x11300b80 0 0x80>,
+ <0 0x11300c00 0 0x80>,
+ <0 0x11300c80 0 0x80>,
+ <0 0x11300d00 0 0x80>,
+ <0 0x11300d80 0 0x80>,
+ <0 0x11300e00 0 0x80>,
+ <0 0x11300e80 0 0x80>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "apdma";
+ dma-requests = <8>;
+ #dma-cells = <1>;
+ };
+
+ auxadc: adc@11019000 {
+ compatible = "mediatek,mt8189-auxadc", "mediatek,mt8173-auxadc";
+ reg = <0 0x11019000 0 0x1000>;
+ clocks = <&peri_ao CLK_PERAO_AUXADC_26M>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ apmixedsys: clock-controller@1000c000 {
+ compatible = "mediatek,mt8189-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@d01a000 {
+ compatible = "mediatek,mt8189-dbg-ao";
+ reg = <0 0xd01a000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@d0a0000 {
+ compatible = "mediatek,mt8189-dem";
+ reg = <0 0xd0a0000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1c00f000 {
+ compatible = "mediatek,mt8189-dvfsrc-top";
+ reg = <0 0x1c00f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iic_wrap_e: clock-controller@11c22e00 {
+ compatible = "mediatek,mt8189-iic-wrap-e";
+ reg = <0 0x11c22e00 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ iic_wrap_en: clock-controller@11f32e00 {
+ compatible = "mediatek,mt8189-iic-wrap-en";
+ reg = <0 0x11f32e00 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ iic_wrap_s: clock-controller@11d74e00 {
+ compatible = "mediatek,mt8189-iic-wrap-s";
+ reg = <0 0x11d74e00 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ iic_wrap_ws: clock-controller@11b21e00 {
+ compatible = "mediatek,mt8189-iic-wrap-ws";
+ reg = <0 0x11b21e00 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ infra_ao: clock-controller@10001000 {
+ compatible = "mediatek,mt8189-infra-ao", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ peri_ao: clock-controller@11036000 {
+ compatible = "mediatek,mt8189-peri-ao", "syscon";
+ reg = <0 0x11036000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8189-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1c80ae10 {
+ compatible = "mediatek,mt8189-scp-i2c-clk";
+ reg = <0 0x1c80ae10 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@1cb21150 {
+ compatible = "mediatek,mt8189-scp-clk";
+ reg = <0 0x1cb21150 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ clock-controller@112b8000 {
+ compatible = "mediatek,mt8189-ufscfg-ao";
+ reg = <0 0x112b8000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@112bb000 {
+ compatible = "mediatek,mt8189-ufscfg-pdn";
+ reg = <0 0x112bb000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@1c000800 {
+ compatible = "mediatek,mt8189-vlpcfg-ao";
+ reg = <0 0x1c000800 0 0x10>;
+ #clock-cells = <1>;
+ };
+
+ vlpcfg: clock-controller@1c00c000 {
+ compatible = "mediatek,mt8189-vlpcfg";
+ reg = <0 0x1c00c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vlpckgen: clock-controller@1c012000 {
+ compatible = "mediatek,mt8189-vlpckgen", "syscon";
+ reg = <0 0x1c012000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ efuse@11f10000 {
+ compatible = "mediatek,mt8189-efuse", "mediatek,mt8186-efuse";
+ reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ socinfo-data1@7a0 {
+ reg = <0x7a0 0x4>;
+ };
+
+ socinfo-data2@7e0 {
+ reg = <0x7e0 0x4>;
+ };
+ };
+
+ i2c0: i2c@11c20000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11c20000 0 0x1000>, <0 0x11300200 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_e CLK_IMPE_I2C0>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11c21000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11c21000 0 0x1000>, <0 0x11300300 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_e CLK_IMPE_I2C1>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11b20000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11b20000 0 0x1000>, <0 0x11300400 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_ws CLK_IMPWS_I2C2>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11d70000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11d70000 0 0x1000>, <0 0x11300500 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_s CLK_IMPS_I2C3>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11d71000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11d71000 0 0x1000>, <0 0x11300600 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_s CLK_IMPS_I2C4>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@11d72000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11d72000 0 0x1000>, <0 0x11300700 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_s CLK_IMPS_I2C5>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11d73000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11d73000 0 0x1000>, <0 0x11300800 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_s CLK_IMPS_I2C6>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@11f30000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11f30000 0 0x1000>, <0 0x11300900 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_en CLK_IMPEN_I2C7>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@11f31000 {
+ compatible = "mediatek,mt8189-i2c", "mediatek,mt8188-i2c";
+ reg = <0 0x11f31000 0 0x1000>, <0 0x11300a00 0 0x80>;
+ #address-cells = <1>;
+ clock-div = <1>;
+ clocks = <&iic_wrap_en CLK_IMPEN_I2C8>, <&peri_ao CLK_PERAO_DMA_B>;
+ clock-names = "main", "dma";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8189-mmc";
+ reg = <0 0x11230000 0 0x10000>, <0 0x11e70000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&peri_ao CLK_PERAO_MSDC0_H>,
+ <&peri_ao CLK_PERAO_MSDC0>,
+ <&topckgen CLK_TOP_MSDC50_0_HCLK_SEL>,
+ <&peri_ao CLK_PERAO_MSDC0_SLV_H>,
+ <&peri_ao CLK_PERAO_MSDC0_MST_F>;
+ clock-names = "source", "hclk", "source_cg",
+ "bus_clk", "pclk_cg", "axi_cg";
+ interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8189-mmc";
+ reg = <0 0x11240000 0 0x1000>, <0 0x11d80000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&peri_ao CLK_PERAO_MSDC1_H>,
+ <&peri_ao CLK_PERAO_MSDC1>,
+ <&topckgen CLK_TOP_MSDC30_1_HCLK_SEL>,
+ <&peri_ao CLK_PERAO_MSDC1_SLV_H>,
+ <&peri_ao CLK_PERAO_MSDC1_MST_F>;
+ clock-names = "source", "hclk", "source_cg",
+ "bus_clk", "pclk_cg", "axi_cg";
+ interrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ pcie: pcie@112f0000 {
+ compatible = "mediatek,mt8189-pcie", "mediatek,mt8192-pcie";
+ reg = <0 0x112f0000 0 0x4000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0 0x30000000 0x0 0x30000000 0 0x04000000>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&peri_ao CLK_PERAO_AHB_APB>,
+ <&topckgen CLK_TOP_F26M_CK_EN>,
+ <&peri_ao CLK_PERAO_TL>,
+ <&clk32k>,
+ <&peri_ao CLK_PERAO_REF>,
+ <&peri_ao CLK_PERAO_AXI>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m",
+ "tl_32k", "peri_26m", "peri_mem";
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ phys = <&pcieport PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&spm MT8189_POWER_DOMAIN_PCIE>;
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ pciephy: t-phy@11e50700 {
+ compatible = "mediatek,mt8189-tphy", "mediatek,generic-tphy-v3";
+ ranges = <0x0 0x0 0x11e50700 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&spm MT8189_POWER_DOMAIN_PCIE_PHY>;
+ status = "disabled";
+
+ pcieport: pcie-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSPXTP_F26M_CK_EN>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8189-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11b50000 0 0x1000>,
+ <0 0x11c50000 0 0x1000>,
+ <0 0x11c60000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e30000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11ce0000 0 0x1000>,
+ <0 0x11de0000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>,
+ <0 0x1c01e000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>;
+ reg-names = "base", "lm", "rb0", "rb1", "bm0", "bm1",
+ "bm2", "lt0", "lt1", "rt", "eint0", "eint1",
+ "eint2", "eint3", "eint4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 182>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ pwrap: pwrap@1cc04000 {
+ compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x1cc04000 0 0x1000>;
+ reg-names = "pwrap";
+ assigned-clocks = <&vlpckgen CLK_VLP_CK_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ clocks = <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>,
+ <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>;
+ clock-names = "spi", "wrap";
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ spmi: spmi@1cc06000 {
+ compatible = "mediatek,mt8189-spmi", "mediatek,mt8195-spmi";
+ reg = <0 0x1cc06000 0 0x0008ff>, <0 0x1cc00000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_P_SYS>,
+ <&vlpcfg CLK_VLPCFG_REG_PMIF_SPMI_P_TMR>,
+ <&vlpckgen CLK_VLP_CK_SPMI_P_MST_SEL>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ scpsys: syscon@1c001000 {
+ compatible = "mediatek,mt8189-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x1c001000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8189-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ power-domain@MT8189_POWER_DOMAIN_CONN {
+ reg = <MT8189_POWER_DOMAIN_CONN>;
+ mediatek,infracfg = <&infra_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8189_POWER_DOMAIN_AUDIO {
+ reg = <MT8189_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>;
+ clock-names = "audio";
+ mediatek,infracfg = <&infra_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8189_POWER_DOMAIN_ADSP_AO {
+ reg = <MT8189_POWER_DOMAIN_ADSP_AO>;
+ clocks = <&vlpckgen CLK_VLP_CK_VADSP_SEL>;
+ clock-names = "vadsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8189_POWER_DOMAIN_ADSP_INFRA {
+ reg = <MT8189_POWER_DOMAIN_ADSP_INFRA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT {
+ reg = <MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8189_POWER_DOMAIN_SSUSB {
+ reg = <MT8189_POWER_DOMAIN_SSUSB>;
+ mediatek,infracfg = <&infra_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8189_POWER_DOMAIN_PCIE {
+ reg = <MT8189_POWER_DOMAIN_PCIE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8189_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8189_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ timer@1cc10000 {
+ compatible = "mediatek,mt8189-timer", "mediatek,mt6765-timer";
+ reg = <0 0x1cc10000 0 0x1000>;
+ clocks = <&clk13m>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ uart0: serial@11001000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&peri_ao CLK_PERAO_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11002000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&peri_ao CLK_PERAO_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11003000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&peri_ao CLK_PERAO_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart3: serial@11004000 {
+ compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&peri_ao CLK_PERAO_UART3>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 6>, <&apdma 7>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ watchdog@1c00a000 {
+ compatible = "mediatek,mt8189-wdt", "mediatek,mt6589-wdt";
+ reg = <0 0x1c00a000 0 0x100>;
+ #reset-cells = <1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts b/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts
new file mode 100644
index 000000000000..717077806e24
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+/dts-v1/;
+
+#include "mt8189.dtsi"
+#include "mt8391-genio-common.dtsi"
+
+/ {
+ model = "MediaTek Genio 720 EVK";
+ compatible = "mediatek,mt8391-evk", "mediatek,mt8391",
+ "mediatek,mt8189";
+};
+
+&cpu6 {
+ cpu-supply = <&mt6319_sid7_vbuck1>;
+};
+
+&cpu7 {
+ cpu-supply = <&mt6319_sid7_vbuck1>;
+};
+
+&mt6319_sid7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi
new file mode 100644
index 000000000000..fbb202e34474
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include "mt6365.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include "mt8189-pinfunc.h"
+
+/ {
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: memory@54600000 {
+ reg = <0 0x54600000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ /* system wide 4.2V power rail from charger */
+ reg_vsys: regulator-vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* used by PCIe Wi-Fi Module */
+ reg_wifi_3v3: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "wifi_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 79 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_3v3_en_pins>;
+ vin-supply = <®_vsys>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&cpu1 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&cpu2 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&cpu3 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&cpu5 {
+ cpu-supply = <&mt6359_vmodem_buck_reg>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "disabled";
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+};
+
+&i2c7 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pins>;
+ status = "okay";
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x1481b>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ supports-cqe;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ max-frequency = <200000000>;
+ no-mmc;
+ no-sdio;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ vmmc-supply = <&mt6359_vpa_buck_reg>;
+ vqmmc-supply = <&mt6359_vsim1_ldo_reg>;
+ status = "okay";
+};
+
+&mt6359_va09_ldo_reg{
+ regulator-name = "dvdd_sram_vadsp";
+ regulator-always-on;
+};
+
+&mt6359_vaux18_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-name = "dvdd_apu";
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-name = "dvdd_sram_core";
+ regulator-always-on;
+};
+
+&mt6359_vmodem_buck_reg {
+ regulator-name = "dvdd_proc_l";
+ regulator-always-on;
+};
+
+&mt6359_vproc1_buck_reg {
+ regulator-name = "vgpu";
+};
+
+&mt6359_vproc2_buck_reg {
+ regulator-name = "dvdd_core";
+ regulator-always-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-name = "avdd075_emi";
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-name = "va12_abb2";
+ regulator-always-on;
+};
+
+&mt6359_vrfck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+ regulator-name = "dvdd_sram_proc_l";
+ regulator-always-on;
+};
+
+&mt6359_vsram_proc1_ldo_reg {
+ regulator-name = "vsram_gpu";
+};
+
+&mt6359_vsram_proc2_ldo_reg {
+ regulator-name = "dvdd_sram_proc_b";
+ regulator-always-on;
+};
+
+&mt6359_vsram_others_ldo_reg {
+ regulator-name = "dvdd_sram_apu";
+ regulator-always-on;
+};
+
+&mt6359_vufs_ldo_reg {
+ regulator-always-on;
+};
+
+&pcie {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie_default_pins>;
+ pinctrl-1 = <&pcie_sleep_pins>;
+ status = "okay";
+};
+
+&pciephy {
+ status = "okay";
+};
+
+&pio {
+ i2c0_pins: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO52__FUNC_SDA0>,
+ <PINMUX_GPIO51__FUNC_SCL0>;
+ bias-pull-up;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO54__FUNC_SDA1>,
+ <PINMUX_GPIO53__FUNC_SCL1>;
+ bias-pull-up;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins {
+ pinmux = <PINMUX_GPIO56__FUNC_SDA2>,
+ <PINMUX_GPIO55__FUNC_SCL2>;
+ bias-pull-up;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins {
+ pinmux = <PINMUX_GPIO58__FUNC_SDA3>,
+ <PINMUX_GPIO57__FUNC_SCL3>;
+ bias-pull-up;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO60__FUNC_SDA4>,
+ <PINMUX_GPIO59__FUNC_SCL4>;
+ bias-pull-up;
+ };
+ };
+ i2c5_pins: i2c5-pins {
+ pins {
+ pinmux = <PINMUX_GPIO62__FUNC_SDA5>,
+ <PINMUX_GPIO61__FUNC_SCL5>;
+ bias-pull-up;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO64__FUNC_SDA6>,
+ <PINMUX_GPIO63__FUNC_SCL6>;
+ bias-pull-up;
+ };
+ };
+
+ i2c7_pins: i2c7-pins {
+ pins {
+ pinmux = <PINMUX_GPIO66__FUNC_SDA7>,
+ <PINMUX_GPIO65__FUNC_SCL7>;
+ bias-pull-up;
+ };
+ };
+
+ i2c8_pins: i2c8-pins {
+ pins {
+ pinmux = <PINMUX_GPIO68__FUNC_SDA8>,
+ <PINMUX_GPIO67__FUNC_SCL8>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO161__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO166__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO161__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO167__FUNC_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO171__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO172__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO173__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO168__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-insert {
+ pinmux = <PINMUX_GPIO2__FUNC_GPIO2>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO170__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO171__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO172__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO173__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO168__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ pcie_default_pins: pcie-default-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO48__FUNC_WAKEN>,
+ <PINMUX_GPIO49__FUNC_PERSTN>,
+ <PINMUX_GPIO50__FUNC_CLKREQN>;
+ bias-pull-up;
+ };
+ };
+
+ pcie_sleep_pins: pcie-sleep-pins {
+ pins {
+ pinmux = <PINMUX_GPIO49__FUNC_PERSTN>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ pcie_3v3_en_pins: pcie-3v3-en-pins {
+ pins {
+ pinmux = <PINMUX_GPIO79__FUNC_GPIO79>;
+ output-high;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO31__FUNC_UTXD0>,
+ <PINMUX_GPIO32__FUNC_URXD0>;
+ bias-pull-up;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO33__FUNC_UTXD1>,
+ <PINMUX_GPIO34__FUNC_URXD1>;
+ bias-pull-up;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <PINMUX_GPIO35__FUNC_UTXD2>,
+ <PINMUX_GPIO36__FUNC_URXD2>;
+ bias-pull-up;
+ };
+
+ pins-rtscts {
+ pinmux = <PINMUX_GPIO16__FUNC_UCTS2>,
+ <PINMUX_GPIO17__FUNC_URTS2>;
+ };
+ };
+
+ uart3_pins: uart3-pins {
+ pins {
+ pinmux = <PINMUX_GPIO37__FUNC_UTXD3>,
+ <PINMUX_GPIO38__FUNC_URXD3>;
+ bias-pull-up;
+ };
+
+ pins-rtscts {
+ pinmux = <PINMUX_GPIO14__FUNC_UCTS3>,
+ <PINMUX_GPIO15__FUNC_URTS3>;
+ };
+ };
+};
+
+&pmic {
+ interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>;
+ vsys-smps-supply = <®_vsys>;
+ vsys-vcore-supply = <®_vsys>;
+ vsys-vgpu11-supply = <®_vsys>;
+ vsys-vgpu12-supply = <®_vsys>;
+ vsys-vpa-supply = <®_vsys>;
+ vsys-vproc1-supply = <®_vsys>;
+ vsys-vproc2-supply = <®_vsys>;
+ vsys-vpu-supply = <®_vsys>;
+ vsys-vs1-supply = <®_vsys>;
+ vsys-vs2-supply = <®_vsys>;
+ vsys-vmodem-supply = <®_vsys>;
+ vsys-ldo1-supply = <®_vsys>;
+ vsys-ldo2-supply = <®_vsys>;
+ vs1-ldo1-supply = <&mt6359_vs1_buck_reg>;
+ vs1-ldo2-supply = <&mt6359_vs1_buck_reg>;
+ vs2-ldo1-supply = <&mt6359_vs2_buck_reg>;
+ vs2-ldo2-supply = <&mt6359_vs2_buck_reg>;
+
+ keys {
+ compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys";
+ mediatek,long-press-mode = <1>;
+ power-off-time-sec = <0>;
+
+ power-key {
+ linux,keycodes = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ home {
+ linux,keycodes = <KEY_HOME>;
+ };
+ };
+};
+
+&spmi {
+ /*
+ * MT6319 PMIC SID can change depending on the boards so add
+ * in this include file the nodes for the possible values,
+ * disabled by default to limit the code duplication.
+ */
+ mt6319_sid6: pmic@6 {
+ compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator";
+ reg = <0x6 SPMI_USID>;
+
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
+ status = "disabled";
+
+ regulators {
+ mt6319_sid6_vbuck1: vbuck1 {
+ regulator-name = "dvdd_proc_b";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ vbuck3 {
+ regulator-name = "vdd2h_emi";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ vbuck4 {
+ regulator-name = "avddq_emi";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ mt6319_sid7: pmic@7 {
+ compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator";
+ reg = <0x7 SPMI_USID>;
+
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
+ status = "disabled";
+
+ regulators {
+ mt6319_sid7_vbuck1: vbuck1 {
+ regulator-name = "dvdd_proc_b";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ vbuck3 {
+ regulator-name = "vdd2h_emi";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+
+ vbuck4 {
+ regulator-name = "avddq_emi";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <256>;
+ regulator-allowed-modes = <0 1 2>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-0 = <&uart3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.54.0
^ permalink raw reply related
* [PATCH 07/12] phy: phy-mtk-dp: Support setting volt swing and preemphasis values
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunfeng.yun
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, chunkuang.hu, p.zabel, justin.yeh,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel, dri-devel, kernel
In-Reply-To: <20260701122008.19509-1-angelogioacchino.delregno@collabora.com>
Add support for honoring the set_voltages request to set the
voltage swing and preemphasis values in the .configure() callback.
For proper hardware cleanup, reset both in the .reset() callback.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/phy-mtk-dp.c | 41 ++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index a2cd22b9da06..17d871530cca 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -48,6 +48,11 @@
/* DP_PHYD_TX_CTL_0 */
#define PHYD_TX_LN_EN GENMASK(7, 4)
+/* DP_PHYD_DRIVING_FORCE */
+#define PHYD_DP_TX_FORCE_VOLT_SWING_EN BIT(0)
+#define PHYD_DP_TX_FORCE_VOLT_SWING_VAL GENMASK(2, 1)
+#define PHYD_DP_TX_FORCE_PRE_EMPH_VAL GENMASK(4, 3)
+
#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)
@@ -101,6 +106,7 @@ enum mtk_dp_phya_ana_glb_regidx {
};
enum mtk_dp_phyd_dig_lane_regidx {
+ DP_PHYD_LAN_DRIVING_FORCE,
DP_PHYD_LAN_DRIVING_PARAM_0,
DP_PHYD_LAN_MAX
};
@@ -121,6 +127,7 @@ static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] = {
};
static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] = {
+ [DP_PHYD_LAN_DRIVING_FORCE] = 0x18,
[DP_PHYD_LAN_DRIVING_PARAM_0] = 0x2c,
};
@@ -235,6 +242,28 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
PHYD_TX_LN_EN, val);
}
+ if (opts->dp.set_voltages) {
+ const u32 reg_drv_force = pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_FORCE];
+
+ if (opts->dp.lanes > 4) {
+ dev_err(&phy->dev, "Wrong lanes config %u\n", opts->dp.lanes);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < opts->dp.lanes; i++) {
+ const u32 off_dig_lane = pdata->off_dig_lane[i];
+ u32 val;
+
+ val = FIELD_PREP(PHYD_DP_TX_FORCE_VOLT_SWING_VAL, opts->dp.voltage[i]);
+ val |= FIELD_PREP(PHYD_DP_TX_FORCE_PRE_EMPH_VAL, opts->dp.pre[i]);
+
+ regmap_update_bits(dp_phy->regmap, off_dig_lane + reg_drv_force,
+ PHYD_DP_TX_FORCE_VOLT_SWING_VAL |
+ PHYD_DP_TX_FORCE_PRE_EMPH_VAL,
+ val);
+ }
+ }
+
regmap_update_bits(dp_phy->regmap,
pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1],
TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
@@ -329,7 +358,8 @@ static int mtk_dp_phy_reset(struct phy *phy)
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
const u32 reg_rst = pdata->regs_dig_glb[DP_PHYD_SW_RST];
- int ret;
+ const u32 reg_drv_force = pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_FORCE];
+ int i, ret;
/* Clearing bits sets reset state */
regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW_RST_PHYD);
@@ -345,6 +375,15 @@ static int mtk_dp_phy_reset(struct phy *phy)
if (ret)
dev_err(dp_phy->dev, "Could not disable lanes during reset!\n");
+ /* Reset Voltage Swing and Preemphasis values */
+ for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++) {
+ const u32 off_dig_lane = pdata->off_dig_lane[i];
+
+ regmap_clear_bits(dp_phy->regmap, off_dig_lane + reg_drv_force,
+ PHYD_DP_TX_FORCE_VOLT_SWING_VAL |
+ PHYD_DP_TX_FORCE_PRE_EMPH_VAL);
+ }
+
return 0;
}
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v3 1/3] KVM: arm64: skip pKVM cache flushes for non cacheable mappings
From: Bradley Morgan @ 2026-07-01 16:40 UTC (permalink / raw)
To: Leonardo Bras
Cc: Marc Zyngier, Oliver Upton, Fuad Tabba, Joey Gouly, Steffen Eiden,
Suzuki K Poulose, Zenghui Yu, Catalin Marinas, Will Deacon,
Quentin Perret, Vincent Donnefort, Gavin Shan, Alexandru Elisei,
linux-arm-kernel, kvmarm, linux-kernel
In-Reply-To: <akU64YK5dqcWGdCD@LeoBrasDK>
On July 1, 2026 5:05:53 PM GMT+01:00, Leonardo Bras <leo.bras@arm.com>
wrote:
>On Wed, Jun 24, 2026 at 04:00:26PM +0000, Bradley Morgan wrote:
>> pKVM keeps its own mapping list for stage 2 operations. Its flush path
>> uses that list directly, so it lost the PTE attribute check done by the
>> generic stage 2 walker.
>>
>> Record whether a mapping is cacheable and skip cache maintenance for
>> mappings that are not cacheable.
>>
>> Fixes: e912efed485a ("KVM: arm64: Introduce the EL1 pKVM MMU")
>> Signed-off-by: Bradley Morgan <include@grrlz.net>
>> ---
>> arch/arm64/kvm/pkvm.c | 51 ++++++++++++++++++++++++++++++++++---------
>> 1 file changed, 41 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c
>> index 428723b1b0f5..ca6e823028c2 100644
>> --- a/arch/arm64/kvm/pkvm.c
>> +++ b/arch/arm64/kvm/pkvm.c
>> @@ -302,9 +302,32 @@ static u64 __pkvm_mapping_start(struct pkvm_mapping
>*m)
>> return m->gfn * PAGE_SIZE;
>> }
>>
>> +#define PKVM_MAPPING_NR_PAGES_MASK GENMASK_ULL(47, 0)
>> +#define PKVM_MAPPING_CACHEABLE BIT_ULL(48)
>
>Out of curiosity here, why do you choose to use bit 48 here instead of,
>let's say, bit 63?
>
>(I know it makes absolutely no difference to inner working here, as there
>should probably not be 2^48 pages in one mapping.)
>
>Thanks!
>Leo
sup Leo, here's a quote from maz
"This thing is already big enough, let's not add a bool right in the
middle (use pahole to find out why this is bad). Given that nr_pages
is for a range, and that the minimum page size uses 12 bits, the
largest number of pages you can have here is 56-12=48 bit wide. That's
another 16 bits worth of flags you can use."
this should just clarify things, any questions, feel more than free to ask!
(btw V4 is coming soon)
>> +
>> +static u64 pkvm_mapping_nr_pages(struct pkvm_mapping *m)
>> +{
>> + return m->nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
>> +}
>> +
>> +static bool pkvm_mapping_is_cacheable(struct pkvm_mapping *m)
>> +{
>> + return m->nr_pages & PKVM_MAPPING_CACHEABLE;
>> +}
>> +
>> +static void pkvm_mapping_set_nr_pages(struct pkvm_mapping *m, u64
>nr_pages,
>> + bool cacheable)
>> +{
>> + WARN_ON_ONCE(nr_pages & ~PKVM_MAPPING_NR_PAGES_MASK);
>> +
>> + m->nr_pages = nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
>> + if (cacheable)
>> + m->nr_pages |= PKVM_MAPPING_CACHEABLE;
>> +}
>> +
>> static u64 __pkvm_mapping_end(struct pkvm_mapping *m)
>> {
>> - return (m->gfn + m->nr_pages) * PAGE_SIZE - 1;
>> + return (m->gfn + pkvm_mapping_nr_pages(m)) * PAGE_SIZE - 1;
>> }
>>
>> INTERVAL_TREE_DEFINE(struct pkvm_mapping, node, u64, __subtree_last,
>> @@ -350,7 +373,7 @@ static int __pkvm_pgtable_stage2_reclaim(struct
>kvm_pgtable *pgt, u64 start, u64
>> continue;
>>
>> page = pfn_to_page(mapping->pfn);
>> - WARN_ON_ONCE(mapping->nr_pages != 1);
>> + WARN_ON_ONCE(pkvm_mapping_nr_pages(mapping) != 1);
>> unpin_user_pages_dirty_lock(&page, 1, true);
>> account_locked_vm(kvm->mm, 1, false);
>> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
>> @@ -369,7 +392,7 @@ static int __pkvm_pgtable_stage2_unshare(struct
>kvm_pgtable *pgt, u64 start, u64
>>
>> for_each_mapping_in_range_safe(pgt, start, end, mapping) {
>> ret = kvm_call_hyp_nvhe(__pkvm_host_unshare_guest, handle, mapping->gfn,
>> - mapping->nr_pages);
>> + pkvm_mapping_nr_pages(mapping));
>> if (WARN_ON(ret))
>> return ret;
>> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
>> @@ -448,7 +471,7 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt,
>u64 addr, u64 size,
>> * permission faults are handled in the relax_perms() path.
>> */
>> if (mapping) {
>> - if (size == (mapping->nr_pages * PAGE_SIZE))
>> + if (size == (pkvm_mapping_nr_pages(mapping) * PAGE_SIZE))
>> return -EAGAIN;
>>
>> /*
>> @@ -472,7 +495,9 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt,
>u64 addr, u64 size,
>> swap(mapping, cache->mapping);
>> mapping->gfn = gfn;
>> mapping->pfn = pfn;
>> - mapping->nr_pages = size / PAGE_SIZE;
>> + pkvm_mapping_set_nr_pages(mapping, size / PAGE_SIZE,
>> + !(prot & (KVM_PGTABLE_PROT_DEVICE |
>> + KVM_PGTABLE_PROT_NORMAL_NC)));
>> pkvm_mapping_insert(mapping, &pgt->pkvm_mappings);
>>
>> return ret;
>> @@ -503,7 +528,7 @@ int pkvm_pgtable_stage2_wrprotect(struct kvm_pgtable
>*pgt, u64 addr, u64 size)
>> lockdep_assert_held(&kvm->mmu_lock);
>> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
>> ret = kvm_call_hyp_nvhe(__pkvm_host_wrprotect_guest, handle, mapping->gfn,
>> - mapping->nr_pages);
>> + pkvm_mapping_nr_pages(mapping));
>> if (WARN_ON(ret))
>> break;
>> }
>> @@ -517,9 +542,13 @@ int pkvm_pgtable_stage2_flush(struct kvm_pgtable
>*pgt, u64 addr, u64 size)
>> struct pkvm_mapping *mapping;
>>
>> lockdep_assert_held(&kvm->mmu_lock);
>> - for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
>> + for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
>> + if (!pkvm_mapping_is_cacheable(mapping))
>> + continue;
>> +
>> __clean_dcache_guest_page(pfn_to_kaddr(mapping->pfn),
>> - PAGE_SIZE * mapping->nr_pages);
>> + PAGE_SIZE * pkvm_mapping_nr_pages(mapping));
>> + }
>>
>> return 0;
>> }
>> @@ -536,8 +565,10 @@ bool pkvm_pgtable_stage2_test_clear_young(struct
>kvm_pgtable *pgt, u64 addr, u64
>>
>> lockdep_assert_held(&kvm->mmu_lock);
>> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
>> - young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest, handle, mapping->gfn,
>> - mapping->nr_pages, mkold);
>> + young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest,
>> + handle, mapping->gfn,
>> + pkvm_mapping_nr_pages(mapping),
>> + mkold);
>>
>> return young;
>> }
>> --
>> 2.53.0
>>
>
Thanks!
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: rtc: Add sii,wakealarm-output-pin property for S35390A
From: Markus Probst @ 2026-07-01 16:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Uwe Kleine-König, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, linux-arm-kernel, linux-rtc, devicetree,
linux-kernel
In-Reply-To: <7de66163-369e-4118-af51-6913b565fa4b@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 1865 bytes --]
On Wed, 2026-07-01 at 17:14 +0200, Krzysztof Kozlowski wrote:
> On 01/07/2026 15:25, Markus Probst wrote:
> > > > +
> > > > +maintainers:
> > > > + - Alexandre Belloni <alexandre.belloni@bootlin.com>
> > >
> > > This should be someone caring about this hardware.
> > He does have the majority of commits on this driver (excluding merge
> > commits and commits not exclusive to this driver), although most of
> > them are pretty tiny.
> >
> > Who would you suggest instead?
>
> Someone adding features for this driver, maybe driver maintainers. But
> if Alexandre is fine, you can leave him.
>
> > >
> > > > +
> > > > +description:
> > > > + The S-35390A is a CMOS 2-wire real-time clock IC which operates with the
> > > > + very low current consumption in the wide range of operation voltage.
> > > > +
> > > > +allOf:
> > > > + - $ref: rtc.yaml#
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: sii,s35390a
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + sii,wakealarm-output-pin:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > + enum: [1, 2]
> > > > + description: |
> > > > + The output pin to wake up the system.
> > > > + Default will use the output pin for interrupt signal 2.
> > > > + <S35390A_OUTPUT_PIN_INT1> : Output pin for interrupt signal 1
> > > > + <S35390A_OUTPUT_PIN_INT2> : Output pin for interrupt signal 2
> > >
> > > Does that mean device generates the interrupts?
> > Yes.
> >
>
>
> Then I think you miss interrupts property.
From what I can tell the line is used to generate a system wakeup
event.
There would be no obvious benefit of connecting it to an interrupt
controller, so this property would be obsolete?
Thanks
- Markus Probst
>
> Best regards,
> Krzysztof
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 870 bytes --]
^ permalink raw reply
* [PATCH v3 0/3] Add devicetree for the Graperain G3568 v2
From: Coia Prant @ 2026-07-01 16:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Dragan Simic, Jonas Karlman
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Coia Prant
Changes in v2:
- Fix trailing whitespaces and other formatting issues.
Changes in v3:
- Picked up Acked-by tag for patch 1.
- Fixed text wrapping in the commit message of patch 2.
- Replace the legacy 'gpio' label with 'gpios'.
- Add the Bluetooth UART child node.
Notes/Unchanged from v1:
- ADC keys have been verified with evtest and works fine; kept unchanged.
- The 'regulator-off-in-suspend' property for vqmmc-supply is retained.
This is a known issue shared by most similar boards and should be
addressed globally later.
---
Coia Prant (3):
dt-bindings: vendor-prefixes: Add graperain
dt-bindings: arm: rockchip: Add Graperain G3568 series
arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2
.../devicetree/bindings/arm/rockchip.yaml | 6 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../rockchip/rk3568-graperain-g3568-v2.dts | 931 ++++++++++++++++++
4 files changed, 940 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts
--
2.47.3
^ permalink raw reply
* [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add graperain
From: Coia Prant @ 2026-07-01 16:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Dragan Simic, Jonas Karlman
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Coia Prant, Krzysztof Kozlowski
In-Reply-To: <20260701164543.3967388-3-coiaprant@gmail.com>
Add graperain to the vendor prefixes.
Link: https://www.graperain.cn/ (China)
Link: https://www.graperain.com/ (Global)
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 396044f368e7c..641a37c0debc9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -682,6 +682,8 @@ patternProperties:
description: Goramo Gorecki
"^gplus,.*":
description: GPLUS
+ "^graperain,.*":
+ description: Shenzhen Graperain Technology Co., Ltd.
"^grinn,.*":
description: Grinn
"^grmn,.*":
--
2.47.3
^ permalink raw reply related
* [PATCH v3 2/3] dt-bindings: arm: rockchip: Add Graperain G3568 series
From: Coia Prant @ 2026-07-01 16:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Dragan Simic, Jonas Karlman
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Coia Prant
In-Reply-To: <20260701164543.3967388-3-coiaprant@gmail.com>
Document the Graperain G3568 v2, which is a development board based on
the Rockchip RK3568 SoC.
Graperain G3568 series also have an SBC series with the suffix "box".
Graperain G3568 v2 belongs to development board series, not SBC series.
Link: https://www.graperain.cn/RK3568/RK3568-Development/ (China)
Link: https://www.graperain.com/ARM-Embedded-RK3568-Development-Board/ (Global)
Link: https://image.chukouplus.com/upload/C_153/product_file/20211022/6daddec9e400458816dd4c57ba807fc3.pdf
Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 1a9dde18626d0..9eb2f66ba3856 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -684,6 +684,12 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
+ - description: Graperain G3568 series board
+ items:
+ - enum:
+ - graperain,g3568-v2
+ - const: rockchip,rk3568
+
- description: H96 Max V58 TV Box
items:
- const: haochuangyi,h96-max-v58
--
2.47.3
^ permalink raw reply related
* [PATCH v3 3/3] arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2
From: Coia Prant @ 2026-07-01 16:45 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Dragan Simic, Jonas Karlman
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
Coia Prant
In-Reply-To: <20260701164543.3967388-3-coiaprant@gmail.com>
The Graperain G3568 v2 is an RK3568-based development board, just like
the RK3568-EVB.
It always uses soldered connections between the GR3568CV2 core board and
the RK3568BV2/GR3568BV2 I/O board.
The G3568 board has multiple hardware revisions, and we currently
support v2 (I/O board).
Specification:
- SoC: RockChip RK3568 ARM64 (4 cores)
- eMMC: 16-128 GB
- RAM: 2-16 GB
- Power: DC 12V 2A
- Ethernet: 2x RTL8211F RGMII (10/100/1000 Mbps)
- Wireless radio: 802.11b/g/n/ac dual-band
- LED:
Power: AlwaysOn
User: GPIO
- Button:
ESC: SARADC/0 <1100k µV>
MENU: SARADC/0 <1400k µV>
VOL-: SARADC/0 <430k µV>
VOL+: SARADC/0 <50k µV>
Power/Reset: PMIC RK809
- CAN
CAN/1: 4-pin (PH 2.0)
- PWM
PWM/4: Backlight
PWM/5: Backlight
PWM/7: IR Receiver
- UART:
UART/2: Debug TTL - 1500000 8N1 (1.25mm)
UART/3: TTL (PH 2.0)
UART/4: TTL (PH 2.0)
UART/8: AP6356S Bluetooth
UART/9: TTL (PH 2.0)
- I2C:
I2C/0: PMIC RK809
I2C/1: Touchscreen
I2C/4: Camera
I2C/5: RTC@51 PCF8563
- I2S:
I2S/0: HDMI Sound
I2S/1: RK809 Audio Codec
I2S/3: AP6356S Bluetooth Sound
- SDMMC:
SDMMC/0: microSD (TF) slot
SDMMC/2: AP6356S SDIO WiFi card
- Camera: 1x CSI
- Video: HDMI / DSI0 (MIPI/LVDS) / DSI1 (MIPI/EDP)
- Audio: HDMI / MIC / Speaker / SPDIF / 3.5mm Headphones / AP6356S Bluetooth
- USB:
USB 2.0 HOST x2
USB 2.0 OTG x1 (shared with USB 3.0 OTG/HOST)
USB 3.0 HOST x1
USB 3.0 OTG/HOST x1
- SATA: 1x SATA 3.0 with Power/4-pin
- PCIe: 1x PCIe 3.0 x2 (x4 connector)
Link:
- https://image.chukouplus.com/upload/C_153/product_file/20211022/6daddec9e400458816dd4c57ba807fc3.pdf
- https://blog.gov.cooking/archives/research-graperain-g3568-v2-and-flash.html
Signed-off-by: Coia Prant <coiaprant@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../rockchip/rk3568-graperain-g3568-v2.dts | 931 ++++++++++++++++++
2 files changed, 932 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 761d82b4f4f2a..6e9d049e8ddaf 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-graperain-g3568-v2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts b/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts
new file mode 100644
index 0000000000000..ee1ba8e106142
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts
@@ -0,0 +1,931 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Graperain G3568 v2";
+ compatible = "graperain,g3568-v2", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
+ rtc0 = &rtc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-esc {
+ label = "esc";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1250000>;
+ };
+
+ button-menu {
+ label = "menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <1600000>;
+ };
+
+ button-vol-down {
+ label = "volume down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <600000>;
+ };
+
+ button-vol-up {
+ label = "volume up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <100000>;
+ };
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_work: led-0 {
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_BLUE>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_work_en>;
+ };
+ };
+
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
+ pdm_codec: pdm-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ #sound-dai-cells = <0>;
+ };
+
+ pdm_sound: pdm-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "microphone";
+
+ simple-audio-card,cpu {
+ sound-dai = <&pdm>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&pdm_codec>;
+ };
+ };
+
+ spdif_dit: spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <300>;
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ };
+
+ dc_12v: regulator-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_pcie_en_pin>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: regulator-vcc5v0-usb {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: regulator-vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: regulator-vcc5v0-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+};
+
+&can1 {
+ assigned-clocks = <&cru CLK_CAN1>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m1_pins>;
+ status = "okay";
+};
+
+/* used for usb_host0_xhci */
+&combphy0 {
+ status = "okay";
+};
+
+/* used for usb_host1_xhci */
+&combphy1 {
+ status = "okay";
+};
+
+/* connected to sata2 */
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ system-power-controller;
+ #sound-dai-cells = <0>;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ codec {
+ rockchip,mic-in-differential;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ rtc0: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+/* used for AP6356S Bluetooth Sound */
+&i2s3_2ch {
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
+ };
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pin>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pdm {
+ status = "okay";
+};
+
+&pinctrl {
+ bluetooth {
+ bt_reg_on_h_gpio3_a0: bt-reg-on-h-gpio4-b2 {
+ rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_h_gpio3_a1: bt-wake-host-h-gpio4-b4 {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ host_wake_bt_h_gpio3_a2: host-wake-bt-h-gpio4-b5 {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led_work_en: led_work_en {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable: wifi-enable {
+ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0_usb_host_en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_reset_pin: pcie-reset-pin {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm5 {
+ status = "okay";
+};
+
+/* Required remotectl for IR receiver */
+&pwm7 {
+ status = "disabled";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+/* used for eMMC */
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+/* used for microSD (TF) Slot */
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+/* used for AP6356S WiFi */
+&sdmmc2 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4356-fmac";
+ reg = <1>;
+ };
+};
+
+&spdif {
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+/* used for Debug */
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-0 = <&uart3m1_xfer>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-0 = <&uart4m1_xfer>;
+ status = "okay";
+};
+
+/* used for AP6356S Bluetooth */
+&uart8 {
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+ max-speed = <1500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h_gpio3_a0
+ &bt_wake_host_h_gpio3_a1
+ &host_wake_bt_h_gpio3_a2>;
+ shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
+
+&uart9 {
+ pinctrl-0 = <&uart9m1_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--
2.47.3
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: rtc: Add sii,wakealarm-output-pin property for S35390A
From: Alexandre Belloni @ 2026-07-01 16:48 UTC (permalink / raw)
To: Markus Probst
Cc: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Uwe Kleine-König, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, linux-arm-kernel, linux-rtc, devicetree,
linux-kernel
In-Reply-To: <d06dd0726aa3795ae99df5fa8a9c05d6e2001efd.camel@posteo.de>
On 01/07/2026 16:43:07+0000, Markus Probst wrote:
> On Wed, 2026-07-01 at 17:14 +0200, Krzysztof Kozlowski wrote:
> > On 01/07/2026 15:25, Markus Probst wrote:
> > > > > +
> > > > > +maintainers:
> > > > > + - Alexandre Belloni <alexandre.belloni@bootlin.com>
> > > >
> > > > This should be someone caring about this hardware.
> > > He does have the majority of commits on this driver (excluding merge
> > > commits and commits not exclusive to this driver), although most of
> > > them are pretty tiny.
> > >
> > > Who would you suggest instead?
> >
> > Someone adding features for this driver, maybe driver maintainers. But
> > if Alexandre is fine, you can leave him.
> >
> > > >
> > > > > +
> > > > > +description:
> > > > > + The S-35390A is a CMOS 2-wire real-time clock IC which operates with the
> > > > > + very low current consumption in the wide range of operation voltage.
> > > > > +
> > > > > +allOf:
> > > > > + - $ref: rtc.yaml#
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + const: sii,s35390a
> > > > > +
> > > > > + reg:
> > > > > + maxItems: 1
> > > > > +
> > > > > + sii,wakealarm-output-pin:
> > > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > > + enum: [1, 2]
> > > > > + description: |
> > > > > + The output pin to wake up the system.
> > > > > + Default will use the output pin for interrupt signal 2.
> > > > > + <S35390A_OUTPUT_PIN_INT1> : Output pin for interrupt signal 1
> > > > > + <S35390A_OUTPUT_PIN_INT2> : Output pin for interrupt signal 2
> > > >
> > > > Does that mean device generates the interrupts?
> > > Yes.
> > >
> >
> >
> > Then I think you miss interrupts property.
> From what I can tell the line is used to generate a system wakeup
> event.
>
> There would be no obvious benefit of connecting it to an interrupt
> controller, so this property would be obsolete?
>
Then you need proper wakeup-source support
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v2 01/14] firmware: arm_scmi: Fix OF node reference handling
From: Sudeep Holla @ 2026-07-01 16:52 UTC (permalink / raw)
To: arm-scmi, linux-arm-kernel; +Cc: Cristian Marussi
In-Reply-To: <20260701-scmi_core_fixes-v2-0-1f5e85553f73@kernel.org>
SCMI devices store the DT node in dev.of_node through
device_set_node(), but that helper only assigns the fwnode and
of_node pointers without taking an OF node reference.
Take a reference when assigning the node and release it from the
SCMI device release path. With the device owning that reference,
remove the separate channel-side get/put pair from the core driver.
Fixes: 96da4a99ce50 ("firmware: arm_scmi: Set fwnode for the scmi_device")
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
drivers/firmware/arm_scmi/bus.c | 3 ++-
drivers/firmware/arm_scmi/driver.c | 4 ----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/firmware/arm_scmi/bus.c b/drivers/firmware/arm_scmi/bus.c
index 793be9eabaed..f643a1f0e282 100644
--- a/drivers/firmware/arm_scmi/bus.c
+++ b/drivers/firmware/arm_scmi/bus.c
@@ -395,6 +395,7 @@ static void scmi_device_release(struct device *dev)
{
struct scmi_device *scmi_dev = to_scmi_dev(dev);
+ of_node_put(dev->of_node);
kfree_const(scmi_dev->name);
kfree(scmi_dev);
}
@@ -465,7 +466,7 @@ __scmi_device_create(struct device_node *np, struct device *parent,
scmi_dev->id = id;
scmi_dev->protocol_id = protocol;
scmi_dev->dev.parent = parent;
- device_set_node(&scmi_dev->dev, of_fwnode_handle(np));
+ device_set_node(&scmi_dev->dev, of_fwnode_handle(of_node_get(np)));
scmi_dev->dev.bus = &scmi_bus_type;
scmi_dev->dev.release = scmi_device_release;
dev_set_name(&scmi_dev->dev, "scmi_dev.%d", id);
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index 3e0d975ec94c..b9245238e293 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -2778,13 +2778,11 @@ static int scmi_chan_setup(struct scmi_info *info, struct device_node *of_node,
devm_kfree(info->dev, cinfo);
return -EINVAL;
}
- of_node_get(of_node);
cinfo->id = prot_id;
cinfo->dev = &tdev->dev;
ret = info->desc->ops->chan_setup(cinfo, info->dev, tx);
if (ret) {
- of_node_put(of_node);
scmi_device_destroy(info->dev, prot_id, name);
devm_kfree(info->dev, cinfo);
return ret;
@@ -2807,7 +2805,6 @@ static int scmi_chan_setup(struct scmi_info *info, struct device_node *of_node,
"unable to allocate SCMI idr slot err %d\n", ret);
/* Destroy channel and device only if created by this call. */
if (tdev) {
- of_node_put(of_node);
scmi_device_destroy(info->dev, prot_id, name);
devm_kfree(info->dev, cinfo);
}
@@ -2892,7 +2889,6 @@ static int scmi_chan_destroy(int id, void *p, void *idr)
struct scmi_info *info = handle_to_scmi_info(cinfo->handle);
struct scmi_device *sdev = to_scmi_dev(cinfo->dev);
- of_node_put(cinfo->dev->of_node);
scmi_device_destroy(info->dev, id, sdev->name);
cinfo->dev = NULL;
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 02/14] firmware: arm_scmi: Fix transport device teardown lookup
From: Sudeep Holla @ 2026-07-01 16:52 UTC (permalink / raw)
To: arm-scmi, linux-arm-kernel; +Cc: Cristian Marussi
In-Reply-To: <20260701-scmi_core_fixes-v2-0-1f5e85553f73@kernel.org>
SCMI transport devices are deliberately excluded from normal SCMI bus
matching so protocol drivers cannot bind to the internal transport
children. However, scmi_device_destroy() uses the same protocol/name
lookup to find devices that must be unregistered during channel teardown.
Split the match helper so driver matching still skips transport devices,
while explicit child lookup can find them for teardown. Use a shared
transport-device name prefix macro for both matching and name generation.
Since transport-device names are derived from direction and protocol ID,
reject duplicate protocol channel setup before creating or finding a
transport device. This prevents malformed firmware with duplicate
protocol child nodes from reusing an existing transport device and then
destroying it when the duplicate IDR insertion fails.
Fixes: 9593804c44c2 ("firmware: arm_scmi: Exclude transport devices from bus matching")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
---
drivers/firmware/arm_scmi/bus.c | 22 +++++++++++++++++-----
drivers/firmware/arm_scmi/common.h | 2 ++
drivers/firmware/arm_scmi/driver.c | 5 ++++-
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/firmware/arm_scmi/bus.c b/drivers/firmware/arm_scmi/bus.c
index f643a1f0e282..d4beefa4234f 100644
--- a/drivers/firmware/arm_scmi/bus.c
+++ b/drivers/firmware/arm_scmi/bus.c
@@ -201,21 +201,33 @@ scmi_protocol_table_unregister(const struct scmi_device_id *id_table)
scmi_protocol_device_unrequest(entry);
}
-static int scmi_dev_match_by_id_table(struct scmi_device *scmi_dev,
- const struct scmi_device_id *id_table)
+static bool scmi_device_is_transport(const struct scmi_device *scmi_dev)
+{
+ return !strncmp(scmi_dev->name, SCMI_TRANSPORT_DEVNAME_PREFIX,
+ strlen(SCMI_TRANSPORT_DEVNAME_PREFIX));
+}
+
+static int __scmi_dev_match_by_id_table(struct scmi_device *scmi_dev,
+ const struct scmi_device_id *id_table,
+ bool skip_transport)
{
if (!id_table || !id_table->name)
return 0;
- /* Always skip transport devices from matching */
for (; id_table->protocol_id && id_table->name; id_table++)
if (id_table->protocol_id == scmi_dev->protocol_id &&
- strncmp(scmi_dev->name, "__scmi_transport_device", 23) &&
+ !(skip_transport && scmi_device_is_transport(scmi_dev)) &&
!strcmp(id_table->name, scmi_dev->name))
return 1;
return 0;
}
+static int scmi_dev_match_by_id_table(struct scmi_device *scmi_dev,
+ const struct scmi_device_id *id_table)
+{
+ return __scmi_dev_match_by_id_table(scmi_dev, id_table, true);
+}
+
static int scmi_dev_match_id(struct scmi_device *scmi_dev,
const struct scmi_driver *scmi_drv)
{
@@ -235,7 +247,7 @@ static int scmi_match_by_id_table(struct device *dev, const void *data)
struct scmi_device *scmi_dev = to_scmi_dev(dev);
const struct scmi_device_id *id_table = data;
- return scmi_dev_match_by_id_table(scmi_dev, id_table);
+ return __scmi_dev_match_by_id_table(scmi_dev, id_table, false);
}
static struct scmi_device *scmi_child_dev_find(struct device *parent,
diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h
index b9723c105fc1..fe8c22cfb9f7 100644
--- a/drivers/firmware/arm_scmi/common.h
+++ b/drivers/firmware/arm_scmi/common.h
@@ -34,6 +34,8 @@
#define SCMI_SHMEM_MAX_PAYLOAD_SIZE 104
+#define SCMI_TRANSPORT_DEVNAME_PREFIX "__scmi_transport_device"
+
enum scmi_error_codes {
SCMI_SUCCESS = 0, /* Success */
SCMI_ERR_SUPPORT = -1, /* Not supported */
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index b9245238e293..b9ba566fc759 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -2751,6 +2751,9 @@ static int scmi_chan_setup(struct scmi_info *info, struct device_node *of_node,
idx = tx ? 0 : 1;
idr = tx ? &info->tx_idr : &info->rx_idr;
+ if (idr_find(idr, prot_id))
+ return -EEXIST;
+
if (!info->desc->ops->chan_available(of_node, idx)) {
cinfo = idr_find(idr, SCMI_PROTOCOL_BASE);
if (unlikely(!cinfo)) /* Possible only if platform has no Rx */
@@ -2768,7 +2771,7 @@ static int scmi_chan_setup(struct scmi_info *info, struct device_node *of_node,
cinfo->no_completion_irq = info->desc->no_completion_irq;
/* Create a unique name for this transport device */
- snprintf(name, 32, "__scmi_transport_device_%s_%02X",
+ snprintf(name, sizeof(name), SCMI_TRANSPORT_DEVNAME_PREFIX "_%s_%02X",
idx ? "rx" : "tx", prot_id);
/* Create a uniquely named, dedicated transport device for this chan */
tdev = scmi_device_create(of_node, info->dev, prot_id, name);
--
2.43.0
^ permalink raw reply related
* [PATCH v2 00/14] firmware: arm_scmi: Fix SCMI core cleanup paths
From: Sudeep Holla @ 2026-07-01 16:52 UTC (permalink / raw)
To: arm-scmi, linux-arm-kernel; +Cc: Cristian Marussi
This series fixes a set of SCMI core and mailbox transport lifetime issues
found around device creation, channel setup failure, notification teardown
and malformed firmware descriptions.
Most of these issues were found by Sashiko[1][2] while reviewing the ACPI SCMI
PCC work[3]. They are posted separately because the problems are independent
SCMI core and mailbox transport cleanup bugs, and do not depend on the ACPI
PCC series.
Here is the attempt to fix them, some of them can be dropped if it is too
theoretical. I have addressed all the issues that made sense to me at the
time of reading the report.
The fixes tighten ownership and teardown rules for generated SCMI devices,
transport devices and transport channels. They make internal transport
devices reachable by explicit teardown without exposing them to normal SCMI
driver binding, ensure partially initialized channels are unwound on setup
failures, and avoid IDR/device lifetime races during probe failure and device
unbind.
The series also fixes notifier and notification teardown ordering. Requested
device notifiers are unregistered before protocol IDRs are destroyed, RCU is
used around requested-device protocol lookups, and transport callbacks are
stopped before notification state is released.
The mailbox transport fixes cover both setup failure unwinding and an early
interrupt window: mailbox callbacks can run as soon as mbox_request_channel()
binds the client and starts the controller, so the SCMI mailbox transport now
publishes its cinfo before requesting channels.
Fixes tags need to be checked again or even dropped if it is not a stable
material. Just some placeholders that I thought are appropriated are in place.
Summary:
- Fix OF node reference ownership for generated SCMI devices.
- Allow explicit teardown lookup of internal transport devices.
- Clean up TX/RX channels when SCMI channel setup fails midway.
- Fix SCMI device lifetime handling around child lookup and bus ID reuse.
- Free transport resources when IDR insertion fails after channel setup.
- Unregister requested-device notifier before active protocol IDR teardown.
- Unwind mailbox channels on TX receiver and P2A receiver setup failures.
- Protect requested-device protocol lookup with RCU.
- Avoid modifying an IDR while iterating it during channel cleanup.
- Clear the SystemPower singleton flag on SCMI device creation failure.
- Reject out-of-range DT protocol IDs instead of allowing u8 truncation.
- Stop transport callbacks before releasing notification state.
- Publish mailbox cinfo before requesting mailbox channels.
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
[1] https://sashiko.dev/#/patchset/20260525-acpi_scmi_pcc-v2-0-4f38938d08d8@arm.com
[2] https://sashiko.dev/#/patchset/20260630-scmi_core_fixes-v1-0-f932c1e51992@kernel.org
[3] https://patch.msgid.link/20260525-acpi_scmi_pcc-v2-0-4f38938d08d8@arm.com
---
Changes in v2:
(Mostly addressing the additional issues found by Sashiko)
- Added fixes for IDR mutation during channel cleanup.
- Added SystemPower singleton flag unwind on device creation failure.
- Added validation to skip out-of-range DT protocol IDs.
- Moved notification teardown after transport channel cleanup.
- Published mailbox cinfo before mbox_request_channel() can enable callbacks.
- Link to v1: https://patch.msgid.link/20260630-scmi_core_fixes-v1-0-f932c1e51992@kernel.org
---
Sudeep Holla (14):
firmware: arm_scmi: Fix OF node reference handling
firmware: arm_scmi: Fix transport device teardown lookup
firmware: arm_scmi: Clean up channels on setup failure
firmware: arm_scmi: Fix SCMI device destroy lifetimes
firmware: arm_scmi: Free transport channel on IDR failure
firmware: arm_scmi: Unregister device notifier before IDR teardown
firmware: arm_scmi: Unwind TX receiver mailbox setup failure
firmware: arm_scmi: Unwind P2A receiver mailbox setup failure
firmware: arm_scmi: Protect device request lookup with RCU
firmware: arm_scmi: Avoid IDR updates while cleaning channels
firmware: arm_scmi: Clear SystemPower flag on create failure
firmware: arm_scmi: Reject out of range DT protocol IDs
firmware: arm_scmi: Stop channels before notification teardown
firmware: arm_scmi: Publish mailbox cinfo before channel request
drivers/firmware/arm_scmi/bus.c | 72 ++++++++++++++++----------
drivers/firmware/arm_scmi/common.h | 2 +
drivers/firmware/arm_scmi/driver.c | 44 +++++++++-------
drivers/firmware/arm_scmi/transports/mailbox.c | 26 +++++++---
4 files changed, 90 insertions(+), 54 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260629-scmi_core_fixes-da3cd753b4ea
--
Regards,
Sudeep
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox