From: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jessica.zhang@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Subject: Re: [PATCH v3 15/38] drm/msm/dp: use stream_id to change offsets in dp_catalog
Date: Wed, 1 Apr 2026 14:33:49 +0800 [thread overview]
Message-ID: <0037ba69-c104-488c-a388-8d31dcbbc78f@oss.qualcomm.com> (raw)
In-Reply-To: <vrbxqjfvg6urywwmehoykz463vphfg6c2qiryedulvlrcbvals@55lm4fmgf3in>
On 8/26/2025 2:01 AM, Dmitry Baryshkov wrote:
> On Mon, Aug 25, 2025 at 10:16:01PM +0800, Yongxing Mou wrote:
>> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>> Use the dp_panel's stream_id to adjust the offsets for stream 1
>> which will be used for MST in the dp_catalog. Stream 1 share the
>> same link clk with stream 0 with different reg offset. Also add
>
> Shares what? How do we handle streams 2 and 3?
>
Stream 0 and stream 1 are controlled by *_DPTX0_LCLK, stream 2 uses
*_MST_2_LCLK, and stream 3 uses *_MST_3_LCLK. Will update commit message.
>> additional register defines for stream 1.
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++---
>> drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++------------
>> drivers/gpu/drm/msm/dp/dp_reg.h | 9 +++++
>> 3 files changed, 79 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> index d4a74c6b70fb182ad8a0a786f85a0f50982d3858..b8b6a09966aed96f705bdd54cb16ea63e5f0141f 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> @@ -384,6 +384,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,
>> struct msm_dp_panel *msm_dp_panel)
>> {
>> u32 config = 0, tbd;
>> + u32 reg_offset = 0;
>>
>> config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL);
>>
>> @@ -400,7 +401,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl,
>>
>> drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config);
>>
>> - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config);
>> + if (msm_dp_panel->stream_id == DP_STREAM_1)
>> + reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL;
>> }
>>
>> static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl)
>> @@ -451,12 +453,16 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
>> struct msm_dp_panel *msm_dp_panel)
>> {
>> u32 colorimetry_cfg, test_bits_depth, misc_val;
>> + u32 reg_offset = 0;
>>
>> test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link,
>> msm_dp_panel->msm_dp_mode.bpp);
>> colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link);
>>
>> - misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0);
>> + if (msm_dp_panel->stream_id == DP_STREAM_1)
>> + reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
>> +
>> + misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset);
>>
>> /* clear bpp bits */
>> misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT);
>> @@ -466,7 +472,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl,
>> misc_val |= DP_MISC0_SYNCHRONOUS_CLK;
>>
>> drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val);
>> - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val);
>> + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val);
>> }
>>
>> static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl,
>> @@ -2431,6 +2437,7 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl)
>> }
>>
>> static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
>> + struct msm_dp_panel *msm_dp_panel,
>> u32 rate, u32 stream_rate_khz,
>> bool is_ycbcr_420)
>> {
>> @@ -2440,6 +2447,12 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
>> u32 const link_rate_hbr2 = 540000;
>> u32 const link_rate_hbr3 = 810000;
>> unsigned long den, num;
>> + u32 mvid_reg_off = 0, nvid_reg_off = 0;
>> +
>> + if (msm_dp_panel->stream_id == DP_STREAM_1) {
>> + mvid_reg_off = REG_DP1_SOFTWARE_MVID - REG_DP_SOFTWARE_MVID;
>> + nvid_reg_off = REG_DP1_SOFTWARE_NVID - REG_DP_SOFTWARE_NVID;
>> + }
>>
>> if (rate == link_rate_hbr3)
>> pixel_div = 6;
>> @@ -2482,8 +2495,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
>> nvid *= 3;
>>
>> drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
>> - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid);
>> - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid);
>> + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid);
>> + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid);
>> }
>>
>> int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train)
>> @@ -2559,6 +2572,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *
>> msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel);
>>
>> msm_dp_ctrl_config_msa(ctrl,
>> + msm_dp_panel,
>> ctrl->link->link_params.rate,
>> pixel_rate_orig,
>> msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420);
>> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
>> index e8c1cf0c7dab7217b8bfe7ecd586af33d7547ca9..d1af389dffcfee2d21a616de6ee027374997aaee 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
>> @@ -377,27 +377,35 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct
>> u32 header[2];
>> u32 val;
>> int i;
>> + u32 offset = 0;
>> +
>> + if (panel->msm_dp_panel.stream_id == DP_STREAM_1)
>> + offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0;
>>
>> msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header);
>>
>> - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]);
>> - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]);
>> + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]);
>> + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]);
>>
>> for (i = 0; i < sizeof(vsc_sdp->db); i += 4) {
>> val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) |
>> (vsc_sdp->db[i + 3] << 24));
>> - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val);
>> + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val);
>> }
>> }
>>
>> static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel)
>> {
>> u32 hw_revision = panel->msm_dp_panel.hw_revision;
>> + u32 offset = 0;
>> +
>> + if (panel->msm_dp_panel.stream_id == DP_STREAM_1)
>> + offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3;
>>
>> if (hw_revision >= DP_HW_VERSION_1_0 &&
>> hw_revision < DP_HW_VERSION_1_2) {
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP);
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0);
>> }
>> }
>>
>> @@ -406,16 +414,25 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd
>> struct msm_dp_panel_private *panel =
>> container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
>> u32 cfg, cfg2, misc;
>> + u32 misc_reg_offset = 0;
>> + u32 sdp_cfg_offset = 0;
>> + u32 sdp_cfg2_offset = 0;
>> +
>> + if (msm_dp_panel->stream_id == DP_STREAM_1) {
>> + misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
>> + sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
>> + sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
>> + }
>>
>> - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG);
>> - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2);
>> - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0);
>> + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset);
>> + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset);
>> + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset);
>>
>> cfg |= GEN0_SDP_EN;
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg);
>>
>> cfg2 |= GENERIC0_SDPSIZE_VALID;
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2);
>>
>> msm_dp_panel_send_vsc_sdp(panel, vsc_sdp);
>>
>> @@ -425,7 +442,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd
>> drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n");
>>
>> pr_debug("misc settings = 0x%x\n", misc);
>> - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
>> + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc);
>>
>> msm_dp_panel_update_sdp(panel);
>> }
>> @@ -435,16 +452,25 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)
>> struct msm_dp_panel_private *panel =
>> container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
>> u32 cfg, cfg2, misc;
>> + u32 misc_reg_offset = 0;
>> + u32 sdp_cfg_offset = 0;
>> + u32 sdp_cfg2_offset = 0;
>> +
>> + if (msm_dp_panel->stream_id == DP_STREAM_1) {
>> + misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0;
>> + sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG;
>> + sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2;
>> + }
>>
>> - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG);
>> - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2);
>> - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0);
>> + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset);
>> + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset);
>> + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset);
>>
>> cfg &= ~GEN0_SDP_EN;
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg);
>>
>> cfg2 &= ~GENERIC0_SDPSIZE_VALID;
>> - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2);
>> + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2);
>>
>> /* switch back to MSA */
>> misc &= ~DP_MISC1_VSC_SDP;
>> @@ -452,7 +478,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel)
>> drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n");
>>
>> pr_debug("misc settings = 0x%x\n", misc);
>> - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc);
>> + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc);
>>
>> msm_dp_panel_update_sdp(panel);
>> }
>> @@ -510,6 +536,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)
>> u32 msm_dp_active;
>> u32 total;
>> u32 reg;
>> + u32 offset = 0;
>>
>> panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
>> drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode;
>> @@ -524,6 +551,9 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)
>> drm_mode->vsync_start - drm_mode->vdisplay,
>> drm_mode->vsync_end - drm_mode->vsync_start);
>>
>> + if (msm_dp_panel->stream_id == DP_STREAM_1)
>> + offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER;
>> +
>> total_hor = drm_mode->htotal;
>>
>> total_ver = drm_mode->vtotal;
>> @@ -554,10 +584,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en)
>>
>> msm_dp_active = data;
>>
>> - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total);
>> - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);
>> - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);
>> - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active);
>> + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total);
>> + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start);
>> + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking);
>> + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active);
>>
>> reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG);
>> if (wide_bus_en)
>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
>> index b851efc132ea03884ce2563990fbc24c9577e724..43a9ce0539906e1f185abf250fdf161e462d9645 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
>> @@ -141,6 +141,7 @@
>> #define DP_STATE_CTRL_PUSH_IDLE (0x00000100)
>>
>> #define REG_DP_CONFIGURATION_CTRL (0x00000008)
>> +#define REG_DP1_CONFIGURATION_CTRL (0x00000400)
>> #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001)
>> #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002)
>> #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004)
>> @@ -159,11 +160,15 @@
>> #define REG_DP_SOFTWARE_MVID (0x00000010)
>> #define REG_DP_SOFTWARE_NVID (0x00000018)
>> #define REG_DP_TOTAL_HOR_VER (0x0000001C)
>> +#define REG_DP1_SOFTWARE_MVID (0x00000414)
>> +#define REG_DP1_SOFTWARE_NVID (0x00000418)
>> +#define REG_DP1_TOTAL_HOR_VER (0x0000041C)
>> #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020)
>> #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024)
>> #define REG_DP_ACTIVE_HOR_VER (0x00000028)
>>
>> #define REG_DP_MISC1_MISC0 (0x0000002C)
>> +#define REG_DP1_MISC1_MISC0 (0x0000042C)
>> #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001)
>> #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001)
>> #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005)
>> @@ -230,8 +235,10 @@
>> #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214)
>>
>> #define MMSS_DP_SDP_CFG (0x00000228)
>> +#define MMSS_DP1_SDP_CFG (0x000004E0)
>> #define GEN0_SDP_EN (0x00020000)
>> #define MMSS_DP_SDP_CFG2 (0x0000022C)
>> +#define MMSS_DP1_SDP_CFG2 (0x000004E4)
>> #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230)
>> #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234)
>> #define GENERIC0_SDPSIZE_VALID (0x00010000)
>> @@ -240,6 +247,7 @@
>> #define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
>>
>> #define MMSS_DP_SDP_CFG3 (0x0000024c)
>> +#define MMSS_DP1_SDP_CFG3 (0x000004E8)
>> #define UPDATE_SDP (0x00000001)
>>
>> #define MMSS_DP_EXTENSION_0 (0x00000250)
>> @@ -288,6 +296,7 @@
>> #define MMSS_DP_GENERIC1_7 (0x00000344)
>> #define MMSS_DP_GENERIC1_8 (0x00000348)
>> #define MMSS_DP_GENERIC1_9 (0x0000034C)
>> +#define MMSS_DP1_GENERIC0_0 (0x00000490)
>>
>> #define MMSS_DP_VSCEXT_0 (0x000002D0)
>> #define MMSS_DP_VSCEXT_1 (0x000002D4)
>>
>> --
>> 2.34.1
>>
>
next prev parent reply other threads:[~2026-04-01 6:33 UTC|newest]
Thread overview: 138+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-25 14:15 [PATCH v3 00/38] drm/msm/dp: Add MST support for MSM chipsets Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 01/38] drm/msm/dp: remove cached drm_edid from panel Yongxing Mou
2025-08-25 16:41 ` Dmitry Baryshkov
2025-09-02 8:42 ` Yongxing Mou
2025-09-02 9:36 ` Dmitry Baryshkov
2025-09-02 10:19 ` Yongxing Mou
2025-09-02 12:34 ` Dmitry Baryshkov
2025-11-25 6:37 ` Yongxing Mou
2025-11-26 0:44 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 02/38] drm/msm/dp: remove dp_display's dp_mode and use dp_panel's instead Yongxing Mou
2025-08-25 16:50 ` Dmitry Baryshkov
2026-03-30 7:51 ` Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 03/38] drm/msm/dp: break up dp_display_enable into two parts Yongxing Mou
2025-08-25 17:13 ` Dmitry Baryshkov
2026-03-30 7:53 ` Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 04/38] drm/msm/dp: re-arrange dp_display_disable() into functional parts Yongxing Mou
2025-08-25 17:25 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 05/38] drm/msm/dp: splite msm_dp_ctrl_config_ctrl() into link parts and stream parts Yongxing Mou
2025-08-25 17:28 ` Dmitry Baryshkov
2026-03-30 9:00 ` Yongxing Mou
2026-03-30 10:33 ` Dmitry Baryshkov
2026-03-30 11:26 ` Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 06/38] drm/msm/dp: extract MISC1_MISC0 configuration into a separate function Yongxing Mou
2025-08-25 17:30 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 07/38] drm/msm/dp: allow dp_ctrl stream APIs to use any panel passed to it Yongxing Mou
2025-08-25 17:32 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 08/38] drm/msm/dp: move the pixel clock control to its own API Yongxing Mou
2025-08-25 17:34 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 09/38] drm/msm/dp: split dp_ctrl_off() into stream and link parts Yongxing Mou
2025-08-25 17:35 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 10/38] drm/msm/dp: make bridge helpers use dp_display to allow re-use Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 11/38] drm/msm/dp: separate dp_display_prepare() into its own API Yongxing Mou
2025-08-25 17:39 ` Dmitry Baryshkov
2026-03-30 9:46 ` Yongxing Mou
2026-03-30 10:33 ` Dmitry Baryshkov
2025-08-25 14:15 ` [PATCH v3 12/38] drm/msm/dp: introduce max_streams for DP controller MST support Yongxing Mou
2025-08-25 17:42 ` Dmitry Baryshkov
2026-03-30 9:57 ` Yongxing Mou
2026-03-30 10:35 ` Dmitry Baryshkov
2026-03-30 11:32 ` Yongxing Mou
2026-03-30 11:42 ` Dmitry Baryshkov
2026-03-30 11:52 ` Yongxing Mou
2025-09-02 9:41 ` Dmitry Baryshkov
2026-03-30 9:59 ` Yongxing Mou
2026-03-30 10:36 ` Dmitry Baryshkov
2026-03-30 11:36 ` Yongxing Mou
2025-08-25 14:15 ` [PATCH v3 13/38] drm/msm/dp: introduce stream_id for each DP panel Yongxing Mou
2025-08-25 17:56 ` Dmitry Baryshkov
2026-03-30 10:00 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 14/38] drm/msm/dp: Add support for programming p1/p2/p3 register blocks Yongxing Mou
2025-08-25 17:59 ` Dmitry Baryshkov
2026-03-30 10:27 ` Yongxing Mou
2026-03-30 10:39 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 15/38] drm/msm/dp: use stream_id to change offsets in dp_catalog Yongxing Mou
2025-08-25 18:01 ` Dmitry Baryshkov
2026-04-01 6:33 ` Yongxing Mou [this message]
2026-04-01 11:26 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 16/38] drm/msm/dp: Add catalog support for 3rd/4th stream MST Yongxing Mou
2025-08-25 20:35 ` Dmitry Baryshkov
2026-04-01 6:40 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 17/38] drm/msm/dp: add support to send ACT packets for MST Yongxing Mou
2025-08-25 21:10 ` Dmitry Baryshkov
2026-04-01 6:44 ` Yongxing Mou
2026-04-01 6:47 ` Dmitry Baryshkov
2026-04-01 6:55 ` Yongxing Mou
2026-04-01 11:27 ` Dmitry Baryshkov
2026-04-09 11:33 ` Yongxing Mou
2026-04-09 14:08 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 18/38] drm/msm/dp: Add support to enable MST in mainlink control Yongxing Mou
2025-08-25 21:24 ` Dmitry Baryshkov
2026-04-01 6:46 ` Yongxing Mou
2026-04-01 6:49 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 19/38] drm/msm/dp: no need to update tu calculation for mst Yongxing Mou
2025-08-25 21:25 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 20/38] drm/msm/dp: Add support for MST channel slot allocation Yongxing Mou
2025-08-25 21:52 ` Dmitry Baryshkov
2026-04-01 7:20 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 21/38] drm/msm/dp: Add support for sending VCPF packets in DP controller Yongxing Mou
2025-08-26 21:28 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 22/38] drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases Yongxing Mou
2025-08-25 21:55 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 23/38] drm/msm/dp: abstract out the dp_display stream helpers to accept a panel Yongxing Mou
2025-08-25 22:18 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 24/38] drm/msm/dp: replace power_on with active_stream_cnt for dp_display Yongxing Mou
2025-08-25 22:22 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 25/38] drm/msm/dp: Mark the SST bridge disconnected when mst is active Yongxing Mou
2025-08-25 22:23 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 26/38] drm/msm/dp: add an API to initialize MST on sink side Yongxing Mou
2025-08-26 9:26 ` Dmitry Baryshkov
2026-04-07 4:19 ` Yongxing Mou
2026-04-09 14:11 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 27/38] drm/msm/dp: add dp_display_get_panel() to initialize DP panel Yongxing Mou
2025-08-26 16:33 ` Dmitry Baryshkov
2026-04-01 9:43 ` Yongxing Mou
2026-04-01 11:29 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 28/38] drm/msm/dp: add dp_mst_drm to manage DP MST bridge operations Yongxing Mou
2025-08-26 17:36 ` Dmitry Baryshkov
2026-04-01 7:07 ` Yongxing Mou
2026-04-01 7:29 ` Dmitry Baryshkov
2026-04-07 7:42 ` Yongxing Mou
2026-04-09 14:13 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 29/38] drm/msm/dp: add MST atomic check to msm_atomic_check() Yongxing Mou
2025-08-26 17:44 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 30/38] drm/msm/dp: add connector abstraction for DP MST Yongxing Mou
2025-08-26 18:31 ` Dmitry Baryshkov
2026-04-09 4:01 ` Yongxing Mou
2026-04-09 14:50 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 31/38] drm/msm/dp: add HPD callback for dp MST Yongxing Mou
2025-08-26 18:40 ` Dmitry Baryshkov
2026-03-24 13:04 ` Yongxing Mou
2026-03-24 19:30 ` Dmitry Baryshkov
2026-04-14 9:51 ` Yongxing Mou
2026-04-14 18:43 ` Dmitry Baryshkov
2026-04-15 10:32 ` Yongxing Mou
2026-04-19 0:29 ` Dmitry Baryshkov
2026-05-14 7:12 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 32/38] drm/msm/dp: propagate MST state changes to dp mst module Yongxing Mou
2025-08-26 18:43 ` Dmitry Baryshkov
2026-04-07 2:38 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 33/38] drm/msm: add support for MST non-blocking commits Yongxing Mou
2025-08-26 18:47 ` Dmitry Baryshkov
2026-04-07 2:36 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 34/38] drm/msm: initialize DRM MST encoders for DP controllers Yongxing Mou
2025-08-26 18:55 ` Dmitry Baryshkov
2026-04-07 2:35 ` Yongxing Mou
2026-04-09 14:50 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 35/38] drm/msm/dp: initialize dp_mst module for each DP MST controller Yongxing Mou
2025-08-26 21:27 ` Dmitry Baryshkov
2026-04-07 2:33 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 36/38] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id Yongxing Mou
2025-08-26 23:42 ` Dmitry Baryshkov
2026-04-07 2:32 ` Yongxing Mou
2026-04-09 14:52 ` Dmitry Baryshkov
2025-08-25 14:16 ` [PATCH v3 37/38] drm/msm/dp: fix the intf_type of MST interfaces Yongxing Mou
2025-08-27 1:18 ` Dmitry Baryshkov
2025-11-25 6:47 ` Yongxing Mou
2025-08-25 14:16 ` [PATCH v3 38/38] drm/msm/dp: Add MST stream support for SA8775P DP controller 0 and 1 Yongxing Mou
2025-08-27 1:19 ` Dmitry Baryshkov
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