Re: [PATCH v3 18/38] drm/msm/dp: Add support to enable MST in mainlink control

[Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>]

On 01/04/2026 09:46, Yongxing Mou wrote:
> 
> 
> On 8/26/2025 5:24 AM, Dmitry Baryshkov wrote:
>> On Mon, Aug 25, 2025 at 10:16:04PM +0800, Yongxing Mou wrote:
>>> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>>
>>> Add support to program the MST enable bit in the mainlink control
>>> register when an MST session is active or being disabled.
>>>
>>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
>>> ---
>>>   drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++
>>>   drivers/gpu/drm/msm/dp/dp_reg.h  |  1 +
>>>   2 files changed, 18 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/ 
>>> dp/dp_reg.h
>>> index 
>>> de3d0b8b52c269fd7575edf3f4096a4284ad0b8d..fda847b33f8d0d6ec4d2589586b5a3d6c9b1ccf3 100644
>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
>>> @@ -128,6 +128,7 @@
>>>   #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP    
>>> FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1)
>>>   #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE    
>>> FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3)
>>>   #define DP_MAINLINK_FB_BOUNDARY_SEL        (0x02000000)
>>> +#define DP_MAINLINK_CTRL_MST_EN            (0x04000100)
>>
>> Why are there two bits?
>>
> Bit 8 enables MST, and bit 26 was set to select the required ECF 
> endianness.
> 
> 27:26    ECF_MODE        MST ECF Endianness
> 
>                                    0x0: [63:56], [55:48], ... [7:0]
> 
>                                    0x1: [7:0], [15:8], ... [63:56]
> 
>                                    0x2: [56:63], [48:55], ... [0:7]
> 
>                                    0x3: [0:7], [8:15], ... [56:63]
> 
> 8    MST_EN        Multi Stream Enable

You can guess, #define them separately (and the ECF should be the GENMASK).

>>>   #define REG_DP_STATE_CTRL            (0x00000004)
>>>   #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1    (0x00000001)
>>>
>>> -- 
>>> 2.34.1
>>>
>>
> 


-- 
With best wishes
Dmitry