[RFC PATCH 0/8] Fix TCSR representation on SM8750

[RFC PATCH 0/8] Fix TCSR representation on SM8750

[Konrad Dybcio]

As sparked by this thread:
<20260112151725.2308971-1-mukesh.ojha@oss.qualcomm.com>

The current representation of TCSR is wrong.

On platforms post and including SM8550, the TCSR had a sub-block in it,
containing gate clocks used for distributing the XO output to various
consumers. This is what we refer to as TCSR_CC upstream.

SM8750 however, is notably different. That same set of tunables had
been moved to the TLMM register space. This is made worse, as the
sm8750-tcsrcc driver consumes the qcom,sm8750-tcsr compatible.

This hardware change had been undone with the generation following
8750.

This series attempts to unwind that. It's difficult to merge, both for
bindings and functional reasons..

I think it goes without saying this breaks backwards compatibility, but
it has to be done to represent TCSR at all. The patches are ordered in
a least-destructive order..

I gave this a quick spin on (remote) hw, the UFS (one of the consumers)
still works, but more testing would be greatly appreciated.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Konrad Dybcio (8):
      dt-bindings: Move qcom,sm8750-tcsr from clock/tcsr to mfd/tcsr
      dt-bindings: pinctrl: qcom,sm8750-tlmm: Allow clocks/clock-cells
      pinctrl: qcom: Allow exposing reference clocks living in TLMM reg space
      pinctrl: qcom: sm8750: Expose reference clocks
      arm64: dts: qcom: Remove inexistent TCSR_CC
      clk: qcom: Remove tcsrcc-sm8750
      arm64: dts: qcom: sm8750: Describe TCSR
      arm64: defconfig: Remove CONFIG_SM_TCSRCC_8750

 .../bindings/clock/qcom,sm8550-tcsr.yaml           |   2 -
 .../devicetree/bindings/mfd/qcom,tcsr.yaml         |   1 +
 .../bindings/pinctrl/qcom,sm8750-tlmm.yaml         |  12 ++
 arch/arm64/boot/dts/qcom/sm8750.dtsi               |  27 ++--
 arch/arm64/configs/defconfig                       |   1 -
 drivers/clk/qcom/Kconfig                           |   8 --
 drivers/clk/qcom/Makefile                          |   1 -
 drivers/clk/qcom/tcsrcc-sm8750.c                   | 141 ---------------------
 drivers/pinctrl/qcom/pinctrl-msm.c                 |  92 ++++++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h                 |  14 ++
 drivers/pinctrl/qcom/pinctrl-sm8750.c              |  31 +++++
 11 files changed, 163 insertions(+), 167 deletions(-)
---
base-commit: 4c87cdd0328495759f6e9f9f4e1e53ef8032a76f
change-id: 20260202-topic-8750_tcsr-e2dafc2f11d1

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

[PATCH RFC 1/8] dt-bindings: Move qcom,sm8750-tcsr from clock/tcsr to mfd/tcsr

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The TCSR block is described in two places: clock/qcom,sm8550-tcsr.yaml
and mfd/qcom,tcsr.yaml.

The former refers to the version of the block containing various gate
clocks, downstream from the main system refclk.

The latter refers to a version lacking that, instead only providing
various general tunables.

The clock gates on SM8750 specifically (unlike a generation preceding
and following it) do NOT live in TCSR, but in the TLMM (pinmux/cfg IP)
register space instead. Move it to the mfd/tcsr binding to represent
that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml | 2 --
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml          | 1 +
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
index 784fef830681..8da8f44fc8a5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -18,7 +18,6 @@ description: |
   - include/dt-bindings/clock/qcom,glymur-tcsr.h
   - include/dt-bindings/clock/qcom,sm8550-tcsr.h
   - include/dt-bindings/clock/qcom,sm8650-tcsr.h
-  - include/dt-bindings/clock/qcom,sm8750-tcsr.h
 
 properties:
   compatible:
@@ -30,7 +29,6 @@ properties:
           - qcom,sar2130p-tcsr
           - qcom,sm8550-tcsr
           - qcom,sm8650-tcsr
-          - qcom,sm8750-tcsr
           - qcom,x1e80100-tcsr
       - const: syscon
 
diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index 14ae3f00ef7e..1a1fa2b79476 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -39,6 +39,7 @@ properties:
           - qcom,sm8250-tcsr
           - qcom,sm8350-tcsr
           - qcom,sm8450-tcsr
+          - qcom,sm8750-tcsr
           - qcom,tcsr-apq8064
           - qcom,tcsr-apq8084
           - qcom,tcsr-ipq5018

-- 
2.52.0

[PATCH RFC 2/8] dt-bindings: pinctrl: qcom,sm8750-tlmm: Allow clocks/clock-cells

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

On SM8750 specifically, the TLMM block register space contains a number
of gates that forward the system XO (reference) clock to various IP
blocks.

Allow '#clock-cells' (since it provides clocks) and 'clocks' (so that
the parent clock may be consumed and linked with the clocks provided).

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 .../devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml        | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml
index 7aecc97745a8..136366d89290 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml
@@ -19,6 +19,10 @@ properties:
   compatible:
     const: qcom,sm8750-tlmm
 
+  clocks:
+    items:
+      - description: RPMh XO clock
+
   reg:
     maxItems: 1
 
@@ -32,6 +36,9 @@ properties:
   gpio-line-names:
     maxItems: 215
 
+  '#clock-cells':
+    const: 1
+
 patternProperties:
   "-state$":
     oneOf:
@@ -100,6 +107,8 @@ $defs:
 required:
   - compatible
   - reg
+  - clocks
+  - '#clock-cells'
 
 unevaluatedProperties: false
 
@@ -109,6 +118,7 @@ examples:
     tlmm: pinctrl@f100000 {
         compatible = "qcom,sm8750-tlmm";
         reg = <0x0f100000 0x300000>;
+        clocks = <&rpmhcc_xo>;
         gpio-controller;
         #gpio-cells = <2>;
         gpio-ranges = <&tlmm 0 0 216>;
@@ -116,6 +126,8 @@ examples:
         #interrupt-cells = <2>;
         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 
+        #clock-cells = <1>;
+
         gpio-wo-state {
             pins = "gpio1";
             function = "gpio";

-- 
2.52.0

[PATCH RFC 3/8] pinctrl: qcom: Allow exposing reference clocks living in TLMM reg space

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Certain platforms (at least SM8750) had a number of registers
(responsible for gating refclk output to various consumers) moved to
TLMM. They're simple on/off toggles.

Expose them from the msm-pinctrl driver to allow for a reasonable DT
representation.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 92 ++++++++++++++++++++++++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h | 14 ++++++
 2 files changed, 106 insertions(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index e99871b90ab9..1a52431a8605 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -4,6 +4,7 @@
  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  */
 
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio/driver.h>
@@ -16,6 +17,7 @@
 #include <linux/pm.h>
 #include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/reboot.h>
+#include <linux/regmap.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
@@ -80,6 +82,7 @@ struct msm_pinctrl {
 	const struct msm_pinctrl_soc_data *soc;
 	void __iomem *regs[MAX_NR_TILES];
 	u32 phys_base[MAX_NR_TILES];
+	struct ref_clk ref_clks[];
 };
 
 #define MSM_ACCESSOR(name) \
@@ -1525,9 +1528,69 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
 
 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
 
+static int clkref_enable(struct clk_hw *hw)
+{
+	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
+	u32 val;
+
+	regmap_write(rclk->regmap, rclk->init.offset, BIT(0));
+	udelay(10);
+
+	regmap_read(rclk->regmap, rclk->init.offset, &val);
+
+	return (val & BIT(0)) ? 0 : -EINVAL;
+}
+
+static void clkref_disable(struct clk_hw *hw)
+{
+	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
+
+	regmap_write(rclk->regmap, rclk->init.offset, 0);
+
+	udelay(10);
+}
+
+static int clkref_is_enabled(struct clk_hw *hw)
+{
+	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
+	u32 val;
+
+	regmap_read(rclk->regmap, rclk->init.offset, &val);
+
+	return !!val;
+}
+
+static const struct clk_ops clkref_ops = {
+	.enable = clkref_enable,
+	.disable = clkref_disable,
+	.is_enabled = clkref_is_enabled,
+};
+
+static struct clk_hw *msm_pinctrl_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct msm_pinctrl *pctrl = data;
+	u32 idx = clkspec->args[0];
+
+	if (idx >= pctrl->soc->num_ref_clks)
+		return ERR_PTR(-EINVAL);
+
+	return &pctrl->ref_clks[idx].hw;
+}
+
+static const struct clk_parent_data clkref_parent_data = {
+	.index = 0, /* RPM(h) XO clock */
+};
+
+static const struct regmap_config clkref_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+};
+
 int msm_pinctrl_probe(struct platform_device *pdev,
 		      const struct msm_pinctrl_soc_data *soc_data)
 {
+	struct device *dev = &pdev->dev;
 	const struct pinfunction *func;
 	struct msm_pinctrl *pctrl;
 	struct resource *res;
@@ -1595,6 +1658,35 @@ int msm_pinctrl_probe(struct platform_device *pdev,
 	if (ret)
 		return ret;
 
+	if (soc_data->num_ref_clks) {
+		struct regmap *regmap = devm_regmap_init_mmio(dev, pctrl->regs[0],
+							      &clkref_regmap_config);
+		if (IS_ERR(regmap))
+			return PTR_ERR(regmap);
+
+		for (int i = 0; i < soc_data->num_ref_clks; i++) {
+			struct clk_hw *hw = &pctrl->ref_clks[i].hw;
+			struct clk_init_data init = { };
+
+			init.name = pctrl->soc->ref_clks[i]->name;
+			init.parent_data = &clkref_parent_data;
+			init.num_parents = 1;
+			init.ops = &clkref_ops;
+			hw->init = &init;
+
+			ret = devm_clk_hw_register(dev, hw);
+			if (ret)
+				return dev_err_probe(dev, ret, "Couldn't register clock %s\n",
+						     init.name);
+
+			pctrl->ref_clks[i].regmap = regmap;
+		}
+
+		ret = devm_of_clk_add_hw_provider(dev, msm_pinctrl_clk_get, pctrl);
+		if (ret)
+			return dev_err_probe(dev, ret, "Couldn't register clk provider\n");
+	}
+
 	platform_set_drvdata(pdev, pctrl);
 
 	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 4625fa5320a9..213cc789711d 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -5,6 +5,7 @@
 #ifndef __PINCTRL_MSM_H__
 #define __PINCTRL_MSM_H__
 
+#include <linux/clk-provider.h>
 #include <linux/pm.h>
 #include <linux/types.h>
 
@@ -129,6 +130,17 @@ struct msm_gpio_wakeirq_map {
 	unsigned int wakeirq;
 };
 
+struct ref_clk_init_data {
+	const char * const name;
+	u32 offset;
+};
+
+struct ref_clk {
+	struct clk_hw hw;
+	struct regmap *regmap;
+	struct ref_clk_init_data init;
+};
+
 /**
  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
  * @pins:	    An array describing all pins the pin controller affects.
@@ -170,6 +182,8 @@ struct msm_pinctrl_soc_data {
 	bool wakeirq_dual_edge_errata;
 	unsigned int gpio_func;
 	unsigned int egpio_func;
+	const struct ref_clk_init_data **ref_clks;
+	unsigned int num_ref_clks;
 };
 
 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;

-- 
2.52.0

Re: [PATCH RFC 3/8] pinctrl: qcom: Allow exposing reference clocks living in TLMM reg space

[Dmitry Baryshkov]

On Mon, Feb 02, 2026 at 03:57:35PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Certain platforms (at least SM8750) had a number of registers
> (responsible for gating refclk output to various consumers) moved to
> TLMM. They're simple on/off toggles.
> 
> Expose them from the msm-pinctrl driver to allow for a reasonable DT
> representation.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  drivers/pinctrl/qcom/pinctrl-msm.c | 92 ++++++++++++++++++++++++++++++++++++++
>  drivers/pinctrl/qcom/pinctrl-msm.h | 14 ++++++
>  2 files changed, 106 insertions(+)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index e99871b90ab9..1a52431a8605 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -4,6 +4,7 @@
>   * Copyright (c) 2013, The Linux Foundation. All rights reserved.
>   */
>  
> +#include <linux/clk-provider.h>
>  #include <linux/delay.h>
>  #include <linux/err.h>
>  #include <linux/gpio/driver.h>
> @@ -16,6 +17,7 @@
>  #include <linux/pm.h>
>  #include <linux/firmware/qcom/qcom_scm.h>
>  #include <linux/reboot.h>
> +#include <linux/regmap.h>
>  #include <linux/seq_file.h>
>  #include <linux/slab.h>
>  #include <linux/spinlock.h>
> @@ -80,6 +82,7 @@ struct msm_pinctrl {
>  	const struct msm_pinctrl_soc_data *soc;
>  	void __iomem *regs[MAX_NR_TILES];
>  	u32 phys_base[MAX_NR_TILES];
> +	struct ref_clk ref_clks[];
>  };
>  
>  #define MSM_ACCESSOR(name) \
> @@ -1525,9 +1528,69 @@ SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
>  
>  EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
>  
> +static int clkref_enable(struct clk_hw *hw)
> +{
> +	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
> +	u32 val;
> +
> +	regmap_write(rclk->regmap, rclk->init.offset, BIT(0));
> +	udelay(10);
> +
> +	regmap_read(rclk->regmap, rclk->init.offset, &val);
> +
> +	return (val & BIT(0)) ? 0 : -EINVAL;
> +}
> +
> +static void clkref_disable(struct clk_hw *hw)
> +{
> +	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
> +
> +	regmap_write(rclk->regmap, rclk->init.offset, 0);
> +
> +	udelay(10);
> +}
> +
> +static int clkref_is_enabled(struct clk_hw *hw)
> +{
> +	struct ref_clk *rclk = container_of(hw, struct ref_clk, hw);
> +	u32 val;
> +
> +	regmap_read(rclk->regmap, rclk->init.offset, &val);
> +
> +	return !!val;
> +}
> +
> +static const struct clk_ops clkref_ops = {
> +	.enable = clkref_enable,
> +	.disable = clkref_disable,
> +	.is_enabled = clkref_is_enabled,
> +};
> +
> +static struct clk_hw *msm_pinctrl_clk_get(struct of_phandle_args *clkspec, void *data)
> +{
> +	struct msm_pinctrl *pctrl = data;
> +	u32 idx = clkspec->args[0];
> +
> +	if (idx >= pctrl->soc->num_ref_clks)
> +		return ERR_PTR(-EINVAL);
> +
> +	return &pctrl->ref_clks[idx].hw;
> +}
> +
> +static const struct clk_parent_data clkref_parent_data = {
> +	.index = 0, /* RPM(h) XO clock */
> +};
> +
> +static const struct regmap_config clkref_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +};
> +
>  int msm_pinctrl_probe(struct platform_device *pdev,
>  		      const struct msm_pinctrl_soc_data *soc_data)
>  {
> +	struct device *dev = &pdev->dev;
>  	const struct pinfunction *func;
>  	struct msm_pinctrl *pctrl;
>  	struct resource *res;
> @@ -1595,6 +1658,35 @@ int msm_pinctrl_probe(struct platform_device *pdev,
>  	if (ret)
>  		return ret;
>  
> +	if (soc_data->num_ref_clks) {
> +		struct regmap *regmap = devm_regmap_init_mmio(dev, pctrl->regs[0],
> +							      &clkref_regmap_config);
> +		if (IS_ERR(regmap))
> +			return PTR_ERR(regmap);
> +
> +		for (int i = 0; i < soc_data->num_ref_clks; i++) {
> +			struct clk_hw *hw = &pctrl->ref_clks[i].hw;
> +			struct clk_init_data init = { };
> +
> +			init.name = pctrl->soc->ref_clks[i]->name;
> +			init.parent_data = &clkref_parent_data;
> +			init.num_parents = 1;
> +			init.ops = &clkref_ops;
> +			hw->init = &init;
> +
> +			ret = devm_clk_hw_register(dev, hw);
> +			if (ret)
> +				return dev_err_probe(dev, ret, "Couldn't register clock %s\n",
> +						     init.name);
> +
> +			pctrl->ref_clks[i].regmap = regmap;

This will access beyond the end of the allocated chunk, because you
haven't extended pctrl allocation.

> +		}
> +
> +		ret = devm_of_clk_add_hw_provider(dev, msm_pinctrl_clk_get, pctrl);
> +		if (ret)
> +			return dev_err_probe(dev, ret, "Couldn't register clk provider\n");
> +	}
> +
>  	platform_set_drvdata(pdev, pctrl);
>  
>  	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
> index 4625fa5320a9..213cc789711d 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.h
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.h
> @@ -5,6 +5,7 @@
>  #ifndef __PINCTRL_MSM_H__
>  #define __PINCTRL_MSM_H__
>  
> +#include <linux/clk-provider.h>
>  #include <linux/pm.h>
>  #include <linux/types.h>
>  
> @@ -129,6 +130,17 @@ struct msm_gpio_wakeirq_map {
>  	unsigned int wakeirq;
>  };
>  
> +struct ref_clk_init_data {
> +	const char * const name;
> +	u32 offset;
> +};
> +
> +struct ref_clk {
> +	struct clk_hw hw;
> +	struct regmap *regmap;
> +	struct ref_clk_init_data init;
> +};
> +
>  /**
>   * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
>   * @pins:	    An array describing all pins the pin controller affects.
> @@ -170,6 +182,8 @@ struct msm_pinctrl_soc_data {
>  	bool wakeirq_dual_edge_errata;
>  	unsigned int gpio_func;
>  	unsigned int egpio_func;
> +	const struct ref_clk_init_data **ref_clks;
> +	unsigned int num_ref_clks;
>  };
>  
>  extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
> 
> -- 
> 2.52.0
> 

-- 
With best wishes
Dmitry

[PATCH RFC 4/8] pinctrl: qcom: sm8750: Expose reference clocks

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The gating toggles were moved to the TLMM register space on this
platform. They lived inside TCSR a generation prior and are back there
again a generation after.

Expose them, so that they can be consumed by other blocks.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/pinctrl/qcom/pinctrl-sm8750.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c
index 6f92f176edd4..1d29cc89e72f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8750.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c
@@ -9,6 +9,8 @@
 
 #include "pinctrl-msm.h"
 
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+
 #define REG_SIZE 0x1000
 
 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)	\
@@ -1682,6 +1684,33 @@ static const struct msm_gpio_wakeirq_map sm8750_pdc_map[] = {
 	{ 204, 158 }, { 205, 107 }, { 209, 159 },
 };
 
+static const struct ref_clk_init_data pcie_0_refclk = {
+	.name = "pcie_0_clkref",
+	.offset = 0x104008,
+};
+
+static const struct ref_clk_init_data ufs_refclk = {
+	.name = "ufs_clkref",
+	.offset = 0x105008,
+};
+
+static const struct ref_clk_init_data usb2_refclk = {
+	.name = "usb2_clkref",
+	.offset = 0x106008,
+};
+
+static const struct ref_clk_init_data usb3_refclk = {
+	.name = "usb3_clkref",
+	.offset = 0x107008,
+};
+
+static const struct ref_clk_init_data *sm8750_ref_clks[] = {
+	[TCSR_PCIE_0_CLKREF_EN] = &pcie_0_refclk,
+	[TCSR_UFS_CLKREF_EN] = &ufs_refclk,
+	[TCSR_USB2_CLKREF_EN] = &usb2_refclk,
+	[TCSR_USB3_CLKREF_EN] = &usb3_refclk,
+};
+
 static const struct msm_pinctrl_soc_data sm8750_tlmm = {
 	.pins = sm8750_pins,
 	.npins = ARRAY_SIZE(sm8750_pins),
@@ -1693,6 +1722,8 @@ static const struct msm_pinctrl_soc_data sm8750_tlmm = {
 	.wakeirq_map = sm8750_pdc_map,
 	.nwakeirq_map = ARRAY_SIZE(sm8750_pdc_map),
 	.egpio_func = 11,
+	.ref_clks = sm8750_ref_clks,
+	.num_ref_clks = ARRAY_SIZE(sm8750_ref_clks),
 };
 
 static int sm8750_tlmm_probe(struct platform_device *pdev)

-- 
2.52.0

Re: [PATCH RFC 4/8] pinctrl: qcom: sm8750: Expose reference clocks

[Abel Vesa]

On 26-02-02 15:57:36, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> The gating toggles were moved to the TLMM register space on this
> platform. They lived inside TCSR a generation prior and are back there
> again a generation after.
> 
> Expose them, so that they can be consumed by other blocks.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

On SM8750 specifically, the block which provides various reference
clocks does *NOT* live inside TCSR, but rather TLMM.

With the former now being able to properly expose them, switch over to
the proper source.

Now, the TCSR still exists as a block for various tunables and
switches, however the prior misuse resulted in its 8750-specifc
compatible being already in use. With it freed up, it is now free again
to be described properly.

Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index f56b1f889b85..0c034ba0517f 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2727,7 +2727,7 @@ usb_hsphy: phy@88e3000 {
 			compatible = "qcom,sm8750-m31-eusb2-phy";
 			reg = <0x0 0x88e3000 0x0 0x29c>;
 
-			clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
+			clocks = <&tlmm TCSR_USB2_CLKREF_EN>;
 			clock-names = "ref";
 
 			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
@@ -2742,7 +2742,7 @@ usb_dp_qmpphy: phy@88e8000 {
 			reg = <0x0 0x088e8000 0x0 0x4000>;
 
 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
-				 <&tcsrcc TCSR_USB3_CLKREF_EN>,
+				 <&tlmm TCSR_USB3_CLKREF_EN>,
 				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
 				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 			clock-names = "aux",
@@ -3063,6 +3063,8 @@ tlmm: pinctrl@f100000 {
 			compatible = "qcom,sm8750-tlmm";
 			reg = <0x0 0x0f100000 0x0 0x102000>;
 
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
@@ -3074,6 +3076,8 @@ tlmm: pinctrl@f100000 {
 			gpio-ranges = <&tlmm 0 0 216>;
 			wakeup-parent = <&pdc>;
 
+			#clock-cells = <1>;
+
 			hub_i2c0_data_clk: hub-i2c0-data-clk-state {
 				/* SDA, SCL */
 				pins = "gpio64", "gpio65";
@@ -3564,16 +3568,6 @@ data-pins {
 			};
 		};
 
-		tcsrcc: clock-controller@f204008 {
-			compatible = "qcom,sm8750-tcsr", "syscon";
-			reg = <0x0 0x0f204008 0x0 0x3004>;
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
 		stm@10002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x10002000 0x0 0x1000>,
@@ -4818,7 +4812,7 @@ pcie0_phy: phy@1c06000 {
 
 			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
 				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
-				 <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+				 <&tlmm TCSR_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
 			clock-names = "aux",
@@ -4849,7 +4843,7 @@ ufs_mem_phy: phy@1d80000 {
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
-				 <&tcsrcc TCSR_UFS_CLKREF_EN>;
+				 <&tlmm TCSR_UFS_CLKREF_EN>;
 
 			clock-names = "ref",
 				      "ref_aux",

-- 
2.52.0

Re: [PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Abel Vesa]

On 26-02-02 15:57:37, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> On SM8750 specifically, the block which provides various reference
> clocks does *NOT* live inside TCSR, but rather TLMM.
> 
> With the former now being able to properly expose them, switch over to
> the proper source.
> 
> Now, the TCSR still exists as a block for various tunables and
> switches, however the prior misuse resulted in its 8750-specifc
> compatible being already in use. With it freed up, it is now free again
> to be described properly.
> 
> Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
> Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Krzysztof Kozlowski]

On 02/02/2026 15:57, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> On SM8750 specifically, the block which provides various reference
> clocks does *NOT* live inside TCSR, but rather TLMM.
> 
> With the former now being able to properly expose them, switch over to
> the proper source.
> 
> Now, the TCSR still exists as a block for various tunables and
> switches, however the prior misuse resulted in its 8750-specifc
> compatible being already in use. With it freed up, it is now free again
> to be described properly.
> 
> Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
> Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++--------------


This will break all the users of this DTS and commit msg is silent about
this. It's also silent on actual bug being supposedly fixed here.

So again - as explained many times to other Qualcomm engineers - you
cannot just break the users silently and without justified reason.

That's RFC, so maybe you planned to rewrite it later, dunno. That's why
I did not review the rest.

Best regards,
Krzysztof

Re: [PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Konrad Dybcio]

On 2/17/26 1:39 PM, Krzysztof Kozlowski wrote:
> On 02/02/2026 15:57, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> On SM8750 specifically, the block which provides various reference
>> clocks does *NOT* live inside TCSR, but rather TLMM.
>>
>> With the former now being able to properly expose them, switch over to
>> the proper source.
>>
>> Now, the TCSR still exists as a block for various tunables and
>> switches, however the prior misuse resulted in its 8750-specifc
>> compatible being already in use. With it freed up, it is now free again
>> to be described properly.
>>
>> Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
>> Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++--------------
> 
> 
> This will break all the users of this DTS and commit msg is silent about
> this. It's also silent on actual bug being supposedly fixed here.
> 
> So again - as explained many times to other Qualcomm engineers - you
> cannot just break the users silently and without justified reason.
> 
> That's RFC, so maybe you planned to rewrite it later, dunno. That's why
> I did not review the rest.

I assumed the explanation in the cover letter is enough, but I can
include some more context here too

Konrad

Re: [PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Krzysztof Kozlowski]

On 17/02/2026 13:43, Konrad Dybcio wrote:
> On 2/17/26 1:39 PM, Krzysztof Kozlowski wrote:
>> On 02/02/2026 15:57, Konrad Dybcio wrote:
>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> On SM8750 specifically, the block which provides various reference
>>> clocks does *NOT* live inside TCSR, but rather TLMM.
>>>
>>> With the former now being able to properly expose them, switch over to
>>> the proper source.
>>>
>>> Now, the TCSR still exists as a block for various tunables and
>>> switches, however the prior misuse resulted in its 8750-specifc
>>> compatible being already in use. With it freed up, it is now free again
>>> to be described properly.
>>>
>>> Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
>>> Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++--------------
>>
>>
>> This will break all the users of this DTS and commit msg is silent about
>> this. It's also silent on actual bug being supposedly fixed here.
>>
>> So again - as explained many times to other Qualcomm engineers - you
>> cannot just break the users silently and without justified reason.
>>
>> That's RFC, so maybe you planned to rewrite it later, dunno. That's why
>> I did not review the rest.
> 
> I assumed the explanation in the cover letter is enough, but I can
> include some more context here too


No one reads cover letters, they don't matter and they are not ending up
in git history, thus this commit - which is supposedly fixing something
- must tell what you are fixing.

Best regards,
Krzysztof

[PATCH RFC 6/8] clk: qcom: Remove tcsrcc-sm8750

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

This is now handled from within the pinctrl subsystem, since there is
no "CC" block inside SM8750's TCSR, as the corresponding hardware is
present within TLMM. Remove the leftovers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 drivers/clk/qcom/Kconfig         |   8 ---
 drivers/clk/qcom/Makefile        |   1 -
 drivers/clk/qcom/tcsrcc-sm8750.c | 141 ---------------------------------------
 3 files changed, 150 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index a8a86ea6bb74..f3ed33173ef6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1506,14 +1506,6 @@ config SM_TCSRCC_8650
 	  Support for the TCSR clock controller on SM8650 devices.
 	  Say Y if you want to use peripheral devices such as SD/UFS.
 
-config SM_TCSRCC_8750
-	tristate "SM8750 TCSR Clock Controller"
-	depends on ARM64 || COMPILE_TEST
-	select QCOM_GDSC
-	help
-	  Support for the TCSR clock controller on SM8750 devices.
-	  Say Y if you want to use peripheral devices such as UFS/USB/PCIe.
-
 config SA_VIDEOCC_8775P
 	tristate "SA8775P Video Clock Controller"
 	depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6b0ad8832b55..f8c81844ee48 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -184,7 +184,6 @@ obj-$(CONFIG_SM_GPUCC_MILOS) += gpucc-milos.o
 obj-$(CONFIG_SM_LPASSCC_6115) += lpasscc-sm6115.o
 obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
 obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
-obj-$(CONFIG_SM_TCSRCC_8750) += tcsrcc-sm8750.o
 obj-$(CONFIG_SM_VIDEOCC_6350) += videocc-sm6350.o
 obj-$(CONFIG_SM_VIDEOCC_7150) += videocc-sm7150.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
diff --git a/drivers/clk/qcom/tcsrcc-sm8750.c b/drivers/clk/qcom/tcsrcc-sm8750.c
deleted file mode 100644
index 242e320986ef..000000000000
--- a/drivers/clk/qcom/tcsrcc-sm8750.c
+++ /dev/null
@@ -1,141 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
- */
-
-#include <linux/clk-provider.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
-
-#include "clk-branch.h"
-#include "clk-regmap.h"
-#include "clk-regmap-divider.h"
-#include "clk-regmap-mux.h"
-#include "common.h"
-
-enum {
-	DT_BI_TCXO_PAD,
-};
-
-static struct clk_branch tcsr_pcie_0_clkref_en = {
-	.halt_reg = 0x0,
-	.halt_check = BRANCH_HALT_DELAY,
-	.clkr = {
-		.enable_reg = 0x0,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "tcsr_pcie_0_clkref_en",
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch tcsr_ufs_clkref_en = {
-	.halt_reg = 0x1000,
-	.halt_check = BRANCH_HALT_DELAY,
-	.clkr = {
-		.enable_reg = 0x1000,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "tcsr_ufs_clkref_en",
-			.parent_data = &(const struct clk_parent_data){
-				.index = DT_BI_TCXO_PAD,
-			},
-			.num_parents = 1,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch tcsr_usb2_clkref_en = {
-	.halt_reg = 0x2000,
-	.halt_check = BRANCH_HALT_DELAY,
-	.clkr = {
-		.enable_reg = 0x2000,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "tcsr_usb2_clkref_en",
-			.parent_data = &(const struct clk_parent_data){
-				.index = DT_BI_TCXO_PAD,
-			},
-			.num_parents = 1,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_branch tcsr_usb3_clkref_en = {
-	.halt_reg = 0x3000,
-	.halt_check = BRANCH_HALT_DELAY,
-	.clkr = {
-		.enable_reg = 0x3000,
-		.enable_mask = BIT(0),
-		.hw.init = &(const struct clk_init_data) {
-			.name = "tcsr_usb3_clkref_en",
-			.parent_data = &(const struct clk_parent_data){
-				.index = DT_BI_TCXO_PAD,
-			},
-			.num_parents = 1,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
-static struct clk_regmap *tcsr_cc_sm8750_clocks[] = {
-	[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
-	[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
-	[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
-	[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
-};
-
-static const struct regmap_config tcsr_cc_sm8750_regmap_config = {
-	.reg_bits = 32,
-	.reg_stride = 4,
-	.val_bits = 32,
-	.max_register = 0x3000,
-	.fast_io = true,
-};
-
-static const struct qcom_cc_desc tcsr_cc_sm8750_desc = {
-	.config = &tcsr_cc_sm8750_regmap_config,
-	.clks = tcsr_cc_sm8750_clocks,
-	.num_clks = ARRAY_SIZE(tcsr_cc_sm8750_clocks),
-};
-
-static const struct of_device_id tcsr_cc_sm8750_match_table[] = {
-	{ .compatible = "qcom,sm8750-tcsr" },
-	{ }
-};
-MODULE_DEVICE_TABLE(of, tcsr_cc_sm8750_match_table);
-
-static int tcsr_cc_sm8750_probe(struct platform_device *pdev)
-{
-	return qcom_cc_probe(pdev, &tcsr_cc_sm8750_desc);
-}
-
-static struct platform_driver tcsr_cc_sm8750_driver = {
-	.probe = tcsr_cc_sm8750_probe,
-	.driver = {
-		.name = "tcsr_cc-sm8750",
-		.of_match_table = tcsr_cc_sm8750_match_table,
-	},
-};
-
-static int __init tcsr_cc_sm8750_init(void)
-{
-	return platform_driver_register(&tcsr_cc_sm8750_driver);
-}
-subsys_initcall(tcsr_cc_sm8750_init);
-
-static void __exit tcsr_cc_sm8750_exit(void)
-{
-	platform_driver_unregister(&tcsr_cc_sm8750_driver);
-}
-module_exit(tcsr_cc_sm8750_exit);
-
-MODULE_DESCRIPTION("QTI TCSR_CC SM8750 Driver");
-MODULE_LICENSE("GPL");

-- 
2.52.0

Re: [PATCH RFC 6/8] clk: qcom: Remove tcsrcc-sm8750

[Abel Vesa]

On 26-02-02 15:57:38, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> This is now handled from within the pinctrl subsystem, since there is
> no "CC" block inside SM8750's TCSR, as the corresponding hardware is
> present within TLMM. Remove the leftovers.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

So bindings remain in then...

Anyway:

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH RFC 6/8] clk: qcom: Remove tcsrcc-sm8750

[Konrad Dybcio]

On 2/17/26 12:48 PM, Abel Vesa wrote:
> On 26-02-02 15:57:38, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> This is now handled from within the pinctrl subsystem, since there is
>> no "CC" block inside SM8750's TCSR, as the corresponding hardware is
>> present within TLMM. Remove the leftovers.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> So bindings remain in then...

Yes, to limit the explosiveness I decided to reuse the existing
ones.. I think that's the reasonable way to go

Konrad

Re: [PATCH RFC 6/8] clk: qcom: Remove tcsrcc-sm8750

[Abel Vesa]

On 26-02-17 12:50:50, Konrad Dybcio wrote:
> On 2/17/26 12:48 PM, Abel Vesa wrote:
> > On 26-02-02 15:57:38, Konrad Dybcio wrote:
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> This is now handled from within the pinctrl subsystem, since there is
> >> no "CC" block inside SM8750's TCSR, as the corresponding hardware is
> >> present within TLMM. Remove the leftovers.
> >>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > 
> > So bindings remain in then...
> 
> Yes, to limit the explosiveness I decided to reuse the existing
> ones.. I think that's the reasonable way to go

Yeah, realized that after having another look.

Good work.

[PATCH RFC 7/8] arm64: dts: qcom: sm8750: Describe TCSR

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

SM8750 features a TCSR block (like any other Qualcomm platform),
however unlike its sibling platforms, it most notably does NOT contain
a clock controller, where XO-fed gates would reside.

Describe it.

Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 0c034ba0517f..7ccbc3ad212b 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2124,6 +2124,11 @@ tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: clock-controller@1fc0000 {
+			compatible = "qcom,sm8750-tcsr", "syscon";
+			reg = <0x0 0x01fc0000 0x0 0x30000>;
+		};
+
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8750-mpss-pas";
 			reg = <0x0 0x04080000 0x0 0x10000>;

-- 
2.52.0

[PATCH RFC 8/8] arm64: defconfig: Remove CONFIG_SM_TCSRCC_8750

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The driver and the config option have been removed. Clean it up.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/configs/defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b67d5b1fc45b..dd37285e223d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1552,7 +1552,6 @@ CONFIG_SM_GPUCC_8550=m
 CONFIG_SM_GPUCC_8650=m
 CONFIG_SM_TCSRCC_8550=y
 CONFIG_SM_TCSRCC_8650=y
-CONFIG_SM_TCSRCC_8750=m
 CONFIG_SA_VIDEOCC_8775P=m
 CONFIG_SM_VIDEOCC_6350=m
 CONFIG_SM_VIDEOCC_MILOS=m

-- 
2.52.0

Re: [PATCH RFC 8/8] arm64: defconfig: Remove CONFIG_SM_TCSRCC_8750

[Abel Vesa]

On 26-02-02 15:57:40, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> The driver and the config option have been removed. Clean it up.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [RFC PATCH 0/8] Fix TCSR representation on SM8750

[Mukesh Ojha]

On Mon, Feb 02, 2026 at 03:57:32PM +0100, Konrad Dybcio wrote:
> As sparked by this thread:
> <20260112151725.2308971-1-mukesh.ojha@oss.qualcomm.com>
> 
> The current representation of TCSR is wrong.
> 
> On platforms post and including SM8550, the TCSR had a sub-block in it,
> containing gate clocks used for distributing the XO output to various
> consumers. This is what we refer to as TCSR_CC upstream.
> 
> SM8750 however, is notably different. That same set of tunables had
> been moved to the TLMM register space. This is made worse, as the
> sm8750-tcsrcc driver consumes the qcom,sm8750-tcsr compatible.
> 
> This hardware change had been undone with the generation following
> 8750.
> 
> This series attempts to unwind that. It's difficult to merge, both for
> bindings and functional reasons..
> 
> I think it goes without saying this breaks backwards compatibility, but
> it has to be done to represent TCSR at all. The patches are ordered in
> a least-destructive order..
> 
> I gave this a quick spin on (remote) hw, the UFS (one of the consumers)
> still works, but more testing would be greatly appreciated.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Thanks Konrad for taking this forward, while I was also working on your
suggestion to make tlmm a clock provider.

> ---
> Konrad Dybcio (8):
>       dt-bindings: Move qcom,sm8750-tcsr from clock/tcsr to mfd/tcsr
>       dt-bindings: pinctrl: qcom,sm8750-tlmm: Allow clocks/clock-cells
>       pinctrl: qcom: Allow exposing reference clocks living in TLMM reg space
>       pinctrl: qcom: sm8750: Expose reference clocks
>       arm64: dts: qcom: Remove inexistent TCSR_CC
>       clk: qcom: Remove tcsrcc-sm8750
>       arm64: dts: qcom: sm8750: Describe TCSR
>       arm64: defconfig: Remove CONFIG_SM_TCSRCC_8750
> 
>  .../bindings/clock/qcom,sm8550-tcsr.yaml           |   2 -
>  .../devicetree/bindings/mfd/qcom,tcsr.yaml         |   1 +
>  .../bindings/pinctrl/qcom,sm8750-tlmm.yaml         |  12 ++
>  arch/arm64/boot/dts/qcom/sm8750.dtsi               |  27 ++--
>  arch/arm64/configs/defconfig                       |   1 -
>  drivers/clk/qcom/Kconfig                           |   8 --
>  drivers/clk/qcom/Makefile                          |   1 -
>  drivers/clk/qcom/tcsrcc-sm8750.c                   | 141 ---------------------
>  drivers/pinctrl/qcom/pinctrl-msm.c                 |  92 ++++++++++++++
>  drivers/pinctrl/qcom/pinctrl-msm.h                 |  14 ++
>  drivers/pinctrl/qcom/pinctrl-sm8750.c              |  31 +++++
>  11 files changed, 163 insertions(+), 167 deletions(-)
> ---
> base-commit: 4c87cdd0328495759f6e9f9f4e1e53ef8032a76f
> change-id: 20260202-topic-8750_tcsr-e2dafc2f11d1
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 

-- 
-Mukesh Ojha

Re: [RFC PATCH 0/8] Fix TCSR representation on SM8750

[Konrad Dybcio]

On 2/2/26 7:19 PM, Mukesh Ojha wrote:
> On Mon, Feb 02, 2026 at 03:57:32PM +0100, Konrad Dybcio wrote:
>> As sparked by this thread:
>> <20260112151725.2308971-1-mukesh.ojha@oss.qualcomm.com>
>>
>> The current representation of TCSR is wrong.
>>
>> On platforms post and including SM8550, the TCSR had a sub-block in it,
>> containing gate clocks used for distributing the XO output to various
>> consumers. This is what we refer to as TCSR_CC upstream.
>>
>> SM8750 however, is notably different. That same set of tunables had
>> been moved to the TLMM register space. This is made worse, as the
>> sm8750-tcsrcc driver consumes the qcom,sm8750-tcsr compatible.
>>
>> This hardware change had been undone with the generation following
>> 8750.
>>
>> This series attempts to unwind that. It's difficult to merge, both for
>> bindings and functional reasons..
>>
>> I think it goes without saying this breaks backwards compatibility, but
>> it has to be done to represent TCSR at all. The patches are ordered in
>> a least-destructive order..
>>
>> I gave this a quick spin on (remote) hw, the UFS (one of the consumers)
>> still works, but more testing would be greatly appreciated.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Thanks Konrad for taking this forward, while I was also working on your
> suggestion to make tlmm a clock provider.

I was under the impression you abandoned that patch, but indeed I
should have asked first. My intention wasn't to beat you to it, but
to unblock it. Please accept my apologies.

Konrad