Re: [PATCH 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC

[Jie Luo <quic_luoj@quicinc.com>]

On 3/25/2025 4:22 PM, Krzysztof Kozlowski wrote:
>>>> --- a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
>>>> +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
>>>> @@ -1,6 +1,6 @@
>>>>   /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>>>   /*
>>>> - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
>>>>    */
>>>>   
>>>>   #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
>>>> @@ -19,4 +19,12 @@
>>>>   #define ETH1_50MHZ_CLK			7
>>>>   #define ETH2_50MHZ_CLK			8
>>>>   #define ETH_25MHZ_CLK			9
>>>> +
>>>> +/*
>>>> + * The CMN PLL output clock rates that are specifically applicable for IPQ5424
>>>> + * SoC. For IPQ5424, the other output clocks and their rates are same as IPQ9574.
>>>> + */
>>>> +#define NSS_300MHZ_CLK			4
>>>> +#define PPE_375MHZ_CLK			5
>>> Not a huge fan of this, such differences are only relevant to the driver
>>> part in my view - bindings only let a consumer reference a specific piece
>>> of hardware
>> Oh I the bindings are stepping into the frequency department already,
>> hmm.. Then I suppose it's fine if the dt-bindings maintainers don't have any
>> concerns
> 
> Nooooo, it was said these are output clocks, not rates. If these are
> rates, then NAK.
> 
> Best regards,
> Krzysztof

Yes, rates themselves are not defined here, they are defined in the
driver data structure.

The output clocks of CMN PLL are always fixed clock rate, so the clock
frequency was added into the clock specifier macro names defined in
this header file for clarity.