* [PATCH v9 1/6] firmware: qcom_scm: ipq5332: add support to pass metadata size
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
2026-01-06 16:11 ` Dmitry Baryshkov
2026-01-06 10:54 ` [PATCH v9 2/6] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL Varadarajan Narayanan
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: Konrad Dybcio, Gokul Sriram Palanisamy, Varadarajan Narayanan
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
IPQ5332 security software running under trustzone requires metadata size.
With new command support added in TrustZone that includes a size parameter,
pass metadata size as well.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v9: Added signed-off-by tag
---
drivers/firmware/qcom/qcom_scm.c | 17 +++++++++++++----
drivers/firmware/qcom/qcom_scm.h | 1 +
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 1a6f85e463e0..c970157f75b5 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -583,9 +583,6 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
int ret;
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
- .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
- .args[0] = peripheral,
.owner = ARM_SMCCC_OWNER_SIP,
};
struct qcom_scm_res res;
@@ -617,7 +614,19 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
if (ret)
goto disable_clk;
- desc.args[1] = mdata_phys;
+ if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
+ QCOM_SCM_PIL_PAS_INIT_IMAGE_V2)) {
+ desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE_V2;
+ desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL);
+ desc.args[0] = peripheral;
+ desc.args[1] = mdata_phys;
+ desc.args[2] = size;
+ } else {
+ desc.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE;
+ desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
+ desc.args[0] = peripheral;
+ desc.args[1] = mdata_phys;
+ }
ret = qcom_scm_call(__scm->dev, &desc, &res);
qcom_scm_bw_disable();
diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h
index a56c8212cc0c..57d63e932f62 100644
--- a/drivers/firmware/qcom/qcom_scm.h
+++ b/drivers/firmware/qcom/qcom_scm.h
@@ -105,6 +105,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev);
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
+#define QCOM_SCM_PIL_PAS_INIT_IMAGE_V2 0x1a
#define QCOM_SCM_SVC_IO 0x05
#define QCOM_SCM_IO_READ 0x01
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v9 1/6] firmware: qcom_scm: ipq5332: add support to pass metadata size
2026-01-06 10:54 ` [PATCH v9 1/6] firmware: qcom_scm: ipq5332: add support to pass metadata size Varadarajan Narayanan
@ 2026-01-06 16:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-01-06 16:11 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Konrad Dybcio, Gokul Sriram Palanisamy
On Tue, Jan 06, 2026 at 04:24:07PM +0530, Varadarajan Narayanan wrote:
> From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>
> IPQ5332 security software running under trustzone requires metadata size.
> With new command support added in TrustZone that includes a size parameter,
> pass metadata size as well.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
> v9: Added signed-off-by tag
> ---
> drivers/firmware/qcom/qcom_scm.c | 17 +++++++++++++----
> drivers/firmware/qcom/qcom_scm.h | 1 +
> 2 files changed, 14 insertions(+), 4 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 2/6] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 1/6] firmware: qcom_scm: ipq5332: add support to pass metadata size Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
2026-01-07 7:32 ` Krzysztof Kozlowski
2026-01-06 10:54 ` [PATCH v9 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver Varadarajan Narayanan
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: Gokul Sriram Palanisamy, George Moussalem, Varadarajan Narayanan
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Add new binding document for hexagon based WCSS secure PIL remoteproc.
IPQ5018, IPQ5332 and IPQ9574 follow secure PIL remoteproc.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
[ Dropped ipq5424 support ]
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v9: Rename qcom,wcss-sec-pil.yaml -> qcom,ipq5018-wcss-sec-pil.yaml
Fix 'clocks' and 'clock-names' definitions
v8: Dropped Krzysztof's 'Reviewed-by' as the bindings file has changed significantly
Drop ipq5424 support
Update example to ipq9574 instead of ipq5424
Change 'mboxes' description
---
.../remoteproc/qcom,ipq5018-wcss-sec-pil.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml
new file mode 100644
index 000000000000..a73edb447d26
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,ipq5018-wcss-sec-pil.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCSS Secure Peripheral Image Loader
+
+maintainers:
+ - Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
+
+description:
+ Wireless Connectivity Subsystem (WCSS) Secure Peripheral Image Loader loads
+ firmware and power up QDSP6 remoteproc on the Qualcomm IPQ series SoC.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5018-wcss-sec-pil
+ - qcom,ipq5332-wcss-sec-pil
+ - qcom,ipq9574-wcss-sec-pil
+
+ reg:
+ maxItems: 1
+
+ firmware-name:
+ maxItems: 1
+ description: Firmware name for the Hexagon core
+
+ interrupts:
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+
+ interrupt-names:
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+
+ clocks:
+ minItems: 1
+ items:
+ - description: sleep clock
+ - description: AHB interconnect clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: sleep
+ - const: interconnect
+
+ mboxes:
+ items:
+ - description: TMECom mailbox driver
+
+ qcom,smem-states:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: States used by the AP to signal the remote processor
+ items:
+ - description: Stop Q6
+ - description: Shutdown Q6
+
+ qcom,smem-state-names:
+ description:
+ Names of the states used by the AP to signal the remote processor
+ items:
+ - const: stop
+ - const: shutdown
+
+ memory-region:
+ items:
+ - description: Q6 reserved region
+
+ glink-edge:
+ $ref: /schemas/remoteproc/qcom,glink-edge.yaml#
+ description:
+ Qualcomm G-Link subnode which represents communication edge, channels
+ and devices related to the Modem.
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - firmware-name
+ - interrupts
+ - interrupt-names
+ - qcom,smem-states
+ - qcom,smem-state-names
+ - memory-region
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ipq5018-wcss-sec-pil
+ then:
+ properties:
+ clocks:
+ items:
+ - description: sleep clock
+ - description: AHB interconnect clock
+ clock-names:
+ items:
+ - const: sleep
+ - const: interconnect
+ required:
+ - clocks
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ipq5332-wcss-sec-pil
+ then:
+ properties:
+ clocks:
+ items:
+ - description: sleep clock
+ clock-names:
+ items:
+ - const: sleep
+ required:
+ - clocks
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-wcss-sec-pil
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ q6v5_wcss: remoteproc@cd00000 {
+ compatible = "qcom,ipq9574-wcss-sec-pil";
+ reg = <0x0cd00000 0x10000>;
+ firmware-name = "ath11k/IPQ9574/hw1.0/q6_fw.mbn";
+ interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wcss_in 0 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 1 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 2 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 3 IRQ_TYPE_NONE>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ qcom,smem-states = <&smp2p_wcss_out 1>,
+ <&smp2p_wcss_out 0>;
+ qcom,smem-state-names = "stop",
+ "shutdown";
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v9 2/6] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL
2026-01-06 10:54 ` [PATCH v9 2/6] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL Varadarajan Narayanan
@ 2026-01-07 7:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-07 7:32 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Gokul Sriram Palanisamy, George Moussalem
On Tue, Jan 06, 2026 at 04:24:08PM +0530, Varadarajan Narayanan wrote:
> From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>
> Add new binding document for hexagon based WCSS secure PIL remoteproc.
> IPQ5018, IPQ5332 and IPQ9574 follow secure PIL remoteproc.
>
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> [ Dropped ipq5424 support ]
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 1/6] firmware: qcom_scm: ipq5332: add support to pass metadata size Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 2/6] dt-bindings: remoteproc: qcom: document hexagon based WCSS secure PIL Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
2026-01-12 6:08 ` Gokul Sriram P
2026-01-06 10:54 ` [PATCH v9 4/6] arm64: dts: qcom: ipq5018: add nodes to bring up q6 Varadarajan Narayanan
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: Vignesh Viswanathan, Gokul Sriram Palanisamy, George Moussalem,
Varadarajan Narayanan
From: Vignesh Viswanathan <vignesh.viswanathan@oss.qualcomm.com>
Add support to bring up hexagon based WCSS using secure PIL. All IPQxxxx
SoCs support secure Peripheral Image Loading (PIL).
Secure PIL image is signed firmware image which only trusted software such
as TrustZone (TZ) can authenticate and load. Linux kernel will send a
Peripheral Authentication Service (PAS) request to TZ to authenticate and
load the PIL images.
In order to avoid overloading the existing WCSS driver or PAS driver, we
came up with this new PAS based IPQ WCSS driver.
Signed-off-by: Vignesh Viswanathan <vignesh.viswanathan@oss.qualcomm.com>
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
[ Dropped ipq5424 support ]
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v8: Dropped ipq5424 support.
The comments related to 'use_tmelcom' in [1] not applicable
[1] https://lore.kernel.org/linux-arm-msm/72f0d4f7-8d8a-4fc5-bac2-8094e971a0e3@oss.qualcomm.com/
Changed copyright for drivers/remoteproc/qcom_q6v5_wcss_sec.c
---
drivers/remoteproc/Kconfig | 19 ++
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/qcom_q6v5_wcss_sec.c | 328 ++++++++++++++++++++++++
include/linux/remoteproc.h | 2 +
4 files changed, 350 insertions(+)
create mode 100644 drivers/remoteproc/qcom_q6v5_wcss_sec.c
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 48a0d3a69ed0..eaa427e4e9ec 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -254,6 +254,25 @@ config QCOM_Q6V5_WCSS
Hexagon V5 based WCSS remote processors on e.g. IPQ8074. This is
a non-TrustZone wireless subsystem.
+config QCOM_Q6V5_WCSS_SEC
+ tristate "Qualcomm Hexagon based WCSS Secure Peripheral Image Loader"
+ depends on OF && ARCH_QCOM
+ depends on QCOM_SMEM
+ depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
+ depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n
+ select QCOM_MDT_LOADER
+ select QCOM_PIL_INFO
+ select QCOM_Q6V5_COMMON
+ select QCOM_RPROC_COMMON
+ select QCOM_SCM
+ help
+ Say y here to support the Qualcomm Secure Peripheral Image Loader
+ for the Hexagon based remote processors on e.g. IPQ5332.
+
+ This is TrustZone wireless subsystem. The firmware is
+ verified and booted with the help of the Peripheral Authentication
+ System (PAS) in TrustZone.
+
config QCOM_SYSMON
tristate "Qualcomm sysmon driver"
depends on RPMSG
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 1c7598b8475d..08705ef62bce 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o
obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o
obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o
obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o
+obj-$(CONFIG_QCOM_Q6V5_WCSS_SEC) += qcom_q6v5_wcss_sec.o
obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o
qcom_wcnss_pil-y += qcom_wcnss.o
diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/qcom_q6v5_wcss_sec.c
new file mode 100644
index 000000000000..10fe3391decb
--- /dev/null
+++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/clk.h>
+#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/io.h>
+#include <linux/mailbox_client.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+#include <linux/soc/qcom/mdt_loader.h>
+
+#include "qcom_common.h"
+#include "qcom_q6v5.h"
+#include "qcom_pil_info.h"
+
+#define WCSS_CRASH_REASON 421
+
+#define WCSS_PAS_ID 0x6
+#define MPD_WCSS_PAS_ID 0xd
+
+#define Q6_WAIT_TIMEOUT (5 * HZ)
+
+struct wcss_sec {
+ struct device *dev;
+ struct qcom_rproc_glink glink_subdev;
+ struct qcom_rproc_ssr ssr_subdev;
+ struct qcom_q6v5 q6;
+ phys_addr_t mem_phys;
+ phys_addr_t mem_reloc;
+ void *mem_region;
+ size_t mem_size;
+ const struct wcss_data *desc;
+
+ struct mbox_client mbox_client;
+ struct mbox_chan *mbox_chan;
+ void *metadata;
+ size_t metadata_len;
+};
+
+struct wcss_data {
+ u32 pasid;
+ const char *ss_name;
+ bool auto_boot;
+};
+
+static int wcss_sec_start(struct rproc *rproc)
+{
+ struct wcss_sec *wcss = rproc->priv;
+ struct device *dev = wcss->dev;
+ int ret;
+
+ ret = qcom_q6v5_prepare(&wcss->q6);
+ if (ret)
+ return ret;
+
+ ret = qcom_scm_pas_auth_and_reset(wcss->desc->pasid);
+ if (ret) {
+ dev_err(dev, "wcss_reset failed\n");
+ goto unprepare;
+ }
+
+ ret = qcom_q6v5_wait_for_start(&wcss->q6, Q6_WAIT_TIMEOUT);
+ if (ret == -ETIMEDOUT)
+ dev_err(dev, "start timed out\n");
+
+unprepare:
+ qcom_q6v5_unprepare(&wcss->q6);
+
+ return ret;
+}
+
+static int wcss_sec_stop(struct rproc *rproc)
+{
+ struct wcss_sec *wcss = rproc->priv;
+ struct device *dev = wcss->dev;
+ int ret;
+
+ ret = qcom_scm_pas_shutdown(wcss->desc->pasid);
+ if (ret) {
+ dev_err(dev, "not able to shutdown\n");
+ return ret;
+ }
+
+ qcom_q6v5_unprepare(&wcss->q6);
+
+ return 0;
+}
+
+static void *wcss_sec_da_to_va(struct rproc *rproc, u64 da, size_t len,
+ bool *is_iomem)
+{
+ struct wcss_sec *wcss = rproc->priv;
+ int offset;
+
+ offset = da - wcss->mem_reloc;
+ if (offset < 0 || offset + len > wcss->mem_size)
+ return NULL;
+
+ return wcss->mem_region + offset;
+}
+
+static int wcss_sec_load(struct rproc *rproc, const struct firmware *fw)
+{
+ struct wcss_sec *wcss = rproc->priv;
+ struct device *dev = wcss->dev;
+ int ret;
+
+ ret = qcom_mdt_load(dev, fw, rproc->firmware, wcss->desc->pasid, wcss->mem_region,
+ wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc);
+ if (ret)
+ return ret;
+
+ qcom_pil_info_store("wcss", wcss->mem_phys, wcss->mem_size);
+
+ return 0;
+}
+
+static unsigned long wcss_sec_panic(struct rproc *rproc)
+{
+ struct wcss_sec *wcss = rproc->priv;
+
+ return qcom_q6v5_panic(&wcss->q6);
+}
+
+static void wcss_sec_copy_segment(struct rproc *rproc,
+ struct rproc_dump_segment *segment,
+ void *dest, size_t offset, size_t size)
+{
+ struct wcss_sec *wcss = rproc->priv;
+ struct device *dev = wcss->dev;
+
+ if (!segment->io_ptr)
+ segment->io_ptr = ioremap_wc(segment->da, segment->size);
+
+ if (!segment->io_ptr) {
+ dev_err(dev, "Failed to ioremap segment %pad size 0x%zx\n",
+ &segment->da, segment->size);
+ return;
+ }
+
+ if (offset + size < segment->size) {
+ memcpy(dest, segment->io_ptr + offset, size);
+ } else {
+ iounmap(segment->io_ptr);
+ segment->io_ptr = NULL;
+ }
+}
+
+static int wcss_sec_dump_segments(struct rproc *rproc,
+ const struct firmware *fw)
+{
+ struct device *dev = rproc->dev.parent;
+ struct reserved_mem *rmem = NULL;
+ struct device_node *node;
+ int num_segs, index;
+ int ret;
+
+ /*
+ * Parse through additional reserved memory regions for the rproc
+ * and add them to the coredump segments
+ */
+ num_segs = of_count_phandle_with_args(dev->of_node,
+ "memory-region", NULL);
+ for (index = 0; index < num_segs; index++) {
+ node = of_parse_phandle(dev->of_node,
+ "memory-region", index);
+ if (!node)
+ return -EINVAL;
+
+ rmem = of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem) {
+ dev_err(dev, "unable to acquire memory-region index %d num_segs %d\n",
+ index, num_segs);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "Adding segment 0x%pa size 0x%pa",
+ &rmem->base, &rmem->size);
+ ret = rproc_coredump_add_custom_segment(rproc,
+ rmem->base,
+ rmem->size,
+ wcss_sec_copy_segment,
+ NULL);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct rproc_ops wcss_sec_ops = {
+ .start = wcss_sec_start,
+ .stop = wcss_sec_stop,
+ .da_to_va = wcss_sec_da_to_va,
+ .load = wcss_sec_load,
+ .get_boot_addr = rproc_elf_get_boot_addr,
+ .panic = wcss_sec_panic,
+ .parse_fw = wcss_sec_dump_segments,
+};
+
+static int wcss_sec_alloc_memory_region(struct wcss_sec *wcss)
+{
+ struct device *dev = wcss->dev;
+ struct resource res;
+ int ret;
+
+ ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
+ if (ret) {
+ dev_err(dev, "unable to acquire memory-region resource\n");
+ return ret;
+ }
+
+ wcss->mem_phys = res.start;
+ wcss->mem_reloc = res.start;
+ wcss->mem_size = resource_size(&res);
+ wcss->mem_region = devm_ioremap_resource_wc(dev, &res);
+ if (!wcss->mem_region) {
+ dev_err(dev, "unable to map memory region: %pR\n", &res);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int wcss_sec_probe(struct platform_device *pdev)
+{
+ const struct wcss_data *desc = of_device_get_match_data(&pdev->dev);
+ const char *fw_name = NULL;
+ struct wcss_sec *wcss;
+ struct clk *sleep_clk;
+ struct clk *int_clk;
+ struct rproc *rproc;
+ int ret;
+
+ ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
+ &fw_name);
+ if (ret < 0)
+ return ret;
+
+ rproc = devm_rproc_alloc(&pdev->dev, desc->ss_name, &wcss_sec_ops,
+ fw_name, sizeof(*wcss));
+ if (!rproc) {
+ dev_err(&pdev->dev, "failed to allocate rproc\n");
+ return -ENOMEM;
+ }
+
+ wcss = rproc->priv;
+ wcss->dev = &pdev->dev;
+ wcss->desc = desc;
+
+ ret = wcss_sec_alloc_memory_region(wcss);
+ if (ret)
+ return ret;
+
+ sleep_clk = devm_clk_get_optional_enabled(&pdev->dev, "sleep");
+ if (IS_ERR(sleep_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(sleep_clk),
+ "Failed to get sleep clock\n");
+
+ int_clk = devm_clk_get_optional_enabled(&pdev->dev, "interconnect");
+ if (IS_ERR(int_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(int_clk),
+ "Failed to get interconnect clock\n");
+
+ ret = qcom_q6v5_init(&wcss->q6, pdev, rproc,
+ WCSS_CRASH_REASON, NULL, NULL);
+ if (ret)
+ return ret;
+
+ qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ss_name);
+ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ss_name);
+
+ rproc->auto_boot = false;
+ rproc->dump_conf = RPROC_COREDUMP_INLINE;
+ rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
+
+ ret = devm_rproc_add(&pdev->dev, rproc);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, rproc);
+
+ return 0;
+}
+
+static void wcss_sec_remove(struct platform_device *pdev)
+{
+ struct rproc *rproc = platform_get_drvdata(pdev);
+ struct wcss_sec *wcss = rproc->priv;
+
+ mbox_free_channel(wcss->mbox_chan);
+ qcom_remove_glink_subdev(rproc, &wcss->glink_subdev);
+ qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev);
+ qcom_q6v5_deinit(&wcss->q6);
+}
+
+static const struct wcss_data wcss_sec_ipq5332_res_init = {
+ .pasid = MPD_WCSS_PAS_ID,
+ .ss_name = "q6wcss",
+};
+
+static const struct wcss_data wcss_sec_ipq9574_res_init = {
+ .pasid = WCSS_PAS_ID,
+ .ss_name = "q6wcss",
+};
+
+static const struct of_device_id wcss_sec_of_match[] = {
+ { .compatible = "qcom,ipq5018-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init },
+ { .compatible = "qcom,ipq5332-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init },
+ { .compatible = "qcom,ipq9574-wcss-sec-pil", .data = &wcss_sec_ipq9574_res_init },
+ { },
+};
+MODULE_DEVICE_TABLE(of, wcss_sec_of_match);
+
+static struct platform_driver wcss_sec_driver = {
+ .probe = wcss_sec_probe,
+ .remove = wcss_sec_remove,
+ .driver = {
+ .name = "qcom-wcss-secure-pil",
+ .of_match_table = wcss_sec_of_match,
+ },
+};
+module_platform_driver(wcss_sec_driver);
+
+MODULE_DESCRIPTION("Hexagon WCSS Secure Peripheral Image Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index b4795698d8c2..7b2159853345 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -472,6 +472,7 @@ enum rproc_dump_mechanism {
* @node: list node related to the rproc segment list
* @da: device address of the segment
* @size: size of the segment
+ * @io_ptr: ptr to store the ioremapped dump segment
* @priv: private data associated with the dump_segment
* @dump: custom dump function to fill device memory segment associated
* with coredump
@@ -483,6 +484,7 @@ struct rproc_dump_segment {
dma_addr_t da;
size_t size;
+ void *io_ptr;
void *priv;
void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment,
void *dest, size_t offset, size_t size);
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v9 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver
2026-01-06 10:54 ` [PATCH v9 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver Varadarajan Narayanan
@ 2026-01-12 6:08 ` Gokul Sriram P
0 siblings, 0 replies; 10+ messages in thread
From: Gokul Sriram P @ 2026-01-12 6:08 UTC (permalink / raw)
To: Varadarajan Narayanan, andersson, mathieu.poirier, robh, krzk+dt,
conor+dt, konradybcio, quic_mmanikan, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel
Cc: Vignesh Viswanathan, Gokul Sriram Palanisamy, George Moussalem
Hi Varada,
On 1/6/2026 4:24 PM, Varadarajan Narayanan wrote:
> From: Vignesh Viswanathan <vignesh.viswanathan@oss.qualcomm.com>
>
> Add support to bring up hexagon based WCSS using secure PIL. All IPQxxxx
> SoCs support secure Peripheral Image Loading (PIL).
>
> Secure PIL image is signed firmware image which only trusted software such
> as TrustZone (TZ) can authenticate and load. Linux kernel will send a
> Peripheral Authentication Service (PAS) request to TZ to authenticate and
> load the PIL images.
>
> In order to avoid overloading the existing WCSS driver or PAS driver, we
> came up with this new PAS based IPQ WCSS driver.
>
> Signed-off-by: Vignesh Viswanathan <vignesh.viswanathan@oss.qualcomm.com>
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> [ Dropped ipq5424 support ]
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---
> v8: Dropped ipq5424 support.
> The comments related to 'use_tmelcom' in [1] not applicable
> [1] https://lore.kernel.org/linux-arm-msm/72f0d4f7-8d8a-4fc5-bac2-8094e971a0e3@oss.qualcomm.com/
> Changed copyright for drivers/remoteproc/qcom_q6v5_wcss_sec.c
> ---
> drivers/remoteproc/Kconfig | 19 ++
> drivers/remoteproc/Makefile | 1 +
> drivers/remoteproc/qcom_q6v5_wcss_sec.c | 328 ++++++++++++++++++++++++
> include/linux/remoteproc.h | 2 +
> 4 files changed, 350 insertions(+)
> create mode 100644 drivers/remoteproc/qcom_q6v5_wcss_sec.c
>
[...]
> diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/qcom_q6v5_wcss_sec.c
> new file mode 100644
> index 000000000000..10fe3391decb
> --- /dev/null
> +++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c
> @@ -0,0 +1,328 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#include <linux/clk.h>
> +#include <linux/firmware/qcom/qcom_scm.h>
> +#include <linux/io.h>
> +#include <linux/mailbox_client.h>
> +#include <linux/of_reserved_mem.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/qcom/mdt_loader.h>
> +
> +#include "qcom_common.h"
> +#include "qcom_q6v5.h"
> +#include "qcom_pil_info.h"
> +
> +#define WCSS_CRASH_REASON 421
> +
> +#define WCSS_PAS_ID 0x6
> +#define MPD_WCSS_PAS_ID 0xd
> +
> +#define Q6_WAIT_TIMEOUT (5 * HZ)
> +
> +struct wcss_sec {
> + struct device *dev;
> + struct qcom_rproc_glink glink_subdev;
> + struct qcom_rproc_ssr ssr_subdev;
> + struct qcom_q6v5 q6;
> + phys_addr_t mem_phys;
> + phys_addr_t mem_reloc;
> + void *mem_region;
> + size_t mem_size;
> + const struct wcss_data *desc;
> +
> + struct mbox_client mbox_client;
> + struct mbox_chan *mbox_chan;
> + void *metadata;
> + size_t metadata_len;
above member variables are now unused.
[...]
> +
> +static int wcss_sec_probe(struct platform_device *pdev)
> +{
> + const struct wcss_data *desc = of_device_get_match_data(&pdev->dev);
> + const char *fw_name = NULL;
> + struct wcss_sec *wcss;
> + struct clk *sleep_clk;
> + struct clk *int_clk;
> + struct rproc *rproc;
> + int ret;
> +
> + ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
> + &fw_name);
> + if (ret < 0)
> + return ret;
> +
> + rproc = devm_rproc_alloc(&pdev->dev, desc->ss_name, &wcss_sec_ops,
> + fw_name, sizeof(*wcss));
> + if (!rproc) {
> + dev_err(&pdev->dev, "failed to allocate rproc\n");
> + return -ENOMEM;
> + }
> +
> + wcss = rproc->priv;
> + wcss->dev = &pdev->dev;
> + wcss->desc = desc;
> +
> + ret = wcss_sec_alloc_memory_region(wcss);
> + if (ret)
> + return ret;
> +
> + sleep_clk = devm_clk_get_optional_enabled(&pdev->dev, "sleep");
> + if (IS_ERR(sleep_clk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(sleep_clk),
> + "Failed to get sleep clock\n");
> +
> + int_clk = devm_clk_get_optional_enabled(&pdev->dev, "interconnect");
> + if (IS_ERR(int_clk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(int_clk),
> + "Failed to get interconnect clock\n");
> +
> + ret = qcom_q6v5_init(&wcss->q6, pdev, rproc,
> + WCSS_CRASH_REASON, NULL, NULL);
> + if (ret)
> + return ret;
> +
> + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ss_name);
> + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ss_name);
> +
> + rproc->auto_boot = false;
> + rproc->dump_conf = RPROC_COREDUMP_INLINE;
> + rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
> +
> + ret = devm_rproc_add(&pdev->dev, rproc);
> + if (ret)
On failure, please include
qcom_remove_glink_subdev(rproc, &wcss->glink_subdev);
qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev);Regards,
Regards,
Gokul
> + return ret;
> +
> + platform_set_drvdata(pdev, rproc);
> +
> + return 0;
> +}
> +
> +static void wcss_sec_remove(struct platform_device *pdev)
> +{
> + struct rproc *rproc = platform_get_drvdata(pdev);
> + struct wcss_sec *wcss = rproc->priv;
> +
> + mbox_free_channel(wcss->mbox_chan);
> + qcom_remove_glink_subdev(rproc, &wcss->glink_subdev);
> + qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev);
> + qcom_q6v5_deinit(&wcss->q6);
> +}
> +
> +static const struct wcss_data wcss_sec_ipq5332_res_init = {
> + .pasid = MPD_WCSS_PAS_ID,
> + .ss_name = "q6wcss",
> +};
> +
> +static const struct wcss_data wcss_sec_ipq9574_res_init = {
> + .pasid = WCSS_PAS_ID,
> + .ss_name = "q6wcss",
> +};
> +
> +static const struct of_device_id wcss_sec_of_match[] = {
> + { .compatible = "qcom,ipq5018-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init },
> + { .compatible = "qcom,ipq5332-wcss-sec-pil", .data = &wcss_sec_ipq5332_res_init },
> + { .compatible = "qcom,ipq9574-wcss-sec-pil", .data = &wcss_sec_ipq9574_res_init },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, wcss_sec_of_match);
> +
> +static struct platform_driver wcss_sec_driver = {
> + .probe = wcss_sec_probe,
> + .remove = wcss_sec_remove,
> + .driver = {
> + .name = "qcom-wcss-secure-pil",
> + .of_match_table = wcss_sec_of_match,
> + },
> +};
> +module_platform_driver(wcss_sec_driver);
> +
> +MODULE_DESCRIPTION("Hexagon WCSS Secure Peripheral Image Loader");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
> index b4795698d8c2..7b2159853345 100644
> --- a/include/linux/remoteproc.h
> +++ b/include/linux/remoteproc.h
> @@ -472,6 +472,7 @@ enum rproc_dump_mechanism {
> * @node: list node related to the rproc segment list
> * @da: device address of the segment
> * @size: size of the segment
> + * @io_ptr: ptr to store the ioremapped dump segment
> * @priv: private data associated with the dump_segment
> * @dump: custom dump function to fill device memory segment associated
> * with coredump
> @@ -483,6 +484,7 @@ struct rproc_dump_segment {
> dma_addr_t da;
> size_t size;
>
> + void *io_ptr;
> void *priv;
> void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment,
> void *dest, size_t offset, size_t size);
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v9 4/6] arm64: dts: qcom: ipq5018: add nodes to bring up q6
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
` (2 preceding siblings ...)
2026-01-06 10:54 ` [PATCH v9 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 5/6] arm64: dts: qcom: ipq5332: " Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 6/6] arm64: dts: qcom: ipq9574: " Varadarajan Narayanan
5 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: George Moussalem, Dmitry Baryshkov, Varadarajan Narayanan
From: George Moussalem <george.moussalem@outlook.com>
Enable nodes required for q6 remoteproc bring up.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
[ Change 'qcom,smem-state-names' order to resolve dt-bindings-check error ]
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v8: Swap the order of the items in 'qcom,smem-state-names" to resolve dt-bindings-check error
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 64 +++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index f024b3cba33f..d077f0ed9e46 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -158,6 +158,35 @@ tz_region: tz@4ac00000 {
reg = <0x0 0x4ac00000 0x0 0x200000>;
no-map;
};
+
+ q6_region: wcss@4b000000 {
+ no-map;
+ reg = <0x0 0x4b000000 0x0 0x1b00000>;
+ };
+ };
+
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
soc: soc@0 {
@@ -717,6 +746,41 @@ frame@b128000 {
};
};
+ q6v5_wcss: remoteproc@cd00000 {
+ compatible = "qcom,ipq5018-wcss-sec-pil";
+ reg = <0x0cd00000 0x10000>;
+ firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mbn";
+ interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <&wcss_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&wcss_smp2p_in 3 IRQ_TYPE_NONE>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&gcc GCC_SLEEP_CLK_SRC>,
+ <&gcc GCC_SYS_NOC_WCSS_AHB_CLK>;
+ clock-names = "sleep",
+ "interconnect";
+
+ qcom,smem-states = <&wcss_smp2p_out 1>,
+ <&wcss_smp2p_out 0>;
+ qcom,smem-state-names = "stop",
+ "shutdown";
+
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
+
pcie1: pcie@80000000 {
compatible = "qcom,pcie-ipq5018";
reg = <0x80000000 0xf1d>,
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 5/6] arm64: dts: qcom: ipq5332: add nodes to bring up q6
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
` (3 preceding siblings ...)
2026-01-06 10:54 ` [PATCH v9 4/6] arm64: dts: qcom: ipq5018: add nodes to bring up q6 Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
2026-01-06 10:54 ` [PATCH v9 6/6] arm64: dts: qcom: ipq9574: " Varadarajan Narayanan
5 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: Gokul Sriram Palanisamy, George Moussalem, Konrad Dybcio,
Dmitry Baryshkov, Varadarajan Narayanan
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Enable nodes required for q6 remoteproc bring up.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v9: Add R-b Konrad and Signed-off-by
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 64 ++++++++++++++++++++++++++-
1 file changed, 63 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 45fc512a3bab..c31b6906355e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -2,7 +2,7 @@
/*
* IPQ5332 device tree source
*
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
@@ -146,6 +146,35 @@ smem@4a800000 {
hwlocks = <&tcsr_mutex 3>;
};
+
+ q6_region: wcss@4a900000 {
+ reg = <0x0 0x4a900000 0x0 0x2b00000>;
+ no-map;
+ };
+ };
+
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_wcss_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wcss_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
soc@0 {
@@ -586,6 +615,39 @@ frame@b128000 {
};
};
+ q6v5_wcss: remoteproc@d100000 {
+ compatible = "qcom,ipq5332-wcss-sec-pil";
+ reg = <0x0d100000 0x10000>;
+ firmware-name = "ath12k/IPQ5332/hw1.0/q6_fw0.mbn";
+ interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wcss_in 0 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 1 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 2 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 3 IRQ_TYPE_NONE>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&gcc GCC_IM_SLEEP_CLK>;
+ clock-names = "sleep";
+
+ qcom,smem-states = <&smp2p_wcss_out 1>,
+ <&smp2p_wcss_out 0>;
+ qcom,smem-state-names = "stop",
+ "shutdown";
+
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
+
pcie1: pcie@18000000 {
compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
reg = <0x18000000 0xf1c>,
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v9 6/6] arm64: dts: qcom: ipq9574: add nodes to bring up q6
2026-01-06 10:54 [PATCH v9 0/6] Add new driver for WCSS secure PIL loading Varadarajan Narayanan
` (4 preceding siblings ...)
2026-01-06 10:54 ` [PATCH v9 5/6] arm64: dts: qcom: ipq5332: " Varadarajan Narayanan
@ 2026-01-06 10:54 ` Varadarajan Narayanan
5 siblings, 0 replies; 10+ messages in thread
From: Varadarajan Narayanan @ 2026-01-06 10:54 UTC (permalink / raw)
To: andersson, mathieu.poirier, robh, krzk+dt, conor+dt, konradybcio,
quic_mmanikan, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Cc: Gokul Sriram Palanisamy, George Moussalem, Konrad Dybcio,
Dmitry Baryshkov, Varadarajan Narayanan
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Enable nodes required for q6 remoteproc bring up.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <gokul.sriram.p@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
v9: Add R-b Konrad and Signed-off-by
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 86c9cb9fffc9..6d513fe6ad58 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -3,7 +3,7 @@
* IPQ9574 SoC device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
@@ -226,6 +226,35 @@ smem@4aa00000 {
hwlocks = <&tcsr_mutex 3>;
no-map;
};
+
+ q6_region: wcss@4ab00000 {
+ reg = <0x0 0x4ab00000 0x0 0x2b00000>;
+ no-map;
+ };
+ };
+
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_wcss_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wcss_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
soc: soc@0 {
@@ -903,6 +932,35 @@ frame@b128000 {
};
};
+ q6v5_wcss: remoteproc@cd00000 {
+ compatible = "qcom,ipq9574-wcss-sec-pil";
+ reg = <0x0cd00000 0x10000>;
+ firmware-name = "ath11k/IPQ9574/hw1.0/q6_fw.mbn";
+ interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wcss_in 0 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 1 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 2 IRQ_TYPE_NONE>,
+ <&smp2p_wcss_in 3 IRQ_TYPE_NONE>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ qcom,smem-states = <&smp2p_wcss_out 1>,
+ <&smp2p_wcss_out 0>;
+ qcom,smem-state-names = "stop",
+ "shutdown";
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ label = "rtr";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+ };
+ };
+
pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq9574";
reg = <0x10000000 0xf1d>,
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread