* [PATCH] iommu/arm-smmu: Fix bug in ARM_SMMU_FEAT_TRANS_OPS condition check
@ 2015-06-23 12:07 Sricharan R
2015-06-23 12:12 ` Baptiste Reynal
0 siblings, 1 reply; 3+ messages in thread
From: Sricharan R @ 2015-06-23 12:07 UTC (permalink / raw)
To: linux-arm-kernel, iommu, will.deacon, b.reynal, linux-arm-msm,
linux-kernel
Cc: sricharan
Patch 'fix ARM_SMMU_FEAT_TRANS_OPS condition' changed the check
for ARM_SMMU_FEAT_TRANS_OPS to be based on presence of stage1 check,
but used (id & ID0_ATOSNS) instead of !(id & ID0_ATOSNS).
Fix it here.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/iommu/arm-smmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 09091e9..fbf4af6 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1866,7 +1866,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
return -ENODEV;
}
- if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
+ if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) {
smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
dev_notice(smmu->dev, "\taddress translation ops\n");
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] iommu/arm-smmu: Fix bug in ARM_SMMU_FEAT_TRANS_OPS condition check
2015-06-23 12:07 [PATCH] iommu/arm-smmu: Fix bug in ARM_SMMU_FEAT_TRANS_OPS condition check Sricharan R
@ 2015-06-23 12:12 ` Baptiste Reynal
[not found] ` <CAN9JPjGw+abvTX9mCb0M1K5AaxCHzVNx+ccf+iyDo34EL8KzRA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Baptiste Reynal @ 2015-06-23 12:12 UTC (permalink / raw)
To: Sricharan R
Cc: moderated list:ARM SMMU DRIVER, Linux IOMMU, Will Deacon,
linux-arm-msm, open list
This issue has already been fixed here :
http://www.spinics.net/lists/arm-kernel/msg424824.html
Regards,
Baptiste
On Tue, Jun 23, 2015 at 2:07 PM, Sricharan R <sricharan@codeaurora.org> wrote:
> Patch 'fix ARM_SMMU_FEAT_TRANS_OPS condition' changed the check
> for ARM_SMMU_FEAT_TRANS_OPS to be based on presence of stage1 check,
> but used (id & ID0_ATOSNS) instead of !(id & ID0_ATOSNS).
> Fix it here.
>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> drivers/iommu/arm-smmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 09091e9..fbf4af6 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1866,7 +1866,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
> return -ENODEV;
> }
>
> - if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
> + if ((id & ID0_S1TS) && ((smmu->version == 1) || !(id & ID0_ATOSNS))) {
> smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
> dev_notice(smmu->dev, "\taddress translation ops\n");
> }
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-06-25 6:59 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-06-23 12:07 [PATCH] iommu/arm-smmu: Fix bug in ARM_SMMU_FEAT_TRANS_OPS condition check Sricharan R
2015-06-23 12:12 ` Baptiste Reynal
[not found] ` <CAN9JPjGw+abvTX9mCb0M1K5AaxCHzVNx+ccf+iyDo34EL8KzRA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-06-25 6:59 ` Sricharan
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox