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From: Rajendra Nayak <rnayak@codeaurora.org>
To: bjorn.andersson@linaro.org, agross@kernel.org,
	robdclark@gmail.com, robdclark@chromium.org,
	stanimir.varbanov@linaro.org
Cc: viresh.kumar@linaro.org, sboyd@kernel.org, mka@chromium.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rajendra Nayak <rnayak@codeaurora.org>,
	Sean Paul <sean@poorly.run>,
	dri-devel@lists.freedesktop.org
Subject: [PATCH v6 3/6] drm/msm/dpu: Use OPP API to set clk/perf state
Date: Mon, 15 Jun 2020 17:32:41 +0530	[thread overview]
Message-ID: <1592222564-13556-4-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1592222564-13556-1-git-send-email-rnayak@codeaurora.org>

On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: dri-devel@lists.freedesktop.org
---
No functional change in v6, rebased over 5.8-rc1

 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  3 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       | 26 +++++++++++++++++++++++++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h       |  4 ++++
 3 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 7c230f7..b36919d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -7,6 +7,7 @@
 #include <linux/debugfs.h>
 #include <linux/errno.h>
 #include <linux/mutex.h>
+#include <linux/pm_opp.h>
 #include <linux/sort.h>
 #include <linux/clk.h>
 #include <linux/bitmap.h>
@@ -218,7 +219,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
 		rate = core_clk->max_rate;
 
 	core_clk->rate = rate;
-	return msm_dss_clk_set_rate(core_clk, 1);
+	return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
 }
 
 static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index b8615d4..0bc8ec4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -10,6 +10,7 @@
 #include <linux/debugfs.h>
 #include <linux/dma-buf.h>
 #include <linux/of_irq.h>
+#include <linux/pm_opp.h>
 
 #include <drm/drm_crtc.h>
 #include <drm/drm_file.h>
@@ -1025,11 +1026,23 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
 	if (!dpu_kms)
 		return -ENOMEM;
 
+	dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
+	if (IS_ERR(dpu_kms->opp_table))
+		return PTR_ERR(dpu_kms->opp_table);
+	/* OPP table is optional */
+	ret = dev_pm_opp_of_add_table(dev);
+	if (!ret) {
+		dpu_kms->has_opp_table = true;
+	} else if (ret != -ENODEV) {
+		dev_err(dev, "invalid OPP table in device tree\n");
+		return ret;
+	}
+
 	mp = &dpu_kms->mp;
 	ret = msm_dss_parse_clock(pdev, mp);
 	if (ret) {
 		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
-		return ret;
+		goto err;
 	}
 
 	platform_set_drvdata(pdev, dpu_kms);
@@ -1043,6 +1056,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
 
 	priv->kms = &dpu_kms->base;
 	return ret;
+err:
+	if (dpu_kms->has_opp_table)
+		dev_pm_opp_of_remove_table(dev);
+	dev_pm_opp_put_clkname(dpu_kms->opp_table);
+	return ret;
 }
 
 static void dpu_unbind(struct device *dev, struct device *master, void *data)
@@ -1057,6 +1075,10 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
 
 	if (dpu_kms->rpm_enabled)
 		pm_runtime_disable(&pdev->dev);
+
+	if (dpu_kms->has_opp_table)
+		dev_pm_opp_of_remove_table(dev);
+	dev_pm_opp_put_clkname(dpu_kms->opp_table);
 }
 
 static const struct component_ops dpu_ops = {
@@ -1082,6 +1104,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
 	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
 	struct dss_module_power *mp = &dpu_kms->mp;
 
+	/* Drop the performance state vote */
+	dev_pm_opp_set_rate(dev, 0);
 	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
 	if (rc)
 		DPU_ERROR("clock disable failed rc:%d\n", rc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index a3b122b..7400cd7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -128,6 +128,10 @@ struct dpu_kms {
 
 	struct platform_device *pdev;
 	bool rpm_enabled;
+
+	struct opp_table *opp_table;
+	bool has_opp_table;
+
 	struct dss_module_power mp;
 
 	/* reference count bandwidth requests, so we know when we can
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


  parent reply	other threads:[~2020-06-15 12:04 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-15 12:02 [PATCH v6 0/6] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-06-15 12:02 ` [PATCH v6 1/6] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-06-25  5:08   ` Bjorn Andersson
2020-06-30 12:16     ` Rajendra Nayak
2020-06-29 23:17   ` Stephen Boyd
2020-06-30  3:01     ` Rajendra Nayak
2020-06-30  3:05       ` Viresh Kumar
2020-07-21  8:43         ` Stephen Boyd
2020-07-22  5:24           ` Viresh Kumar
2020-08-20 10:45             ` Viresh Kumar
2020-06-15 12:02 ` [PATCH v6 2/6] spi: spi-geni-qcom: " Rajendra Nayak
2020-06-15 12:02 ` Rajendra Nayak [this message]
2020-06-15 12:02 ` [PATCH v6 4/6] drm/msm: dsi: " Rajendra Nayak
2020-06-15 12:02 ` [PATCH v6 5/6] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-06-18 14:54   ` Stanimir Varbanov
2020-06-15 12:02 ` [PATCH v6 6/6] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-06-24 17:09   ` Matthias Kaehlcke
2020-06-24 17:15     ` Mark Brown
2020-06-24 17:39       ` Matthias Kaehlcke
2020-06-24 17:44         ` Mark Brown
2020-06-24 17:55           ` Matthias Kaehlcke
2020-06-24 18:00             ` Mark Brown
2020-06-24 18:12               ` Matthias Kaehlcke
2020-06-24 18:15                 ` Mark Brown
2020-06-25 15:25                 ` Matthias Kaehlcke
2020-06-29 11:30                   ` Rajendra Nayak
2020-06-29 10:57                 ` Rajendra Nayak
2020-06-17 22:15 ` [PATCH v6 0/6] DVFS for IO devices on sdm845 and sc7180 Matthias Kaehlcke
2020-06-18  4:47   ` Rajendra Nayak
2020-06-18  8:20     ` Stanimir Varbanov
2020-06-18 12:11       ` Rajendra Nayak
2020-06-18 12:25         ` Stanimir Varbanov
2020-07-01 11:28           ` Rajendra Nayak

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