From: Bjorn Andersson <andersson@kernel.org>
To: konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Qiang Yu <quic_qianyu@quicinc.com>
Cc: johan@kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
quic_cang@quicinc.com, quic_mrana@quicinc.com,
stable@vger.kernel.org
Subject: Re: (subset) [PATCH 1/1] arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
Date: Tue, 17 Dec 2024 10:38:54 -0600 [thread overview]
Message-ID: <173445353302.470882.8616229131234263005.b4-ty@kernel.org> (raw)
In-Reply-To: <20241113080508.3458849-1-quic_qianyu@quicinc.com>
On Wed, 13 Nov 2024 00:05:08 -0800, Qiang Yu wrote:
> As per memory map table, the region for PCIe6a is 64MByte. Hence, set the
> size of 32 bit non-prefetchable memory region beginning on address
> 0x70300000 as 0x3d00000 so that BAR space assigned to BAR registers can be
> allocated from 0x70300000 to 0x74000000.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
commit: fb8e7b33c2174e00dfa411361eeed21eeaf3634b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
prev parent reply other threads:[~2024-12-17 16:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-13 8:05 [PATCH 1/1] arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a Qiang Yu
2024-11-13 14:17 ` Johan Hovold
2024-12-17 16:38 ` Bjorn Andersson [this message]
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