Re: [PATCH v2 1/5] clk: qcom: cmnpll: Account for reference clock divider

[Jie Luo <jie.luo@oss.qualcomm.com>]

On 1/7/2026 9:17 PM, George Moussalem wrote:
>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>> rate = (parent_rate / ref_div) * 2 * factor.
>>
>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>> IPQ5424, IPQ5018) that use ref_div = 1.
> Just tested this patch and can confirm IPQ5018 also has a ref_div of 2.
> With this patch applied, the correct assigned clock rate of 4.8GHz is
> also reported:
> 
> root@OpenWrt:~# cat /sys/kernel/debug/clk/clk_summary | grep cmn -A 3 -B 3
> 
>                                   deviceless
> no_connection_id
>  xo-clk                              1       1        0        48000000
>   0          0     50000      Y   deviceless
> no_connection_id
>     ref-96mhz-clk                    1       1        0        96000000
>   0          0     50000      Y      deviceless
> no_connection_id
>        cmn_pll                       0       0        0
> 4800000000  0          0     50000      Y         deviceless
>          no_connection_id
>           eth-50mhz                  0       0        0        50000000
>   0          0     50000      Y            deviceless
>   no_connection_id
>           sleep-32khz                0       0        0        32000
>   0          0     50000      Y            deviceless
>   no_connection_id
>           xo-24mhz                   0       0        0        24000000
>   0          0     50000      Y            deviceless
>   no_connection_id
> 
> Once accepted, I will submit a patch to correct the assigned clock rate
> from 9.6GHz to 4.8GHz as the ref div is now properly applied.

Thanks for validating this on the IPQ5018 platform.