Re: [PATCH v2 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 1/7/26 6:35 AM, Luo Jie wrote:
> The CMN PLL in IPQ5332 SoC produces different output clocks when compared
> to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch
> (50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different.
> 
> Add IPQ5332-specific clock definitions and of_device_id entry.
> 
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/ipq-cmn-pll.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
> index 369798d1ce42..962462286837 100644
> --- a/drivers/clk/qcom/ipq-cmn-pll.c
> +++ b/drivers/clk/qcom/ipq-cmn-pll.c
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  /*
> - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>   */
>  
>  /*
> @@ -20,6 +20,11 @@
>   * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
>   * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
>   *
> + * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to
> + * the Ethernet PHY (or switch) via the UNIPHY (PCS). It also supplies a 200
> + * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS
> + * are the same as those in the IPQ9574 SoC.
> + *
>   *               +---------+
>   *               |   GCC   |
>   *               +--+---+--+
> @@ -51,6 +56,7 @@
>  
>  #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
>  #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
> +#include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h>
>  #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
>  
>  #define CMN_PLL_REFCLK_SRC_SELECTION		0x28
> @@ -117,6 +123,16 @@ static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = {
>  	{ /* Sentinel */ }
>  };
>  
> +static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = {
> +	CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
> +	CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
> +	CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
> +	CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
> +	CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL),
> +	CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
> +	{ /* Sentinel */ }

Trusting you on these entries as I can't find a source

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad