From: Jeffrey Hugo <jhugo@codeaurora.org>
To: Marc Gonzalez <marc.w.gonzalez@free.fr>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Nicolas Dechesne <nicolas.dechesne@linaro.org>,
Niklas Cassel <niklas.cassel@linaro.org>,
Andy Gross <andy.gross@linaro.org>
Cc: MSM <linux-arm-msm@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: WIP: UFS on apq8098
Date: Tue, 4 Dec 2018 10:21:59 -0700 [thread overview]
Message-ID: <1dbb2f0b-0ad1-e622-a9c4-9ff7284dbee7@codeaurora.org> (raw)
In-Reply-To: <0c189977-62dd-3539-3b5c-233773682e69@free.fr>
On 12/4/2018 10:11 AM, Marc Gonzalez wrote:
> On 04/12/2018 18:05, Jeffrey Hugo wrote:
>
>> mount -t debugfs none /sys/kernel/debug
>
> Doh!
>
> # cat /sys/kernel/debug/clk/clk_summary
> enable prepare protect duty
> clock count count count rate accuracy phase cycle
> ---------------------------------------------------------------------------------------------
> gcc_usb_phy_cfg_ahb2phy_clk 0 0 0 0 0 0 50000
> gcc_usb3_phy_pipe_clk 0 0 0 0 0 0 50000
> gcc_usb30_sleep_clk 0 0 0 0 0 0 50000
> gcc_ufs_unipro_core_clk 0 0 0 0 0 0 50000
Yeah, this clock has no parent, and is one of the ones that is a delta
from the downsteam per your logs.
> gcc_ufs_tx_symbol_0_clk 0 0 0 0 0 0 50000
> gcc_ufs_rx_symbol_1_clk 0 0 0 0 0 0 50000
> gcc_ufs_rx_symbol_0_clk 0 0 0 0 0 0 50000
> gcc_ufs_phy_aux_clk 0 0 0 0 0 0 50000
> gcc_ufs_ice_core_clk 0 0 0 0 0 0 50000
> gcc_ufs_ahb_clk 0 0 0 0 0 0 50000
> gcc_tsif_inactivity_timers_clk 0 0 0 0 0 0 50000
> gcc_tsif_ahb_clk 0 0 0 0 0 0 50000
> gcc_sdcc4_ahb_clk 0 0 0 0 0 0 50000
> gcc_sdcc2_ahb_clk 0 0 0 0 0 0 50000
> gcc_prng_ahb_clk 0 0 0 0 0 0 50000
> gcc_pdm_xo4_clk 0 0 0 0 0 0 50000
> gcc_pdm_ahb_clk 0 0 0 0 0 0 50000
> gcc_pcie_0_slv_axi_clk 0 0 0 0 0 0 50000
> gcc_pcie_0_pipe_clk 0 0 0 0 0 0 50000
> gcc_pcie_0_mstr_axi_clk 0 0 0 0 0 0 50000
> gcc_pcie_0_cfg_ahb_clk 0 0 0 0 0 0 50000
> gcc_mss_at_clk 0 0 0 0 0 0 50000
> gcc_mmss_sys_noc_axi_clk 0 0 0 0 0 0 50000
> gcc_mmss_qm_core_clk 0 0 0 0 0 0 50000
> gcc_mmss_qm_ahb_clk 0 0 0 0 0 0 50000
> gcc_mmss_noc_cfg_ahb_clk 0 0 0 0 0 0 50000
> gcc_lpass_trig_clk 0 0 0 0 0 0 50000
> gcc_lpass_at_clk 1 1 0 0 0 0 50000
> gcc_hmss_trig_clk 0 0 0 0 0 0 50000
> gcc_hmss_dvm_bus_clk 1 1 0 0 0 0 50000
> gcc_hmss_at_clk 0 0 0 0 0 0 50000
> gcc_gpu_snoc_dvm_gfx_clk 0 0 0 0 0 0 50000
> gcc_gpu_cfg_ahb_clk 0 0 0 0 0 0 50000
> gcc_gpu_bimc_gfx_src_clk 0 0 0 0 0 0 50000
> gcc_gpu_bimc_gfx_clk 0 0 0 0 0 0 50000
> gcc_blsp2_sleep_clk 0 0 0 0 0 0 50000
> gcc_blsp2_ahb_clk 3 3 0 0 0 0 50000
> gcc_blsp1_sleep_clk 0 0 0 0 0 0 50000
> gcc_blsp1_ahb_clk 0 0 0 0 0 0 50000
> gcc_bimc_mss_q6_axi_clk 0 0 0 0 0 0 50000
> gcc_bimc_hmss_axi_clk 0 0 0 0 0 0 50000
> gcc_apss_qdss_tsctr_div8_clk 0 0 0 0 0 0 50000
> gcc_apss_qdss_tsctr_div2_clk 0 0 0 0 0 0 50000
> gcc_aggre1_noc_xo_clk 0 0 0 0 0 0 50000
> sleep_clk 0 0 0 32764 0 0 50000
> xo 1 1 0 19200000 0 0 50000
> gcc_rx1_usb2_clkref_clk 0 0 0 19200000 0 0 50000
> gcc_pcie_clkref_clk 0 0 0 19200000 0 0 50000
> gcc_ufs_clkref_clk 0 0 0 19200000 0 0 50000
> gcc_hdmi_clkref_clk 0 0 0 19200000 0 0 50000
> gcc_usb3_clkref_clk 0 0 0 19200000 0 0 50000
> usb3_phy_aux_clk_src 0 0 0 1200000 0 0 50000
> gcc_usb3_phy_aux_clk 0 0 0 1200000 0 0 50000
> usb30_mock_utmi_clk_src 0 0 0 19200000 0 0 50000
> gcc_usb30_mock_utmi_clk 0 0 0 19200000 0 0 50000
> tsif_ref_clk_src 0 0 0 19200000 0 0 50000
> gcc_tsif_ref_clk 0 0 0 19200000 0 0 50000
> sdcc4_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_sdcc4_apps_clk 0 0 0 19200000 0 0 50000
> sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000
> pdm2_clk_src 0 0 0 19200000 0 0 50000
> gcc_pdm2_clk 0 0 0 19200000 0 0 50000
> pcie_aux_clk_src 0 0 0 19200000 0 0 50000
> gcc_pcie_0_aux_clk 0 0 0 19200000 0 0 50000
> gcc_pcie_phy_aux_clk 0 0 0 19200000 0 0 50000
> hmss_rbcpr_clk_src 0 0 0 19200000 0 0 50000
> gcc_hmss_rbcpr_clk 0 0 0 19200000 0 0 50000
> hmss_ahb_clk_src 0 0 0 19200000 0 0 50000
> gcc_hmss_ahb_clk 0 0 0 19200000 0 0 50000
> gpll4 0 0 0 384000000 0 0 50000
> gpll4_out_test 0 0 0 384000000 0 0 50000
> gpll4_out_odd 0 0 0 384000000 0 0 50000
> gpll4_out_main 0 0 0 384000000 0 0 50000
> gpll4_out_even 0 0 0 384000000 0 0 50000
> gpll3 0 0 0 921600000 0 0 50000
> gpll3_out_test 0 0 0 921600000 0 0 50000
> gpll3_out_odd 0 0 0 921600000 0 0 50000
> gpll3_out_main 0 0 0 921600000 0 0 50000
> gpll3_out_even 0 0 0 921600000 0 0 50000
> gpll2 0 0 0 1286400000 0 0 50000
> gpll2_out_test 0 0 0 1286400000 0 0 50000
> gpll2_out_odd 0 0 0 1286400000 0 0 50000
> gpll2_out_main 0 0 0 1286400000 0 0 50000
> gpll2_out_even 0 0 0 1286400000 0 0 50000
> gpll1 0 0 0 1056000000 0 0 50000
> gpll1_out_test 0 0 0 1056000000 0 0 50000
> gpll1_out_odd 0 0 0 1056000000 0 0 50000
> gpll1_out_main 0 0 0 1056000000 0 0 50000
> gpll1_out_even 0 0 0 1056000000 0 0 50000
> gpll0 0 0 0 595200000 0 0 50000
> gpll0_out_test 0 0 0 595200000 0 0 50000
> gpll0_out_odd 0 0 0 595200000 0 0 50000
> gpll0_out_main 0 0 0 595200000 0 0 50000
> usb30_master_clk_src 0 0 0 119040000 0 0 50000
> gcc_aggre1_usb3_axi_clk 0 0 0 119040000 0 0 50000
> gcc_cfg_noc_usb3_axi_clk 0 0 0 119040000 0 0 50000
> gcc_usb30_master_clk 0 0 0 119040000 0 0 50000
> ufs_axi_clk_src 0 0 0 198400000 0 0 50000
> gcc_aggre1_ufs_axi_clk 0 0 0 198400000 0 0 50000
> gcc_ufs_axi_clk 0 0 0 198400000 0 0 50000
> gpll0_out_even 0 0 0 595200000 0 0 50000
> gp3_clk_src 0 0 0 19200000 0 0 50000
> gcc_gp3_clk 0 0 0 19200000 0 0 50000
> gp2_clk_src 0 0 0 19200000 0 0 50000
> gcc_gp2_clk 0 0 0 19200000 0 0 50000
> gp1_clk_src 0 0 0 19200000 0 0 50000
> gcc_gp1_clk 0 0 0 19200000 0 0 50000
> blsp2_uart3_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_uart3_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_uart2_apps_clk_src 1 1 0 1843200 0 0 50000
> gcc_blsp2_uart2_apps_clk 3 3 0 1843200 0 0 50000
> blsp2_uart1_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_uart1_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup6_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup6_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup6_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup6_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup5_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup5_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup5_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup5_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup4_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup4_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup4_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup4_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup3_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup3_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup3_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup3_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup2_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup2_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup2_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup2_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup1_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup1_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp2_qup1_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp2_qup1_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup6_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup6_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup6_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup6_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup5_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup5_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup5_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup5_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup4_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup4_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup4_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup4_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup3_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup3_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup3_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup3_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup2_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup2_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup2_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup2_i2c_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup1_spi_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup1_spi_apps_clk 0 0 0 19200000 0 0 50000
> blsp1_qup1_i2c_apps_clk_src 0 0 0 19200000 0 0 50000
> gcc_blsp1_qup1_i2c_apps_clk 0 0 0 19200000 0 0 50000
> ln_bb_a_clk1 0 0 0 0 0 0 50000
> ln_bb_clk1 0 0 0 0 0 0 50000
>
>
> There is no clock summary in 4.4 to compare the downstream kernel?
Not that I've seen. You can check each clock individually, but I
realize that is tedious.
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2018-12-04 17:21 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 15:18 WIP: UFS on apq8098 Marc Gonzalez
2018-12-03 15:27 ` Jeffrey Hugo
2018-12-03 15:47 ` Jeffrey Hugo
2018-12-03 15:53 ` Marc Gonzalez
2018-12-03 16:03 ` Jeffrey Hugo
2018-12-03 16:13 ` Marc Gonzalez
2018-12-03 16:18 ` Jeffrey Hugo
2018-12-03 16:22 ` Marc Gonzalez
2018-12-03 16:09 ` Bjorn Andersson
2018-12-03 16:53 ` Marc Gonzalez
2018-12-04 15:23 ` Marc Gonzalez
2018-12-04 15:45 ` Jeffrey Hugo
2018-12-04 16:14 ` Jeffrey Hugo
2018-12-04 16:17 ` Marc Gonzalez
2018-12-04 16:35 ` Jeffrey Hugo
2018-12-04 17:03 ` Marc Gonzalez
2018-12-04 17:05 ` Jeffrey Hugo
2018-12-04 17:11 ` Marc Gonzalez
2018-12-04 17:21 ` Jeffrey Hugo [this message]
2018-12-04 17:31 ` Jeffrey Hugo
2018-12-06 16:15 ` Marc Gonzalez
2018-12-06 16:45 ` Evan Green
2018-12-07 8:57 ` Marc Gonzalez
2018-12-07 9:29 ` Marc Gonzalez
2018-12-07 12:10 ` Marc Gonzalez
2018-12-07 17:14 ` Evan Green
2018-12-12 17:34 ` Marc Gonzalez
2018-12-13 10:51 ` Marc Gonzalez
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