Re: WIP: UFS on apq8098

[Jeffrey Hugo <jhugo@codeaurora.org>]

On 12/3/2018 8:27 AM, Jeffrey Hugo wrote:
> On 12/3/2018 8:18 AM, Marc Gonzalez wrote:
>> Hello,
>>
>> I'm trying to enable UFS on apq8098. Just wanted to share my progress
>> so far, in case someone spots any glaring mistakes.
> 
> Excellent.  This was down on my todo list.  I'm glad its getting some 
> attention.
> 
>>
>> (WIP patch provided at message's end.)
>>
>> rpm_smd_clk_probe() runs successfully, and returns 0.
>>
>> qcom_qmp_phy_probe() fails:
>>
>> [    0.913707] qcom-qmp-phy 1da7000.phy: Failed to get clk 'ref': -2
>> [    0.913761] qcom-qmp-phy: probe of 1da7000.phy failed with error -2
>>
>> ufs_qcom_probe() also fails (which may be caused by PHY failure)
>>
>> [    2.368486] ufshcd-qcom 1da4000.ufshc: ufshcd_get_vreg: vdd-hba get 
>> failed, err=-517
>> [    2.370673] ufshcd-qcom 1da4000.ufshc: Initialization failed
>> [    2.412908] ufshcd-qcom 1da4000.ufshc: ufshcd_pltfrm_init() failed 
>> -517
>>
>> I'll investigate the PHY init.
>>
>> Regards.
>>
>>
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> index b4276da1fb0d..ad7542f461af 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
>> @@ -241,3 +241,26 @@
>>           };
>>       };
>>   };
>> +
>> +&ufshc {
>> +    status = "ok";
>> +    vdd-hba-supply = <&gcc UFS_GDSC>;
>> +    vdd-hba-fixed-regulator;
>> +    vcc-supply = <&vreg_l20a_2p95>;
>> +    vccq-supply = <&vreg_l26a_1p2>;
>> +    vccq2-supply = <&vreg_s4a_1p8>;
>> +    vcc-max-microamp = <750000>;
>> +    vccq-max-microamp = <560000>;
>> +    vccq2-max-microamp = <750000>;
>> +};
>> +
>> +&ufsphy {
>> +    status = "ok";
>> +    vdda-phy-supply = <&vreg_l1a_0p875>;
>> +    vdda-pll-supply = <&vreg_l2a_1p2>;
>> +    vddp-ref-clk-supply = <&vreg_l26a_1p2>;
>> +    vdda-phy-max-microamp = <51400>;
>> +    vdda-pll-max-microamp = <14600>;
>> +    vddp-ref-clk-max-microamp = <100>;
>> +    vddp-ref-clk-always-on;
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi 
>> b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> index d291b4713c33..10e7b8a55b8a 100644
>> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
>> @@ -264,6 +264,11 @@
>>           rpm_requests: rpm-requests {
>>               compatible = "qcom,rpm-msm8998";
>>               qcom,glink-channels = "rpm_requests";
>> +
>> +            rpmcc: qcom,rpmcc {
>> +                compatible = "qcom,rpmcc-msm8998";
>> +                #clock-cells = <1>;
>> +            };
>>           };
>>       };
>> @@ -686,5 +691,79 @@
>>               redistributor-stride = <0x0 0x20000>;
>>               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>           };
>> +
>> +        ufshc: ufshc@1da4000 {
>> +            compatible = "qcom,msm8998-ufshc", "qcom,ufshc",
>> +                     "jedec,ufs-2.0";
>> +            reg = <0x1da4000 0x2500>;
>> +            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>> +            phys = <&ufsphy_lanes>;
>> +            phy-names = "ufsphy";
>> +            lanes-per-direction = <2>;
>> +            power-domains = <&gcc UFS_GDSC>;
>> +
>> +            clock-names =
>> +                "core_clk",
>> +                "bus_aggr_clk",
>> +                "iface_clk",
>> +                "core_clk_unipro",
>> +                "core_clk_ice",
>> +                "ref_clk",
>> +                "tx_lane0_sync_clk",
>> +                "rx_lane0_sync_clk",
>> +                "rx_lane1_sync_clk";
>> +            clocks =
>> +                <&gcc GCC_UFS_AXI_CLK>,
>> +                <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
>> +                <&gcc GCC_UFS_AHB_CLK>,
>> +                <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
>> +                <&gcc GCC_UFS_ICE_CORE_CLK>,
>> +                <&rpmcc 0>,
>> +                <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
>> +                <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
>> +                <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
>> +            freq-table-hz =
>> +                <50000000 200000000>,
>> +                <0 0>,
>> +                <0 0>,
>> +                <37500000 150000000>,
>> +                <75000000 300000000>,
>> +                <0 0>,
>> +                <0 0>,
>> +                <0 0>,
>> +                <0 0>;
>> +
>> +            resets = <&gcc GCC_UFS_BCR>;
> 
> I dunno how much this factors into your issues, but the resets defined 
> in gcc-msm8998.c are wrong.  I'm posting a patch later today.  I know 
> this was a problem for me with USB.
> 
>> +            reset-names = "rst";
>> +
>> +            status = "disabled";
>> +        };
>> +
>> +        ufsphy: phy@1da7000 {
>> +            compatible = "qcom,sdm845-qmp-ufs-phy";
>> +            reg = <0x1da7000 0x18c>;
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +            ranges;
>> +            clock-names =
>> +                "ref_clk_src",
>> +                "ref_clk",
>> +                "ref_aux_clk";
>> +            clocks =
>> +                <&rpmcc 0>,
>> +                <&gcc GCC_UFS_CLKREF_CLK>,

Also, "GCC_UFS_CLKREF_CLK" is not defined in 
include/dt-bindings/clock/qcom,gcc-msm8998.h which is probably the cause 
of your -2 error listed above.

>> +                <&gcc GCC_UFS_PHY_AUX_CLK>;
>> +
>> +            status = "disabled";
>> +
>> +            ufsphy_lanes: lanes@1da7400 {
>> +                reg = <0x1da7400 0x108>,
>> +                      <0x1da7600 0x1e0>,
>> +                      <0x1da7c00 0x1dc>,
>> +                      <0x1da7800 0x108>,
>> +                      <0x1da7a00 0x1e0>;
>> +                #phy-cells = <0>;
>> +            };
>> +        };
>>       };
>>   };
>> diff --git a/drivers/clk/qcom/clk-smd-rpm.c 
>> b/drivers/clk/qcom/clk-smd-rpm.c
>> index 850c02a52248..12a0a2d6ec7b 100644
>> --- a/drivers/clk/qcom/clk-smd-rpm.c
>> +++ b/drivers/clk/qcom/clk-smd-rpm.c
>> @@ -611,10 +611,25 @@ static const struct rpm_smd_clk_desc 
>> rpm_clk_msm8996 = {
>>       .num_clks = ARRAY_SIZE(msm8996_clks),
>>   };
>> +/* msm8998 */
>> +#define LN_BB_CLK1_ID 0x1
>> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_a_clk1, 
>> LN_BB_CLK1_ID);
>> +
>> +static struct clk_smd_rpm *msm8998_clks[] = {
>> +    [0] = &msm8998_ln_bb_clk1,
>> +    [1] = &msm8998_ln_bb_a_clk1,
>> +};
>> +
>> +static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
>> +    .clks = msm8998_clks,
>> +    .num_clks = ARRAY_SIZE(msm8998_clks),
>> +};
>> +
>>   static const struct of_device_id rpm_smd_clk_match_table[] = {
>>       { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
>>       { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
>>       { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
>> +    { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
>>       { }
>>   };
>>   MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
>>
> 
> 


-- 
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

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