From: Stephen Boyd <sboyd@codeaurora.org>
To: Archit Taneja <architt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96
Date: Thu, 19 Jan 2017 12:17:04 -0800 [thread overview]
Message-ID: <20170119201704.GC7829@codeaurora.org> (raw)
In-Reply-To: <1483794642-2184-11-git-send-email-architt@codeaurora.org>
On 01/07, Archit Taneja wrote:
> +
> +static struct clk *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
> + const char *name,
> + const char *parent_name,
> + unsigned long flags,
> + u8 shift)
> +{
> + struct dsi_pll_14nm_postdiv *pll_postdiv;
> + struct device *dev = &pll_14nm->pdev->dev;
> + struct clk_init_data postdiv_init = {
> + .parent_names = (const char *[]) { parent_name },
> + .num_parents = 1,
> + .name = name,
> + .flags = flags,
> + .ops = &clk_ops_dsi_pll_14nm_postdiv,
> + };
> +
> + pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
> + if (!pll_postdiv)
> + return ERR_PTR(-ENOMEM);
> +
> + pll_postdiv->pll = pll_14nm;
> + pll_postdiv->shift = shift;
> + /* both N1 and N2 postdividers are 4 bits wide */
> + pll_postdiv->width = 4;
> + /* range of each divider is from 1 to 15 */
> + pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
> + pll_postdiv->hw.init = &postdiv_init;
> +
> + return clk_register(dev, &pll_postdiv->hw);
Can you use clk_hw_register() and the variants instead? Same for
the clk_provider calls in this patch.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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next prev parent reply other threads:[~2017-01-19 20:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-07 13:10 [PATCH 00/10] drm/msm/dsi: Dual DSI and 8x96 PHY/PLL support Archit Taneja
2017-01-07 13:10 ` [PATCH 01/10] drm/msm/dsi: Don't error if a DSI host doesn't have a device connected Archit Taneja
2017-01-07 13:10 ` [PATCH 02/10] drm/msm/dsi: Add 8x96 info in dsi_cfg Archit Taneja
2017-01-07 13:10 ` [PATCH 03/10] drm/msm/dsi: Add a PHY op that initializes version specific stuff Archit Taneja
2017-01-07 13:10 ` [PATCH 04/10] drm/msm/dsi: Return more timings from PHY to host Archit Taneja
2017-01-07 13:10 ` [PATCH 05/10] drm/msm/dsi: Pass down use case to PHY Archit Taneja
2017-01-07 13:10 ` [PATCH 06/10] drm/msm/dsi: Reset both PHYs before clock operation for dual DSI Archit Taneja
2017-01-07 13:10 ` [PATCH 07/10] drm/msm/dsi: Move PHY operations out of host Archit Taneja
2017-01-07 13:10 ` [PATCH 08/10] drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL Archit Taneja
2017-01-07 13:10 ` [PATCH 09/10] drm/msm/dsi: Add new method to calculate 14nm PHY timings Archit Taneja
2017-01-07 13:10 ` [PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96 Archit Taneja
2017-01-19 20:17 ` Stephen Boyd [this message]
2017-01-23 4:06 ` Archit Taneja
2017-01-25 4:09 ` [PATCH v2 " Archit Taneja
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