[PATCH] drm/msm/adreno/a6xx: Set the GPU frequency after turning on the GMU

[PATCH] drm/msm/adreno/a6xx: Set the GPU frequency after turning on the GMU

[Jordan Crouse]

Set the correct initial GPU frequency on the GMU just after turning on
or resetting the GMU so it doesn't keep running at a horribly slow
speed.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index c49ca275a3b3..f8227f38b8cd 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -65,6 +65,26 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
 		A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 }
 
+static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
+{
+	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
+
+	gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
+		((index << 24) & 0xff) | (3 & 0xf));
+
+	/*
+	 * Send an invalid index as a vote for the bus bandwidth and let the
+	 * firmware decide on the right vote
+	 */
+	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
+
+	/* Set and clear the OOB for DCVS to trigger the GMU */
+	a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
+	a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
+
+	return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
+}
+
 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
 {
 	u32 val;
@@ -602,6 +622,9 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
 	if (!ret)
 		ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT);
 
+	/* Set the GPU back to the highest power frequency */
+	a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
+
 	if (ret)
 		a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
 
@@ -635,6 +658,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 
 	ret = a6xx_hfi_start(gmu, status);
 
+	/* Set the GPU to the highest power frequency */
+	a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
+
 out:
 	/* Make sure to turn off the boot OOB request on error */
 	if (ret)
-- 
2.18.0

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Re: [PATCH] drm/msm/adreno/a6xx: Set the GPU frequency after turning on the GMU

[Rob Clark]

On Fri, Aug 3, 2018 at 5:06 PM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Set the correct initial GPU frequency on the GMU just after turning on
> or resetting the GMU so it doesn't keep running at a horribly slow
> speed.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>


*much* better :-)

Tested-by: Rob Clark <robdclark@gmail.com>

> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index c49ca275a3b3..f8227f38b8cd 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -65,6 +65,26 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
>                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
>  }
>
> +static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
> +{
> +       gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
> +
> +       gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
> +               ((index << 24) & 0xff) | (3 & 0xf));
> +
> +       /*
> +        * Send an invalid index as a vote for the bus bandwidth and let the
> +        * firmware decide on the right vote
> +        */
> +       gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
> +
> +       /* Set and clear the OOB for DCVS to trigger the GMU */
> +       a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
> +       a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
> +
> +       return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
> +}
> +
>  static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
>  {
>         u32 val;
> @@ -602,6 +622,9 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
>         if (!ret)
>                 ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT);
>
> +       /* Set the GPU back to the highest power frequency */
> +       a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
> +
>         if (ret)
>                 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
>
> @@ -635,6 +658,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
>
>         ret = a6xx_hfi_start(gmu, status);
>
> +       /* Set the GPU to the highest power frequency */
> +       a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
> +
>  out:
>         /* Make sure to turn off the boot OOB request on error */
>         if (ret)
> --
> 2.18.0
>
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Re: [PATCH] drm/msm/adreno/a6xx: Set the GPU frequency after turning on the GMU

[Kristian Høgsberg]

On Fri, Aug 3, 2018 at 8:43 PM Rob Clark <robdclark@gmail.com> wrote:
>
> On Fri, Aug 3, 2018 at 5:06 PM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> >
> > Set the correct initial GPU frequency on the GMU just after turning on
> > or resetting the GMU so it doesn't keep running at a horribly slow
> > speed.
> >
> > Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
>
>
> *much* better :-)

Awesome, thanks Jordan.

> Tested-by: Rob Clark <robdclark@gmail.com>
>
> > ---
> >  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 26 ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > index c49ca275a3b3..f8227f38b8cd 100644
> > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> > @@ -65,6 +65,26 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
> >                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
> >  }
> >
> > +static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
> > +{
> > +       gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
> > +
> > +       gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
> > +               ((index << 24) & 0xff) | (3 & 0xf));
> > +
> > +       /*
> > +        * Send an invalid index as a vote for the bus bandwidth and let the
> > +        * firmware decide on the right vote
> > +        */
> > +       gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
> > +
> > +       /* Set and clear the OOB for DCVS to trigger the GMU */
> > +       a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
> > +       a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
> > +
> > +       return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
> > +}
> > +
> >  static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
> >  {
> >         u32 val;
> > @@ -602,6 +622,9 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
> >         if (!ret)
> >                 ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT);
> >
> > +       /* Set the GPU back to the highest power frequency */
> > +       a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
> > +
> >         if (ret)
> >                 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
> >
> > @@ -635,6 +658,9 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
> >
> >         ret = a6xx_hfi_start(gmu, status);
> >
> > +       /* Set the GPU to the highest power frequency */
> > +       a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
> > +
> >  out:
> >         /* Make sure to turn off the boot OOB request on error */
> >         if (ret)
> > --
> > 2.18.0
> >
> _______________________________________________
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> Freedreno@lists.freedesktop.org
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