Re: [PATCH v2] bus: mhi: Ensure correct ring update ordering with memory barrier

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

On Thu, Nov 26, 2020 at 04:06:41PM +0100, Loic Poulain wrote:
> The ring element data, though being part of coherent memory, still need
> to be performed before updating the ring context to point to this new
> element. That can be guaranteed with a memory barrier (dma_wmb).
> 
> Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
> ---
>  v2: fix comment style
> 
>  drivers/bus/mhi/core/main.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c
> index 67188ea..ea39df0 100644
> --- a/drivers/bus/mhi/core/main.c
> +++ b/drivers/bus/mhi/core/main.c
> @@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl,
>  	dma_addr_t db;
>  
>  	db = ring->iommu_base + (ring->wp - ring->base);
> +
> +	/*
> +	 * Writes to the new ring element must be visible to the hardware
> +	 * before letting h/w know there is new element to fetch.
> +	 */
> +	dma_wmb();
>  	*ring->ctxt_wp = db;

As Jeff pointed out, the barrier should come after updating ctxt_wp.

Thanks,
Mani

> +
>  	mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg,
>  				    ring->db_addr, db);
>  }
> -- 
> 2.7.4
>