* [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000
@ 2022-10-14 22:11 Melody Olvera
2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera
` (3 more replies)
0 siblings, 4 replies; 28+ messages in thread
From: Melody Olvera @ 2022-10-14 22:11 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
This series adds the base device tree files and DTS support for the
Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
regulators, mmc, interconnects, cpufreq, and qup.
This patchset is based off of [1] which adds support for the PMIC arb used
on these SoCs.
The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
[1] https://lore.kernel.org/all/20220914165212.3705892-3-vkoul@kernel.org/
Melody Olvera (3):
dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards
arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
.../devicetree/bindings/arm/qcom.yaml | 16 +
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++
arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 +
6 files changed, 2151 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
base-commit: dca0a0385a4963145593ba417e1417af88a7c18d
prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
--
2.38.0
^ permalink raw reply [flat|nested] 28+ messages in thread* [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards 2022-10-14 22:11 [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera @ 2022-10-14 22:11 ` Melody Olvera 2022-10-15 13:19 ` Krzysztof Kozlowski 2022-10-16 22:58 ` Rob Herring 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera ` (2 subsequent siblings) 3 siblings, 2 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-14 22:11 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera Document the QDU1000 and QRU1000 SoC bindings and the boards that use them. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1b5ac6b02bc5..3370a50644a6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -40,6 +40,8 @@ description: | msm8996 msm8998 qcs404 + qdu1000 + qru1000 sa8155p sa8540p sc7180 @@ -76,6 +78,7 @@ description: | mtp qrd sbc + x100 The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same @@ -493,6 +496,19 @@ properties: - const: google,pompom-sku0 - const: qcom,sc7180 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform + - items: + - enum: + - qcom,qdu1000-idp + - qcom,qdu1000-x100 + - const: qcom,qdu1000 + + - description: Qualcomm Technologies, Inc. Radio Unit 1000 platform + - items: + - enum: + -qcom,qru1000-idp + - const: qcom,qru1000 + - description: Google Quackingstick (newest rev) items: - const: google,quackingstick-sku1537 -- 2.38.0 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards 2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera @ 2022-10-15 13:19 ` Krzysztof Kozlowski 2022-10-16 22:58 ` Rob Herring 1 sibling, 0 replies; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-15 13:19 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 14/10/2022 18:11, Melody Olvera wrote: > Document the QDU1000 and QRU1000 SoC bindings and the boards that use > them. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml > index 1b5ac6b02bc5..3370a50644a6 100644 > --- a/Documentation/devicetree/bindings/arm/qcom.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom.yaml > @@ -40,6 +40,8 @@ description: | > msm8996 > msm8998 > qcs404 > + qdu1000 > + qru1000 > sa8155p > sa8540p > sc7180 > @@ -76,6 +78,7 @@ description: | > mtp > qrd > sbc > + x100 > > The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> > where the minor number may be omitted when it's zero, i.e. v1.0 is the same > @@ -493,6 +496,19 @@ properties: > - const: google,pompom-sku0 > - const: qcom,sc7180 > > + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform > + - items: > + - enum: > + - qcom,qdu1000-idp > + - qcom,qdu1000-x100 > + - const: qcom,qdu1000 > + > + - description: Qualcomm Technologies, Inc. Radio Unit 1000 platform > + - items: > + - enum: > + -qcom,qru1000-idp > + - const: qcom,qru1000 This is still wrong order. All entries are ordered by SoC compatible. So this should go before sc7180, not after. > + > - description: Google Quackingstick (newest rev) > items: > - const: google,quackingstick-sku1537 Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards 2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera 2022-10-15 13:19 ` Krzysztof Kozlowski @ 2022-10-16 22:58 ` Rob Herring 1 sibling, 0 replies; 28+ messages in thread From: Rob Herring @ 2022-10-16 22:58 UTC (permalink / raw) To: Melody Olvera Cc: Andy Gross, Krzysztof Kozlowski, Rob Herring, linux-kernel, Bjorn Andersson, linux-arm-msm, devicetree On Fri, 14 Oct 2022 15:11:36 -0700, Melody Olvera wrote: > Document the QDU1000 and QRU1000 SoC bindings and the boards that use > them. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/arm/qcom.yaml:496:18: [error] syntax error: mapping values are not allowed here (syntax) dtschema/dtc warnings/errors: make[1]: *** Deleting file 'Documentation/devicetree/bindings/arm/qcom.example.dts' Documentation/devicetree/bindings/arm/qcom.yaml:496:18: mapping values are not allowed in this context make[1]: *** [Documentation/devicetree/bindings/Makefile:26: Documentation/devicetree/bindings/arm/qcom.example.dts] Error 1 make[1]: *** Waiting for unfinished jobs.... ./Documentation/devicetree/bindings/arm/qcom.yaml:496:18: mapping values are not allowed in this context /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/arm/qcom.yaml: ignoring, error parsing file make: *** [Makefile:1420: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-14 22:11 [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera 2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera @ 2022-10-14 22:11 ` Melody Olvera 2022-10-15 13:28 ` Krzysztof Kozlowski ` (3 more replies) 2022-10-14 22:11 ` [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera 2022-10-15 0:04 ` [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera 3 siblings, 4 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-14 22:11 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller to boot to shell with console on these SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + 2 files changed, 1673 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi new file mode 100644 index 000000000000..777734b30f56 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -0,0 +1,1646 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/interconnect/qcom,qdu1000.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domain-names = "psci"; + power-domains = <&CPU_PD0>; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-off"; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + firmware { + qcom_scm { + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_dt_log_mem: memory@80600000 { + no-map; + reg = <0x0 0x80600000 0x0 0x40000>; + }; + + xbl_ramdump_mem: memory@80640000 { + no-map; + reg = <0x0 0x80640000 0x0 0x1c0000>; + }; + + aop_image_mem: memory@80800000 { + no-map; + reg = <0x0 0x80800000 0x0 0x60000>; + }; + + aop_cmd_db_mem: memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + aop_config_mem: memory@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x20000>; + }; + + tme_crash_dump_mem: memory@808a0000 { + no-map; + reg = <0x0 0x808a0000 0x0 0x40000>; + }; + + tme_log_mem: memory@808e0000 { + no-map; + reg = <0x0 0x808e0000 0x0 0x4000>; + }; + + uefi_log_mem: memory@808e4000 { + no-map; + reg = <0x0 0x808e4000 0x0 0x10000>; + }; + + /* secdata region can be reused by apps */ + + smem_mem: memory@80900000 { + compatible = "qcom,smem"; + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: memory@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + xbl_sc_mem: memory@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x40000>; + }; + + /* uefi region can be reused by apps */ + + tz_stat_mem: memory@81d00000 { + no-map; + reg = <0x0 0x81d00000 0x0 0x100000>; + }; + + tags_mem: memory@81e00000 { + no-map; + reg = <0x0 0x81e00000 0x0 0x500000>; + }; + + qtee_mem: memory@82300000 { + no-map; + reg = <0x0 0x82300000 0x0 0x500000>; + }; + + ta_mem: memory@82800000 { + no-map; + reg = <0x0 0x82800000 0x0 0xa00000>; + }; + + fs1_mem: memory@83200000 { + no-map; + reg = <0x0 0x83200000 0x0 0x400000>; + }; + + fs2_mem: memory@83600000 { + no-map; + reg = <0x0 0x83600000 0x0 0x400000>; + }; + + fs3_mem: memory@83a00000 { + no-map; + reg = <0x0 0x83a00000 0x0 0x400000>; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: memory@8be00000 { + no-map; + reg = <0x0 0x8be00000 0x0 0x10000>; + }; + + ipa_gsi_mem: memory@8be10000 { + no-map; + reg = <0x0 0x8be10000 0x0 0x14000>; + }; + + mpss_mem: memory@8c000000 { + no-map; + reg = <0x0 0x8c000000 0x0 0x12c00000>; + }; + + q6_mpss_dtb_mem: memory@9ec00000 { + no-map; + reg = <0x0 0x9ec00000 0x0 0x80000>; + }; + + tenx_mem: memory@a0000000 { + no-map; + reg = <0x0 0xa0000000 0x0 0x19600000>; + }; + + oem_tenx_mem: memory@b9600000 { + no-map; + reg = <0x0 0xb9600000 0x0 0x6a00000>; + }; + + tenx_q6_buffer_mem: memory@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x3200000>; + }; + + ipa_buffer_mem: memory@c3200000 { + no-map; + reg = <0x0 0xc3200000 0x0 0x12c00000>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@80000 { + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; + reg = <0x0 0x80000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; + #dma-cells = <5>; + reg = <0x0 0x900000 0x0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0xf6 0x0>; + status = "ok"; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart0_default>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x99c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; + #dma-cells = <5>; + reg = <0x0 0xa00000 0x0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x116 0x0>; + status = "ok"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x103 0x0>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + + ranges; + status = "disabled"; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_default>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart13_default>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + dmas = <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa9c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + dmas = <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + system_noc: interconnect@1640000 { + reg = <0x0 0x1640000 0x0 0x45080>; + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc500000 0x0 0x400000>, + <0x0 0xc440000 0x0 0x80000>, + <0x0 0xc4c0000 0x0 0x10000>, + <0x0 0xc42d000 0x0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk { + pins = "gpio10", "gpio11"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup01"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk { + pins = "gpio12", "gpio13"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { + pins = "gpio12", "gpio13", "gpio10"; + function = "qup02"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk { + pins = "gpio14", "gpio15"; + function = "qup03"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { + pins = "gpio14", "gpio15", "gpio16"; + function = "qup03"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs { + pins = "gpio17"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk { + pins = "gpio16", "gpio17"; + function = "qup04"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { + pins = "gpio16", "gpio17", "gpio14"; + function = "qup04"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk { + pins = "gpio130", "gpio131"; + function = "qup05"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { + pins = "gpio130", "gpio131", "gpio132"; + function = "qup05"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs { + pins = "gpio133"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk { + pins = "gpio132", "gpio133"; + function = "qup06"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { + pins = "gpio132", "gpio133", "gpio130"; + function = "qup06"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs { + pins = "gpio131"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart7_rx: qup-uart7-rx { + pins = "gpio135"; + function = "qup07"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx { + pins = "gpio134"; + function = "qup07"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk { + pins = "gpio22", "gpio23"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { + pins = "gpio22", "gpio23", "gpio24"; + function = "qup11"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk { + pins = "gpio24", "gpio25"; + function = "qup12"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { + pins = "gpio24", "gpio25", "gpio22"; + function = "qup12"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk { + pins = "gpio26", "gpio27"; + function = "qup13"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { + pins = "gpio26", "gpio27", "gpio28"; + function = "qup13"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs { + pins = "gpio29"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk { + pins = "gpio28", "gpio29"; + function = "qup14"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { + pins = "gpio28", "gpio29", "gpio26"; + function = "qup14"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins = "gpio30", "gpio31"; + function = "qup15"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { + pins = "gpio30", "gpio31", "gpio32"; + function = "qup15"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart13_default: qup-uart13-default { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup15"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins = "gpio34", "gpio35"; + function = "qup16"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { + pins = "gpio34", "gpio35", "gpio36"; + function = "qup16"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs { + pins = "gpio37", "gpio38"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk { + pins = "gpio40", "gpio41"; + function = "qup17"; + drive-strength = <2>; + bias-pulll-up; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { + pins = "gpio40", "gpio41", "gpio30"; + function = "qup17"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs { + pins = "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17420000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x17421000 0x0 0x1000>, + <0x0 0x17422000 0x0 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x17423000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x17425000 0x0 0x1000>, + <0x0 0x17426000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x17427000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x17429000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x1742b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0 0x1742d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 0>; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0"; + #freq-domain-cells = <1>; + }; + + gem_noc: interconnect@19100000 { + reg = <0x0 0x19100000 0x0 0xB8080>; + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi new file mode 100644 index 000000000000..074fe126e85e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdu1000.dtsi" + +&reserved_memory { + /delete-node/ memory@a0000000; + /delete-node/ memory@b9600000; + /delete-node/ memory@c0000000; + + oem_tenx_mem: memory@a0000000 { + no-map; + reg = <0x0 0xa0000000 0x0 0x6400000>; + }; + + mpss_diag_buffer_mem: memory@aea00000 { + no-map; + reg = <0x0 0xaea00000 0x0 0x6400000>; + }; + + tenx_q6_buffer_mem: memory@b4e00000 { + no-map; + reg = <0x0 0xb4e00000 0x0 0x3200000>; + }; +}; -- 2.38.0 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera @ 2022-10-15 13:28 ` Krzysztof Kozlowski 2022-10-19 20:21 ` Melody Olvera 2022-10-15 15:11 ` Krzysztof Kozlowski ` (2 subsequent siblings) 3 siblings, 1 reply; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-15 13:28 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 14/10/2022 18:11, Melody Olvera wrote: > Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base > descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller > to boot to shell with console on these SoCs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + > 2 files changed, 1673 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > new file mode 100644 > index 000000000000..777734b30f56 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -0,0 +1,1646 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/interconnect/qcom,qdu1000.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen: chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + clock-frequency = <19200000>; Both clocks are not a property of a SoC. They are provided by the board, so they should either be defined by board DTS or at least their frequency must be provided by the board. > + clock-output-names = "xo_board"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + power-domain-names = "psci"; > + power-domains = <&CPU_PD0>; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; Wrong indentation. > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_100>; > + L2_100: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + Drop empty lines like that. > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + power-domains = <&CPU_PD2>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_200>; > + L2_200: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + power-domains = <&CPU_PD3>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_300>; > + L2_300: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + Here... > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_OFF: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "rail-pc"; > + entry-latency-us = <274>; > + exit-latency-us = <480>; > + min-residency-us = <3934>; > + arm,psci-suspend-param = <0x40000004>; > + local-timer-stop; > + }; > + }; > + > + domain-idle-states { > + CLUSTER_SLEEP_0: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + idle-state-name = "cluster-l3-off"; > + entry-latency-us = <584>; > + exit-latency-us = <2332>; > + min-residency-us = <6118>; > + arm,psci-suspend-param = <0x41000044>; > + }; > + > + CLUSTER_SLEEP_1: cluster-sleep-1 { > + compatible = "domain-idle-state"; > + idle-state-name = "cluster-power-collapse"; > + entry-latency-us = <2893>; > + exit-latency-us = <4023>; > + min-residency-us = <9987>; > + arm,psci-suspend-param = <0x41003344>; > + }; > + }; > + > + firmware { > + qcom_scm { No underscores in node names. This applies everywhere. Node names should be generic, so just scm. https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; > + #reset-cells = <1>; > + }; > + }; > + > + clk_virt: interconnect-0 { > + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-1 { > + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + > + CPU_PD0: cpu-pd0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD1: cpu-pd1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD2: cpu-pd2 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD3: cpu-pd3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CLUSTER_PD: cluster-pd { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; > + }; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: memory@80000000 { > + no-map; > + reg = <0x0 0x80000000 0x0 0x600000>; > + }; > + > + xbl_dt_log_mem: memory@80600000 { > + no-map; > + reg = <0x0 0x80600000 0x0 0x40000>; > + }; > + > + xbl_ramdump_mem: memory@80640000 { > + no-map; > + reg = <0x0 0x80640000 0x0 0x1c0000>; > + }; > + > + aop_image_mem: memory@80800000 { > + no-map; > + reg = <0x0 0x80800000 0x0 0x60000>; > + }; > + > + aop_cmd_db_mem: memory@80860000 { > + compatible = "qcom,cmd-db"; > + no-map; > + reg = <0x0 0x80860000 0x0 0x20000>; > + }; > + > + aop_config_mem: memory@80880000 { > + no-map; > + reg = <0x0 0x80880000 0x0 0x20000>; > + }; > + > + tme_crash_dump_mem: memory@808a0000 { > + no-map; > + reg = <0x0 0x808a0000 0x0 0x40000>; > + }; > + > + tme_log_mem: memory@808e0000 { > + no-map; > + reg = <0x0 0x808e0000 0x0 0x4000>; > + }; > + > + uefi_log_mem: memory@808e4000 { > + no-map; > + reg = <0x0 0x808e4000 0x0 0x10000>; > + }; > + > + /* secdata region can be reused by apps */ > + > + smem_mem: memory@80900000 { > + compatible = "qcom,smem"; > + no-map; > + reg = <0x0 0x80900000 0x0 0x200000>; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: memory@80b00000 { > + no-map; > + reg = <0x0 0x80b00000 0x0 0x100000>; > + }; > + > + xbl_sc_mem: memory@80c00000 { > + no-map; > + reg = <0x0 0x80c00000 0x0 0x40000>; > + }; > + > + /* uefi region can be reused by apps */ > + > + tz_stat_mem: memory@81d00000 { > + no-map; > + reg = <0x0 0x81d00000 0x0 0x100000>; > + }; > + > + tags_mem: memory@81e00000 { > + no-map; > + reg = <0x0 0x81e00000 0x0 0x500000>; > + }; > + > + qtee_mem: memory@82300000 { > + no-map; > + reg = <0x0 0x82300000 0x0 0x500000>; > + }; > + > + ta_mem: memory@82800000 { > + no-map; > + reg = <0x0 0x82800000 0x0 0xa00000>; > + }; > + > + fs1_mem: memory@83200000 { > + no-map; > + reg = <0x0 0x83200000 0x0 0x400000>; > + }; > + > + fs2_mem: memory@83600000 { > + no-map; > + reg = <0x0 0x83600000 0x0 0x400000>; > + }; > + > + fs3_mem: memory@83a00000 { > + no-map; > + reg = <0x0 0x83a00000 0x0 0x400000>; > + }; > + > + /* Linux kernel image is loaded at 0x83e00000 */ > + > + ipa_fw_mem: memory@8be00000 { > + no-map; > + reg = <0x0 0x8be00000 0x0 0x10000>; > + }; > + > + ipa_gsi_mem: memory@8be10000 { > + no-map; > + reg = <0x0 0x8be10000 0x0 0x14000>; > + }; > + > + mpss_mem: memory@8c000000 { > + no-map; > + reg = <0x0 0x8c000000 0x0 0x12c00000>; > + }; > + > + q6_mpss_dtb_mem: memory@9ec00000 { > + no-map; > + reg = <0x0 0x9ec00000 0x0 0x80000>; > + }; > + > + tenx_mem: memory@a0000000 { > + no-map; > + reg = <0x0 0xa0000000 0x0 0x19600000>; > + }; > + > + oem_tenx_mem: memory@b9600000 { > + no-map; > + reg = <0x0 0xb9600000 0x0 0x6a00000>; > + }; > + > + tenx_q6_buffer_mem: memory@c0000000 { > + no-map; > + reg = <0x0 0xc0000000 0x0 0x3200000>; > + }; > + > + ipa_buffer_mem: memory@c3200000 { > + no-map; > + reg = <0x0 0xc3200000 0x0 0x12c00000>; > + }; > + }; > + > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@80000 { > + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; > + reg = <0x0 0x80000 0x0 0x1f4200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + }; > + > + gpi_dma0: dma-controller@900000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; > + #dma-cells = <5>; > + reg = <0x0 0x900000 0x0 0x60000>; > + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0xf6 0x0>; > + status = "ok"; Drop it everywhere. It's by default. > + }; > + > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x9c0000 0x0 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + iommus = <&apps_smmu 0xe3 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 > + &clk_virt SLAVE_QUP_CORE_0 0>; > + interconnect-names = "qup-core"; > + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; > + qcom,iommu-geometry = <0x40000000 0x10000000>; > + qcom,iommu-dma = "fastmap"; > + dma-coherent; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart0: serial@980000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x980000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart0_default>; > + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@984000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x984000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c1_data_clk>; > + dmas = <&gpi_dma0 0 1 3 64 0>, > + <&gpi_dma0 1 1 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi1: spi@984000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x984000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; > + dmas = <&gpi_dma0 0 1 1 64 0>, > + <&gpi_dma0 1 1 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c2: i2c@988000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x988000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_data_clk>; > + dmas = <&gpi_dma0 0 2 3 64 0>, > + <&gpi_dma0 1 2 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@988000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x988000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; > + dmas = <&gpi_dma0 0 2 1 64 0>, > + <&gpi_dma0 1 2 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c3: i2c@98c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c3_data_clk>; > + dmas = <&gpi_dma0 0 3 3 64 0>, > + <&gpi_dma0 1 3 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@98c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; > + dmas = <&gpi_dma0 0 3 1 64 0>, > + <&gpi_dma0 1 3 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c4: i2c@990000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x990000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_data_clk>; > + dmas = <&gpi_dma0 0 4 3 64 0>, > + <&gpi_dma0 1 4 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi4: spi@990000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x990000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; > + dmas = <&gpi_dma0 0 4 1 64 0>, > + <&gpi_dma0 1 4 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c5: i2c@994000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x994000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c5_data_clk>; > + dmas = <&gpi_dma0 0 5 3 64 0>, > + <&gpi_dma0 1 5 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi5: spi@994000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x994000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; > + dmas = <&gpi_dma0 0 5 1 64 0>, > + <&gpi_dma0 1 5 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c6: i2c@998000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x998000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c6_data_clk>; > + dmas = <&gpi_dma0 0 6 3 64 0>, > + <&gpi_dma0 1 6 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi6: spi@998000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x998000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; > + dmas = <&gpi_dma0 0 6 1 64 0>, > + <&gpi_dma0 1 6 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + uart7: serial@99c000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x99c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; > + #dma-cells = <5>; > + reg = <0x0 0xa00000 0x0 0x60000>; > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0x116 0x0>; > + status = "ok"; And here > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0xac0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + iommus = <&apps_smmu 0x103 0x0>; > + #address-cells = <1>; > + #size-cells = <1>; > + clock-names = "m-ahb", "s-ahb"; clock-names *always* follow clocks > + > + ranges; > + status = "disabled"; > + > + uart8: serial@a80000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa80000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart8_default>; > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c9: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c9_data_clk>; > + dmas = <&gpi_dma1 0 1 3 64 0>, > + <&gpi_dma1 1 1 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi9: spi@a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; > + dmas = <&gpi_dma1 0 1 1 64 0>, > + <&gpi_dma1 1 1 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c10: i2c@a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c10_data_clk>; > + dmas = <&gpi_dma1 0 2 3 64 0>, > + <&gpi_dma1 1 2 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi10: spi@a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; > + dmas = <&gpi_dma1 0 2 1 64 0>, > + <&gpi_dma1 1 2 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c11: i2c@a8c000 { > + compatible = "qcom,i2c-geni"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c11_data_clk>; > + dmas = <&gpi_dma1 0 3 3 64 0>, > + <&gpi_dma1 1 3 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi11: spi@a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; > + dmas = <&gpi_dma1 0 3 1 64 0>, > + <&gpi_dma1 1 3 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c12: i2c@a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c12_data_clk>; > + dmas = <&gpi_dma1 0 4 3 64 0>, > + <&gpi_dma1 1 4 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi12: spi@a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; > + dmas = <&gpi_dma1 0 4 1 64 0>, > + <&gpi_dma1 1 4 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c13: i2c@a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c13_data_clk>; > + dmas = <&gpi_dma1 0 5 3 64 0>, > + <&gpi_dma1 1 5 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart13: serial@a94000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart13_default>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi13: spi@a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; > + dmas = <&gpi_dma1 0 5 1 64 0>, > + <&gpi_dma1 1 5 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c14: i2c@a98000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c14_data_clk>; > + dmas = <&gpi_dma1 0 6 3 64 0>, > + <&gpi_dma1 1 6 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi14: spi@a98000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; > + dmas = <&gpi_dma1 0 6 1 64 0>, > + <&gpi_dma1 1 6 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c15: i2c@a9c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c15_data_clk>; > + dmas = <&gpi_dma1 0 7 3 64 0>, > + <&gpi_dma1 1 7 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi15: spi@a9c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; > + dmas = <&gpi_dma1 0 7 1 64 0>, > + <&gpi_dma1 1 7 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + }; > + > + system_noc: interconnect@1640000 { > + reg = <0x0 0x1640000 0x0 0x45080>; > + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; > + #interconnect-cells = <1>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x1f40000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,pdc"; > + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; > + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; > + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, > + <94 609 31>, <125 63 1>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0xc400000 0x0 0x3000>, > + <0x0 0xc500000 0x0 0x400000>, > + <0x0 0xc440000 0x0 0x80000>, > + <0x0 0xc4c0000 0x0 0x10000>, > + <0x0 0xc42d000 0x0 0x4000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; > + reg = <0x0 0xf000000 0x0 0x1000000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 151>; > + wakeup-parent = <&pdc>; > + > + qup_uart0_default: qup-uart0-default-state { > + pins = "gpio6", "gpio7", "gpio8", "gpio9"; > + function = "qup00"; > + }; > + > + qup_i2c1_data_clk: qup-i2c1-data-clk { -state suffix This is a friendly reminder during the review process. It seems my previous comments were not fully addressed. Maybe my feedback got lost between the quotes, maybe you just forgot to apply it. Please go back to the previous discussion and either implement all requested changes or keep discussing them. Thank you. > + pins = "gpio10", "gpio11"; > + function = "qup01"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi1_data_clk: qup-spi1-data-clk {> + pins = "gpio10", "gpio11", "gpio12"; > + function = "qup01"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi1_cs: qup-spi1-cs { > + pins = "gpio13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c2_data_clk: qup-i2c2-data-clk { > + pins = "gpio12", "gpio13"; > + function = "qup02"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi2_data_clk: qup-spi2-data-clk { > + pins = "gpio12", "gpio13", "gpio10"; > + function = "qup02"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi2_cs: qup-spi2-cs { > + pins = "gpio11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c3_data_clk: qup-i2c3-data-clk { > + pins = "gpio14", "gpio15"; > + function = "qup03"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi3_data_clk: qup-spi3-data-clk { > + pins = "gpio14", "gpio15", "gpio16"; > + function = "qup03"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi3_cs: qup-spi3-cs { > + pins = "gpio17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c4_data_clk: qup-i2c4-data-clk { > + pins = "gpio16", "gpio17"; > + function = "qup04"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi4_data_clk: qup-spi4-data-clk { > + pins = "gpio16", "gpio17", "gpio14"; > + function = "qup04"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi4_cs: qup-spi4-cs { > + pins = "gpio15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c5_data_clk: qup-i2c5-data-clk { > + pins = "gpio130", "gpio131"; > + function = "qup05"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi5_data_clk: qup-spi5-data-clk { > + pins = "gpio130", "gpio131", "gpio132"; > + function = "qup05"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi5_cs: qup-spi5-cs { > + pins = "gpio133"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c6_data_clk: qup-i2c6-data-clk { > + pins = "gpio132", "gpio133"; > + function = "qup06"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi6_data_clk: qup-spi6-data-clk { > + pins = "gpio132", "gpio133", "gpio130"; > + function = "qup06"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi6_cs: qup-spi6-cs { > + pins = "gpio131"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart7_rx: qup-uart7-rx { > + pins = "gpio135"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart7_tx: qup-uart7-tx { > + pins = "gpio134"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart8_default: qup-uart8-default { > + pins = "gpio18", "gpio19", "gpio20", "gpio21"; > + function = "qup10"; > + }; > + > + qup_i2c9_data_clk: qup-i2c9-data-clk { > + pins = "gpio22", "gpio23"; > + function = "qup11"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi9_data_clk: qup-spi9-data-clk { > + pins = "gpio22", "gpio23", "gpio24"; > + function = "qup11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi9_cs: qup-spi9-cs { > + pins = "gpio25"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c10_data_clk: qup-i2c10-data-clk { > + pins = "gpio24", "gpio25"; > + function = "qup12"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi10_data_clk: qup-spi10-data-clk { > + pins = "gpio24", "gpio25", "gpio22"; > + function = "qup12"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi10_cs: qup-spi10-cs { > + pins = "gpio23"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c11_data_clk: qup-i2c11-data-clk { > + pins = "gpio26", "gpio27"; > + function = "qup13"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi11_data_clk: qup-spi11-data-clk { > + pins = "gpio26", "gpio27", "gpio28"; > + function = "qup13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi11_cs: qup-spi11-cs { > + pins = "gpio29"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c12_data_clk: qup-i2c12-data-clk { > + pins = "gpio28", "gpio29"; > + function = "qup14"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi12_data_clk: qup-spi12-data-clk { > + pins = "gpio28", "gpio29", "gpio26"; > + function = "qup14"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi12_cs: qup-spi12-cs { > + pins = "gpio27"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c13_data_clk: qup-i2c13-data-clk { > + pins = "gpio30", "gpio31"; > + function = "qup15"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi13_data_clk: qup-spi13-data-clk { > + pins = "gpio30", "gpio31", "gpio32"; > + function = "qup15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi13_cs: qup-spi13-cs { > + pins = "gpio33"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart13_default: qup-uart13-default { > + pins = "gpio30", "gpio31", "gpio32", "gpio33"; > + function = "qup15"; > + }; > + > + qup_i2c14_data_clk: qup-i2c14-data-clk { > + pins = "gpio34", "gpio35"; > + function = "qup16"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi14_data_clk: qup-spi14-data-clk { > + pins = "gpio34", "gpio35", "gpio36"; > + function = "qup16"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi14_cs: qup-spi14-cs { > + pins = "gpio37", "gpio38"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c15_data_clk: qup-i2c15-data-clk { > + pins = "gpio40", "gpio41"; > + function = "qup17"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi15_data_clk: qup-spi15-data-clk { > + pins = "gpio40", "gpio41", "gpio30"; > + function = "qup17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi15_cs: qup-spi15-cs { > + pins = "gpio31"; > + drive-strength = <6>; > + bias-disable; > + }; > + }; > + > + apps_smmu: apps-smmu@15000000 { > + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", > + "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + intc: interrupt-controller@17200000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + timer@17420000 { > + compatible = "arm,armv7-timer-mem"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + reg = <0x0 0x17420000 0x0 0x1000>; > + clock-frequency = <19200000>; > + > + frame@17421000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17421000 0x0 0x1000>, > + <0x0 0x17422000 0x0 0x1000>; > + }; > + > + frame@17423000 { > + frame-number = <1>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17423000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17425000 { > + frame-number = <2>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17425000 0x0 0x1000>, > + <0x0 0x17426000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17427000 { > + frame-number = <3>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17427000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17429000 { > + frame-number = <4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17429000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742b000 { > + frame-number = <5>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x1742b000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742d000 { > + frame-number = <6>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x1742d000 0x0 0x1000>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@17a00000 { > + label = "apps_rsc"; > + compatible = "qcom,rpmh-rsc"; compatible, then reg, then the rest. > + reg = <0x0 0x17a00000 0x0 0x10000>, > + <0x0 0x17a10000 0x0 0x10000>, > + <0x0 0x17a20000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 0>; > + > + apps_bcm_voter: bcm_voter { Eh... Does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). > + compatible = "qcom,bcm-voter"; > + }; Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-15 13:28 ` Krzysztof Kozlowski @ 2022-10-19 20:21 ` Melody Olvera 2022-10-20 12:41 ` Krzysztof Kozlowski 0 siblings, 1 reply; 28+ messages in thread From: Melody Olvera @ 2022-10-19 20:21 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: > On 14/10/2022 18:11, Melody Olvera wrote: >> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >> to boot to shell with console on these SoCs. >> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >> 2 files changed, 1673 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> new file mode 100644 >> index 000000000000..777734b30f56 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -0,0 +1,1646 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >> +#include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/dma/qcom-gpi.h> >> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >> +#include <dt-bindings/power/qcom-rpmpd.h> >> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + chosen: chosen { }; >> + >> + clocks { >> + xo_board: xo-board { >> + compatible = "fixed-clock"; >> + clock-frequency = <19200000>; > Both clocks are not a property of a SoC. They are provided by the board, > so they should either be defined by board DTS or at least their > frequency must be provided by the board. That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in the dtsi. These are common to the boards anyways. > >> + clock-output-names = "xo_board"; >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <32000>; >> + #clock-cells = <0>; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + CPU0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + power-domain-names = "psci"; >> + power-domains = <&CPU_PD0>; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_0>; >> + L2_0: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; > Wrong indentation. Will fix for all caches. > >> + L3_0: l3-cache { >> + compatible = "cache"; >> + }; >> + }; >> + }; >> + >> + CPU1: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD1>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_100>; >> + L2_100: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + > Drop empty lines like that. Ack. > >> + }; >> + >> + CPU2: cpu@200 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x200>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD2>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_200>; >> + L2_200: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + }; >> + >> + CPU3: cpu@300 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x300>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD3>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_300>; >> + L2_300: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + > Here... Ack. > >> + }; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&CPU0>; >> + }; >> + >> + core1 { >> + cpu = <&CPU1>; >> + }; >> + >> + core2 { >> + cpu = <&CPU2>; >> + }; >> + >> + core3 { >> + cpu = <&CPU3>; >> + }; >> + }; >> + }; >> + }; >> + >> + idle-states { >> + entry-method = "psci"; >> + >> + CPU_OFF: cpu-sleep-0 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "rail-pc"; >> + entry-latency-us = <274>; >> + exit-latency-us = <480>; >> + min-residency-us = <3934>; >> + arm,psci-suspend-param = <0x40000004>; >> + local-timer-stop; >> + }; >> + }; >> + >> + domain-idle-states { >> + CLUSTER_SLEEP_0: cluster-sleep-0 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "cluster-l3-off"; >> + entry-latency-us = <584>; >> + exit-latency-us = <2332>; >> + min-residency-us = <6118>; >> + arm,psci-suspend-param = <0x41000044>; >> + }; >> + >> + CLUSTER_SLEEP_1: cluster-sleep-1 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "cluster-power-collapse"; >> + entry-latency-us = <2893>; >> + exit-latency-us = <4023>; >> + min-residency-us = <9987>; >> + arm,psci-suspend-param = <0x41003344>; >> + }; >> + }; >> + >> + firmware { >> + qcom_scm { > No underscores in node names. This applies everywhere. Understood; must've missed prior to submitting. Will be more meticulous. > Node names should be generic, so just scm. > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Got it. > >> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >> + #reset-cells = <1>; >> + }; >> + }; >> + >> + clk_virt: interconnect-0 { >> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + mc_virt: interconnect-1 { >> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + memory@80000000 { >> + device_type = "memory"; >> + /* We expect the bootloader to fill in the size */ >> + reg = <0x0 0x80000000 0x0 0x0>; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + >> + CPU_PD0: cpu-pd0 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD1: cpu-pd1 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD2: cpu-pd2 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD3: cpu-pd3 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CLUSTER_PD: cluster-pd { >> + #power-domain-cells = <0>; >> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >> + }; >> + }; >> + >> + reserved_memory: reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + hyp_mem: memory@80000000 { >> + no-map; >> + reg = <0x0 0x80000000 0x0 0x600000>; >> + }; >> + >> + xbl_dt_log_mem: memory@80600000 { >> + no-map; >> + reg = <0x0 0x80600000 0x0 0x40000>; >> + }; >> + >> + xbl_ramdump_mem: memory@80640000 { >> + no-map; >> + reg = <0x0 0x80640000 0x0 0x1c0000>; >> + }; >> + >> + aop_image_mem: memory@80800000 { >> + no-map; >> + reg = <0x0 0x80800000 0x0 0x60000>; >> + }; >> + >> + aop_cmd_db_mem: memory@80860000 { >> + compatible = "qcom,cmd-db"; >> + no-map; >> + reg = <0x0 0x80860000 0x0 0x20000>; >> + }; >> + >> + aop_config_mem: memory@80880000 { >> + no-map; >> + reg = <0x0 0x80880000 0x0 0x20000>; >> + }; >> + >> + tme_crash_dump_mem: memory@808a0000 { >> + no-map; >> + reg = <0x0 0x808a0000 0x0 0x40000>; >> + }; >> + >> + tme_log_mem: memory@808e0000 { >> + no-map; >> + reg = <0x0 0x808e0000 0x0 0x4000>; >> + }; >> + >> + uefi_log_mem: memory@808e4000 { >> + no-map; >> + reg = <0x0 0x808e4000 0x0 0x10000>; >> + }; >> + >> + /* secdata region can be reused by apps */ >> + >> + smem_mem: memory@80900000 { >> + compatible = "qcom,smem"; >> + no-map; >> + reg = <0x0 0x80900000 0x0 0x200000>; >> + hwlocks = <&tcsr_mutex 3>; >> + }; >> + >> + cpucp_fw_mem: memory@80b00000 { >> + no-map; >> + reg = <0x0 0x80b00000 0x0 0x100000>; >> + }; >> + >> + xbl_sc_mem: memory@80c00000 { >> + no-map; >> + reg = <0x0 0x80c00000 0x0 0x40000>; >> + }; >> + >> + /* uefi region can be reused by apps */ >> + >> + tz_stat_mem: memory@81d00000 { >> + no-map; >> + reg = <0x0 0x81d00000 0x0 0x100000>; >> + }; >> + >> + tags_mem: memory@81e00000 { >> + no-map; >> + reg = <0x0 0x81e00000 0x0 0x500000>; >> + }; >> + >> + qtee_mem: memory@82300000 { >> + no-map; >> + reg = <0x0 0x82300000 0x0 0x500000>; >> + }; >> + >> + ta_mem: memory@82800000 { >> + no-map; >> + reg = <0x0 0x82800000 0x0 0xa00000>; >> + }; >> + >> + fs1_mem: memory@83200000 { >> + no-map; >> + reg = <0x0 0x83200000 0x0 0x400000>; >> + }; >> + >> + fs2_mem: memory@83600000 { >> + no-map; >> + reg = <0x0 0x83600000 0x0 0x400000>; >> + }; >> + >> + fs3_mem: memory@83a00000 { >> + no-map; >> + reg = <0x0 0x83a00000 0x0 0x400000>; >> + }; >> + >> + /* Linux kernel image is loaded at 0x83e00000 */ >> + >> + ipa_fw_mem: memory@8be00000 { >> + no-map; >> + reg = <0x0 0x8be00000 0x0 0x10000>; >> + }; >> + >> + ipa_gsi_mem: memory@8be10000 { >> + no-map; >> + reg = <0x0 0x8be10000 0x0 0x14000>; >> + }; >> + >> + mpss_mem: memory@8c000000 { >> + no-map; >> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >> + }; >> + >> + q6_mpss_dtb_mem: memory@9ec00000 { >> + no-map; >> + reg = <0x0 0x9ec00000 0x0 0x80000>; >> + }; >> + >> + tenx_mem: memory@a0000000 { >> + no-map; >> + reg = <0x0 0xa0000000 0x0 0x19600000>; >> + }; >> + >> + oem_tenx_mem: memory@b9600000 { >> + no-map; >> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >> + }; >> + >> + tenx_q6_buffer_mem: memory@c0000000 { >> + no-map; >> + reg = <0x0 0xc0000000 0x0 0x3200000>; >> + }; >> + >> + ipa_buffer_mem: memory@c3200000 { >> + no-map; >> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >> + }; >> + }; >> + >> + soc: soc@0 { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0 0 0 0 0x10 0>; >> + dma-ranges = <0 0 0 0 0x10 0>; >> + compatible = "simple-bus"; >> + >> + gcc: clock-controller@80000 { >> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >> + reg = <0x0 0x80000 0x0 0x1f4200>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >> + clock-names = "bi_tcxo", "sleep_clk"; >> + }; >> + >> + gpi_dma0: dma-controller@900000 { >> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >> + #dma-cells = <5>; >> + reg = <0x0 0x900000 0x0 0x60000>; >> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <12>; >> + dma-channel-mask = <0x3f>; >> + iommus = <&apps_smmu 0xf6 0x0>; >> + status = "ok"; > Drop it everywhere. It's by default. Ack. > >> + }; >> + >> + qupv3_id_0: geniqup@9c0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x9c0000 0x0 0x2000>; >> + clock-names = "m-ahb", "s-ahb"; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + iommus = <&apps_smmu 0xe3 0x0>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >> + &clk_virt SLAVE_QUP_CORE_0 0>; >> + interconnect-names = "qup-core"; >> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >> + qcom,iommu-geometry = <0x40000000 0x10000000>; >> + qcom,iommu-dma = "fastmap"; >> + dma-coherent; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + uart0: serial@980000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0x980000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart0_default>; >> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@984000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x984000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c1_data_clk>; >> + dmas = <&gpi_dma0 0 1 3 64 0>, >> + <&gpi_dma0 1 1 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi1: spi@984000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x984000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >> + dmas = <&gpi_dma0 0 1 1 64 0>, >> + <&gpi_dma0 1 1 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@988000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x988000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c2_data_clk>; >> + dmas = <&gpi_dma0 0 2 3 64 0>, >> + <&gpi_dma0 1 2 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi2: spi@988000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x988000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >> + dmas = <&gpi_dma0 0 2 1 64 0>, >> + <&gpi_dma0 1 2 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@98c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x98c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c3_data_clk>; >> + dmas = <&gpi_dma0 0 3 3 64 0>, >> + <&gpi_dma0 1 3 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi3: spi@98c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x98c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >> + dmas = <&gpi_dma0 0 3 1 64 0>, >> + <&gpi_dma0 1 3 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@990000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x990000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c4_data_clk>; >> + dmas = <&gpi_dma0 0 4 3 64 0>, >> + <&gpi_dma0 1 4 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi4: spi@990000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x990000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >> + dmas = <&gpi_dma0 0 4 1 64 0>, >> + <&gpi_dma0 1 4 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c5: i2c@994000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x994000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c5_data_clk>; >> + dmas = <&gpi_dma0 0 5 3 64 0>, >> + <&gpi_dma0 1 5 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi5: spi@994000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x994000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >> + dmas = <&gpi_dma0 0 5 1 64 0>, >> + <&gpi_dma0 1 5 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c6: i2c@998000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x998000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c6_data_clk>; >> + dmas = <&gpi_dma0 0 6 3 64 0>, >> + <&gpi_dma0 1 6 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi6: spi@998000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x998000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >> + dmas = <&gpi_dma0 0 6 1 64 0>, >> + <&gpi_dma0 1 6 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + uart7: serial@99c000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0x0 0x99c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + }; >> + >> + gpi_dma1: dma-controller@a00000 { >> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >> + #dma-cells = <5>; >> + reg = <0x0 0xa00000 0x0 0x60000>; >> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <12>; >> + dma-channel-mask = <0x3f>; >> + iommus = <&apps_smmu 0x116 0x0>; >> + status = "ok"; > And here Ack. >> + }; >> + >> + qupv3_id_1: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0xac0000 0x0 0x2000>; >> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >> + iommus = <&apps_smmu 0x103 0x0>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clock-names = "m-ahb", "s-ahb"; > clock-names *always* follow clocks Got it. > >> + >> + ranges; >> + status = "disabled"; >> + >> + uart8: serial@a80000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0xa80000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart8_default>; >> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c9: i2c@a84000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa84000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c9_data_clk>; >> + dmas = <&gpi_dma1 0 1 3 64 0>, >> + <&gpi_dma1 1 1 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi9: spi@a84000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa84000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >> + dmas = <&gpi_dma1 0 1 1 64 0>, >> + <&gpi_dma1 1 1 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c10: i2c@a88000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa88000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c10_data_clk>; >> + dmas = <&gpi_dma1 0 2 3 64 0>, >> + <&gpi_dma1 1 2 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi10: spi@a88000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa88000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >> + dmas = <&gpi_dma1 0 2 1 64 0>, >> + <&gpi_dma1 1 2 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c11: i2c@a8c000 { >> + compatible = "qcom,i2c-geni"; >> + reg = <0x0 0xa8c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c11_data_clk>; >> + dmas = <&gpi_dma1 0 3 3 64 0>, >> + <&gpi_dma1 1 3 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi11: spi@a8c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa8c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >> + dmas = <&gpi_dma1 0 3 1 64 0>, >> + <&gpi_dma1 1 3 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c12: i2c@a90000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa90000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c12_data_clk>; >> + dmas = <&gpi_dma1 0 4 3 64 0>, >> + <&gpi_dma1 1 4 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi12: spi@a90000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa90000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >> + dmas = <&gpi_dma1 0 4 1 64 0>, >> + <&gpi_dma1 1 4 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c13: i2c@a94000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c13_data_clk>; >> + dmas = <&gpi_dma1 0 5 3 64 0>, >> + <&gpi_dma1 1 5 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + uart13: serial@a94000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart13_default>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi13: spi@a94000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >> + dmas = <&gpi_dma1 0 5 1 64 0>, >> + <&gpi_dma1 1 5 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c14: i2c@a98000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa98000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c14_data_clk>; >> + dmas = <&gpi_dma1 0 6 3 64 0>, >> + <&gpi_dma1 1 6 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi14: spi@a98000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa98000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >> + dmas = <&gpi_dma1 0 6 1 64 0>, >> + <&gpi_dma1 1 6 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c15: i2c@a9c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa9c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c15_data_clk>; >> + dmas = <&gpi_dma1 0 7 3 64 0>, >> + <&gpi_dma1 1 7 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi15: spi@a9c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa9c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >> + dmas = <&gpi_dma1 0 7 1 64 0>, >> + <&gpi_dma1 1 7 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + }; >> + >> + system_noc: interconnect@1640000 { >> + reg = <0x0 0x1640000 0x0 0x45080>; >> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >> + #interconnect-cells = <1>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + tcsr_mutex: hwlock@1f40000 { >> + compatible = "qcom,tcsr-mutex"; >> + reg = <0x0 0x1f40000 0x0 0x20000>; >> + #hwlock-cells = <1>; >> + }; >> + >> + pdc: interrupt-controller@b220000 { >> + compatible = "qcom,pdc"; >> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >> + <94 609 31>, <125 63 1>; >> + #interrupt-cells = <2>; >> + interrupt-parent = <&intc>; >> + interrupt-controller; >> + }; >> + >> + spmi_bus: spmi@c400000 { >> + compatible = "qcom,spmi-pmic-arb"; >> + reg = <0x0 0xc400000 0x0 0x3000>, >> + <0x0 0xc500000 0x0 0x400000>, >> + <0x0 0xc440000 0x0 0x80000>, >> + <0x0 0xc4c0000 0x0 0x10000>, >> + <0x0 0xc42d000 0x0 0x4000>; >> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >> + interrupt-names = "periph_irq"; >> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >> + qcom,ee = <0>; >> + qcom,channel = <0>; >> + #address-cells = <2>; >> + #size-cells = <0>; >> + interrupt-controller; >> + #interrupt-cells = <4>; >> + }; >> + >> + tlmm: pinctrl@f000000 { >> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >> + reg = <0x0 0xf000000 0x0 0x1000000>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 151>; >> + wakeup-parent = <&pdc>; >> + >> + qup_uart0_default: qup-uart0-default-state { >> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >> + function = "qup00"; >> + }; >> + >> + qup_i2c1_data_clk: qup-i2c1-data-clk { > -state suffix Didn't realize this was for all pins. Will correct. > This is a friendly reminder during the review process. > > It seems my previous comments were not fully addressed. Maybe my > feedback got lost between the quotes, maybe you just forgot to apply it. > Please go back to the previous discussion and either implement all > requested changes or keep discussing them. > > Thank you. > >> + pins = "gpio10", "gpio11"; >> + function = "qup01"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi1_data_clk: qup-spi1-data-clk {> + pins = "gpio10", "gpio11", "gpio12"; >> + function = "qup01"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi1_cs: qup-spi1-cs { >> + pins = "gpio13"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c2_data_clk: qup-i2c2-data-clk { >> + pins = "gpio12", "gpio13"; >> + function = "qup02"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi2_data_clk: qup-spi2-data-clk { >> + pins = "gpio12", "gpio13", "gpio10"; >> + function = "qup02"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi2_cs: qup-spi2-cs { >> + pins = "gpio11"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c3_data_clk: qup-i2c3-data-clk { >> + pins = "gpio14", "gpio15"; >> + function = "qup03"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi3_data_clk: qup-spi3-data-clk { >> + pins = "gpio14", "gpio15", "gpio16"; >> + function = "qup03"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi3_cs: qup-spi3-cs { >> + pins = "gpio17"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c4_data_clk: qup-i2c4-data-clk { >> + pins = "gpio16", "gpio17"; >> + function = "qup04"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi4_data_clk: qup-spi4-data-clk { >> + pins = "gpio16", "gpio17", "gpio14"; >> + function = "qup04"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi4_cs: qup-spi4-cs { >> + pins = "gpio15"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c5_data_clk: qup-i2c5-data-clk { >> + pins = "gpio130", "gpio131"; >> + function = "qup05"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi5_data_clk: qup-spi5-data-clk { >> + pins = "gpio130", "gpio131", "gpio132"; >> + function = "qup05"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi5_cs: qup-spi5-cs { >> + pins = "gpio133"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c6_data_clk: qup-i2c6-data-clk { >> + pins = "gpio132", "gpio133"; >> + function = "qup06"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi6_data_clk: qup-spi6-data-clk { >> + pins = "gpio132", "gpio133", "gpio130"; >> + function = "qup06"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi6_cs: qup-spi6-cs { >> + pins = "gpio131"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_uart7_rx: qup-uart7-rx { >> + pins = "gpio135"; >> + function = "qup07"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart7_tx: qup-uart7-tx { >> + pins = "gpio134"; >> + function = "qup07"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart8_default: qup-uart8-default { >> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >> + function = "qup10"; >> + }; >> + >> + qup_i2c9_data_clk: qup-i2c9-data-clk { >> + pins = "gpio22", "gpio23"; >> + function = "qup11"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi9_data_clk: qup-spi9-data-clk { >> + pins = "gpio22", "gpio23", "gpio24"; >> + function = "qup11"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi9_cs: qup-spi9-cs { >> + pins = "gpio25"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c10_data_clk: qup-i2c10-data-clk { >> + pins = "gpio24", "gpio25"; >> + function = "qup12"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi10_data_clk: qup-spi10-data-clk { >> + pins = "gpio24", "gpio25", "gpio22"; >> + function = "qup12"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi10_cs: qup-spi10-cs { >> + pins = "gpio23"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c11_data_clk: qup-i2c11-data-clk { >> + pins = "gpio26", "gpio27"; >> + function = "qup13"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi11_data_clk: qup-spi11-data-clk { >> + pins = "gpio26", "gpio27", "gpio28"; >> + function = "qup13"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi11_cs: qup-spi11-cs { >> + pins = "gpio29"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c12_data_clk: qup-i2c12-data-clk { >> + pins = "gpio28", "gpio29"; >> + function = "qup14"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi12_data_clk: qup-spi12-data-clk { >> + pins = "gpio28", "gpio29", "gpio26"; >> + function = "qup14"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi12_cs: qup-spi12-cs { >> + pins = "gpio27"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c13_data_clk: qup-i2c13-data-clk { >> + pins = "gpio30", "gpio31"; >> + function = "qup15"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi13_data_clk: qup-spi13-data-clk { >> + pins = "gpio30", "gpio31", "gpio32"; >> + function = "qup15"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi13_cs: qup-spi13-cs { >> + pins = "gpio33"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_uart13_default: qup-uart13-default { >> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >> + function = "qup15"; >> + }; >> + >> + qup_i2c14_data_clk: qup-i2c14-data-clk { >> + pins = "gpio34", "gpio35"; >> + function = "qup16"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi14_data_clk: qup-spi14-data-clk { >> + pins = "gpio34", "gpio35", "gpio36"; >> + function = "qup16"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi14_cs: qup-spi14-cs { >> + pins = "gpio37", "gpio38"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c15_data_clk: qup-i2c15-data-clk { >> + pins = "gpio40", "gpio41"; >> + function = "qup17"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi15_data_clk: qup-spi15-data-clk { >> + pins = "gpio40", "gpio41", "gpio30"; >> + function = "qup17"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi15_cs: qup-spi15-cs { >> + pins = "gpio31"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + }; >> + >> + apps_smmu: apps-smmu@15000000 { >> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >> + "arm,mmu-500"; >> + reg = <0x0 0x15000000 0x0 0x100000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <2>; >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + intc: interrupt-controller@17200000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x20000>; >> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + timer@17420000 { >> + compatible = "arm,armv7-timer-mem"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + reg = <0x0 0x17420000 0x0 0x1000>; >> + clock-frequency = <19200000>; >> + >> + frame@17421000 { >> + frame-number = <0>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17421000 0x0 0x1000>, >> + <0x0 0x17422000 0x0 0x1000>; >> + }; >> + >> + frame@17423000 { >> + frame-number = <1>; >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17423000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17425000 { >> + frame-number = <2>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17425000 0x0 0x1000>, >> + <0x0 0x17426000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17427000 { >> + frame-number = <3>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17427000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17429000 { >> + frame-number = <4>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17429000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@1742b000 { >> + frame-number = <5>; >> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x1742b000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@1742d000 { >> + frame-number = <6>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x1742d000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + }; >> + >> + apps_rsc: rsc@17a00000 { >> + label = "apps_rsc"; >> + compatible = "qcom,rpmh-rsc"; > compatible, then reg, then the rest. Sure. > >> + reg = <0x0 0x17a00000 0x0 0x10000>, >> + <0x0 0x17a10000 0x0 0x10000>, >> + <0x0 0x17a20000 0x0 0x10000>; >> + reg-names = "drv-0", "drv-1", "drv-2"; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >> + qcom,tcs-offset = <0xd00>; >> + qcom,drv-id = <2>; >> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >> + >> + apps_bcm_voter: bcm_voter { > Eh... > > Does not look like you tested the DTS against bindings. Please run `make > dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst > for instructions). Will do. > >> + compatible = "qcom,bcm-voter"; >> + }; > > > > Best regards, > Krzysztof > Thanks, Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-19 20:21 ` Melody Olvera @ 2022-10-20 12:41 ` Krzysztof Kozlowski 2022-10-20 13:54 ` Stephan Gerhold 0 siblings, 1 reply; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-20 12:41 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 19/10/2022 16:21, Melody Olvera wrote: > > > On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: >> On 14/10/2022 18:11, Melody Olvera wrote: >>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>> to boot to shell with console on these SoCs. >>> >>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>> 2 files changed, 1673 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> new file mode 100644 >>> index 000000000000..777734b30f56 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> @@ -0,0 +1,1646 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >>> +#include <dt-bindings/clock/qcom,rpmh.h> >>> +#include <dt-bindings/dma/qcom-gpi.h> >>> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >>> +#include <dt-bindings/power/qcom-rpmpd.h> >>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >>> + >>> +/ { >>> + interrupt-parent = <&intc>; >>> + >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + chosen: chosen { }; >>> + >>> + clocks { >>> + xo_board: xo-board { >>> + compatible = "fixed-clock"; >>> + clock-frequency = <19200000>; >> Both clocks are not a property of a SoC. They are provided by the board, >> so they should either be defined by board DTS or at least their >> frequency must be provided by the board. > That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in > the dtsi. These are common to the boards anyways. Because people do not pay attention what is part of SoC, what is part of board. DTSI is for the SoC and these are inputs to the SoC. We had these talks and my recommendation is the same. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 12:41 ` Krzysztof Kozlowski @ 2022-10-20 13:54 ` Stephan Gerhold 2022-10-20 16:08 ` Krzysztof Kozlowski 0 siblings, 1 reply; 28+ messages in thread From: Stephan Gerhold @ 2022-10-20 13:54 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On Thu, Oct 20, 2022 at 08:41:15AM -0400, Krzysztof Kozlowski wrote: > On 19/10/2022 16:21, Melody Olvera wrote: > > On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: > >> On 14/10/2022 18:11, Melody Olvera wrote: > >> [...] > >>> + clocks { > >>> + xo_board: xo-board { > >>> + compatible = "fixed-clock"; > >>> + clock-frequency = <19200000>; > >> Both clocks are not a property of a SoC. They are provided by the board, > >> so they should either be defined by board DTS or at least their > >> frequency must be provided by the board. > > That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in > > the dtsi. These are common to the boards anyways. > > Because people do not pay attention what is part of SoC, what is part of > board. DTSI is for the SoC and these are inputs to the SoC. > (Just chiming in because I had this thought already a few times when you suggested moving the XO "clock-frequency" to the board DTS:) I understand your reasoning for moving components of the board to the board DTS, but IMHO adding just the clock-frequency to the board DTS is even more misleading: It suggests that there are functional board designs where you would use a XO clock with a different clock-frequency. Is that really realistic though? There are assumptions about the XO clock frequency in a lot of places: You would need to fully rewrite the gcc-<SoC>.c driver because it has fixed multipliers/dividers for one specific XO frequency. All firmware binaries would likely need changes. And does the hardware even support a different XO clock frequency? The APQ8016E datasheet for example strictly documents a XO clock input of 19.2 MHz and a sleep clock of 32.768 kHz. IMHO the only realistic variation of the XO clock setup would be to have a physical "fixed-clock" with a higher frequency, followed by a "fixed-factor-clock" that brings it back to the expected frequency. To model that properly it is not enough to have just the "clock-frequency" in the board DTS. In this case you need two clock nodes, and the xo_board would be the "fixed-factor-clock". Therefore it should be all or nothing IMO: Either we move the full xo-board node to the board DTS (which allows alternatively defining the "fixed-factor-clock" or whatever). Or we assume that there will be always an input clock signal with the fixed frequency and keep it fully in the SoC .dtsi. Having just the "clock-frequency" in the board DTS puts the attention on the wrong detail, IMO. :) Thanks, Stephan ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 13:54 ` Stephan Gerhold @ 2022-10-20 16:08 ` Krzysztof Kozlowski 2022-10-20 16:26 ` Krzysztof Kozlowski 2022-10-20 17:18 ` Stephan Gerhold 0 siblings, 2 replies; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-20 16:08 UTC (permalink / raw) To: Stephan Gerhold Cc: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 20/10/2022 09:54, Stephan Gerhold wrote: > On Thu, Oct 20, 2022 at 08:41:15AM -0400, Krzysztof Kozlowski wrote: >> On 19/10/2022 16:21, Melody Olvera wrote: >>> On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: >>>> On 14/10/2022 18:11, Melody Olvera wrote: >>>> [...] >>>>> + clocks { >>>>> + xo_board: xo-board { >>>>> + compatible = "fixed-clock"; >>>>> + clock-frequency = <19200000>; >>>> Both clocks are not a property of a SoC. They are provided by the board, >>>> so they should either be defined by board DTS or at least their >>>> frequency must be provided by the board. >>> That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in >>> the dtsi. These are common to the boards anyways. >> >> Because people do not pay attention what is part of SoC, what is part of >> board. DTSI is for the SoC and these are inputs to the SoC. >> > > (Just chiming in because I had this thought already a few times when you > suggested moving the XO "clock-frequency" to the board DTS:) > > I understand your reasoning for moving components of the board to the > board DTS, but IMHO adding just the clock-frequency to the board DTS is > even more misleading: It suggests that there are functional board > designs where you would use a XO clock with a different clock-frequency. > Is that really realistic though? Keeping it in DTSI also suggests you could have some different frequency. > > There are assumptions about the XO clock frequency in a lot of places: > You would need to fully rewrite the gcc-<SoC>.c driver because it has > fixed multipliers/dividers for one specific XO frequency. All firmware > binaries would likely need changes. And does the hardware even support a > different XO clock frequency? The APQ8016E datasheet for example > strictly documents a XO clock input of 19.2 MHz and a sleep clock of > 32.768 kHz. I know, the same with most of other platforms. Qualcomm is not special here. Maybe the difference is that some other platforms have few external clocks and not all of them are required. > IMHO the only realistic variation of the XO clock setup would be to have > a physical "fixed-clock" with a higher frequency, followed by a > "fixed-factor-clock" that brings it back to the expected frequency. To > model that properly it is not enough to have just the "clock-frequency" > in the board DTS. In this case you need two clock nodes, and the > xo_board would be the "fixed-factor-clock". It's not about whether you can change it or not. It's about describing hardware - SoC DTSI describes SoC. DTS describes the board (assuming there is no SoM or other DTSI files). This clock is not in DTSI. > Therefore it should be all or nothing IMO: Either we move the full > xo-board node to the board DTS (which allows alternatively defining the > "fixed-factor-clock" or whatever). You can move entire clock to boards. > Or we assume that there will be > always an input clock signal with the fixed frequency and keep it fully > in the SoC .dtsi. > > Having just the "clock-frequency" in the board DTS puts the attention on > the wrong detail, IMO. :) No, it puts attention to the board designer that he needs to provide the clock in his design. We had such talks about other platforms, although I do not have any recent bookmarks. Something older: https://lore.kernel.org/all/3382034.5ADO0F7naY@wuerfel/ https://lore.kernel.org/linux-samsung-soc/53DAB0A6.9030700@gmail.com/ Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 16:08 ` Krzysztof Kozlowski @ 2022-10-20 16:26 ` Krzysztof Kozlowski 2022-10-20 17:18 ` Stephan Gerhold 1 sibling, 0 replies; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-20 16:26 UTC (permalink / raw) To: Stephan Gerhold Cc: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 20/10/2022 12:08, Krzysztof Kozlowski wrote: > On 20/10/2022 09:54, Stephan Gerhold wrote: >> On Thu, Oct 20, 2022 at 08:41:15AM -0400, Krzysztof Kozlowski wrote: >>> On 19/10/2022 16:21, Melody Olvera wrote: >>>> On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: >>>>> On 14/10/2022 18:11, Melody Olvera wrote: >>>>> [...] >>>>>> + clocks { >>>>>> + xo_board: xo-board { >>>>>> + compatible = "fixed-clock"; >>>>>> + clock-frequency = <19200000>; >>>>> Both clocks are not a property of a SoC. They are provided by the board, >>>>> so they should either be defined by board DTS or at least their >>>>> frequency must be provided by the board. >>>> That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in >>>> the dtsi. These are common to the boards anyways. >>> >>> Because people do not pay attention what is part of SoC, what is part of >>> board. DTSI is for the SoC and these are inputs to the SoC. >>> >> >> (Just chiming in because I had this thought already a few times when you >> suggested moving the XO "clock-frequency" to the board DTS:) >> >> I understand your reasoning for moving components of the board to the >> board DTS, but IMHO adding just the clock-frequency to the board DTS is >> even more misleading: It suggests that there are functional board >> designs where you would use a XO clock with a different clock-frequency. >> Is that really realistic though? > > Keeping it in DTSI also suggests you could have some different frequency. > >> >> There are assumptions about the XO clock frequency in a lot of places: >> You would need to fully rewrite the gcc-<SoC>.c driver because it has >> fixed multipliers/dividers for one specific XO frequency. All firmware >> binaries would likely need changes. And does the hardware even support a >> different XO clock frequency? The APQ8016E datasheet for example >> strictly documents a XO clock input of 19.2 MHz and a sleep clock of >> 32.768 kHz. > > I know, the same with most of other platforms. Qualcomm is not special > here. Maybe the difference is that some other platforms have few > external clocks and not all of them are required. > >> IMHO the only realistic variation of the XO clock setup would be to have >> a physical "fixed-clock" with a higher frequency, followed by a >> "fixed-factor-clock" that brings it back to the expected frequency. To >> model that properly it is not enough to have just the "clock-frequency" >> in the board DTS. In this case you need two clock nodes, and the >> xo_board would be the "fixed-factor-clock". > > It's not about whether you can change it or not. It's about describing > hardware - SoC DTSI describes SoC. DTS describes the board (assuming > there is no SoM or other DTSI files). This clock is not in DTSI. > >> Therefore it should be all or nothing IMO: Either we move the full >> xo-board node to the board DTS (which allows alternatively defining the >> "fixed-factor-clock" or whatever). > > You can move entire clock to boards. > >> Or we assume that there will be >> always an input clock signal with the fixed frequency and keep it fully >> in the SoC .dtsi. >> >> Having just the "clock-frequency" in the board DTS puts the attention on >> the wrong detail, IMO. :) > > No, it puts attention to the board designer that he needs to provide the > clock in his design. > Another solution which would satisfy me, would be to put these clocks to a dedicated, re-usable DTSI and include that DTSI in each board DTS. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 16:08 ` Krzysztof Kozlowski 2022-10-20 16:26 ` Krzysztof Kozlowski @ 2022-10-20 17:18 ` Stephan Gerhold 2022-10-20 17:59 ` Krzysztof Kozlowski 1 sibling, 1 reply; 28+ messages in thread From: Stephan Gerhold @ 2022-10-20 17:18 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On Thu, Oct 20, 2022 at 12:08:36PM -0400, Krzysztof Kozlowski wrote: > On 20/10/2022 09:54, Stephan Gerhold wrote: > > On Thu, Oct 20, 2022 at 08:41:15AM -0400, Krzysztof Kozlowski wrote: > >> On 19/10/2022 16:21, Melody Olvera wrote: > >>> On 10/15/2022 6:28 AM, Krzysztof Kozlowski wrote: > >>>> On 14/10/2022 18:11, Melody Olvera wrote: > >>>> [...] > >>>>> + clocks { > >>>>> + xo_board: xo-board { > >>>>> + compatible = "fixed-clock"; > >>>>> + clock-frequency = <19200000>; > >>>> Both clocks are not a property of a SoC. They are provided by the board, > >>>> so they should either be defined by board DTS or at least their > >>>> frequency must be provided by the board. > >>> That doesn't seem in keeping with precedent.... the sm8* series all have the clocks in > >>> the dtsi. These are common to the boards anyways. > >> > >> Because people do not pay attention what is part of SoC, what is part of > >> board. DTSI is for the SoC and these are inputs to the SoC. > >> > > > > (Just chiming in because I had this thought already a few times when you > > suggested moving the XO "clock-frequency" to the board DTS:) > > > > I understand your reasoning for moving components of the board to the > > board DTS, but IMHO adding just the clock-frequency to the board DTS is > > even more misleading: It suggests that there are functional board > > designs where you would use a XO clock with a different clock-frequency. > > Is that really realistic though? > > Keeping it in DTSI also suggests you could have some different frequency. > If the fixed-clock was listed in the SoC DTSI I would personally consider it as fixed and would not try to modify it in the board DTS. The way I see it is that the board DTS mostly _extends_ the SoC DTSI (add peripherals/supplies/...) instead of _modifying_ it. Anyway this is likely subjective and was not my main point/question. :) > > > > There are assumptions about the XO clock frequency in a lot of places: > > You would need to fully rewrite the gcc-<SoC>.c driver because it has > > fixed multipliers/dividers for one specific XO frequency. All firmware > > binaries would likely need changes. And does the hardware even support a > > different XO clock frequency? The APQ8016E datasheet for example > > strictly documents a XO clock input of 19.2 MHz and a sleep clock of > > 32.768 kHz. > > I know, the same with most of other platforms. Qualcomm is not special > here. Maybe the difference is that some other platforms have few > external clocks and not all of them are required. > > > IMHO the only realistic variation of the XO clock setup would be to have > > a physical "fixed-clock" with a higher frequency, followed by a > > "fixed-factor-clock" that brings it back to the expected frequency. To > > model that properly it is not enough to have just the "clock-frequency" > > in the board DTS. In this case you need two clock nodes, and the > > xo_board would be the "fixed-factor-clock". > > It's not about whether you can change it or not. It's about describing > hardware - SoC DTSI describes SoC. DTS describes the board (assuming > there is no SoM or other DTSI files). This clock is not in DTSI. > > > Therefore it should be all or nothing IMO: Either we move the full > > xo-board node to the board DTS (which allows alternatively defining the > > "fixed-factor-clock" or whatever). > > You can move entire clock to boards. > > > Or we assume that there will be > > always an input clock signal with the fixed frequency and keep it fully > > in the SoC .dtsi. > > > > Having just the "clock-frequency" in the board DTS puts the attention on > > the wrong detail, IMO. :) > > No, it puts attention to the board designer that he needs to provide the > clock in his design. > > We had such talks about other platforms, although I do not have any > recent bookmarks. Something older: > > https://lore.kernel.org/all/3382034.5ADO0F7naY@wuerfel/ > > https://lore.kernel.org/linux-samsung-soc/53DAB0A6.9030700@gmail.com/ > If I understand you correctly your argument for having the clock in the board DTS instead of the SoC DTSI is: The SoC DTSI describes the components of the SoC, while the board DTS describes the components of the board (built around the SoC). The clock is part of the board (and not the SoC) and therefore belongs into the board DTS and not the SoC DTSI. Having the SoC/board components clearly separated ensures people writing new board DTS pay attention to everything board-specific. Correct? This sounds reasonable to me. However, the main question of my previous mail was: Why do you alternatively recommend to keep the clock defined in the SoC DTSI and to just put the clock-frequency into the board DTS? This sounds like a contradiction of the above to me: the clock is still (partially) described as part of the SoC, even though it belongs to the board. Someone writing a board DTS should not just put attention to the clock-frequency, but also if they have a single fixed-clock or maybe some kind of clock-fixed-factor setup, as I wrote. Thanks, Stephan ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 17:18 ` Stephan Gerhold @ 2022-10-20 17:59 ` Krzysztof Kozlowski 2022-10-20 18:55 ` Melody Olvera 0 siblings, 1 reply; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-20 17:59 UTC (permalink / raw) To: Stephan Gerhold Cc: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 20/10/2022 13:18, Stephan Gerhold wrote: >> No, it puts attention to the board designer that he needs to provide the >> clock in his design. >> >> We had such talks about other platforms, although I do not have any >> recent bookmarks. Something older: >> >> https://lore.kernel.org/all/3382034.5ADO0F7naY@wuerfel/ >> >> https://lore.kernel.org/linux-samsung-soc/53DAB0A6.9030700@gmail.com/ >> > > If I understand you correctly your argument for having the clock in the > board DTS instead of the SoC DTSI is: > > The SoC DTSI describes the components of the SoC, while the board DTS > describes the components of the board (built around the SoC). The clock > is part of the board (and not the SoC) and therefore belongs into the > board DTS and not the SoC DTSI. Having the SoC/board components clearly > separated ensures people writing new board DTS pay attention to > everything board-specific. > > Correct? This sounds reasonable to me. Yes. > > However, the main question of my previous mail was: Why do you > alternatively recommend to keep the clock defined in the SoC DTSI and to > just put the clock-frequency into the board DTS? This sounds like a > contradiction of the above to me: the clock is still (partially) > described as part of the SoC, even though it belongs to the board. The proposal is a trade-off, compromise between code duplication and above recommendation of splitting SoC <-> board. As you said, all boards will provide this clock, so it is reasonable to put some pieces of it in the SoC DTSI to avoid duplication. But the final piece - what clock is there exactly (model, frequency etc) should be put in board DTS to clarify that this comes with board. > Someone writing a board DTS should not just put attention to the > clock-frequency, but also if they have a single fixed-clock or > maybe some kind of clock-fixed-factor setup, as I wrote. True. If such setup is probably, then my recommendation would be to put entire clock to the board. Just note, that even in proposed frequency->board DTS, it is still possible to use the clock-fixed-factor. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-20 17:59 ` Krzysztof Kozlowski @ 2022-10-20 18:55 ` Melody Olvera 0 siblings, 0 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-20 18:55 UTC (permalink / raw) To: Krzysztof Kozlowski, Stephan Gerhold Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 10/20/2022 10:59 AM, Krzysztof Kozlowski wrote: > On 20/10/2022 13:18, Stephan Gerhold wrote: >>> No, it puts attention to the board designer that he needs to provide the >>> clock in his design. >>> >>> We had such talks about other platforms, although I do not have any >>> recent bookmarks. Something older: >>> >>> https://lore.kernel.org/all/3382034.5ADO0F7naY@wuerfel/ >>> >>> https://lore.kernel.org/linux-samsung-soc/53DAB0A6.9030700@gmail.com/ >>> >> If I understand you correctly your argument for having the clock in the >> board DTS instead of the SoC DTSI is: >> >> The SoC DTSI describes the components of the SoC, while the board DTS >> describes the components of the board (built around the SoC). The clock >> is part of the board (and not the SoC) and therefore belongs into the >> board DTS and not the SoC DTSI. Having the SoC/board components clearly >> separated ensures people writing new board DTS pay attention to >> everything board-specific. >> >> Correct? This sounds reasonable to me. > Yes. > >> However, the main question of my previous mail was: Why do you >> alternatively recommend to keep the clock defined in the SoC DTSI and to >> just put the clock-frequency into the board DTS? This sounds like a >> contradiction of the above to me: the clock is still (partially) >> described as part of the SoC, even though it belongs to the board. > The proposal is a trade-off, compromise between code duplication and > above recommendation of splitting SoC <-> board. > > As you said, all boards will provide this clock, so it is reasonable to > put some pieces of it in the SoC DTSI to avoid duplication. But the > final piece - what clock is there exactly (model, frequency etc) should > be put in board DTS to clarify that this comes with board. > >> Someone writing a board DTS should not just put attention to the >> clock-frequency, but also if they have a single fixed-clock or >> maybe some kind of clock-fixed-factor setup, as I wrote. > True. If such setup is probably, then my recommendation would be to put > entire clock to the board. Going through this thread, this seems to be the conclusion. Will all clock nodes to the DTS files. > > Just note, that even in proposed frequency->board DTS, it is still > possible to use the clock-fixed-factor. > > Thanks, Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera 2022-10-15 13:28 ` Krzysztof Kozlowski @ 2022-10-15 15:11 ` Krzysztof Kozlowski 2022-10-18 22:15 ` Krzysztof Kozlowski 2022-10-24 0:53 ` Richard Acayan 3 siblings, 0 replies; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-15 15:11 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 14/10/2022 18:11, Melody Olvera wrote: (...) > + > + firmware { > + qcom_scm { > + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; > + #reset-cells = <1>; > + }; > + }; > + > + clk_virt: interconnect-0 { > + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; How does this pass your dtbs_check tests? This applies everywhere... Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera 2022-10-15 13:28 ` Krzysztof Kozlowski 2022-10-15 15:11 ` Krzysztof Kozlowski @ 2022-10-18 22:15 ` Krzysztof Kozlowski 2022-10-19 18:56 ` Melody Olvera 2022-10-24 0:53 ` Richard Acayan 3 siblings, 1 reply; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-18 22:15 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 14/10/2022 18:11, Melody Olvera wrote: > Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base > descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller > to boot to shell with console on these SoCs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + > 2 files changed, 1673 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > new file mode 100644 > index 000000000000..777734b30f56 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -0,0 +1,1646 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/interconnect/qcom,qdu1000.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> As pointed out by kernel test robot, your patchset is unbuildable and unmerge'able, so automated tools cannot test it. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-18 22:15 ` Krzysztof Kozlowski @ 2022-10-19 18:56 ` Melody Olvera 0 siblings, 0 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-19 18:56 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/18/2022 3:15 PM, Krzysztof Kozlowski wrote: > On 14/10/2022 18:11, Melody Olvera wrote: >> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >> to boot to shell with console on these SoCs. >> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >> 2 files changed, 1673 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> new file mode 100644 >> index 000000000000..777734b30f56 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -0,0 +1,1646 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >> +#include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/dma/qcom-gpi.h> >> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >> +#include <dt-bindings/power/qcom-rpmpd.h> >> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > As pointed out by kernel test robot, your patchset is unbuildable and > unmerge'able, so automated tools cannot test it. I saw. I will be more explicit about the dependencies on previous patches in the next patchset. Thanks, Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera ` (2 preceding siblings ...) 2022-10-18 22:15 ` Krzysztof Kozlowski @ 2022-10-24 0:53 ` Richard Acayan 2022-10-24 17:10 ` Melody Olvera 3 siblings, 1 reply; 28+ messages in thread From: Richard Acayan @ 2022-10-24 0:53 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel > Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base > descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller > to boot to shell with console on these SoCs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + > 2 files changed, 1673 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > new file mode 100644 > index 000000000000..777734b30f56 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -0,0 +1,1646 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/interconnect/qcom,qdu1000.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen: chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + clock-frequency = <19200000>; > + clock-output-names = "xo_board"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + power-domain-names = "psci"; > + power-domains = <&CPU_PD0>; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_100>; > + L2_100: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + power-domains = <&CPU_PD2>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_200>; > + L2_200: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + power-domains = <&CPU_PD3>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_300>; > + L2_300: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_OFF: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "rail-pc"; > + entry-latency-us = <274>; > + exit-latency-us = <480>; > + min-residency-us = <3934>; > + arm,psci-suspend-param = <0x40000004>; > + local-timer-stop; > + }; > + }; > + > + domain-idle-states { > + CLUSTER_SLEEP_0: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + idle-state-name = "cluster-l3-off"; > + entry-latency-us = <584>; > + exit-latency-us = <2332>; > + min-residency-us = <6118>; > + arm,psci-suspend-param = <0x41000044>; > + }; > + > + CLUSTER_SLEEP_1: cluster-sleep-1 { > + compatible = "domain-idle-state"; > + idle-state-name = "cluster-power-collapse"; > + entry-latency-us = <2893>; > + exit-latency-us = <4023>; > + min-residency-us = <9987>; > + arm,psci-suspend-param = <0x41003344>; > + }; > + }; > + > + firmware { > + qcom_scm { > + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; > + #reset-cells = <1>; > + }; > + }; > + > + clk_virt: interconnect-0 { > + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-1 { > + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + > + CPU_PD0: cpu-pd0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD1: cpu-pd1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD2: cpu-pd2 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD3: cpu-pd3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CLUSTER_PD: cluster-pd { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; > + }; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: memory@80000000 { > + no-map; > + reg = <0x0 0x80000000 0x0 0x600000>; > + }; > + > + xbl_dt_log_mem: memory@80600000 { > + no-map; > + reg = <0x0 0x80600000 0x0 0x40000>; > + }; > + > + xbl_ramdump_mem: memory@80640000 { > + no-map; > + reg = <0x0 0x80640000 0x0 0x1c0000>; > + }; > + > + aop_image_mem: memory@80800000 { > + no-map; > + reg = <0x0 0x80800000 0x0 0x60000>; > + }; > + > + aop_cmd_db_mem: memory@80860000 { > + compatible = "qcom,cmd-db"; > + no-map; > + reg = <0x0 0x80860000 0x0 0x20000>; > + }; > + > + aop_config_mem: memory@80880000 { > + no-map; > + reg = <0x0 0x80880000 0x0 0x20000>; > + }; > + > + tme_crash_dump_mem: memory@808a0000 { > + no-map; > + reg = <0x0 0x808a0000 0x0 0x40000>; > + }; > + > + tme_log_mem: memory@808e0000 { > + no-map; > + reg = <0x0 0x808e0000 0x0 0x4000>; > + }; > + > + uefi_log_mem: memory@808e4000 { > + no-map; > + reg = <0x0 0x808e4000 0x0 0x10000>; > + }; > + > + /* secdata region can be reused by apps */ > + > + smem_mem: memory@80900000 { > + compatible = "qcom,smem"; > + no-map; > + reg = <0x0 0x80900000 0x0 0x200000>; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: memory@80b00000 { > + no-map; > + reg = <0x0 0x80b00000 0x0 0x100000>; > + }; > + > + xbl_sc_mem: memory@80c00000 { > + no-map; > + reg = <0x0 0x80c00000 0x0 0x40000>; > + }; > + > + /* uefi region can be reused by apps */ > + > + tz_stat_mem: memory@81d00000 { > + no-map; > + reg = <0x0 0x81d00000 0x0 0x100000>; > + }; > + > + tags_mem: memory@81e00000 { > + no-map; > + reg = <0x0 0x81e00000 0x0 0x500000>; > + }; > + > + qtee_mem: memory@82300000 { > + no-map; > + reg = <0x0 0x82300000 0x0 0x500000>; > + }; > + > + ta_mem: memory@82800000 { > + no-map; > + reg = <0x0 0x82800000 0x0 0xa00000>; > + }; > + > + fs1_mem: memory@83200000 { > + no-map; > + reg = <0x0 0x83200000 0x0 0x400000>; > + }; > + > + fs2_mem: memory@83600000 { > + no-map; > + reg = <0x0 0x83600000 0x0 0x400000>; > + }; > + > + fs3_mem: memory@83a00000 { > + no-map; > + reg = <0x0 0x83a00000 0x0 0x400000>; > + }; > + > + /* Linux kernel image is loaded at 0x83e00000 */ > + > + ipa_fw_mem: memory@8be00000 { > + no-map; > + reg = <0x0 0x8be00000 0x0 0x10000>; > + }; > + > + ipa_gsi_mem: memory@8be10000 { > + no-map; > + reg = <0x0 0x8be10000 0x0 0x14000>; > + }; > + > + mpss_mem: memory@8c000000 { > + no-map; > + reg = <0x0 0x8c000000 0x0 0x12c00000>; > + }; > + > + q6_mpss_dtb_mem: memory@9ec00000 { > + no-map; > + reg = <0x0 0x9ec00000 0x0 0x80000>; > + }; > + > + tenx_mem: memory@a0000000 { > + no-map; > + reg = <0x0 0xa0000000 0x0 0x19600000>; > + }; > + > + oem_tenx_mem: memory@b9600000 { > + no-map; > + reg = <0x0 0xb9600000 0x0 0x6a00000>; > + }; > + > + tenx_q6_buffer_mem: memory@c0000000 { > + no-map; > + reg = <0x0 0xc0000000 0x0 0x3200000>; > + }; > + > + ipa_buffer_mem: memory@c3200000 { > + no-map; > + reg = <0x0 0xc3200000 0x0 0x12c00000>; > + }; > + }; > + > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@80000 { > + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; > + reg = <0x0 0x80000 0x0 0x1f4200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + }; > + > + gpi_dma0: dma-controller@900000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; This won't work if you drop series [1]. It won't just fail the schema checks, but it would also fail to probe because the driver doesn't recognise it. I think you were told to rebase on [2], and didn't change your own series because it only applied to ee_offset = 0x0. There is another series [3] that was sent to you, meant for ee_offset = 0x10000. You're expected to change your patches (in both series you sent) based on what was changed in that series. [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ > + #dma-cells = <5>; > + reg = <0x0 0x900000 0x0 0x60000>; > + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0xf6 0x0>; > + status = "ok"; > + }; > + > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x9c0000 0x0 0x2000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + iommus = <&apps_smmu 0xe3 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 > + &clk_virt SLAVE_QUP_CORE_0 0>; > + interconnect-names = "qup-core"; > + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; > + qcom,iommu-geometry = <0x40000000 0x10000000>; > + qcom,iommu-dma = "fastmap"; > + dma-coherent; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart0: serial@980000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x980000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart0_default>; > + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@984000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x984000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c1_data_clk>; > + dmas = <&gpi_dma0 0 1 3 64 0>, > + <&gpi_dma0 1 1 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi1: spi@984000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x984000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; > + dmas = <&gpi_dma0 0 1 1 64 0>, > + <&gpi_dma0 1 1 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c2: i2c@988000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x988000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_data_clk>; > + dmas = <&gpi_dma0 0 2 3 64 0>, > + <&gpi_dma0 1 2 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@988000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x988000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; > + dmas = <&gpi_dma0 0 2 1 64 0>, > + <&gpi_dma0 1 2 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c3: i2c@98c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c3_data_clk>; > + dmas = <&gpi_dma0 0 3 3 64 0>, > + <&gpi_dma0 1 3 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@98c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; > + dmas = <&gpi_dma0 0 3 1 64 0>, > + <&gpi_dma0 1 3 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c4: i2c@990000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x990000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_data_clk>; > + dmas = <&gpi_dma0 0 4 3 64 0>, > + <&gpi_dma0 1 4 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi4: spi@990000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x990000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; > + dmas = <&gpi_dma0 0 4 1 64 0>, > + <&gpi_dma0 1 4 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c5: i2c@994000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x994000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c5_data_clk>; > + dmas = <&gpi_dma0 0 5 3 64 0>, > + <&gpi_dma0 1 5 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi5: spi@994000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x994000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; > + dmas = <&gpi_dma0 0 5 1 64 0>, > + <&gpi_dma0 1 5 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c6: i2c@998000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x998000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c6_data_clk>; > + dmas = <&gpi_dma0 0 6 3 64 0>, > + <&gpi_dma0 1 6 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi6: spi@998000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x998000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, > + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; > + dmas = <&gpi_dma0 0 6 1 64 0>, > + <&gpi_dma0 1 6 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + uart7: serial@99c000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x99c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; See above. > + #dma-cells = <5>; > + reg = <0x0 0xa00000 0x0 0x60000>; > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0x116 0x0>; > + status = "ok"; > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0xac0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + iommus = <&apps_smmu 0x103 0x0>; > + #address-cells = <1>; > + #size-cells = <1>; > + clock-names = "m-ahb", "s-ahb"; > + > + ranges; > + status = "disabled"; > + > + uart8: serial@a80000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa80000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart8_default>; > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c9: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c9_data_clk>; > + dmas = <&gpi_dma1 0 1 3 64 0>, > + <&gpi_dma1 1 1 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi9: spi@a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; > + dmas = <&gpi_dma1 0 1 1 64 0>, > + <&gpi_dma1 1 1 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c10: i2c@a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c10_data_clk>; > + dmas = <&gpi_dma1 0 2 3 64 0>, > + <&gpi_dma1 1 2 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi10: spi@a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; > + dmas = <&gpi_dma1 0 2 1 64 0>, > + <&gpi_dma1 1 2 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c11: i2c@a8c000 { > + compatible = "qcom,i2c-geni"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c11_data_clk>; > + dmas = <&gpi_dma1 0 3 3 64 0>, > + <&gpi_dma1 1 3 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi11: spi@a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; > + dmas = <&gpi_dma1 0 3 1 64 0>, > + <&gpi_dma1 1 3 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c12: i2c@a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c12_data_clk>; > + dmas = <&gpi_dma1 0 4 3 64 0>, > + <&gpi_dma1 1 4 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi12: spi@a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; > + dmas = <&gpi_dma1 0 4 1 64 0>, > + <&gpi_dma1 1 4 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c13: i2c@a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c13_data_clk>; > + dmas = <&gpi_dma1 0 5 3 64 0>, > + <&gpi_dma1 1 5 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart13: serial@a94000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart13_default>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi13: spi@a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; > + dmas = <&gpi_dma1 0 5 1 64 0>, > + <&gpi_dma1 1 5 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c14: i2c@a98000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c14_data_clk>; > + dmas = <&gpi_dma1 0 6 3 64 0>, > + <&gpi_dma1 1 6 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi14: spi@a98000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; > + dmas = <&gpi_dma1 0 6 1 64 0>, > + <&gpi_dma1 1 6 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + > + i2c15: i2c@a9c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c15_data_clk>; > + dmas = <&gpi_dma1 0 7 3 64 0>, > + <&gpi_dma1 1 7 3 64 0>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi15: spi@a9c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + interconnect-names = "qup-core", "qup-config", "qup-memory"; > + interconnects = > + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, > + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; > + dmas = <&gpi_dma1 0 7 1 64 0>, > + <&gpi_dma1 1 7 1 64 0>; > + dma-names = "tx", "rx"; > + status = "disabled"; > + }; > + }; > + > + system_noc: interconnect@1640000 { > + reg = <0x0 0x1640000 0x0 0x45080>; > + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; > + #interconnect-cells = <1>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x1f40000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,pdc"; > + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; > + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; > + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, > + <94 609 31>, <125 63 1>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0xc400000 0x0 0x3000>, > + <0x0 0xc500000 0x0 0x400000>, > + <0x0 0xc440000 0x0 0x80000>, > + <0x0 0xc4c0000 0x0 0x10000>, > + <0x0 0xc42d000 0x0 0x4000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; > + reg = <0x0 0xf000000 0x0 0x1000000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 151>; > + wakeup-parent = <&pdc>; > + > + qup_uart0_default: qup-uart0-default-state { > + pins = "gpio6", "gpio7", "gpio8", "gpio9"; > + function = "qup00"; > + }; > + > + qup_i2c1_data_clk: qup-i2c1-data-clk { > + pins = "gpio10", "gpio11"; > + function = "qup01"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi1_data_clk: qup-spi1-data-clk { > + pins = "gpio10", "gpio11", "gpio12"; > + function = "qup01"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi1_cs: qup-spi1-cs { > + pins = "gpio13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c2_data_clk: qup-i2c2-data-clk { > + pins = "gpio12", "gpio13"; > + function = "qup02"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi2_data_clk: qup-spi2-data-clk { > + pins = "gpio12", "gpio13", "gpio10"; > + function = "qup02"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi2_cs: qup-spi2-cs { > + pins = "gpio11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c3_data_clk: qup-i2c3-data-clk { > + pins = "gpio14", "gpio15"; > + function = "qup03"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi3_data_clk: qup-spi3-data-clk { > + pins = "gpio14", "gpio15", "gpio16"; > + function = "qup03"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi3_cs: qup-spi3-cs { > + pins = "gpio17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c4_data_clk: qup-i2c4-data-clk { > + pins = "gpio16", "gpio17"; > + function = "qup04"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi4_data_clk: qup-spi4-data-clk { > + pins = "gpio16", "gpio17", "gpio14"; > + function = "qup04"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi4_cs: qup-spi4-cs { > + pins = "gpio15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c5_data_clk: qup-i2c5-data-clk { > + pins = "gpio130", "gpio131"; > + function = "qup05"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi5_data_clk: qup-spi5-data-clk { > + pins = "gpio130", "gpio131", "gpio132"; > + function = "qup05"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi5_cs: qup-spi5-cs { > + pins = "gpio133"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c6_data_clk: qup-i2c6-data-clk { > + pins = "gpio132", "gpio133"; > + function = "qup06"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi6_data_clk: qup-spi6-data-clk { > + pins = "gpio132", "gpio133", "gpio130"; > + function = "qup06"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi6_cs: qup-spi6-cs { > + pins = "gpio131"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart7_rx: qup-uart7-rx { > + pins = "gpio135"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart7_tx: qup-uart7-tx { > + pins = "gpio134"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart8_default: qup-uart8-default { > + pins = "gpio18", "gpio19", "gpio20", "gpio21"; > + function = "qup10"; > + }; > + > + qup_i2c9_data_clk: qup-i2c9-data-clk { > + pins = "gpio22", "gpio23"; > + function = "qup11"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi9_data_clk: qup-spi9-data-clk { > + pins = "gpio22", "gpio23", "gpio24"; > + function = "qup11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi9_cs: qup-spi9-cs { > + pins = "gpio25"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c10_data_clk: qup-i2c10-data-clk { > + pins = "gpio24", "gpio25"; > + function = "qup12"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi10_data_clk: qup-spi10-data-clk { > + pins = "gpio24", "gpio25", "gpio22"; > + function = "qup12"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi10_cs: qup-spi10-cs { > + pins = "gpio23"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c11_data_clk: qup-i2c11-data-clk { > + pins = "gpio26", "gpio27"; > + function = "qup13"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi11_data_clk: qup-spi11-data-clk { > + pins = "gpio26", "gpio27", "gpio28"; > + function = "qup13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi11_cs: qup-spi11-cs { > + pins = "gpio29"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c12_data_clk: qup-i2c12-data-clk { > + pins = "gpio28", "gpio29"; > + function = "qup14"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi12_data_clk: qup-spi12-data-clk { > + pins = "gpio28", "gpio29", "gpio26"; > + function = "qup14"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi12_cs: qup-spi12-cs { > + pins = "gpio27"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c13_data_clk: qup-i2c13-data-clk { > + pins = "gpio30", "gpio31"; > + function = "qup15"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi13_data_clk: qup-spi13-data-clk { > + pins = "gpio30", "gpio31", "gpio32"; > + function = "qup15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi13_cs: qup-spi13-cs { > + pins = "gpio33"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart13_default: qup-uart13-default { > + pins = "gpio30", "gpio31", "gpio32", "gpio33"; > + function = "qup15"; > + }; > + > + qup_i2c14_data_clk: qup-i2c14-data-clk { > + pins = "gpio34", "gpio35"; > + function = "qup16"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi14_data_clk: qup-spi14-data-clk { > + pins = "gpio34", "gpio35", "gpio36"; > + function = "qup16"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi14_cs: qup-spi14-cs { > + pins = "gpio37", "gpio38"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c15_data_clk: qup-i2c15-data-clk { > + pins = "gpio40", "gpio41"; > + function = "qup17"; > + drive-strength = <2>; > + bias-pulll-up; > + }; > + > + qup_spi15_data_clk: qup-spi15-data-clk { > + pins = "gpio40", "gpio41", "gpio30"; > + function = "qup17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi15_cs: qup-spi15-cs { > + pins = "gpio31"; > + drive-strength = <6>; > + bias-disable; > + }; > + }; > + > + apps_smmu: apps-smmu@15000000 { > + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", > + "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + intc: interrupt-controller@17200000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + timer@17420000 { > + compatible = "arm,armv7-timer-mem"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + reg = <0x0 0x17420000 0x0 0x1000>; > + clock-frequency = <19200000>; > + > + frame@17421000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17421000 0x0 0x1000>, > + <0x0 0x17422000 0x0 0x1000>; > + }; > + > + frame@17423000 { > + frame-number = <1>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17423000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17425000 { > + frame-number = <2>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17425000 0x0 0x1000>, > + <0x0 0x17426000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17427000 { > + frame-number = <3>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17427000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@17429000 { > + frame-number = <4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x17429000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742b000 { > + frame-number = <5>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x1742b000 0x0 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742d000 { > + frame-number = <6>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x0 0x1742d000 0x0 0x1000>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@17a00000 { > + label = "apps_rsc"; > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x17a00000 0x0 0x10000>, > + <0x0 0x17a10000 0x0 0x10000>, > + <0x0 0x17a20000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 0>; > + > + apps_bcm_voter: bcm_voter { > + compatible = "qcom,bcm-voter"; > + }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board>; > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp1 { > + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; > + }; > + > + rpmhpd_opp_min_svs: opp2 { > + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; > + }; > + > + rpmhpd_opp_low_svs: opp3 { > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + }; > + > + rpmhpd_opp_svs: opp4 { > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + }; > + > + rpmhpd_opp_svs_l1: opp5 { > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; > + > + rpmhpd_opp_nom: opp6 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + }; > + > + rpmhpd_opp_nom_l1: opp7 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + }; > + > + rpmhpd_opp_nom_l2: opp8 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; > + }; > + > + rpmhpd_opp_turbo: opp9 { > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; > + }; > + > + rpmhpd_opp_turbo_l1: opp10 { > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; > + }; > + }; > + }; > + }; > + > + cpufreq_hw: cpufreq@17d91000 { > + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", > + "qcom,cpufreq-epss"; > + reg = <0x0 0x17d91000 0x0 0x1000>; > + reg-names = "freq-domain0"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dcvsh-irq-0"; > + #freq-domain-cells = <1>; > + }; > + > + gem_noc: interconnect@19100000 { > + reg = <0x0 0x19100000 0x0 0xB8080>; > + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; > + #interconnect-cells = <1>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + arch_timer: timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <19200000>; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi > new file mode 100644 > index 000000000000..074fe126e85e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "qdu1000.dtsi" > + > +&reserved_memory { > + /delete-node/ memory@a0000000; > + /delete-node/ memory@b9600000; > + /delete-node/ memory@c0000000; > + > + oem_tenx_mem: memory@a0000000 { > + no-map; > + reg = <0x0 0xa0000000 0x0 0x6400000>; > + }; > + > + mpss_diag_buffer_mem: memory@aea00000 { > + no-map; > + reg = <0x0 0xaea00000 0x0 0x6400000>; > + }; > + > + tenx_q6_buffer_mem: memory@b4e00000 { > + no-map; > + reg = <0x0 0xb4e00000 0x0 0x3200000>; > + }; > +}; > -- > 2.38.0 ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-24 0:53 ` Richard Acayan @ 2022-10-24 17:10 ` Melody Olvera 2022-10-24 22:28 ` Richard Acayan 0 siblings, 1 reply; 28+ messages in thread From: Melody Olvera @ 2022-10-24 17:10 UTC (permalink / raw) To: Richard Acayan, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/23/2022 5:53 PM, Richard Acayan wrote: >> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >> to boot to shell with console on these SoCs. >> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >> 2 files changed, 1673 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> new file mode 100644 >> index 000000000000..777734b30f56 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -0,0 +1,1646 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >> +#include <dt-bindings/clock/qcom,rpmh.h> >> +#include <dt-bindings/dma/qcom-gpi.h> >> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >> +#include <dt-bindings/power/qcom-rpmpd.h> >> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + chosen: chosen { }; >> + >> + clocks { >> + xo_board: xo-board { >> + compatible = "fixed-clock"; >> + clock-frequency = <19200000>; >> + clock-output-names = "xo_board"; >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <32000>; >> + #clock-cells = <0>; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + CPU0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + power-domain-names = "psci"; >> + power-domains = <&CPU_PD0>; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_0>; >> + L2_0: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + L3_0: l3-cache { >> + compatible = "cache"; >> + }; >> + }; >> + }; >> + >> + CPU1: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD1>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_100>; >> + L2_100: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + >> + }; >> + >> + CPU2: cpu@200 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x200>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD2>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_200>; >> + L2_200: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + }; >> + >> + CPU3: cpu@300 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a55"; >> + reg = <0x0 0x300>; >> + enable-method = "psci"; >> + power-domains = <&CPU_PD3>; >> + power-domain-names = "psci"; >> + qcom,freq-domains = <&cpufreq_hw 0>; >> + next-level-cache = <&L2_300>; >> + L2_300: l2-cache { >> + compatible = "cache"; >> + next-level-cache = <&L3_0>; >> + }; >> + >> + }; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&CPU0>; >> + }; >> + >> + core1 { >> + cpu = <&CPU1>; >> + }; >> + >> + core2 { >> + cpu = <&CPU2>; >> + }; >> + >> + core3 { >> + cpu = <&CPU3>; >> + }; >> + }; >> + }; >> + }; >> + >> + idle-states { >> + entry-method = "psci"; >> + >> + CPU_OFF: cpu-sleep-0 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "rail-pc"; >> + entry-latency-us = <274>; >> + exit-latency-us = <480>; >> + min-residency-us = <3934>; >> + arm,psci-suspend-param = <0x40000004>; >> + local-timer-stop; >> + }; >> + }; >> + >> + domain-idle-states { >> + CLUSTER_SLEEP_0: cluster-sleep-0 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "cluster-l3-off"; >> + entry-latency-us = <584>; >> + exit-latency-us = <2332>; >> + min-residency-us = <6118>; >> + arm,psci-suspend-param = <0x41000044>; >> + }; >> + >> + CLUSTER_SLEEP_1: cluster-sleep-1 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "cluster-power-collapse"; >> + entry-latency-us = <2893>; >> + exit-latency-us = <4023>; >> + min-residency-us = <9987>; >> + arm,psci-suspend-param = <0x41003344>; >> + }; >> + }; >> + >> + firmware { >> + qcom_scm { >> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >> + #reset-cells = <1>; >> + }; >> + }; >> + >> + clk_virt: interconnect-0 { >> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + mc_virt: interconnect-1 { >> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + memory@80000000 { >> + device_type = "memory"; >> + /* We expect the bootloader to fill in the size */ >> + reg = <0x0 0x80000000 0x0 0x0>; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + >> + CPU_PD0: cpu-pd0 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD1: cpu-pd1 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD2: cpu-pd2 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CPU_PD3: cpu-pd3 { >> + #power-domain-cells = <0>; >> + power-domains = <&CLUSTER_PD>; >> + domain-idle-states = <&CPU_OFF>; >> + }; >> + >> + CLUSTER_PD: cluster-pd { >> + #power-domain-cells = <0>; >> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >> + }; >> + }; >> + >> + reserved_memory: reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + hyp_mem: memory@80000000 { >> + no-map; >> + reg = <0x0 0x80000000 0x0 0x600000>; >> + }; >> + >> + xbl_dt_log_mem: memory@80600000 { >> + no-map; >> + reg = <0x0 0x80600000 0x0 0x40000>; >> + }; >> + >> + xbl_ramdump_mem: memory@80640000 { >> + no-map; >> + reg = <0x0 0x80640000 0x0 0x1c0000>; >> + }; >> + >> + aop_image_mem: memory@80800000 { >> + no-map; >> + reg = <0x0 0x80800000 0x0 0x60000>; >> + }; >> + >> + aop_cmd_db_mem: memory@80860000 { >> + compatible = "qcom,cmd-db"; >> + no-map; >> + reg = <0x0 0x80860000 0x0 0x20000>; >> + }; >> + >> + aop_config_mem: memory@80880000 { >> + no-map; >> + reg = <0x0 0x80880000 0x0 0x20000>; >> + }; >> + >> + tme_crash_dump_mem: memory@808a0000 { >> + no-map; >> + reg = <0x0 0x808a0000 0x0 0x40000>; >> + }; >> + >> + tme_log_mem: memory@808e0000 { >> + no-map; >> + reg = <0x0 0x808e0000 0x0 0x4000>; >> + }; >> + >> + uefi_log_mem: memory@808e4000 { >> + no-map; >> + reg = <0x0 0x808e4000 0x0 0x10000>; >> + }; >> + >> + /* secdata region can be reused by apps */ >> + >> + smem_mem: memory@80900000 { >> + compatible = "qcom,smem"; >> + no-map; >> + reg = <0x0 0x80900000 0x0 0x200000>; >> + hwlocks = <&tcsr_mutex 3>; >> + }; >> + >> + cpucp_fw_mem: memory@80b00000 { >> + no-map; >> + reg = <0x0 0x80b00000 0x0 0x100000>; >> + }; >> + >> + xbl_sc_mem: memory@80c00000 { >> + no-map; >> + reg = <0x0 0x80c00000 0x0 0x40000>; >> + }; >> + >> + /* uefi region can be reused by apps */ >> + >> + tz_stat_mem: memory@81d00000 { >> + no-map; >> + reg = <0x0 0x81d00000 0x0 0x100000>; >> + }; >> + >> + tags_mem: memory@81e00000 { >> + no-map; >> + reg = <0x0 0x81e00000 0x0 0x500000>; >> + }; >> + >> + qtee_mem: memory@82300000 { >> + no-map; >> + reg = <0x0 0x82300000 0x0 0x500000>; >> + }; >> + >> + ta_mem: memory@82800000 { >> + no-map; >> + reg = <0x0 0x82800000 0x0 0xa00000>; >> + }; >> + >> + fs1_mem: memory@83200000 { >> + no-map; >> + reg = <0x0 0x83200000 0x0 0x400000>; >> + }; >> + >> + fs2_mem: memory@83600000 { >> + no-map; >> + reg = <0x0 0x83600000 0x0 0x400000>; >> + }; >> + >> + fs3_mem: memory@83a00000 { >> + no-map; >> + reg = <0x0 0x83a00000 0x0 0x400000>; >> + }; >> + >> + /* Linux kernel image is loaded at 0x83e00000 */ >> + >> + ipa_fw_mem: memory@8be00000 { >> + no-map; >> + reg = <0x0 0x8be00000 0x0 0x10000>; >> + }; >> + >> + ipa_gsi_mem: memory@8be10000 { >> + no-map; >> + reg = <0x0 0x8be10000 0x0 0x14000>; >> + }; >> + >> + mpss_mem: memory@8c000000 { >> + no-map; >> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >> + }; >> + >> + q6_mpss_dtb_mem: memory@9ec00000 { >> + no-map; >> + reg = <0x0 0x9ec00000 0x0 0x80000>; >> + }; >> + >> + tenx_mem: memory@a0000000 { >> + no-map; >> + reg = <0x0 0xa0000000 0x0 0x19600000>; >> + }; >> + >> + oem_tenx_mem: memory@b9600000 { >> + no-map; >> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >> + }; >> + >> + tenx_q6_buffer_mem: memory@c0000000 { >> + no-map; >> + reg = <0x0 0xc0000000 0x0 0x3200000>; >> + }; >> + >> + ipa_buffer_mem: memory@c3200000 { >> + no-map; >> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >> + }; >> + }; >> + >> + soc: soc@0 { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0 0 0 0 0x10 0>; >> + dma-ranges = <0 0 0 0 0x10 0>; >> + compatible = "simple-bus"; >> + >> + gcc: clock-controller@80000 { >> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >> + reg = <0x0 0x80000 0x0 0x1f4200>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >> + clock-names = "bi_tcxo", "sleep_clk"; >> + }; >> + >> + gpi_dma0: dma-controller@900000 { >> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; > This won't work if you drop series [1]. It won't just fail the schema checks, > but it would also fail to probe because the driver doesn't recognise it. > > I think you were told to rebase on [2], and didn't change your own series > because it only applied to ee_offset = 0x0. There is another series [3] that > was sent to you, meant for ee_offset = 0x10000. You're expected to change your > patches (in both series you sent) based on what was changed in that series. > > [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ > [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ > [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ Hi Richard; I was aware of this feedback and was planning to make that change in v3. PS [1] will be dropped and this compatible will be modified similar to PS [3]; that was what I meant by my final comment on [1]. > >> + #dma-cells = <5>; >> + reg = <0x0 0x900000 0x0 0x60000>; >> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <12>; >> + dma-channel-mask = <0x3f>; >> + iommus = <&apps_smmu 0xf6 0x0>; >> + status = "ok"; >> + }; >> + >> + qupv3_id_0: geniqup@9c0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x9c0000 0x0 0x2000>; >> + clock-names = "m-ahb", "s-ahb"; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + iommus = <&apps_smmu 0xe3 0x0>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >> + &clk_virt SLAVE_QUP_CORE_0 0>; >> + interconnect-names = "qup-core"; >> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >> + qcom,iommu-geometry = <0x40000000 0x10000000>; >> + qcom,iommu-dma = "fastmap"; >> + dma-coherent; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + uart0: serial@980000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0x980000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart0_default>; >> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@984000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x984000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c1_data_clk>; >> + dmas = <&gpi_dma0 0 1 3 64 0>, >> + <&gpi_dma0 1 1 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi1: spi@984000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x984000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >> + dmas = <&gpi_dma0 0 1 1 64 0>, >> + <&gpi_dma0 1 1 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@988000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x988000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c2_data_clk>; >> + dmas = <&gpi_dma0 0 2 3 64 0>, >> + <&gpi_dma0 1 2 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi2: spi@988000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x988000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >> + dmas = <&gpi_dma0 0 2 1 64 0>, >> + <&gpi_dma0 1 2 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@98c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x98c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c3_data_clk>; >> + dmas = <&gpi_dma0 0 3 3 64 0>, >> + <&gpi_dma0 1 3 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi3: spi@98c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x98c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >> + dmas = <&gpi_dma0 0 3 1 64 0>, >> + <&gpi_dma0 1 3 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@990000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x990000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c4_data_clk>; >> + dmas = <&gpi_dma0 0 4 3 64 0>, >> + <&gpi_dma0 1 4 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi4: spi@990000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x990000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >> + dmas = <&gpi_dma0 0 4 1 64 0>, >> + <&gpi_dma0 1 4 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c5: i2c@994000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x994000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c5_data_clk>; >> + dmas = <&gpi_dma0 0 5 3 64 0>, >> + <&gpi_dma0 1 5 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi5: spi@994000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x994000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >> + dmas = <&gpi_dma0 0 5 1 64 0>, >> + <&gpi_dma0 1 5 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c6: i2c@998000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x998000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c6_data_clk>; >> + dmas = <&gpi_dma0 0 6 3 64 0>, >> + <&gpi_dma0 1 6 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi6: spi@998000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x998000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >> + dmas = <&gpi_dma0 0 6 1 64 0>, >> + <&gpi_dma0 1 6 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + uart7: serial@99c000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0x0 0x99c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + }; >> + >> + gpi_dma1: dma-controller@a00000 { >> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; > See above. > >> + #dma-cells = <5>; >> + reg = <0x0 0xa00000 0x0 0x60000>; >> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <12>; >> + dma-channel-mask = <0x3f>; >> + iommus = <&apps_smmu 0x116 0x0>; >> + status = "ok"; >> + }; >> + >> + qupv3_id_1: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0xac0000 0x0 0x2000>; >> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >> + iommus = <&apps_smmu 0x103 0x0>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clock-names = "m-ahb", "s-ahb"; >> + >> + ranges; >> + status = "disabled"; >> + >> + uart8: serial@a80000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0xa80000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart8_default>; >> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c9: i2c@a84000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa84000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c9_data_clk>; >> + dmas = <&gpi_dma1 0 1 3 64 0>, >> + <&gpi_dma1 1 1 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi9: spi@a84000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa84000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >> + dmas = <&gpi_dma1 0 1 1 64 0>, >> + <&gpi_dma1 1 1 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c10: i2c@a88000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa88000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c10_data_clk>; >> + dmas = <&gpi_dma1 0 2 3 64 0>, >> + <&gpi_dma1 1 2 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi10: spi@a88000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa88000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >> + dmas = <&gpi_dma1 0 2 1 64 0>, >> + <&gpi_dma1 1 2 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c11: i2c@a8c000 { >> + compatible = "qcom,i2c-geni"; >> + reg = <0x0 0xa8c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c11_data_clk>; >> + dmas = <&gpi_dma1 0 3 3 64 0>, >> + <&gpi_dma1 1 3 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi11: spi@a8c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa8c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >> + dmas = <&gpi_dma1 0 3 1 64 0>, >> + <&gpi_dma1 1 3 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c12: i2c@a90000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa90000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c12_data_clk>; >> + dmas = <&gpi_dma1 0 4 3 64 0>, >> + <&gpi_dma1 1 4 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi12: spi@a90000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa90000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >> + dmas = <&gpi_dma1 0 4 1 64 0>, >> + <&gpi_dma1 1 4 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c13: i2c@a94000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c13_data_clk>; >> + dmas = <&gpi_dma1 0 5 3 64 0>, >> + <&gpi_dma1 1 5 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + uart13: serial@a94000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_uart13_default>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi13: spi@a94000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa94000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >> + dmas = <&gpi_dma1 0 5 1 64 0>, >> + <&gpi_dma1 1 5 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c14: i2c@a98000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa98000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c14_data_clk>; >> + dmas = <&gpi_dma1 0 6 3 64 0>, >> + <&gpi_dma1 1 6 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi14: spi@a98000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa98000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >> + dmas = <&gpi_dma1 0 6 1 64 0>, >> + <&gpi_dma1 1 6 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + >> + i2c15: i2c@a9c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0xa9c000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_i2c15_data_clk>; >> + dmas = <&gpi_dma1 0 7 3 64 0>, >> + <&gpi_dma1 1 7 3 64 0>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi15: spi@a9c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0xa9c000 0x0 0x4000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >> + interconnects = >> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >> + dmas = <&gpi_dma1 0 7 1 64 0>, >> + <&gpi_dma1 1 7 1 64 0>; >> + dma-names = "tx", "rx"; >> + status = "disabled"; >> + }; >> + }; >> + >> + system_noc: interconnect@1640000 { >> + reg = <0x0 0x1640000 0x0 0x45080>; >> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >> + #interconnect-cells = <1>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + tcsr_mutex: hwlock@1f40000 { >> + compatible = "qcom,tcsr-mutex"; >> + reg = <0x0 0x1f40000 0x0 0x20000>; >> + #hwlock-cells = <1>; >> + }; >> + >> + pdc: interrupt-controller@b220000 { >> + compatible = "qcom,pdc"; >> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >> + <94 609 31>, <125 63 1>; >> + #interrupt-cells = <2>; >> + interrupt-parent = <&intc>; >> + interrupt-controller; >> + }; >> + >> + spmi_bus: spmi@c400000 { >> + compatible = "qcom,spmi-pmic-arb"; >> + reg = <0x0 0xc400000 0x0 0x3000>, >> + <0x0 0xc500000 0x0 0x400000>, >> + <0x0 0xc440000 0x0 0x80000>, >> + <0x0 0xc4c0000 0x0 0x10000>, >> + <0x0 0xc42d000 0x0 0x4000>; >> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >> + interrupt-names = "periph_irq"; >> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >> + qcom,ee = <0>; >> + qcom,channel = <0>; >> + #address-cells = <2>; >> + #size-cells = <0>; >> + interrupt-controller; >> + #interrupt-cells = <4>; >> + }; >> + >> + tlmm: pinctrl@f000000 { >> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >> + reg = <0x0 0xf000000 0x0 0x1000000>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + gpio-ranges = <&tlmm 0 0 151>; >> + wakeup-parent = <&pdc>; >> + >> + qup_uart0_default: qup-uart0-default-state { >> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >> + function = "qup00"; >> + }; >> + >> + qup_i2c1_data_clk: qup-i2c1-data-clk { >> + pins = "gpio10", "gpio11"; >> + function = "qup01"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi1_data_clk: qup-spi1-data-clk { >> + pins = "gpio10", "gpio11", "gpio12"; >> + function = "qup01"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi1_cs: qup-spi1-cs { >> + pins = "gpio13"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c2_data_clk: qup-i2c2-data-clk { >> + pins = "gpio12", "gpio13"; >> + function = "qup02"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi2_data_clk: qup-spi2-data-clk { >> + pins = "gpio12", "gpio13", "gpio10"; >> + function = "qup02"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi2_cs: qup-spi2-cs { >> + pins = "gpio11"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c3_data_clk: qup-i2c3-data-clk { >> + pins = "gpio14", "gpio15"; >> + function = "qup03"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi3_data_clk: qup-spi3-data-clk { >> + pins = "gpio14", "gpio15", "gpio16"; >> + function = "qup03"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi3_cs: qup-spi3-cs { >> + pins = "gpio17"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c4_data_clk: qup-i2c4-data-clk { >> + pins = "gpio16", "gpio17"; >> + function = "qup04"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi4_data_clk: qup-spi4-data-clk { >> + pins = "gpio16", "gpio17", "gpio14"; >> + function = "qup04"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi4_cs: qup-spi4-cs { >> + pins = "gpio15"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c5_data_clk: qup-i2c5-data-clk { >> + pins = "gpio130", "gpio131"; >> + function = "qup05"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi5_data_clk: qup-spi5-data-clk { >> + pins = "gpio130", "gpio131", "gpio132"; >> + function = "qup05"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi5_cs: qup-spi5-cs { >> + pins = "gpio133"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c6_data_clk: qup-i2c6-data-clk { >> + pins = "gpio132", "gpio133"; >> + function = "qup06"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi6_data_clk: qup-spi6-data-clk { >> + pins = "gpio132", "gpio133", "gpio130"; >> + function = "qup06"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi6_cs: qup-spi6-cs { >> + pins = "gpio131"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_uart7_rx: qup-uart7-rx { >> + pins = "gpio135"; >> + function = "qup07"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart7_tx: qup-uart7-tx { >> + pins = "gpio134"; >> + function = "qup07"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart8_default: qup-uart8-default { >> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >> + function = "qup10"; >> + }; >> + >> + qup_i2c9_data_clk: qup-i2c9-data-clk { >> + pins = "gpio22", "gpio23"; >> + function = "qup11"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi9_data_clk: qup-spi9-data-clk { >> + pins = "gpio22", "gpio23", "gpio24"; >> + function = "qup11"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi9_cs: qup-spi9-cs { >> + pins = "gpio25"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c10_data_clk: qup-i2c10-data-clk { >> + pins = "gpio24", "gpio25"; >> + function = "qup12"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi10_data_clk: qup-spi10-data-clk { >> + pins = "gpio24", "gpio25", "gpio22"; >> + function = "qup12"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi10_cs: qup-spi10-cs { >> + pins = "gpio23"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c11_data_clk: qup-i2c11-data-clk { >> + pins = "gpio26", "gpio27"; >> + function = "qup13"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi11_data_clk: qup-spi11-data-clk { >> + pins = "gpio26", "gpio27", "gpio28"; >> + function = "qup13"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi11_cs: qup-spi11-cs { >> + pins = "gpio29"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c12_data_clk: qup-i2c12-data-clk { >> + pins = "gpio28", "gpio29"; >> + function = "qup14"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi12_data_clk: qup-spi12-data-clk { >> + pins = "gpio28", "gpio29", "gpio26"; >> + function = "qup14"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi12_cs: qup-spi12-cs { >> + pins = "gpio27"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c13_data_clk: qup-i2c13-data-clk { >> + pins = "gpio30", "gpio31"; >> + function = "qup15"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi13_data_clk: qup-spi13-data-clk { >> + pins = "gpio30", "gpio31", "gpio32"; >> + function = "qup15"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi13_cs: qup-spi13-cs { >> + pins = "gpio33"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_uart13_default: qup-uart13-default { >> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >> + function = "qup15"; >> + }; >> + >> + qup_i2c14_data_clk: qup-i2c14-data-clk { >> + pins = "gpio34", "gpio35"; >> + function = "qup16"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi14_data_clk: qup-spi14-data-clk { >> + pins = "gpio34", "gpio35", "gpio36"; >> + function = "qup16"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi14_cs: qup-spi14-cs { >> + pins = "gpio37", "gpio38"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_i2c15_data_clk: qup-i2c15-data-clk { >> + pins = "gpio40", "gpio41"; >> + function = "qup17"; >> + drive-strength = <2>; >> + bias-pulll-up; >> + }; >> + >> + qup_spi15_data_clk: qup-spi15-data-clk { >> + pins = "gpio40", "gpio41", "gpio30"; >> + function = "qup17"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi15_cs: qup-spi15-cs { >> + pins = "gpio31"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + }; >> + >> + apps_smmu: apps-smmu@15000000 { >> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >> + "arm,mmu-500"; >> + reg = <0x0 0x15000000 0x0 0x100000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <2>; >> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + intc: interrupt-controller@17200000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x20000>; >> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + timer@17420000 { >> + compatible = "arm,armv7-timer-mem"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + reg = <0x0 0x17420000 0x0 0x1000>; >> + clock-frequency = <19200000>; >> + >> + frame@17421000 { >> + frame-number = <0>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17421000 0x0 0x1000>, >> + <0x0 0x17422000 0x0 0x1000>; >> + }; >> + >> + frame@17423000 { >> + frame-number = <1>; >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17423000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17425000 { >> + frame-number = <2>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17425000 0x0 0x1000>, >> + <0x0 0x17426000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17427000 { >> + frame-number = <3>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17427000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@17429000 { >> + frame-number = <4>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x17429000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@1742b000 { >> + frame-number = <5>; >> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x1742b000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + >> + frame@1742d000 { >> + frame-number = <6>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + reg = <0x0 0x1742d000 0x0 0x1000>; >> + status = "disabled"; >> + }; >> + }; >> + >> + apps_rsc: rsc@17a00000 { >> + label = "apps_rsc"; >> + compatible = "qcom,rpmh-rsc"; >> + reg = <0x0 0x17a00000 0x0 0x10000>, >> + <0x0 0x17a10000 0x0 0x10000>, >> + <0x0 0x17a20000 0x0 0x10000>; >> + reg-names = "drv-0", "drv-1", "drv-2"; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >> + qcom,tcs-offset = <0xd00>; >> + qcom,drv-id = <2>; >> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >> + >> + apps_bcm_voter: bcm_voter { >> + compatible = "qcom,bcm-voter"; >> + }; >> + >> + rpmhcc: clock-controller { >> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; >> + #clock-cells = <1>; >> + clock-names = "xo"; >> + clocks = <&xo_board>; >> + }; >> + >> + rpmhpd: power-controller { >> + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; >> + #power-domain-cells = <1>; >> + operating-points-v2 = <&rpmhpd_opp_table>; >> + >> + rpmhpd_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + rpmhpd_opp_ret: opp1 { >> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; >> + }; >> + >> + rpmhpd_opp_min_svs: opp2 { >> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >> + }; >> + >> + rpmhpd_opp_low_svs: opp3 { >> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >> + }; >> + >> + rpmhpd_opp_svs: opp4 { >> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >> + }; >> + >> + rpmhpd_opp_svs_l1: opp5 { >> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >> + }; >> + >> + rpmhpd_opp_nom: opp6 { >> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >> + }; >> + >> + rpmhpd_opp_nom_l1: opp7 { >> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >> + }; >> + >> + rpmhpd_opp_nom_l2: opp8 { >> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; >> + }; >> + >> + rpmhpd_opp_turbo: opp9 { >> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >> + }; >> + >> + rpmhpd_opp_turbo_l1: opp10 { >> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >> + }; >> + }; >> + }; >> + }; >> + >> + cpufreq_hw: cpufreq@17d91000 { >> + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", >> + "qcom,cpufreq-epss"; >> + reg = <0x0 0x17d91000 0x0 0x1000>; >> + reg-names = "freq-domain0"; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "dcvsh-irq-0"; >> + #freq-domain-cells = <1>; >> + }; >> + >> + gem_noc: interconnect@19100000 { >> + reg = <0x0 0x19100000 0x0 0xB8080>; >> + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; >> + #interconnect-cells = <1>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + arch_timer: timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >> + clock-frequency = <19200000>; >> + }; >> + }; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi >> new file mode 100644 >> index 000000000000..074fe126e85e >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi >> @@ -0,0 +1,27 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include "qdu1000.dtsi" >> + >> +&reserved_memory { >> + /delete-node/ memory@a0000000; >> + /delete-node/ memory@b9600000; >> + /delete-node/ memory@c0000000; >> + >> + oem_tenx_mem: memory@a0000000 { >> + no-map; >> + reg = <0x0 0xa0000000 0x0 0x6400000>; >> + }; >> + >> + mpss_diag_buffer_mem: memory@aea00000 { >> + no-map; >> + reg = <0x0 0xaea00000 0x0 0x6400000>; >> + }; >> + >> + tenx_q6_buffer_mem: memory@b4e00000 { >> + no-map; >> + reg = <0x0 0xb4e00000 0x0 0x3200000>; >> + }; >> +}; >> -- >> 2.38.0 Thanks, Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-24 17:10 ` Melody Olvera @ 2022-10-24 22:28 ` Richard Acayan 2022-10-24 22:31 ` Melody Olvera 0 siblings, 1 reply; 28+ messages in thread From: Richard Acayan @ 2022-10-24 22:28 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel > On 10/23/2022 5:53 PM, Richard Acayan wrote: >>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>> to boot to shell with console on these SoCs. >>> >>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>> 2 files changed, 1673 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> new file mode 100644 >>> index 000000000000..777734b30f56 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>> @@ -0,0 +1,1646 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >>> +#include <dt-bindings/clock/qcom,rpmh.h> >>> +#include <dt-bindings/dma/qcom-gpi.h> >>> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >>> +#include <dt-bindings/power/qcom-rpmpd.h> >>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >>> + >>> +/ { >>> + interrupt-parent = <&intc>; >>> + >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + chosen: chosen { }; >>> + >>> + clocks { >>> + xo_board: xo-board { >>> + compatible = "fixed-clock"; >>> + clock-frequency = <19200000>; >>> + clock-output-names = "xo_board"; >>> + #clock-cells = <0>; >>> + }; >>> + >>> + sleep_clk: sleep-clk { >>> + compatible = "fixed-clock"; >>> + clock-frequency = <32000>; >>> + #clock-cells = <0>; >>> + }; >>> + }; >>> + >>> + cpus { >>> + #address-cells = <2>; >>> + #size-cells = <0>; >>> + >>> + CPU0: cpu@0 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55"; >>> + reg = <0x0 0x0>; >>> + enable-method = "psci"; >>> + power-domain-names = "psci"; >>> + power-domains = <&CPU_PD0>; >>> + qcom,freq-domains = <&cpufreq_hw 0>; >>> + next-level-cache = <&L2_0>; >>> + L2_0: l2-cache { >>> + compatible = "cache"; >>> + next-level-cache = <&L3_0>; >>> + L3_0: l3-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + }; >>> + >>> + CPU1: cpu@100 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55"; >>> + reg = <0x0 0x100>; >>> + enable-method = "psci"; >>> + power-domains = <&CPU_PD1>; >>> + power-domain-names = "psci"; >>> + qcom,freq-domains = <&cpufreq_hw 0>; >>> + next-level-cache = <&L2_100>; >>> + L2_100: l2-cache { >>> + compatible = "cache"; >>> + next-level-cache = <&L3_0>; >>> + }; >>> + >>> + }; >>> + >>> + CPU2: cpu@200 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55"; >>> + reg = <0x0 0x200>; >>> + enable-method = "psci"; >>> + power-domains = <&CPU_PD2>; >>> + power-domain-names = "psci"; >>> + qcom,freq-domains = <&cpufreq_hw 0>; >>> + next-level-cache = <&L2_200>; >>> + L2_200: l2-cache { >>> + compatible = "cache"; >>> + next-level-cache = <&L3_0>; >>> + }; >>> + }; >>> + >>> + CPU3: cpu@300 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55"; >>> + reg = <0x0 0x300>; >>> + enable-method = "psci"; >>> + power-domains = <&CPU_PD3>; >>> + power-domain-names = "psci"; >>> + qcom,freq-domains = <&cpufreq_hw 0>; >>> + next-level-cache = <&L2_300>; >>> + L2_300: l2-cache { >>> + compatible = "cache"; >>> + next-level-cache = <&L3_0>; >>> + }; >>> + >>> + }; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&CPU0>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&CPU1>; >>> + }; >>> + >>> + core2 { >>> + cpu = <&CPU2>; >>> + }; >>> + >>> + core3 { >>> + cpu = <&CPU3>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + idle-states { >>> + entry-method = "psci"; >>> + >>> + CPU_OFF: cpu-sleep-0 { >>> + compatible = "arm,idle-state"; >>> + idle-state-name = "rail-pc"; >>> + entry-latency-us = <274>; >>> + exit-latency-us = <480>; >>> + min-residency-us = <3934>; >>> + arm,psci-suspend-param = <0x40000004>; >>> + local-timer-stop; >>> + }; >>> + }; >>> + >>> + domain-idle-states { >>> + CLUSTER_SLEEP_0: cluster-sleep-0 { >>> + compatible = "domain-idle-state"; >>> + idle-state-name = "cluster-l3-off"; >>> + entry-latency-us = <584>; >>> + exit-latency-us = <2332>; >>> + min-residency-us = <6118>; >>> + arm,psci-suspend-param = <0x41000044>; >>> + }; >>> + >>> + CLUSTER_SLEEP_1: cluster-sleep-1 { >>> + compatible = "domain-idle-state"; >>> + idle-state-name = "cluster-power-collapse"; >>> + entry-latency-us = <2893>; >>> + exit-latency-us = <4023>; >>> + min-residency-us = <9987>; >>> + arm,psci-suspend-param = <0x41003344>; >>> + }; >>> + }; >>> + >>> + firmware { >>> + qcom_scm { >>> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >>> + #reset-cells = <1>; >>> + }; >>> + }; >>> + >>> + clk_virt: interconnect-0 { >>> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >>> + #interconnect-cells = <2>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + }; >>> + >>> + mc_virt: interconnect-1 { >>> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >>> + #interconnect-cells = <2>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + }; >>> + >>> + memory@80000000 { >>> + device_type = "memory"; >>> + /* We expect the bootloader to fill in the size */ >>> + reg = <0x0 0x80000000 0x0 0x0>; >>> + }; >>> + >>> + pmu { >>> + compatible = "arm,armv8-pmuv3"; >>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + >>> + psci { >>> + compatible = "arm,psci-1.0"; >>> + method = "smc"; >>> + >>> + CPU_PD0: cpu-pd0 { >>> + #power-domain-cells = <0>; >>> + power-domains = <&CLUSTER_PD>; >>> + domain-idle-states = <&CPU_OFF>; >>> + }; >>> + >>> + CPU_PD1: cpu-pd1 { >>> + #power-domain-cells = <0>; >>> + power-domains = <&CLUSTER_PD>; >>> + domain-idle-states = <&CPU_OFF>; >>> + }; >>> + >>> + CPU_PD2: cpu-pd2 { >>> + #power-domain-cells = <0>; >>> + power-domains = <&CLUSTER_PD>; >>> + domain-idle-states = <&CPU_OFF>; >>> + }; >>> + >>> + CPU_PD3: cpu-pd3 { >>> + #power-domain-cells = <0>; >>> + power-domains = <&CLUSTER_PD>; >>> + domain-idle-states = <&CPU_OFF>; >>> + }; >>> + >>> + CLUSTER_PD: cluster-pd { >>> + #power-domain-cells = <0>; >>> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >>> + }; >>> + }; >>> + >>> + reserved_memory: reserved-memory { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + >>> + hyp_mem: memory@80000000 { >>> + no-map; >>> + reg = <0x0 0x80000000 0x0 0x600000>; >>> + }; >>> + >>> + xbl_dt_log_mem: memory@80600000 { >>> + no-map; >>> + reg = <0x0 0x80600000 0x0 0x40000>; >>> + }; >>> + >>> + xbl_ramdump_mem: memory@80640000 { >>> + no-map; >>> + reg = <0x0 0x80640000 0x0 0x1c0000>; >>> + }; >>> + >>> + aop_image_mem: memory@80800000 { >>> + no-map; >>> + reg = <0x0 0x80800000 0x0 0x60000>; >>> + }; >>> + >>> + aop_cmd_db_mem: memory@80860000 { >>> + compatible = "qcom,cmd-db"; >>> + no-map; >>> + reg = <0x0 0x80860000 0x0 0x20000>; >>> + }; >>> + >>> + aop_config_mem: memory@80880000 { >>> + no-map; >>> + reg = <0x0 0x80880000 0x0 0x20000>; >>> + }; >>> + >>> + tme_crash_dump_mem: memory@808a0000 { >>> + no-map; >>> + reg = <0x0 0x808a0000 0x0 0x40000>; >>> + }; >>> + >>> + tme_log_mem: memory@808e0000 { >>> + no-map; >>> + reg = <0x0 0x808e0000 0x0 0x4000>; >>> + }; >>> + >>> + uefi_log_mem: memory@808e4000 { >>> + no-map; >>> + reg = <0x0 0x808e4000 0x0 0x10000>; >>> + }; >>> + >>> + /* secdata region can be reused by apps */ >>> + >>> + smem_mem: memory@80900000 { >>> + compatible = "qcom,smem"; >>> + no-map; >>> + reg = <0x0 0x80900000 0x0 0x200000>; >>> + hwlocks = <&tcsr_mutex 3>; >>> + }; >>> + >>> + cpucp_fw_mem: memory@80b00000 { >>> + no-map; >>> + reg = <0x0 0x80b00000 0x0 0x100000>; >>> + }; >>> + >>> + xbl_sc_mem: memory@80c00000 { >>> + no-map; >>> + reg = <0x0 0x80c00000 0x0 0x40000>; >>> + }; >>> + >>> + /* uefi region can be reused by apps */ >>> + >>> + tz_stat_mem: memory@81d00000 { >>> + no-map; >>> + reg = <0x0 0x81d00000 0x0 0x100000>; >>> + }; >>> + >>> + tags_mem: memory@81e00000 { >>> + no-map; >>> + reg = <0x0 0x81e00000 0x0 0x500000>; >>> + }; >>> + >>> + qtee_mem: memory@82300000 { >>> + no-map; >>> + reg = <0x0 0x82300000 0x0 0x500000>; >>> + }; >>> + >>> + ta_mem: memory@82800000 { >>> + no-map; >>> + reg = <0x0 0x82800000 0x0 0xa00000>; >>> + }; >>> + >>> + fs1_mem: memory@83200000 { >>> + no-map; >>> + reg = <0x0 0x83200000 0x0 0x400000>; >>> + }; >>> + >>> + fs2_mem: memory@83600000 { >>> + no-map; >>> + reg = <0x0 0x83600000 0x0 0x400000>; >>> + }; >>> + >>> + fs3_mem: memory@83a00000 { >>> + no-map; >>> + reg = <0x0 0x83a00000 0x0 0x400000>; >>> + }; >>> + >>> + /* Linux kernel image is loaded at 0x83e00000 */ >>> + >>> + ipa_fw_mem: memory@8be00000 { >>> + no-map; >>> + reg = <0x0 0x8be00000 0x0 0x10000>; >>> + }; >>> + >>> + ipa_gsi_mem: memory@8be10000 { >>> + no-map; >>> + reg = <0x0 0x8be10000 0x0 0x14000>; >>> + }; >>> + >>> + mpss_mem: memory@8c000000 { >>> + no-map; >>> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >>> + }; >>> + >>> + q6_mpss_dtb_mem: memory@9ec00000 { >>> + no-map; >>> + reg = <0x0 0x9ec00000 0x0 0x80000>; >>> + }; >>> + >>> + tenx_mem: memory@a0000000 { >>> + no-map; >>> + reg = <0x0 0xa0000000 0x0 0x19600000>; >>> + }; >>> + >>> + oem_tenx_mem: memory@b9600000 { >>> + no-map; >>> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >>> + }; >>> + >>> + tenx_q6_buffer_mem: memory@c0000000 { >>> + no-map; >>> + reg = <0x0 0xc0000000 0x0 0x3200000>; >>> + }; >>> + >>> + ipa_buffer_mem: memory@c3200000 { >>> + no-map; >>> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >>> + }; >>> + }; >>> + >>> + soc: soc@0 { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges = <0 0 0 0 0x10 0>; >>> + dma-ranges = <0 0 0 0 0x10 0>; >>> + compatible = "simple-bus"; >>> + >>> + gcc: clock-controller@80000 { >>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >>> + reg = <0x0 0x80000 0x0 0x1f4200>; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >>> + clock-names = "bi_tcxo", "sleep_clk"; >>> + }; >>> + >>> + gpi_dma0: dma-controller@900000 { >>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >> This won't work if you drop series [1]. It won't just fail the schema checks, >> but it would also fail to probe because the driver doesn't recognise it. >> >> I think you were told to rebase on [2], and didn't change your own series >> because it only applied to ee_offset = 0x0. There is another series [3] that >> was sent to you, meant for ee_offset = 0x10000. You're expected to change your >> patches (in both series you sent) based on what was changed in that series. >> >> [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ >> [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ >> [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ > Hi Richard; I was aware of this feedback and was planning to make that change in v3. > PS [1] will be dropped and this compatible will be modified similar to PS [3]; that was > what I meant by my final comment on [1]. Ok, I should have checked the date. What about the schema patch? It might be helpful for the device tree cleanup efforts if you didn't add a compatible without adding a corresponding entry in the device tree bindings. I'm talking about updating this patch in particular: https://lore.kernel.org/linux-arm-msm/20221014221102.7445-2-quic_molvera@quicinc.com/ We still add compat strings in dt-bindings even when there is a fallback, because the schema is meant to specify every combination of compat strings found in the device trees. >> >>> + #dma-cells = <5>; >>> + reg = <0x0 0x900000 0x0 0x60000>; >>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >>> + dma-channels = <12>; >>> + dma-channel-mask = <0x3f>; >>> + iommus = <&apps_smmu 0xf6 0x0>; >>> + status = "ok"; >>> + }; >>> + >>> + qupv3_id_0: geniqup@9c0000 { >>> + compatible = "qcom,geni-se-qup"; >>> + reg = <0x0 0x9c0000 0x0 0x2000>; >>> + clock-names = "m-ahb", "s-ahb"; >>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>> + iommus = <&apps_smmu 0xe3 0x0>; >>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >>> + &clk_virt SLAVE_QUP_CORE_0 0>; >>> + interconnect-names = "qup-core"; >>> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >>> + qcom,iommu-geometry = <0x40000000 0x10000000>; >>> + qcom,iommu-dma = "fastmap"; >>> + dma-coherent; >>> + >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + status = "disabled"; >>> + >>> + uart0: serial@980000 { >>> + compatible = "qcom,geni-uart"; >>> + reg = <0x0 0x980000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_uart0_default>; >>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c1: i2c@984000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x984000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c1_data_clk>; >>> + dmas = <&gpi_dma0 0 1 3 64 0>, >>> + <&gpi_dma0 1 1 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi1: spi@984000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x984000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >>> + dmas = <&gpi_dma0 0 1 1 64 0>, >>> + <&gpi_dma0 1 1 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c2: i2c@988000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x988000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c2_data_clk>; >>> + dmas = <&gpi_dma0 0 2 3 64 0>, >>> + <&gpi_dma0 1 2 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi2: spi@988000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x988000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >>> + dmas = <&gpi_dma0 0 2 1 64 0>, >>> + <&gpi_dma0 1 2 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c3: i2c@98c000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x98c000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c3_data_clk>; >>> + dmas = <&gpi_dma0 0 3 3 64 0>, >>> + <&gpi_dma0 1 3 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi3: spi@98c000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x98c000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >>> + dmas = <&gpi_dma0 0 3 1 64 0>, >>> + <&gpi_dma0 1 3 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c4: i2c@990000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x990000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c4_data_clk>; >>> + dmas = <&gpi_dma0 0 4 3 64 0>, >>> + <&gpi_dma0 1 4 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi4: spi@990000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x990000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >>> + dmas = <&gpi_dma0 0 4 1 64 0>, >>> + <&gpi_dma0 1 4 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c5: i2c@994000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x994000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c5_data_clk>; >>> + dmas = <&gpi_dma0 0 5 3 64 0>, >>> + <&gpi_dma0 1 5 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi5: spi@994000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x994000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >>> + dmas = <&gpi_dma0 0 5 1 64 0>, >>> + <&gpi_dma0 1 5 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c6: i2c@998000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0x998000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c6_data_clk>; >>> + dmas = <&gpi_dma0 0 6 3 64 0>, >>> + <&gpi_dma0 1 6 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi6: spi@998000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0x998000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >>> + dmas = <&gpi_dma0 0 6 1 64 0>, >>> + <&gpi_dma0 1 6 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + uart7: serial@99c000 { >>> + compatible = "qcom,geni-debug-uart"; >>> + reg = <0x0 0x99c000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + }; >>> + >>> + gpi_dma1: dma-controller@a00000 { >>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >> See above. >> >>> + #dma-cells = <5>; >>> + reg = <0x0 0xa00000 0x0 0x60000>; >>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >>> + dma-channels = <12>; >>> + dma-channel-mask = <0x3f>; >>> + iommus = <&apps_smmu 0x116 0x0>; >>> + status = "ok"; >>> + }; >>> + >>> + qupv3_id_1: geniqup@ac0000 { >>> + compatible = "qcom,geni-se-qup"; >>> + reg = <0x0 0xac0000 0x0 0x2000>; >>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >>> + iommus = <&apps_smmu 0x103 0x0>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + clock-names = "m-ahb", "s-ahb"; >>> + >>> + ranges; >>> + status = "disabled"; >>> + >>> + uart8: serial@a80000 { >>> + compatible = "qcom,geni-uart"; >>> + reg = <0x0 0xa80000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_uart8_default>; >>> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c9: i2c@a84000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa84000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c9_data_clk>; >>> + dmas = <&gpi_dma1 0 1 3 64 0>, >>> + <&gpi_dma1 1 1 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi9: spi@a84000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa84000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >>> + dmas = <&gpi_dma1 0 1 1 64 0>, >>> + <&gpi_dma1 1 1 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c10: i2c@a88000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa88000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c10_data_clk>; >>> + dmas = <&gpi_dma1 0 2 3 64 0>, >>> + <&gpi_dma1 1 2 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi10: spi@a88000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa88000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >>> + dmas = <&gpi_dma1 0 2 1 64 0>, >>> + <&gpi_dma1 1 2 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c11: i2c@a8c000 { >>> + compatible = "qcom,i2c-geni"; >>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c11_data_clk>; >>> + dmas = <&gpi_dma1 0 3 3 64 0>, >>> + <&gpi_dma1 1 3 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi11: spi@a8c000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >>> + dmas = <&gpi_dma1 0 3 1 64 0>, >>> + <&gpi_dma1 1 3 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c12: i2c@a90000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa90000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c12_data_clk>; >>> + dmas = <&gpi_dma1 0 4 3 64 0>, >>> + <&gpi_dma1 1 4 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi12: spi@a90000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa90000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >>> + dmas = <&gpi_dma1 0 4 1 64 0>, >>> + <&gpi_dma1 1 4 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c13: i2c@a94000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa94000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c13_data_clk>; >>> + dmas = <&gpi_dma1 0 5 3 64 0>, >>> + <&gpi_dma1 1 5 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + uart13: serial@a94000 { >>> + compatible = "qcom,geni-uart"; >>> + reg = <0x0 0xa94000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_uart13_default>; >>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi13: spi@a94000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa94000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >>> + dmas = <&gpi_dma1 0 5 1 64 0>, >>> + <&gpi_dma1 1 5 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c14: i2c@a98000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa98000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c14_data_clk>; >>> + dmas = <&gpi_dma1 0 6 3 64 0>, >>> + <&gpi_dma1 1 6 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi14: spi@a98000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa98000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >>> + dmas = <&gpi_dma1 0 6 1 64 0>, >>> + <&gpi_dma1 1 6 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + >>> + i2c15: i2c@a9c000 { >>> + compatible = "qcom,geni-i2c"; >>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_i2c15_data_clk>; >>> + dmas = <&gpi_dma1 0 7 3 64 0>, >>> + <&gpi_dma1 1 7 3 64 0>; >>> + dma-names = "tx", "rx"; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "disabled"; >>> + }; >>> + >>> + spi15: spi@a9c000 { >>> + compatible = "qcom,geni-spi"; >>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>> + clock-names = "se"; >>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>> + interconnects = >>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >>> + dmas = <&gpi_dma1 0 7 1 64 0>, >>> + <&gpi_dma1 1 7 1 64 0>; >>> + dma-names = "tx", "rx"; >>> + status = "disabled"; >>> + }; >>> + }; >>> + >>> + system_noc: interconnect@1640000 { >>> + reg = <0x0 0x1640000 0x0 0x45080>; >>> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >>> + #interconnect-cells = <1>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + }; >>> + >>> + tcsr_mutex: hwlock@1f40000 { >>> + compatible = "qcom,tcsr-mutex"; >>> + reg = <0x0 0x1f40000 0x0 0x20000>; >>> + #hwlock-cells = <1>; >>> + }; >>> + >>> + pdc: interrupt-controller@b220000 { >>> + compatible = "qcom,pdc"; >>> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >>> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >>> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >>> + <94 609 31>, <125 63 1>; >>> + #interrupt-cells = <2>; >>> + interrupt-parent = <&intc>; >>> + interrupt-controller; >>> + }; >>> + >>> + spmi_bus: spmi@c400000 { >>> + compatible = "qcom,spmi-pmic-arb"; >>> + reg = <0x0 0xc400000 0x0 0x3000>, >>> + <0x0 0xc500000 0x0 0x400000>, >>> + <0x0 0xc440000 0x0 0x80000>, >>> + <0x0 0xc4c0000 0x0 0x10000>, >>> + <0x0 0xc42d000 0x0 0x4000>; >>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >>> + interrupt-names = "periph_irq"; >>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >>> + qcom,ee = <0>; >>> + qcom,channel = <0>; >>> + #address-cells = <2>; >>> + #size-cells = <0>; >>> + interrupt-controller; >>> + #interrupt-cells = <4>; >>> + }; >>> + >>> + tlmm: pinctrl@f000000 { >>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >>> + reg = <0x0 0xf000000 0x0 0x1000000>; >>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + interrupt-controller; >>> + #interrupt-cells = <2>; >>> + gpio-ranges = <&tlmm 0 0 151>; >>> + wakeup-parent = <&pdc>; >>> + >>> + qup_uart0_default: qup-uart0-default-state { >>> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >>> + function = "qup00"; >>> + }; >>> + >>> + qup_i2c1_data_clk: qup-i2c1-data-clk { >>> + pins = "gpio10", "gpio11"; >>> + function = "qup01"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi1_data_clk: qup-spi1-data-clk { >>> + pins = "gpio10", "gpio11", "gpio12"; >>> + function = "qup01"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi1_cs: qup-spi1-cs { >>> + pins = "gpio13"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c2_data_clk: qup-i2c2-data-clk { >>> + pins = "gpio12", "gpio13"; >>> + function = "qup02"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi2_data_clk: qup-spi2-data-clk { >>> + pins = "gpio12", "gpio13", "gpio10"; >>> + function = "qup02"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi2_cs: qup-spi2-cs { >>> + pins = "gpio11"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c3_data_clk: qup-i2c3-data-clk { >>> + pins = "gpio14", "gpio15"; >>> + function = "qup03"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi3_data_clk: qup-spi3-data-clk { >>> + pins = "gpio14", "gpio15", "gpio16"; >>> + function = "qup03"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi3_cs: qup-spi3-cs { >>> + pins = "gpio17"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c4_data_clk: qup-i2c4-data-clk { >>> + pins = "gpio16", "gpio17"; >>> + function = "qup04"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi4_data_clk: qup-spi4-data-clk { >>> + pins = "gpio16", "gpio17", "gpio14"; >>> + function = "qup04"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi4_cs: qup-spi4-cs { >>> + pins = "gpio15"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c5_data_clk: qup-i2c5-data-clk { >>> + pins = "gpio130", "gpio131"; >>> + function = "qup05"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi5_data_clk: qup-spi5-data-clk { >>> + pins = "gpio130", "gpio131", "gpio132"; >>> + function = "qup05"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi5_cs: qup-spi5-cs { >>> + pins = "gpio133"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c6_data_clk: qup-i2c6-data-clk { >>> + pins = "gpio132", "gpio133"; >>> + function = "qup06"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi6_data_clk: qup-spi6-data-clk { >>> + pins = "gpio132", "gpio133", "gpio130"; >>> + function = "qup06"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi6_cs: qup-spi6-cs { >>> + pins = "gpio131"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_uart7_rx: qup-uart7-rx { >>> + pins = "gpio135"; >>> + function = "qup07"; >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> + qup_uart7_tx: qup-uart7-tx { >>> + pins = "gpio134"; >>> + function = "qup07"; >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >>> + >>> + qup_uart8_default: qup-uart8-default { >>> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >>> + function = "qup10"; >>> + }; >>> + >>> + qup_i2c9_data_clk: qup-i2c9-data-clk { >>> + pins = "gpio22", "gpio23"; >>> + function = "qup11"; >>> + drive-strength = <2>; >>> + bias-pull-up; >>> + }; >>> + >>> + qup_spi9_data_clk: qup-spi9-data-clk { >>> + pins = "gpio22", "gpio23", "gpio24"; >>> + function = "qup11"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi9_cs: qup-spi9-cs { >>> + pins = "gpio25"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c10_data_clk: qup-i2c10-data-clk { >>> + pins = "gpio24", "gpio25"; >>> + function = "qup12"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi10_data_clk: qup-spi10-data-clk { >>> + pins = "gpio24", "gpio25", "gpio22"; >>> + function = "qup12"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi10_cs: qup-spi10-cs { >>> + pins = "gpio23"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c11_data_clk: qup-i2c11-data-clk { >>> + pins = "gpio26", "gpio27"; >>> + function = "qup13"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi11_data_clk: qup-spi11-data-clk { >>> + pins = "gpio26", "gpio27", "gpio28"; >>> + function = "qup13"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi11_cs: qup-spi11-cs { >>> + pins = "gpio29"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c12_data_clk: qup-i2c12-data-clk { >>> + pins = "gpio28", "gpio29"; >>> + function = "qup14"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi12_data_clk: qup-spi12-data-clk { >>> + pins = "gpio28", "gpio29", "gpio26"; >>> + function = "qup14"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi12_cs: qup-spi12-cs { >>> + pins = "gpio27"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c13_data_clk: qup-i2c13-data-clk { >>> + pins = "gpio30", "gpio31"; >>> + function = "qup15"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi13_data_clk: qup-spi13-data-clk { >>> + pins = "gpio30", "gpio31", "gpio32"; >>> + function = "qup15"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi13_cs: qup-spi13-cs { >>> + pins = "gpio33"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_uart13_default: qup-uart13-default { >>> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >>> + function = "qup15"; >>> + }; >>> + >>> + qup_i2c14_data_clk: qup-i2c14-data-clk { >>> + pins = "gpio34", "gpio35"; >>> + function = "qup16"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi14_data_clk: qup-spi14-data-clk { >>> + pins = "gpio34", "gpio35", "gpio36"; >>> + function = "qup16"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi14_cs: qup-spi14-cs { >>> + pins = "gpio37", "gpio38"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_i2c15_data_clk: qup-i2c15-data-clk { >>> + pins = "gpio40", "gpio41"; >>> + function = "qup17"; >>> + drive-strength = <2>; >>> + bias-pulll-up; >>> + }; >>> + >>> + qup_spi15_data_clk: qup-spi15-data-clk { >>> + pins = "gpio40", "gpio41", "gpio30"; >>> + function = "qup17"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + >>> + qup_spi15_cs: qup-spi15-cs { >>> + pins = "gpio31"; >>> + drive-strength = <6>; >>> + bias-disable; >>> + }; >>> + }; >>> + >>> + apps_smmu: apps-smmu@15000000 { >>> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >>> + "arm,mmu-500"; >>> + reg = <0x0 0x15000000 0x0 0x100000>; >>> + #iommu-cells = <2>; >>> + #global-interrupts = <2>; >>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >>> + }; >>> + >>> + intc: interrupt-controller@17200000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + interrupt-controller; >>> + #redistributor-regions = <1>; >>> + redistributor-stride = <0x0 0x20000>; >>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >>> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >>> + }; >>> + >>> + timer@17420000 { >>> + compatible = "arm,armv7-timer-mem"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + ranges; >>> + reg = <0x0 0x17420000 0x0 0x1000>; >>> + clock-frequency = <19200000>; >>> + >>> + frame@17421000 { >>> + frame-number = <0>; >>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x17421000 0x0 0x1000>, >>> + <0x0 0x17422000 0x0 0x1000>; >>> + }; >>> + >>> + frame@17423000 { >>> + frame-number = <1>; >>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x17423000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + >>> + frame@17425000 { >>> + frame-number = <2>; >>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x17425000 0x0 0x1000>, >>> + <0x0 0x17426000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + >>> + frame@17427000 { >>> + frame-number = <3>; >>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x17427000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + >>> + frame@17429000 { >>> + frame-number = <4>; >>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x17429000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + >>> + frame@1742b000 { >>> + frame-number = <5>; >>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x1742b000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + >>> + frame@1742d000 { >>> + frame-number = <6>; >>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >>> + reg = <0x0 0x1742d000 0x0 0x1000>; >>> + status = "disabled"; >>> + }; >>> + }; >>> + >>> + apps_rsc: rsc@17a00000 { >>> + label = "apps_rsc"; >>> + compatible = "qcom,rpmh-rsc"; >>> + reg = <0x0 0x17a00000 0x0 0x10000>, >>> + <0x0 0x17a10000 0x0 0x10000>, >>> + <0x0 0x17a20000 0x0 0x10000>; >>> + reg-names = "drv-0", "drv-1", "drv-2"; >>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >>> + qcom,tcs-offset = <0xd00>; >>> + qcom,drv-id = <2>; >>> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >>> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >>> + >>> + apps_bcm_voter: bcm_voter { >>> + compatible = "qcom,bcm-voter"; >>> + }; >>> + >>> + rpmhcc: clock-controller { >>> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; >>> + #clock-cells = <1>; >>> + clock-names = "xo"; >>> + clocks = <&xo_board>; >>> + }; >>> + >>> + rpmhpd: power-controller { >>> + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; >>> + #power-domain-cells = <1>; >>> + operating-points-v2 = <&rpmhpd_opp_table>; >>> + >>> + rpmhpd_opp_table: opp-table { >>> + compatible = "operating-points-v2"; >>> + >>> + rpmhpd_opp_ret: opp1 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; >>> + }; >>> + >>> + rpmhpd_opp_min_svs: opp2 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >>> + }; >>> + >>> + rpmhpd_opp_low_svs: opp3 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >>> + }; >>> + >>> + rpmhpd_opp_svs: opp4 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >>> + }; >>> + >>> + rpmhpd_opp_svs_l1: opp5 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >>> + }; >>> + >>> + rpmhpd_opp_nom: opp6 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >>> + }; >>> + >>> + rpmhpd_opp_nom_l1: opp7 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >>> + }; >>> + >>> + rpmhpd_opp_nom_l2: opp8 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; >>> + }; >>> + >>> + rpmhpd_opp_turbo: opp9 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >>> + }; >>> + >>> + rpmhpd_opp_turbo_l1: opp10 { >>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + cpufreq_hw: cpufreq@17d91000 { >>> + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", >>> + "qcom,cpufreq-epss"; >>> + reg = <0x0 0x17d91000 0x0 0x1000>; >>> + reg-names = "freq-domain0"; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >>> + clock-names = "xo", "alternate"; >>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>> + interrupt-names = "dcvsh-irq-0"; >>> + #freq-domain-cells = <1>; >>> + }; >>> + >>> + gem_noc: interconnect@19100000 { >>> + reg = <0x0 0x19100000 0x0 0xB8080>; >>> + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; >>> + #interconnect-cells = <1>; >>> + qcom,bcm-voters = <&apps_bcm_voter>; >>> + }; >>> + >>> + arch_timer: timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>> + clock-frequency = <19200000>; >>> + }; >>> + }; >>> +}; >>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>> new file mode 100644 >>> index 000000000000..074fe126e85e >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>> @@ -0,0 +1,27 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +#include "qdu1000.dtsi" >>> + >>> +&reserved_memory { >>> + /delete-node/ memory@a0000000; >>> + /delete-node/ memory@b9600000; >>> + /delete-node/ memory@c0000000; >>> + >>> + oem_tenx_mem: memory@a0000000 { >>> + no-map; >>> + reg = <0x0 0xa0000000 0x0 0x6400000>; >>> + }; >>> + >>> + mpss_diag_buffer_mem: memory@aea00000 { >>> + no-map; >>> + reg = <0x0 0xaea00000 0x0 0x6400000>; >>> + }; >>> + >>> + tenx_q6_buffer_mem: memory@b4e00000 { >>> + no-map; >>> + reg = <0x0 0xb4e00000 0x0 0x3200000>; >>> + }; >>> +}; >>> -- >>> 2.38.0 > Thanks, > Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-24 22:28 ` Richard Acayan @ 2022-10-24 22:31 ` Melody Olvera 2022-10-24 22:51 ` Richard Acayan 0 siblings, 1 reply; 28+ messages in thread From: Melody Olvera @ 2022-10-24 22:31 UTC (permalink / raw) To: Richard Acayan, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/24/2022 3:28 PM, Richard Acayan wrote: >> On 10/23/2022 5:53 PM, Richard Acayan wrote: >>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>>> to boot to shell with console on these SoCs. >>>> >>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>>> --- >>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>>> 2 files changed, 1673 insertions(+) >>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>> new file mode 100644 >>>> index 000000000000..777734b30f56 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>> @@ -0,0 +1,1646 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause >>>> +/* >>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>> + */ >>>> + >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >>>> +#include <dt-bindings/clock/qcom,rpmh.h> >>>> +#include <dt-bindings/dma/qcom-gpi.h> >>>> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >>>> +#include <dt-bindings/power/qcom-rpmpd.h> >>>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>> + >>>> +/ { >>>> + interrupt-parent = <&intc>; >>>> + >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + chosen: chosen { }; >>>> + >>>> + clocks { >>>> + xo_board: xo-board { >>>> + compatible = "fixed-clock"; >>>> + clock-frequency = <19200000>; >>>> + clock-output-names = "xo_board"; >>>> + #clock-cells = <0>; >>>> + }; >>>> + >>>> + sleep_clk: sleep-clk { >>>> + compatible = "fixed-clock"; >>>> + clock-frequency = <32000>; >>>> + #clock-cells = <0>; >>>> + }; >>>> + }; >>>> + >>>> + cpus { >>>> + #address-cells = <2>; >>>> + #size-cells = <0>; >>>> + >>>> + CPU0: cpu@0 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,cortex-a55"; >>>> + reg = <0x0 0x0>; >>>> + enable-method = "psci"; >>>> + power-domain-names = "psci"; >>>> + power-domains = <&CPU_PD0>; >>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>> + next-level-cache = <&L2_0>; >>>> + L2_0: l2-cache { >>>> + compatible = "cache"; >>>> + next-level-cache = <&L3_0>; >>>> + L3_0: l3-cache { >>>> + compatible = "cache"; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + CPU1: cpu@100 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,cortex-a55"; >>>> + reg = <0x0 0x100>; >>>> + enable-method = "psci"; >>>> + power-domains = <&CPU_PD1>; >>>> + power-domain-names = "psci"; >>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>> + next-level-cache = <&L2_100>; >>>> + L2_100: l2-cache { >>>> + compatible = "cache"; >>>> + next-level-cache = <&L3_0>; >>>> + }; >>>> + >>>> + }; >>>> + >>>> + CPU2: cpu@200 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,cortex-a55"; >>>> + reg = <0x0 0x200>; >>>> + enable-method = "psci"; >>>> + power-domains = <&CPU_PD2>; >>>> + power-domain-names = "psci"; >>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>> + next-level-cache = <&L2_200>; >>>> + L2_200: l2-cache { >>>> + compatible = "cache"; >>>> + next-level-cache = <&L3_0>; >>>> + }; >>>> + }; >>>> + >>>> + CPU3: cpu@300 { >>>> + device_type = "cpu"; >>>> + compatible = "arm,cortex-a55"; >>>> + reg = <0x0 0x300>; >>>> + enable-method = "psci"; >>>> + power-domains = <&CPU_PD3>; >>>> + power-domain-names = "psci"; >>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>> + next-level-cache = <&L2_300>; >>>> + L2_300: l2-cache { >>>> + compatible = "cache"; >>>> + next-level-cache = <&L3_0>; >>>> + }; >>>> + >>>> + }; >>>> + >>>> + cpu-map { >>>> + cluster0 { >>>> + core0 { >>>> + cpu = <&CPU0>; >>>> + }; >>>> + >>>> + core1 { >>>> + cpu = <&CPU1>; >>>> + }; >>>> + >>>> + core2 { >>>> + cpu = <&CPU2>; >>>> + }; >>>> + >>>> + core3 { >>>> + cpu = <&CPU3>; >>>> + }; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + idle-states { >>>> + entry-method = "psci"; >>>> + >>>> + CPU_OFF: cpu-sleep-0 { >>>> + compatible = "arm,idle-state"; >>>> + idle-state-name = "rail-pc"; >>>> + entry-latency-us = <274>; >>>> + exit-latency-us = <480>; >>>> + min-residency-us = <3934>; >>>> + arm,psci-suspend-param = <0x40000004>; >>>> + local-timer-stop; >>>> + }; >>>> + }; >>>> + >>>> + domain-idle-states { >>>> + CLUSTER_SLEEP_0: cluster-sleep-0 { >>>> + compatible = "domain-idle-state"; >>>> + idle-state-name = "cluster-l3-off"; >>>> + entry-latency-us = <584>; >>>> + exit-latency-us = <2332>; >>>> + min-residency-us = <6118>; >>>> + arm,psci-suspend-param = <0x41000044>; >>>> + }; >>>> + >>>> + CLUSTER_SLEEP_1: cluster-sleep-1 { >>>> + compatible = "domain-idle-state"; >>>> + idle-state-name = "cluster-power-collapse"; >>>> + entry-latency-us = <2893>; >>>> + exit-latency-us = <4023>; >>>> + min-residency-us = <9987>; >>>> + arm,psci-suspend-param = <0x41003344>; >>>> + }; >>>> + }; >>>> + >>>> + firmware { >>>> + qcom_scm { >>>> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >>>> + #reset-cells = <1>; >>>> + }; >>>> + }; >>>> + >>>> + clk_virt: interconnect-0 { >>>> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >>>> + #interconnect-cells = <2>; >>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>> + }; >>>> + >>>> + mc_virt: interconnect-1 { >>>> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >>>> + #interconnect-cells = <2>; >>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>> + }; >>>> + >>>> + memory@80000000 { >>>> + device_type = "memory"; >>>> + /* We expect the bootloader to fill in the size */ >>>> + reg = <0x0 0x80000000 0x0 0x0>; >>>> + }; >>>> + >>>> + pmu { >>>> + compatible = "arm,armv8-pmuv3"; >>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>> + }; >>>> + >>>> + psci { >>>> + compatible = "arm,psci-1.0"; >>>> + method = "smc"; >>>> + >>>> + CPU_PD0: cpu-pd0 { >>>> + #power-domain-cells = <0>; >>>> + power-domains = <&CLUSTER_PD>; >>>> + domain-idle-states = <&CPU_OFF>; >>>> + }; >>>> + >>>> + CPU_PD1: cpu-pd1 { >>>> + #power-domain-cells = <0>; >>>> + power-domains = <&CLUSTER_PD>; >>>> + domain-idle-states = <&CPU_OFF>; >>>> + }; >>>> + >>>> + CPU_PD2: cpu-pd2 { >>>> + #power-domain-cells = <0>; >>>> + power-domains = <&CLUSTER_PD>; >>>> + domain-idle-states = <&CPU_OFF>; >>>> + }; >>>> + >>>> + CPU_PD3: cpu-pd3 { >>>> + #power-domain-cells = <0>; >>>> + power-domains = <&CLUSTER_PD>; >>>> + domain-idle-states = <&CPU_OFF>; >>>> + }; >>>> + >>>> + CLUSTER_PD: cluster-pd { >>>> + #power-domain-cells = <0>; >>>> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >>>> + }; >>>> + }; >>>> + >>>> + reserved_memory: reserved-memory { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges; >>>> + >>>> + hyp_mem: memory@80000000 { >>>> + no-map; >>>> + reg = <0x0 0x80000000 0x0 0x600000>; >>>> + }; >>>> + >>>> + xbl_dt_log_mem: memory@80600000 { >>>> + no-map; >>>> + reg = <0x0 0x80600000 0x0 0x40000>; >>>> + }; >>>> + >>>> + xbl_ramdump_mem: memory@80640000 { >>>> + no-map; >>>> + reg = <0x0 0x80640000 0x0 0x1c0000>; >>>> + }; >>>> + >>>> + aop_image_mem: memory@80800000 { >>>> + no-map; >>>> + reg = <0x0 0x80800000 0x0 0x60000>; >>>> + }; >>>> + >>>> + aop_cmd_db_mem: memory@80860000 { >>>> + compatible = "qcom,cmd-db"; >>>> + no-map; >>>> + reg = <0x0 0x80860000 0x0 0x20000>; >>>> + }; >>>> + >>>> + aop_config_mem: memory@80880000 { >>>> + no-map; >>>> + reg = <0x0 0x80880000 0x0 0x20000>; >>>> + }; >>>> + >>>> + tme_crash_dump_mem: memory@808a0000 { >>>> + no-map; >>>> + reg = <0x0 0x808a0000 0x0 0x40000>; >>>> + }; >>>> + >>>> + tme_log_mem: memory@808e0000 { >>>> + no-map; >>>> + reg = <0x0 0x808e0000 0x0 0x4000>; >>>> + }; >>>> + >>>> + uefi_log_mem: memory@808e4000 { >>>> + no-map; >>>> + reg = <0x0 0x808e4000 0x0 0x10000>; >>>> + }; >>>> + >>>> + /* secdata region can be reused by apps */ >>>> + >>>> + smem_mem: memory@80900000 { >>>> + compatible = "qcom,smem"; >>>> + no-map; >>>> + reg = <0x0 0x80900000 0x0 0x200000>; >>>> + hwlocks = <&tcsr_mutex 3>; >>>> + }; >>>> + >>>> + cpucp_fw_mem: memory@80b00000 { >>>> + no-map; >>>> + reg = <0x0 0x80b00000 0x0 0x100000>; >>>> + }; >>>> + >>>> + xbl_sc_mem: memory@80c00000 { >>>> + no-map; >>>> + reg = <0x0 0x80c00000 0x0 0x40000>; >>>> + }; >>>> + >>>> + /* uefi region can be reused by apps */ >>>> + >>>> + tz_stat_mem: memory@81d00000 { >>>> + no-map; >>>> + reg = <0x0 0x81d00000 0x0 0x100000>; >>>> + }; >>>> + >>>> + tags_mem: memory@81e00000 { >>>> + no-map; >>>> + reg = <0x0 0x81e00000 0x0 0x500000>; >>>> + }; >>>> + >>>> + qtee_mem: memory@82300000 { >>>> + no-map; >>>> + reg = <0x0 0x82300000 0x0 0x500000>; >>>> + }; >>>> + >>>> + ta_mem: memory@82800000 { >>>> + no-map; >>>> + reg = <0x0 0x82800000 0x0 0xa00000>; >>>> + }; >>>> + >>>> + fs1_mem: memory@83200000 { >>>> + no-map; >>>> + reg = <0x0 0x83200000 0x0 0x400000>; >>>> + }; >>>> + >>>> + fs2_mem: memory@83600000 { >>>> + no-map; >>>> + reg = <0x0 0x83600000 0x0 0x400000>; >>>> + }; >>>> + >>>> + fs3_mem: memory@83a00000 { >>>> + no-map; >>>> + reg = <0x0 0x83a00000 0x0 0x400000>; >>>> + }; >>>> + >>>> + /* Linux kernel image is loaded at 0x83e00000 */ >>>> + >>>> + ipa_fw_mem: memory@8be00000 { >>>> + no-map; >>>> + reg = <0x0 0x8be00000 0x0 0x10000>; >>>> + }; >>>> + >>>> + ipa_gsi_mem: memory@8be10000 { >>>> + no-map; >>>> + reg = <0x0 0x8be10000 0x0 0x14000>; >>>> + }; >>>> + >>>> + mpss_mem: memory@8c000000 { >>>> + no-map; >>>> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >>>> + }; >>>> + >>>> + q6_mpss_dtb_mem: memory@9ec00000 { >>>> + no-map; >>>> + reg = <0x0 0x9ec00000 0x0 0x80000>; >>>> + }; >>>> + >>>> + tenx_mem: memory@a0000000 { >>>> + no-map; >>>> + reg = <0x0 0xa0000000 0x0 0x19600000>; >>>> + }; >>>> + >>>> + oem_tenx_mem: memory@b9600000 { >>>> + no-map; >>>> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >>>> + }; >>>> + >>>> + tenx_q6_buffer_mem: memory@c0000000 { >>>> + no-map; >>>> + reg = <0x0 0xc0000000 0x0 0x3200000>; >>>> + }; >>>> + >>>> + ipa_buffer_mem: memory@c3200000 { >>>> + no-map; >>>> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >>>> + }; >>>> + }; >>>> + >>>> + soc: soc@0 { >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges = <0 0 0 0 0x10 0>; >>>> + dma-ranges = <0 0 0 0 0x10 0>; >>>> + compatible = "simple-bus"; >>>> + >>>> + gcc: clock-controller@80000 { >>>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >>>> + reg = <0x0 0x80000 0x0 0x1f4200>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + #power-domain-cells = <1>; >>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >>>> + clock-names = "bi_tcxo", "sleep_clk"; >>>> + }; >>>> + >>>> + gpi_dma0: dma-controller@900000 { >>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>> This won't work if you drop series [1]. It won't just fail the schema checks, >>> but it would also fail to probe because the driver doesn't recognise it. >>> >>> I think you were told to rebase on [2], and didn't change your own series >>> because it only applied to ee_offset = 0x0. There is another series [3] that >>> was sent to you, meant for ee_offset = 0x10000. You're expected to change your >>> patches (in both series you sent) based on what was changed in that series. >>> >>> [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ >>> [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ >>> [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ >> Hi Richard; I was aware of this feedback and was planning to make that change in v3. >> PS [1] will be dropped and this compatible will be modified similar to PS [3]; that was >> what I meant by my final comment on [1]. > Ok, I should have checked the date. What about the schema patch? It might be > helpful for the device tree cleanup efforts if you didn't add a compatible > without adding a corresponding entry in the device tree bindings. > > I'm talking about updating this patch in particular: > > https://lore.kernel.org/linux-arm-msm/20221014221102.7445-2-quic_molvera@quicinc.com/ > > We still add compat strings in dt-bindings even when there is a fallback, > because the schema is meant to specify every combination of compat strings > found in the device trees. That will be dropped as well. I'll use the sdm845 compat string instead of what's here. > >>>> + #dma-cells = <5>; >>>> + reg = <0x0 0x900000 0x0 0x60000>; >>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >>>> + dma-channels = <12>; >>>> + dma-channel-mask = <0x3f>; >>>> + iommus = <&apps_smmu 0xf6 0x0>; >>>> + status = "ok"; >>>> + }; >>>> + >>>> + qupv3_id_0: geniqup@9c0000 { >>>> + compatible = "qcom,geni-se-qup"; >>>> + reg = <0x0 0x9c0000 0x0 0x2000>; >>>> + clock-names = "m-ahb", "s-ahb"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >>>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>>> + iommus = <&apps_smmu 0xe3 0x0>; >>>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >>>> + &clk_virt SLAVE_QUP_CORE_0 0>; >>>> + interconnect-names = "qup-core"; >>>> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >>>> + qcom,iommu-geometry = <0x40000000 0x10000000>; >>>> + qcom,iommu-dma = "fastmap"; >>>> + dma-coherent; >>>> + >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges; >>>> + status = "disabled"; >>>> + >>>> + uart0: serial@980000 { >>>> + compatible = "qcom,geni-uart"; >>>> + reg = <0x0 0x980000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_uart0_default>; >>>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c1: i2c@984000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c1_data_clk>; >>>> + dmas = <&gpi_dma0 0 1 3 64 0>, >>>> + <&gpi_dma0 1 1 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi1: spi@984000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >>>> + dmas = <&gpi_dma0 0 1 1 64 0>, >>>> + <&gpi_dma0 1 1 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c2: i2c@988000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c2_data_clk>; >>>> + dmas = <&gpi_dma0 0 2 3 64 0>, >>>> + <&gpi_dma0 1 2 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi2: spi@988000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >>>> + dmas = <&gpi_dma0 0 2 1 64 0>, >>>> + <&gpi_dma0 1 2 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c3: i2c@98c000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c3_data_clk>; >>>> + dmas = <&gpi_dma0 0 3 3 64 0>, >>>> + <&gpi_dma0 1 3 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi3: spi@98c000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >>>> + dmas = <&gpi_dma0 0 3 1 64 0>, >>>> + <&gpi_dma0 1 3 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c4: i2c@990000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c4_data_clk>; >>>> + dmas = <&gpi_dma0 0 4 3 64 0>, >>>> + <&gpi_dma0 1 4 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi4: spi@990000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >>>> + dmas = <&gpi_dma0 0 4 1 64 0>, >>>> + <&gpi_dma0 1 4 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c5: i2c@994000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c5_data_clk>; >>>> + dmas = <&gpi_dma0 0 5 3 64 0>, >>>> + <&gpi_dma0 1 5 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi5: spi@994000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >>>> + dmas = <&gpi_dma0 0 5 1 64 0>, >>>> + <&gpi_dma0 1 5 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c6: i2c@998000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c6_data_clk>; >>>> + dmas = <&gpi_dma0 0 6 3 64 0>, >>>> + <&gpi_dma0 1 6 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi6: spi@998000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >>>> + dmas = <&gpi_dma0 0 6 1 64 0>, >>>> + <&gpi_dma0 1 6 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + uart7: serial@99c000 { >>>> + compatible = "qcom,geni-debug-uart"; >>>> + reg = <0x0 0x99c000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >>>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + }; >>>> + >>>> + gpi_dma1: dma-controller@a00000 { >>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>> See above. >>> >>>> + #dma-cells = <5>; >>>> + reg = <0x0 0xa00000 0x0 0x60000>; >>>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >>>> + dma-channels = <12>; >>>> + dma-channel-mask = <0x3f>; >>>> + iommus = <&apps_smmu 0x116 0x0>; >>>> + status = "ok"; >>>> + }; >>>> + >>>> + qupv3_id_1: geniqup@ac0000 { >>>> + compatible = "qcom,geni-se-qup"; >>>> + reg = <0x0 0xac0000 0x0 0x2000>; >>>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >>>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >>>> + iommus = <&apps_smmu 0x103 0x0>; >>>> + #address-cells = <1>; >>>> + #size-cells = <1>; >>>> + clock-names = "m-ahb", "s-ahb"; >>>> + >>>> + ranges; >>>> + status = "disabled"; >>>> + >>>> + uart8: serial@a80000 { >>>> + compatible = "qcom,geni-uart"; >>>> + reg = <0x0 0xa80000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_uart8_default>; >>>> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c9: i2c@a84000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c9_data_clk>; >>>> + dmas = <&gpi_dma1 0 1 3 64 0>, >>>> + <&gpi_dma1 1 1 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi9: spi@a84000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >>>> + dmas = <&gpi_dma1 0 1 1 64 0>, >>>> + <&gpi_dma1 1 1 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c10: i2c@a88000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c10_data_clk>; >>>> + dmas = <&gpi_dma1 0 2 3 64 0>, >>>> + <&gpi_dma1 1 2 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi10: spi@a88000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >>>> + dmas = <&gpi_dma1 0 2 1 64 0>, >>>> + <&gpi_dma1 1 2 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c11: i2c@a8c000 { >>>> + compatible = "qcom,i2c-geni"; >>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c11_data_clk>; >>>> + dmas = <&gpi_dma1 0 3 3 64 0>, >>>> + <&gpi_dma1 1 3 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi11: spi@a8c000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >>>> + dmas = <&gpi_dma1 0 3 1 64 0>, >>>> + <&gpi_dma1 1 3 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c12: i2c@a90000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c12_data_clk>; >>>> + dmas = <&gpi_dma1 0 4 3 64 0>, >>>> + <&gpi_dma1 1 4 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi12: spi@a90000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >>>> + dmas = <&gpi_dma1 0 4 1 64 0>, >>>> + <&gpi_dma1 1 4 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c13: i2c@a94000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c13_data_clk>; >>>> + dmas = <&gpi_dma1 0 5 3 64 0>, >>>> + <&gpi_dma1 1 5 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + uart13: serial@a94000 { >>>> + compatible = "qcom,geni-uart"; >>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_uart13_default>; >>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi13: spi@a94000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >>>> + dmas = <&gpi_dma1 0 5 1 64 0>, >>>> + <&gpi_dma1 1 5 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c14: i2c@a98000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c14_data_clk>; >>>> + dmas = <&gpi_dma1 0 6 3 64 0>, >>>> + <&gpi_dma1 1 6 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi14: spi@a98000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >>>> + dmas = <&gpi_dma1 0 6 1 64 0>, >>>> + <&gpi_dma1 1 6 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + i2c15: i2c@a9c000 { >>>> + compatible = "qcom,geni-i2c"; >>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_i2c15_data_clk>; >>>> + dmas = <&gpi_dma1 0 7 3 64 0>, >>>> + <&gpi_dma1 1 7 3 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + spi15: spi@a9c000 { >>>> + compatible = "qcom,geni-spi"; >>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>> + #address-cells = <1>; >>>> + #size-cells = <0>; >>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>> + clock-names = "se"; >>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>> + interconnects = >>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >>>> + dmas = <&gpi_dma1 0 7 1 64 0>, >>>> + <&gpi_dma1 1 7 1 64 0>; >>>> + dma-names = "tx", "rx"; >>>> + status = "disabled"; >>>> + }; >>>> + }; >>>> + >>>> + system_noc: interconnect@1640000 { >>>> + reg = <0x0 0x1640000 0x0 0x45080>; >>>> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >>>> + #interconnect-cells = <1>; >>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>> + }; >>>> + >>>> + tcsr_mutex: hwlock@1f40000 { >>>> + compatible = "qcom,tcsr-mutex"; >>>> + reg = <0x0 0x1f40000 0x0 0x20000>; >>>> + #hwlock-cells = <1>; >>>> + }; >>>> + >>>> + pdc: interrupt-controller@b220000 { >>>> + compatible = "qcom,pdc"; >>>> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >>>> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >>>> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >>>> + <94 609 31>, <125 63 1>; >>>> + #interrupt-cells = <2>; >>>> + interrupt-parent = <&intc>; >>>> + interrupt-controller; >>>> + }; >>>> + >>>> + spmi_bus: spmi@c400000 { >>>> + compatible = "qcom,spmi-pmic-arb"; >>>> + reg = <0x0 0xc400000 0x0 0x3000>, >>>> + <0x0 0xc500000 0x0 0x400000>, >>>> + <0x0 0xc440000 0x0 0x80000>, >>>> + <0x0 0xc4c0000 0x0 0x10000>, >>>> + <0x0 0xc42d000 0x0 0x4000>; >>>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >>>> + interrupt-names = "periph_irq"; >>>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >>>> + qcom,ee = <0>; >>>> + qcom,channel = <0>; >>>> + #address-cells = <2>; >>>> + #size-cells = <0>; >>>> + interrupt-controller; >>>> + #interrupt-cells = <4>; >>>> + }; >>>> + >>>> + tlmm: pinctrl@f000000 { >>>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >>>> + reg = <0x0 0xf000000 0x0 0x1000000>; >>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >>>> + gpio-controller; >>>> + #gpio-cells = <2>; >>>> + interrupt-controller; >>>> + #interrupt-cells = <2>; >>>> + gpio-ranges = <&tlmm 0 0 151>; >>>> + wakeup-parent = <&pdc>; >>>> + >>>> + qup_uart0_default: qup-uart0-default-state { >>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >>>> + function = "qup00"; >>>> + }; >>>> + >>>> + qup_i2c1_data_clk: qup-i2c1-data-clk { >>>> + pins = "gpio10", "gpio11"; >>>> + function = "qup01"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi1_data_clk: qup-spi1-data-clk { >>>> + pins = "gpio10", "gpio11", "gpio12"; >>>> + function = "qup01"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi1_cs: qup-spi1-cs { >>>> + pins = "gpio13"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c2_data_clk: qup-i2c2-data-clk { >>>> + pins = "gpio12", "gpio13"; >>>> + function = "qup02"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi2_data_clk: qup-spi2-data-clk { >>>> + pins = "gpio12", "gpio13", "gpio10"; >>>> + function = "qup02"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi2_cs: qup-spi2-cs { >>>> + pins = "gpio11"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c3_data_clk: qup-i2c3-data-clk { >>>> + pins = "gpio14", "gpio15"; >>>> + function = "qup03"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi3_data_clk: qup-spi3-data-clk { >>>> + pins = "gpio14", "gpio15", "gpio16"; >>>> + function = "qup03"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi3_cs: qup-spi3-cs { >>>> + pins = "gpio17"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c4_data_clk: qup-i2c4-data-clk { >>>> + pins = "gpio16", "gpio17"; >>>> + function = "qup04"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi4_data_clk: qup-spi4-data-clk { >>>> + pins = "gpio16", "gpio17", "gpio14"; >>>> + function = "qup04"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi4_cs: qup-spi4-cs { >>>> + pins = "gpio15"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c5_data_clk: qup-i2c5-data-clk { >>>> + pins = "gpio130", "gpio131"; >>>> + function = "qup05"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi5_data_clk: qup-spi5-data-clk { >>>> + pins = "gpio130", "gpio131", "gpio132"; >>>> + function = "qup05"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi5_cs: qup-spi5-cs { >>>> + pins = "gpio133"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c6_data_clk: qup-i2c6-data-clk { >>>> + pins = "gpio132", "gpio133"; >>>> + function = "qup06"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi6_data_clk: qup-spi6-data-clk { >>>> + pins = "gpio132", "gpio133", "gpio130"; >>>> + function = "qup06"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi6_cs: qup-spi6-cs { >>>> + pins = "gpio131"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_uart7_rx: qup-uart7-rx { >>>> + pins = "gpio135"; >>>> + function = "qup07"; >>>> + drive-strength = <2>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_uart7_tx: qup-uart7-tx { >>>> + pins = "gpio134"; >>>> + function = "qup07"; >>>> + drive-strength = <2>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_uart8_default: qup-uart8-default { >>>> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >>>> + function = "qup10"; >>>> + }; >>>> + >>>> + qup_i2c9_data_clk: qup-i2c9-data-clk { >>>> + pins = "gpio22", "gpio23"; >>>> + function = "qup11"; >>>> + drive-strength = <2>; >>>> + bias-pull-up; >>>> + }; >>>> + >>>> + qup_spi9_data_clk: qup-spi9-data-clk { >>>> + pins = "gpio22", "gpio23", "gpio24"; >>>> + function = "qup11"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi9_cs: qup-spi9-cs { >>>> + pins = "gpio25"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c10_data_clk: qup-i2c10-data-clk { >>>> + pins = "gpio24", "gpio25"; >>>> + function = "qup12"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi10_data_clk: qup-spi10-data-clk { >>>> + pins = "gpio24", "gpio25", "gpio22"; >>>> + function = "qup12"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi10_cs: qup-spi10-cs { >>>> + pins = "gpio23"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c11_data_clk: qup-i2c11-data-clk { >>>> + pins = "gpio26", "gpio27"; >>>> + function = "qup13"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi11_data_clk: qup-spi11-data-clk { >>>> + pins = "gpio26", "gpio27", "gpio28"; >>>> + function = "qup13"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi11_cs: qup-spi11-cs { >>>> + pins = "gpio29"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c12_data_clk: qup-i2c12-data-clk { >>>> + pins = "gpio28", "gpio29"; >>>> + function = "qup14"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi12_data_clk: qup-spi12-data-clk { >>>> + pins = "gpio28", "gpio29", "gpio26"; >>>> + function = "qup14"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi12_cs: qup-spi12-cs { >>>> + pins = "gpio27"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c13_data_clk: qup-i2c13-data-clk { >>>> + pins = "gpio30", "gpio31"; >>>> + function = "qup15"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi13_data_clk: qup-spi13-data-clk { >>>> + pins = "gpio30", "gpio31", "gpio32"; >>>> + function = "qup15"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi13_cs: qup-spi13-cs { >>>> + pins = "gpio33"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_uart13_default: qup-uart13-default { >>>> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >>>> + function = "qup15"; >>>> + }; >>>> + >>>> + qup_i2c14_data_clk: qup-i2c14-data-clk { >>>> + pins = "gpio34", "gpio35"; >>>> + function = "qup16"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi14_data_clk: qup-spi14-data-clk { >>>> + pins = "gpio34", "gpio35", "gpio36"; >>>> + function = "qup16"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi14_cs: qup-spi14-cs { >>>> + pins = "gpio37", "gpio38"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_i2c15_data_clk: qup-i2c15-data-clk { >>>> + pins = "gpio40", "gpio41"; >>>> + function = "qup17"; >>>> + drive-strength = <2>; >>>> + bias-pulll-up; >>>> + }; >>>> + >>>> + qup_spi15_data_clk: qup-spi15-data-clk { >>>> + pins = "gpio40", "gpio41", "gpio30"; >>>> + function = "qup17"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + >>>> + qup_spi15_cs: qup-spi15-cs { >>>> + pins = "gpio31"; >>>> + drive-strength = <6>; >>>> + bias-disable; >>>> + }; >>>> + }; >>>> + >>>> + apps_smmu: apps-smmu@15000000 { >>>> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >>>> + "arm,mmu-500"; >>>> + reg = <0x0 0x15000000 0x0 0x100000>; >>>> + #iommu-cells = <2>; >>>> + #global-interrupts = <2>; >>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >>>> + }; >>>> + >>>> + intc: interrupt-controller@17200000 { >>>> + compatible = "arm,gic-v3"; >>>> + #interrupt-cells = <3>; >>>> + interrupt-controller; >>>> + #redistributor-regions = <1>; >>>> + redistributor-stride = <0x0 0x20000>; >>>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >>>> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >>>> + }; >>>> + >>>> + timer@17420000 { >>>> + compatible = "arm,armv7-timer-mem"; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges; >>>> + reg = <0x0 0x17420000 0x0 0x1000>; >>>> + clock-frequency = <19200000>; >>>> + >>>> + frame@17421000 { >>>> + frame-number = <0>; >>>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x17421000 0x0 0x1000>, >>>> + <0x0 0x17422000 0x0 0x1000>; >>>> + }; >>>> + >>>> + frame@17423000 { >>>> + frame-number = <1>; >>>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x17423000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + frame@17425000 { >>>> + frame-number = <2>; >>>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x17425000 0x0 0x1000>, >>>> + <0x0 0x17426000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + frame@17427000 { >>>> + frame-number = <3>; >>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x17427000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + frame@17429000 { >>>> + frame-number = <4>; >>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x17429000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + frame@1742b000 { >>>> + frame-number = <5>; >>>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x1742b000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + frame@1742d000 { >>>> + frame-number = <6>; >>>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >>>> + reg = <0x0 0x1742d000 0x0 0x1000>; >>>> + status = "disabled"; >>>> + }; >>>> + }; >>>> + >>>> + apps_rsc: rsc@17a00000 { >>>> + label = "apps_rsc"; >>>> + compatible = "qcom,rpmh-rsc"; >>>> + reg = <0x0 0x17a00000 0x0 0x10000>, >>>> + <0x0 0x17a10000 0x0 0x10000>, >>>> + <0x0 0x17a20000 0x0 0x10000>; >>>> + reg-names = "drv-0", "drv-1", "drv-2"; >>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >>>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >>>> + qcom,tcs-offset = <0xd00>; >>>> + qcom,drv-id = <2>; >>>> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >>>> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >>>> + >>>> + apps_bcm_voter: bcm_voter { >>>> + compatible = "qcom,bcm-voter"; >>>> + }; >>>> + >>>> + rpmhcc: clock-controller { >>>> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; >>>> + #clock-cells = <1>; >>>> + clock-names = "xo"; >>>> + clocks = <&xo_board>; >>>> + }; >>>> + >>>> + rpmhpd: power-controller { >>>> + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; >>>> + #power-domain-cells = <1>; >>>> + operating-points-v2 = <&rpmhpd_opp_table>; >>>> + >>>> + rpmhpd_opp_table: opp-table { >>>> + compatible = "operating-points-v2"; >>>> + >>>> + rpmhpd_opp_ret: opp1 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; >>>> + }; >>>> + >>>> + rpmhpd_opp_min_svs: opp2 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >>>> + }; >>>> + >>>> + rpmhpd_opp_low_svs: opp3 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >>>> + }; >>>> + >>>> + rpmhpd_opp_svs: opp4 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >>>> + }; >>>> + >>>> + rpmhpd_opp_svs_l1: opp5 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >>>> + }; >>>> + >>>> + rpmhpd_opp_nom: opp6 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >>>> + }; >>>> + >>>> + rpmhpd_opp_nom_l1: opp7 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >>>> + }; >>>> + >>>> + rpmhpd_opp_nom_l2: opp8 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; >>>> + }; >>>> + >>>> + rpmhpd_opp_turbo: opp9 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >>>> + }; >>>> + >>>> + rpmhpd_opp_turbo_l1: opp10 { >>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >>>> + }; >>>> + }; >>>> + }; >>>> + }; >>>> + >>>> + cpufreq_hw: cpufreq@17d91000 { >>>> + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", >>>> + "qcom,cpufreq-epss"; >>>> + reg = <0x0 0x17d91000 0x0 0x1000>; >>>> + reg-names = "freq-domain0"; >>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >>>> + clock-names = "xo", "alternate"; >>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>>> + interrupt-names = "dcvsh-irq-0"; >>>> + #freq-domain-cells = <1>; >>>> + }; >>>> + >>>> + gem_noc: interconnect@19100000 { >>>> + reg = <0x0 0x19100000 0x0 0xB8080>; >>>> + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; >>>> + #interconnect-cells = <1>; >>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>> + }; >>>> + >>>> + arch_timer: timer { >>>> + compatible = "arm,armv8-timer"; >>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>>> + clock-frequency = <19200000>; >>>> + }; >>>> + }; >>>> +}; >>>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>> new file mode 100644 >>>> index 000000000000..074fe126e85e >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>> @@ -0,0 +1,27 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause >>>> +/* >>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>> + */ >>>> + >>>> +#include "qdu1000.dtsi" >>>> + >>>> +&reserved_memory { >>>> + /delete-node/ memory@a0000000; >>>> + /delete-node/ memory@b9600000; >>>> + /delete-node/ memory@c0000000; >>>> + >>>> + oem_tenx_mem: memory@a0000000 { >>>> + no-map; >>>> + reg = <0x0 0xa0000000 0x0 0x6400000>; >>>> + }; >>>> + >>>> + mpss_diag_buffer_mem: memory@aea00000 { >>>> + no-map; >>>> + reg = <0x0 0xaea00000 0x0 0x6400000>; >>>> + }; >>>> + >>>> + tenx_q6_buffer_mem: memory@b4e00000 { >>>> + no-map; >>>> + reg = <0x0 0xb4e00000 0x0 0x3200000>; >>>> + }; >>>> +}; >>>> -- >>>> 2.38.0 >> Thanks, >> Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-24 22:31 ` Melody Olvera @ 2022-10-24 22:51 ` Richard Acayan 2022-10-24 22:56 ` Melody Olvera 0 siblings, 1 reply; 28+ messages in thread From: Richard Acayan @ 2022-10-24 22:51 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel > On 10/24/2022 3:28 PM, Richard Acayan wrote: >>> On 10/23/2022 5:53 PM, Richard Acayan wrote: >>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>>>> to boot to shell with console on these SoCs. >>>>> >>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>>>> 2 files changed, 1673 insertions(+) >>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>> new file mode 100644 >>>>> index 000000000000..777734b30f56 >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>> @@ -0,0 +1,1646 @@ >>>>> +// SPDX-License-Identifier: BSD-3-Clause >>>>> +/* >>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>>> + */ >>>>> + >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >>>>> +#include <dt-bindings/clock/qcom,rpmh.h> >>>>> +#include <dt-bindings/dma/qcom-gpi.h> >>>>> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >>>>> +#include <dt-bindings/power/qcom-rpmpd.h> >>>>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>>> + >>>>> +/ { >>>>> + interrupt-parent = <&intc>; >>>>> + >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + >>>>> + chosen: chosen { }; >>>>> + >>>>> + clocks { >>>>> + xo_board: xo-board { >>>>> + compatible = "fixed-clock"; >>>>> + clock-frequency = <19200000>; >>>>> + clock-output-names = "xo_board"; >>>>> + #clock-cells = <0>; >>>>> + }; >>>>> + >>>>> + sleep_clk: sleep-clk { >>>>> + compatible = "fixed-clock"; >>>>> + clock-frequency = <32000>; >>>>> + #clock-cells = <0>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + cpus { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + >>>>> + CPU0: cpu@0 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a55"; >>>>> + reg = <0x0 0x0>; >>>>> + enable-method = "psci"; >>>>> + power-domain-names = "psci"; >>>>> + power-domains = <&CPU_PD0>; >>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>> + next-level-cache = <&L2_0>; >>>>> + L2_0: l2-cache { >>>>> + compatible = "cache"; >>>>> + next-level-cache = <&L3_0>; >>>>> + L3_0: l3-cache { >>>>> + compatible = "cache"; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + CPU1: cpu@100 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a55"; >>>>> + reg = <0x0 0x100>; >>>>> + enable-method = "psci"; >>>>> + power-domains = <&CPU_PD1>; >>>>> + power-domain-names = "psci"; >>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>> + next-level-cache = <&L2_100>; >>>>> + L2_100: l2-cache { >>>>> + compatible = "cache"; >>>>> + next-level-cache = <&L3_0>; >>>>> + }; >>>>> + >>>>> + }; >>>>> + >>>>> + CPU2: cpu@200 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a55"; >>>>> + reg = <0x0 0x200>; >>>>> + enable-method = "psci"; >>>>> + power-domains = <&CPU_PD2>; >>>>> + power-domain-names = "psci"; >>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>> + next-level-cache = <&L2_200>; >>>>> + L2_200: l2-cache { >>>>> + compatible = "cache"; >>>>> + next-level-cache = <&L3_0>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + CPU3: cpu@300 { >>>>> + device_type = "cpu"; >>>>> + compatible = "arm,cortex-a55"; >>>>> + reg = <0x0 0x300>; >>>>> + enable-method = "psci"; >>>>> + power-domains = <&CPU_PD3>; >>>>> + power-domain-names = "psci"; >>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>> + next-level-cache = <&L2_300>; >>>>> + L2_300: l2-cache { >>>>> + compatible = "cache"; >>>>> + next-level-cache = <&L3_0>; >>>>> + }; >>>>> + >>>>> + }; >>>>> + >>>>> + cpu-map { >>>>> + cluster0 { >>>>> + core0 { >>>>> + cpu = <&CPU0>; >>>>> + }; >>>>> + >>>>> + core1 { >>>>> + cpu = <&CPU1>; >>>>> + }; >>>>> + >>>>> + core2 { >>>>> + cpu = <&CPU2>; >>>>> + }; >>>>> + >>>>> + core3 { >>>>> + cpu = <&CPU3>; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + idle-states { >>>>> + entry-method = "psci"; >>>>> + >>>>> + CPU_OFF: cpu-sleep-0 { >>>>> + compatible = "arm,idle-state"; >>>>> + idle-state-name = "rail-pc"; >>>>> + entry-latency-us = <274>; >>>>> + exit-latency-us = <480>; >>>>> + min-residency-us = <3934>; >>>>> + arm,psci-suspend-param = <0x40000004>; >>>>> + local-timer-stop; >>>>> + }; >>>>> + }; >>>>> + >>>>> + domain-idle-states { >>>>> + CLUSTER_SLEEP_0: cluster-sleep-0 { >>>>> + compatible = "domain-idle-state"; >>>>> + idle-state-name = "cluster-l3-off"; >>>>> + entry-latency-us = <584>; >>>>> + exit-latency-us = <2332>; >>>>> + min-residency-us = <6118>; >>>>> + arm,psci-suspend-param = <0x41000044>; >>>>> + }; >>>>> + >>>>> + CLUSTER_SLEEP_1: cluster-sleep-1 { >>>>> + compatible = "domain-idle-state"; >>>>> + idle-state-name = "cluster-power-collapse"; >>>>> + entry-latency-us = <2893>; >>>>> + exit-latency-us = <4023>; >>>>> + min-residency-us = <9987>; >>>>> + arm,psci-suspend-param = <0x41003344>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + firmware { >>>>> + qcom_scm { >>>>> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >>>>> + #reset-cells = <1>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + clk_virt: interconnect-0 { >>>>> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >>>>> + #interconnect-cells = <2>; >>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>> + }; >>>>> + >>>>> + mc_virt: interconnect-1 { >>>>> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >>>>> + #interconnect-cells = <2>; >>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>> + }; >>>>> + >>>>> + memory@80000000 { >>>>> + device_type = "memory"; >>>>> + /* We expect the bootloader to fill in the size */ >>>>> + reg = <0x0 0x80000000 0x0 0x0>; >>>>> + }; >>>>> + >>>>> + pmu { >>>>> + compatible = "arm,armv8-pmuv3"; >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>>> + }; >>>>> + >>>>> + psci { >>>>> + compatible = "arm,psci-1.0"; >>>>> + method = "smc"; >>>>> + >>>>> + CPU_PD0: cpu-pd0 { >>>>> + #power-domain-cells = <0>; >>>>> + power-domains = <&CLUSTER_PD>; >>>>> + domain-idle-states = <&CPU_OFF>; >>>>> + }; >>>>> + >>>>> + CPU_PD1: cpu-pd1 { >>>>> + #power-domain-cells = <0>; >>>>> + power-domains = <&CLUSTER_PD>; >>>>> + domain-idle-states = <&CPU_OFF>; >>>>> + }; >>>>> + >>>>> + CPU_PD2: cpu-pd2 { >>>>> + #power-domain-cells = <0>; >>>>> + power-domains = <&CLUSTER_PD>; >>>>> + domain-idle-states = <&CPU_OFF>; >>>>> + }; >>>>> + >>>>> + CPU_PD3: cpu-pd3 { >>>>> + #power-domain-cells = <0>; >>>>> + power-domains = <&CLUSTER_PD>; >>>>> + domain-idle-states = <&CPU_OFF>; >>>>> + }; >>>>> + >>>>> + CLUSTER_PD: cluster-pd { >>>>> + #power-domain-cells = <0>; >>>>> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + reserved_memory: reserved-memory { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges; >>>>> + >>>>> + hyp_mem: memory@80000000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80000000 0x0 0x600000>; >>>>> + }; >>>>> + >>>>> + xbl_dt_log_mem: memory@80600000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80600000 0x0 0x40000>; >>>>> + }; >>>>> + >>>>> + xbl_ramdump_mem: memory@80640000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80640000 0x0 0x1c0000>; >>>>> + }; >>>>> + >>>>> + aop_image_mem: memory@80800000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80800000 0x0 0x60000>; >>>>> + }; >>>>> + >>>>> + aop_cmd_db_mem: memory@80860000 { >>>>> + compatible = "qcom,cmd-db"; >>>>> + no-map; >>>>> + reg = <0x0 0x80860000 0x0 0x20000>; >>>>> + }; >>>>> + >>>>> + aop_config_mem: memory@80880000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80880000 0x0 0x20000>; >>>>> + }; >>>>> + >>>>> + tme_crash_dump_mem: memory@808a0000 { >>>>> + no-map; >>>>> + reg = <0x0 0x808a0000 0x0 0x40000>; >>>>> + }; >>>>> + >>>>> + tme_log_mem: memory@808e0000 { >>>>> + no-map; >>>>> + reg = <0x0 0x808e0000 0x0 0x4000>; >>>>> + }; >>>>> + >>>>> + uefi_log_mem: memory@808e4000 { >>>>> + no-map; >>>>> + reg = <0x0 0x808e4000 0x0 0x10000>; >>>>> + }; >>>>> + >>>>> + /* secdata region can be reused by apps */ >>>>> + >>>>> + smem_mem: memory@80900000 { >>>>> + compatible = "qcom,smem"; >>>>> + no-map; >>>>> + reg = <0x0 0x80900000 0x0 0x200000>; >>>>> + hwlocks = <&tcsr_mutex 3>; >>>>> + }; >>>>> + >>>>> + cpucp_fw_mem: memory@80b00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80b00000 0x0 0x100000>; >>>>> + }; >>>>> + >>>>> + xbl_sc_mem: memory@80c00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x80c00000 0x0 0x40000>; >>>>> + }; >>>>> + >>>>> + /* uefi region can be reused by apps */ >>>>> + >>>>> + tz_stat_mem: memory@81d00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x81d00000 0x0 0x100000>; >>>>> + }; >>>>> + >>>>> + tags_mem: memory@81e00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x81e00000 0x0 0x500000>; >>>>> + }; >>>>> + >>>>> + qtee_mem: memory@82300000 { >>>>> + no-map; >>>>> + reg = <0x0 0x82300000 0x0 0x500000>; >>>>> + }; >>>>> + >>>>> + ta_mem: memory@82800000 { >>>>> + no-map; >>>>> + reg = <0x0 0x82800000 0x0 0xa00000>; >>>>> + }; >>>>> + >>>>> + fs1_mem: memory@83200000 { >>>>> + no-map; >>>>> + reg = <0x0 0x83200000 0x0 0x400000>; >>>>> + }; >>>>> + >>>>> + fs2_mem: memory@83600000 { >>>>> + no-map; >>>>> + reg = <0x0 0x83600000 0x0 0x400000>; >>>>> + }; >>>>> + >>>>> + fs3_mem: memory@83a00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x83a00000 0x0 0x400000>; >>>>> + }; >>>>> + >>>>> + /* Linux kernel image is loaded at 0x83e00000 */ >>>>> + >>>>> + ipa_fw_mem: memory@8be00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x8be00000 0x0 0x10000>; >>>>> + }; >>>>> + >>>>> + ipa_gsi_mem: memory@8be10000 { >>>>> + no-map; >>>>> + reg = <0x0 0x8be10000 0x0 0x14000>; >>>>> + }; >>>>> + >>>>> + mpss_mem: memory@8c000000 { >>>>> + no-map; >>>>> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >>>>> + }; >>>>> + >>>>> + q6_mpss_dtb_mem: memory@9ec00000 { >>>>> + no-map; >>>>> + reg = <0x0 0x9ec00000 0x0 0x80000>; >>>>> + }; >>>>> + >>>>> + tenx_mem: memory@a0000000 { >>>>> + no-map; >>>>> + reg = <0x0 0xa0000000 0x0 0x19600000>; >>>>> + }; >>>>> + >>>>> + oem_tenx_mem: memory@b9600000 { >>>>> + no-map; >>>>> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >>>>> + }; >>>>> + >>>>> + tenx_q6_buffer_mem: memory@c0000000 { >>>>> + no-map; >>>>> + reg = <0x0 0xc0000000 0x0 0x3200000>; >>>>> + }; >>>>> + >>>>> + ipa_buffer_mem: memory@c3200000 { >>>>> + no-map; >>>>> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >>>>> + }; >>>>> + }; >>>>> + >>>>> + soc: soc@0 { >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges = <0 0 0 0 0x10 0>; >>>>> + dma-ranges = <0 0 0 0 0x10 0>; >>>>> + compatible = "simple-bus"; >>>>> + >>>>> + gcc: clock-controller@80000 { >>>>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >>>>> + reg = <0x0 0x80000 0x0 0x1f4200>; >>>>> + #clock-cells = <1>; >>>>> + #reset-cells = <1>; >>>>> + #power-domain-cells = <1>; >>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >>>>> + clock-names = "bi_tcxo", "sleep_clk"; >>>>> + }; >>>>> + >>>>> + gpi_dma0: dma-controller@900000 { >>>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>>> This won't work if you drop series [1]. It won't just fail the schema checks, >>>> but it would also fail to probe because the driver doesn't recognise it. >>>> >>>> I think you were told to rebase on [2], and didn't change your own series >>>> because it only applied to ee_offset = 0x0. There is another series [3] that >>>> was sent to you, meant for ee_offset = 0x10000. You're expected to change your >>>> patches (in both series you sent) based on what was changed in that series. >>>> >>>> [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ >>>> [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ >>>> [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ >>> Hi Richard; I was aware of this feedback and was planning to make that change in v3. >>> PS [1] will be dropped and this compatible will be modified similar to PS [3]; that was >>> what I meant by my final comment on [1]. >> Ok, I should have checked the date. What about the schema patch? It might be >> helpful for the device tree cleanup efforts if you didn't add a compatible >> without adding a corresponding entry in the device tree bindings. >> >> I'm talking about updating this patch in particular: >> >> https://lore.kernel.org/linux-arm-msm/20221014221102.7445-2-quic_molvera@quicinc.com/ >> >> We still add compat strings in dt-bindings even when there is a fallback, >> because the schema is meant to specify every combination of compat strings >> found in the device trees. > That will be dropped as well. I'll use the sdm845 compat string instead of what's here. I hope you're talking about sm6350, because sdm845 has an ee_offset of 0. But if you think the maintainers will accept this, then it shouldn't be a problem. I just thought that you would copy what the other platforms are doing, which required a schema patch. Example: Documentation/devicetree/bindings/dma/qcom,gpi.yaml: properties: compatible: oneOf: - enum: - qcom,sdm845-gpi-dma - qcom,sm6350-gpi-dma - items: - enum: - qcom,qdu1000-gpi-dma - qcom,sc7280-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma and compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; would pass schema checks. Documentation/devicetree/bindings/dma/qcom,gpi.yaml: properties: compatible: oneOf: - enum: - qcom,sdm845-gpi-dma - qcom,sm6350-gpi-dma - items: - enum: - qcom,sc7280-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma and compatible = "qcom,sm6350-gpi-dma"; would also pass schema checks. Documentation/devicetree/bindings/dma/qcom,gpi.yaml: properties: compatible: oneOf: - enum: - qcom,sdm845-gpi-dma - qcom,sm6350-gpi-dma - items: - enum: - qcom,sc7280-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma and compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; would not pass schema checks. >> >>>>> + #dma-cells = <5>; >>>>> + reg = <0x0 0x900000 0x0 0x60000>; >>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >>>>> + dma-channels = <12>; >>>>> + dma-channel-mask = <0x3f>; >>>>> + iommus = <&apps_smmu 0xf6 0x0>; >>>>> + status = "ok"; >>>>> + }; >>>>> + >>>>> + qupv3_id_0: geniqup@9c0000 { >>>>> + compatible = "qcom,geni-se-qup"; >>>>> + reg = <0x0 0x9c0000 0x0 0x2000>; >>>>> + clock-names = "m-ahb", "s-ahb"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >>>>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>>>> + iommus = <&apps_smmu 0xe3 0x0>; >>>>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >>>>> + &clk_virt SLAVE_QUP_CORE_0 0>; >>>>> + interconnect-names = "qup-core"; >>>>> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >>>>> + qcom,iommu-geometry = <0x40000000 0x10000000>; >>>>> + qcom,iommu-dma = "fastmap"; >>>>> + dma-coherent; >>>>> + >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges; >>>>> + status = "disabled"; >>>>> + >>>>> + uart0: serial@980000 { >>>>> + compatible = "qcom,geni-uart"; >>>>> + reg = <0x0 0x980000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_uart0_default>; >>>>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c1: i2c@984000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c1_data_clk>; >>>>> + dmas = <&gpi_dma0 0 1 3 64 0>, >>>>> + <&gpi_dma0 1 1 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi1: spi@984000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >>>>> + dmas = <&gpi_dma0 0 1 1 64 0>, >>>>> + <&gpi_dma0 1 1 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c2: i2c@988000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c2_data_clk>; >>>>> + dmas = <&gpi_dma0 0 2 3 64 0>, >>>>> + <&gpi_dma0 1 2 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi2: spi@988000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >>>>> + dmas = <&gpi_dma0 0 2 1 64 0>, >>>>> + <&gpi_dma0 1 2 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c3: i2c@98c000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c3_data_clk>; >>>>> + dmas = <&gpi_dma0 0 3 3 64 0>, >>>>> + <&gpi_dma0 1 3 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi3: spi@98c000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >>>>> + dmas = <&gpi_dma0 0 3 1 64 0>, >>>>> + <&gpi_dma0 1 3 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c4: i2c@990000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c4_data_clk>; >>>>> + dmas = <&gpi_dma0 0 4 3 64 0>, >>>>> + <&gpi_dma0 1 4 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi4: spi@990000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >>>>> + dmas = <&gpi_dma0 0 4 1 64 0>, >>>>> + <&gpi_dma0 1 4 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c5: i2c@994000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c5_data_clk>; >>>>> + dmas = <&gpi_dma0 0 5 3 64 0>, >>>>> + <&gpi_dma0 1 5 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi5: spi@994000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >>>>> + dmas = <&gpi_dma0 0 5 1 64 0>, >>>>> + <&gpi_dma0 1 5 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c6: i2c@998000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c6_data_clk>; >>>>> + dmas = <&gpi_dma0 0 6 3 64 0>, >>>>> + <&gpi_dma0 1 6 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi6: spi@998000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >>>>> + dmas = <&gpi_dma0 0 6 1 64 0>, >>>>> + <&gpi_dma0 1 6 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + uart7: serial@99c000 { >>>>> + compatible = "qcom,geni-debug-uart"; >>>>> + reg = <0x0 0x99c000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >>>>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + gpi_dma1: dma-controller@a00000 { >>>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>>> See above. >>>> >>>>> + #dma-cells = <5>; >>>>> + reg = <0x0 0xa00000 0x0 0x60000>; >>>>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >>>>> + dma-channels = <12>; >>>>> + dma-channel-mask = <0x3f>; >>>>> + iommus = <&apps_smmu 0x116 0x0>; >>>>> + status = "ok"; >>>>> + }; >>>>> + >>>>> + qupv3_id_1: geniqup@ac0000 { >>>>> + compatible = "qcom,geni-se-qup"; >>>>> + reg = <0x0 0xac0000 0x0 0x2000>; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >>>>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >>>>> + iommus = <&apps_smmu 0x103 0x0>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <1>; >>>>> + clock-names = "m-ahb", "s-ahb"; >>>>> + >>>>> + ranges; >>>>> + status = "disabled"; >>>>> + >>>>> + uart8: serial@a80000 { >>>>> + compatible = "qcom,geni-uart"; >>>>> + reg = <0x0 0xa80000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_uart8_default>; >>>>> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c9: i2c@a84000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c9_data_clk>; >>>>> + dmas = <&gpi_dma1 0 1 3 64 0>, >>>>> + <&gpi_dma1 1 1 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi9: spi@a84000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >>>>> + dmas = <&gpi_dma1 0 1 1 64 0>, >>>>> + <&gpi_dma1 1 1 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c10: i2c@a88000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c10_data_clk>; >>>>> + dmas = <&gpi_dma1 0 2 3 64 0>, >>>>> + <&gpi_dma1 1 2 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi10: spi@a88000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >>>>> + dmas = <&gpi_dma1 0 2 1 64 0>, >>>>> + <&gpi_dma1 1 2 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c11: i2c@a8c000 { >>>>> + compatible = "qcom,i2c-geni"; >>>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c11_data_clk>; >>>>> + dmas = <&gpi_dma1 0 3 3 64 0>, >>>>> + <&gpi_dma1 1 3 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi11: spi@a8c000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >>>>> + dmas = <&gpi_dma1 0 3 1 64 0>, >>>>> + <&gpi_dma1 1 3 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c12: i2c@a90000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c12_data_clk>; >>>>> + dmas = <&gpi_dma1 0 4 3 64 0>, >>>>> + <&gpi_dma1 1 4 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi12: spi@a90000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >>>>> + dmas = <&gpi_dma1 0 4 1 64 0>, >>>>> + <&gpi_dma1 1 4 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c13: i2c@a94000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c13_data_clk>; >>>>> + dmas = <&gpi_dma1 0 5 3 64 0>, >>>>> + <&gpi_dma1 1 5 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + uart13: serial@a94000 { >>>>> + compatible = "qcom,geni-uart"; >>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_uart13_default>; >>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi13: spi@a94000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >>>>> + dmas = <&gpi_dma1 0 5 1 64 0>, >>>>> + <&gpi_dma1 1 5 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c14: i2c@a98000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c14_data_clk>; >>>>> + dmas = <&gpi_dma1 0 6 3 64 0>, >>>>> + <&gpi_dma1 1 6 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi14: spi@a98000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >>>>> + dmas = <&gpi_dma1 0 6 1 64 0>, >>>>> + <&gpi_dma1 1 6 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + i2c15: i2c@a9c000 { >>>>> + compatible = "qcom,geni-i2c"; >>>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_i2c15_data_clk>; >>>>> + dmas = <&gpi_dma1 0 7 3 64 0>, >>>>> + <&gpi_dma1 1 7 3 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + spi15: spi@a9c000 { >>>>> + compatible = "qcom,geni-spi"; >>>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>>> + #address-cells = <1>; >>>>> + #size-cells = <0>; >>>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>>> + clock-names = "se"; >>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>> + interconnects = >>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >>>>> + dmas = <&gpi_dma1 0 7 1 64 0>, >>>>> + <&gpi_dma1 1 7 1 64 0>; >>>>> + dma-names = "tx", "rx"; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + system_noc: interconnect@1640000 { >>>>> + reg = <0x0 0x1640000 0x0 0x45080>; >>>>> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >>>>> + #interconnect-cells = <1>; >>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>> + }; >>>>> + >>>>> + tcsr_mutex: hwlock@1f40000 { >>>>> + compatible = "qcom,tcsr-mutex"; >>>>> + reg = <0x0 0x1f40000 0x0 0x20000>; >>>>> + #hwlock-cells = <1>; >>>>> + }; >>>>> + >>>>> + pdc: interrupt-controller@b220000 { >>>>> + compatible = "qcom,pdc"; >>>>> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >>>>> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >>>>> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >>>>> + <94 609 31>, <125 63 1>; >>>>> + #interrupt-cells = <2>; >>>>> + interrupt-parent = <&intc>; >>>>> + interrupt-controller; >>>>> + }; >>>>> + >>>>> + spmi_bus: spmi@c400000 { >>>>> + compatible = "qcom,spmi-pmic-arb"; >>>>> + reg = <0x0 0xc400000 0x0 0x3000>, >>>>> + <0x0 0xc500000 0x0 0x400000>, >>>>> + <0x0 0xc440000 0x0 0x80000>, >>>>> + <0x0 0xc4c0000 0x0 0x10000>, >>>>> + <0x0 0xc42d000 0x0 0x4000>; >>>>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >>>>> + interrupt-names = "periph_irq"; >>>>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >>>>> + qcom,ee = <0>; >>>>> + qcom,channel = <0>; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <0>; >>>>> + interrupt-controller; >>>>> + #interrupt-cells = <4>; >>>>> + }; >>>>> + >>>>> + tlmm: pinctrl@f000000 { >>>>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >>>>> + reg = <0x0 0xf000000 0x0 0x1000000>; >>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >>>>> + gpio-controller; >>>>> + #gpio-cells = <2>; >>>>> + interrupt-controller; >>>>> + #interrupt-cells = <2>; >>>>> + gpio-ranges = <&tlmm 0 0 151>; >>>>> + wakeup-parent = <&pdc>; >>>>> + >>>>> + qup_uart0_default: qup-uart0-default-state { >>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >>>>> + function = "qup00"; >>>>> + }; >>>>> + >>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk { >>>>> + pins = "gpio10", "gpio11"; >>>>> + function = "qup01"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi1_data_clk: qup-spi1-data-clk { >>>>> + pins = "gpio10", "gpio11", "gpio12"; >>>>> + function = "qup01"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi1_cs: qup-spi1-cs { >>>>> + pins = "gpio13"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c2_data_clk: qup-i2c2-data-clk { >>>>> + pins = "gpio12", "gpio13"; >>>>> + function = "qup02"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi2_data_clk: qup-spi2-data-clk { >>>>> + pins = "gpio12", "gpio13", "gpio10"; >>>>> + function = "qup02"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi2_cs: qup-spi2-cs { >>>>> + pins = "gpio11"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c3_data_clk: qup-i2c3-data-clk { >>>>> + pins = "gpio14", "gpio15"; >>>>> + function = "qup03"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi3_data_clk: qup-spi3-data-clk { >>>>> + pins = "gpio14", "gpio15", "gpio16"; >>>>> + function = "qup03"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi3_cs: qup-spi3-cs { >>>>> + pins = "gpio17"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c4_data_clk: qup-i2c4-data-clk { >>>>> + pins = "gpio16", "gpio17"; >>>>> + function = "qup04"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi4_data_clk: qup-spi4-data-clk { >>>>> + pins = "gpio16", "gpio17", "gpio14"; >>>>> + function = "qup04"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi4_cs: qup-spi4-cs { >>>>> + pins = "gpio15"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c5_data_clk: qup-i2c5-data-clk { >>>>> + pins = "gpio130", "gpio131"; >>>>> + function = "qup05"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi5_data_clk: qup-spi5-data-clk { >>>>> + pins = "gpio130", "gpio131", "gpio132"; >>>>> + function = "qup05"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi5_cs: qup-spi5-cs { >>>>> + pins = "gpio133"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c6_data_clk: qup-i2c6-data-clk { >>>>> + pins = "gpio132", "gpio133"; >>>>> + function = "qup06"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi6_data_clk: qup-spi6-data-clk { >>>>> + pins = "gpio132", "gpio133", "gpio130"; >>>>> + function = "qup06"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi6_cs: qup-spi6-cs { >>>>> + pins = "gpio131"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_uart7_rx: qup-uart7-rx { >>>>> + pins = "gpio135"; >>>>> + function = "qup07"; >>>>> + drive-strength = <2>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_uart7_tx: qup-uart7-tx { >>>>> + pins = "gpio134"; >>>>> + function = "qup07"; >>>>> + drive-strength = <2>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_uart8_default: qup-uart8-default { >>>>> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >>>>> + function = "qup10"; >>>>> + }; >>>>> + >>>>> + qup_i2c9_data_clk: qup-i2c9-data-clk { >>>>> + pins = "gpio22", "gpio23"; >>>>> + function = "qup11"; >>>>> + drive-strength = <2>; >>>>> + bias-pull-up; >>>>> + }; >>>>> + >>>>> + qup_spi9_data_clk: qup-spi9-data-clk { >>>>> + pins = "gpio22", "gpio23", "gpio24"; >>>>> + function = "qup11"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi9_cs: qup-spi9-cs { >>>>> + pins = "gpio25"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c10_data_clk: qup-i2c10-data-clk { >>>>> + pins = "gpio24", "gpio25"; >>>>> + function = "qup12"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi10_data_clk: qup-spi10-data-clk { >>>>> + pins = "gpio24", "gpio25", "gpio22"; >>>>> + function = "qup12"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi10_cs: qup-spi10-cs { >>>>> + pins = "gpio23"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c11_data_clk: qup-i2c11-data-clk { >>>>> + pins = "gpio26", "gpio27"; >>>>> + function = "qup13"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi11_data_clk: qup-spi11-data-clk { >>>>> + pins = "gpio26", "gpio27", "gpio28"; >>>>> + function = "qup13"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi11_cs: qup-spi11-cs { >>>>> + pins = "gpio29"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c12_data_clk: qup-i2c12-data-clk { >>>>> + pins = "gpio28", "gpio29"; >>>>> + function = "qup14"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi12_data_clk: qup-spi12-data-clk { >>>>> + pins = "gpio28", "gpio29", "gpio26"; >>>>> + function = "qup14"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi12_cs: qup-spi12-cs { >>>>> + pins = "gpio27"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c13_data_clk: qup-i2c13-data-clk { >>>>> + pins = "gpio30", "gpio31"; >>>>> + function = "qup15"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi13_data_clk: qup-spi13-data-clk { >>>>> + pins = "gpio30", "gpio31", "gpio32"; >>>>> + function = "qup15"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi13_cs: qup-spi13-cs { >>>>> + pins = "gpio33"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_uart13_default: qup-uart13-default { >>>>> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >>>>> + function = "qup15"; >>>>> + }; >>>>> + >>>>> + qup_i2c14_data_clk: qup-i2c14-data-clk { >>>>> + pins = "gpio34", "gpio35"; >>>>> + function = "qup16"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi14_data_clk: qup-spi14-data-clk { >>>>> + pins = "gpio34", "gpio35", "gpio36"; >>>>> + function = "qup16"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi14_cs: qup-spi14-cs { >>>>> + pins = "gpio37", "gpio38"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_i2c15_data_clk: qup-i2c15-data-clk { >>>>> + pins = "gpio40", "gpio41"; >>>>> + function = "qup17"; >>>>> + drive-strength = <2>; >>>>> + bias-pulll-up; >>>>> + }; >>>>> + >>>>> + qup_spi15_data_clk: qup-spi15-data-clk { >>>>> + pins = "gpio40", "gpio41", "gpio30"; >>>>> + function = "qup17"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + >>>>> + qup_spi15_cs: qup-spi15-cs { >>>>> + pins = "gpio31"; >>>>> + drive-strength = <6>; >>>>> + bias-disable; >>>>> + }; >>>>> + }; >>>>> + >>>>> + apps_smmu: apps-smmu@15000000 { >>>>> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >>>>> + "arm,mmu-500"; >>>>> + reg = <0x0 0x15000000 0x0 0x100000>; >>>>> + #iommu-cells = <2>; >>>>> + #global-interrupts = <2>; >>>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >>>>> + }; >>>>> + >>>>> + intc: interrupt-controller@17200000 { >>>>> + compatible = "arm,gic-v3"; >>>>> + #interrupt-cells = <3>; >>>>> + interrupt-controller; >>>>> + #redistributor-regions = <1>; >>>>> + redistributor-stride = <0x0 0x20000>; >>>>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >>>>> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >>>>> + }; >>>>> + >>>>> + timer@17420000 { >>>>> + compatible = "arm,armv7-timer-mem"; >>>>> + #address-cells = <2>; >>>>> + #size-cells = <2>; >>>>> + ranges; >>>>> + reg = <0x0 0x17420000 0x0 0x1000>; >>>>> + clock-frequency = <19200000>; >>>>> + >>>>> + frame@17421000 { >>>>> + frame-number = <0>; >>>>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x17421000 0x0 0x1000>, >>>>> + <0x0 0x17422000 0x0 0x1000>; >>>>> + }; >>>>> + >>>>> + frame@17423000 { >>>>> + frame-number = <1>; >>>>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x17423000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + frame@17425000 { >>>>> + frame-number = <2>; >>>>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x17425000 0x0 0x1000>, >>>>> + <0x0 0x17426000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + frame@17427000 { >>>>> + frame-number = <3>; >>>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x17427000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + frame@17429000 { >>>>> + frame-number = <4>; >>>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x17429000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + frame@1742b000 { >>>>> + frame-number = <5>; >>>>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x1742b000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + frame@1742d000 { >>>>> + frame-number = <6>; >>>>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >>>>> + reg = <0x0 0x1742d000 0x0 0x1000>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + }; >>>>> + >>>>> + apps_rsc: rsc@17a00000 { >>>>> + label = "apps_rsc"; >>>>> + compatible = "qcom,rpmh-rsc"; >>>>> + reg = <0x0 0x17a00000 0x0 0x10000>, >>>>> + <0x0 0x17a10000 0x0 0x10000>, >>>>> + <0x0 0x17a20000 0x0 0x10000>; >>>>> + reg-names = "drv-0", "drv-1", "drv-2"; >>>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >>>>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >>>>> + qcom,tcs-offset = <0xd00>; >>>>> + qcom,drv-id = <2>; >>>>> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >>>>> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >>>>> + >>>>> + apps_bcm_voter: bcm_voter { >>>>> + compatible = "qcom,bcm-voter"; >>>>> + }; >>>>> + >>>>> + rpmhcc: clock-controller { >>>>> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; >>>>> + #clock-cells = <1>; >>>>> + clock-names = "xo"; >>>>> + clocks = <&xo_board>; >>>>> + }; >>>>> + >>>>> + rpmhpd: power-controller { >>>>> + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; >>>>> + #power-domain-cells = <1>; >>>>> + operating-points-v2 = <&rpmhpd_opp_table>; >>>>> + >>>>> + rpmhpd_opp_table: opp-table { >>>>> + compatible = "operating-points-v2"; >>>>> + >>>>> + rpmhpd_opp_ret: opp1 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_min_svs: opp2 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_low_svs: opp3 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_svs: opp4 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_svs_l1: opp5 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_nom: opp6 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_nom_l1: opp7 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_nom_l2: opp8 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_turbo: opp9 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >>>>> + }; >>>>> + >>>>> + rpmhpd_opp_turbo_l1: opp10 { >>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + }; >>>>> + >>>>> + cpufreq_hw: cpufreq@17d91000 { >>>>> + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", >>>>> + "qcom,cpufreq-epss"; >>>>> + reg = <0x0 0x17d91000 0x0 0x1000>; >>>>> + reg-names = "freq-domain0"; >>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >>>>> + clock-names = "xo", "alternate"; >>>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>>>> + interrupt-names = "dcvsh-irq-0"; >>>>> + #freq-domain-cells = <1>; >>>>> + }; >>>>> + >>>>> + gem_noc: interconnect@19100000 { >>>>> + reg = <0x0 0x19100000 0x0 0xB8080>; >>>>> + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; >>>>> + #interconnect-cells = <1>; >>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>> + }; >>>>> + >>>>> + arch_timer: timer { >>>>> + compatible = "arm,armv8-timer"; >>>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>>>> + clock-frequency = <19200000>; >>>>> + }; >>>>> + }; >>>>> +}; >>>>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>> new file mode 100644 >>>>> index 000000000000..074fe126e85e >>>>> --- /dev/null >>>>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>> @@ -0,0 +1,27 @@ >>>>> +// SPDX-License-Identifier: BSD-3-Clause >>>>> +/* >>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>>> + */ >>>>> + >>>>> +#include "qdu1000.dtsi" >>>>> + >>>>> +&reserved_memory { >>>>> + /delete-node/ memory@a0000000; >>>>> + /delete-node/ memory@b9600000; >>>>> + /delete-node/ memory@c0000000; >>>>> + >>>>> + oem_tenx_mem: memory@a0000000 { >>>>> + no-map; >>>>> + reg = <0x0 0xa0000000 0x0 0x6400000>; >>>>> + }; >>>>> + >>>>> + mpss_diag_buffer_mem: memory@aea00000 { >>>>> + no-map; >>>>> + reg = <0x0 0xaea00000 0x0 0x6400000>; >>>>> + }; >>>>> + >>>>> + tenx_q6_buffer_mem: memory@b4e00000 { >>>>> + no-map; >>>>> + reg = <0x0 0xb4e00000 0x0 0x3200000>; >>>>> + }; >>>>> +}; >>>>> -- >>>>> 2.38.0 >>> Thanks, >>> Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs 2022-10-24 22:51 ` Richard Acayan @ 2022-10-24 22:56 ` Melody Olvera 0 siblings, 0 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-24 22:56 UTC (permalink / raw) To: Richard Acayan, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/24/2022 3:51 PM, Richard Acayan wrote: >> On 10/24/2022 3:28 PM, Richard Acayan wrote: >>>> On 10/23/2022 5:53 PM, Richard Acayan wrote: >>>>>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base >>>>>> descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller >>>>>> to boot to shell with console on these SoCs. >>>>>> >>>>>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++++++++++ >>>>>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + >>>>>> 2 files changed, 1673 insertions(+) >>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>>> new file mode 100644 >>>>>> index 000000000000..777734b30f56 >>>>>> --- /dev/null >>>>>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >>>>>> @@ -0,0 +1,1646 @@ >>>>>> +// SPDX-License-Identifier: BSD-3-Clause >>>>>> +/* >>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>>>> + */ >>>>>> + >>>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>>>> +#include <dt-bindings/clock/qcom,gcc-qdu1000.h> >>>>>> +#include <dt-bindings/clock/qcom,rpmh.h> >>>>>> +#include <dt-bindings/dma/qcom-gpi.h> >>>>>> +#include <dt-bindings/interconnect/qcom,qdu1000.h> >>>>>> +#include <dt-bindings/power/qcom-rpmpd.h> >>>>>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>>>> + >>>>>> +/ { >>>>>> + interrupt-parent = <&intc>; >>>>>> + >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <2>; >>>>>> + >>>>>> + chosen: chosen { }; >>>>>> + >>>>>> + clocks { >>>>>> + xo_board: xo-board { >>>>>> + compatible = "fixed-clock"; >>>>>> + clock-frequency = <19200000>; >>>>>> + clock-output-names = "xo_board"; >>>>>> + #clock-cells = <0>; >>>>>> + }; >>>>>> + >>>>>> + sleep_clk: sleep-clk { >>>>>> + compatible = "fixed-clock"; >>>>>> + clock-frequency = <32000>; >>>>>> + #clock-cells = <0>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + cpus { >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <0>; >>>>>> + >>>>>> + CPU0: cpu@0 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a55"; >>>>>> + reg = <0x0 0x0>; >>>>>> + enable-method = "psci"; >>>>>> + power-domain-names = "psci"; >>>>>> + power-domains = <&CPU_PD0>; >>>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>>> + next-level-cache = <&L2_0>; >>>>>> + L2_0: l2-cache { >>>>>> + compatible = "cache"; >>>>>> + next-level-cache = <&L3_0>; >>>>>> + L3_0: l3-cache { >>>>>> + compatible = "cache"; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + CPU1: cpu@100 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a55"; >>>>>> + reg = <0x0 0x100>; >>>>>> + enable-method = "psci"; >>>>>> + power-domains = <&CPU_PD1>; >>>>>> + power-domain-names = "psci"; >>>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>>> + next-level-cache = <&L2_100>; >>>>>> + L2_100: l2-cache { >>>>>> + compatible = "cache"; >>>>>> + next-level-cache = <&L3_0>; >>>>>> + }; >>>>>> + >>>>>> + }; >>>>>> + >>>>>> + CPU2: cpu@200 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a55"; >>>>>> + reg = <0x0 0x200>; >>>>>> + enable-method = "psci"; >>>>>> + power-domains = <&CPU_PD2>; >>>>>> + power-domain-names = "psci"; >>>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>>> + next-level-cache = <&L2_200>; >>>>>> + L2_200: l2-cache { >>>>>> + compatible = "cache"; >>>>>> + next-level-cache = <&L3_0>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + CPU3: cpu@300 { >>>>>> + device_type = "cpu"; >>>>>> + compatible = "arm,cortex-a55"; >>>>>> + reg = <0x0 0x300>; >>>>>> + enable-method = "psci"; >>>>>> + power-domains = <&CPU_PD3>; >>>>>> + power-domain-names = "psci"; >>>>>> + qcom,freq-domains = <&cpufreq_hw 0>; >>>>>> + next-level-cache = <&L2_300>; >>>>>> + L2_300: l2-cache { >>>>>> + compatible = "cache"; >>>>>> + next-level-cache = <&L3_0>; >>>>>> + }; >>>>>> + >>>>>> + }; >>>>>> + >>>>>> + cpu-map { >>>>>> + cluster0 { >>>>>> + core0 { >>>>>> + cpu = <&CPU0>; >>>>>> + }; >>>>>> + >>>>>> + core1 { >>>>>> + cpu = <&CPU1>; >>>>>> + }; >>>>>> + >>>>>> + core2 { >>>>>> + cpu = <&CPU2>; >>>>>> + }; >>>>>> + >>>>>> + core3 { >>>>>> + cpu = <&CPU3>; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + idle-states { >>>>>> + entry-method = "psci"; >>>>>> + >>>>>> + CPU_OFF: cpu-sleep-0 { >>>>>> + compatible = "arm,idle-state"; >>>>>> + idle-state-name = "rail-pc"; >>>>>> + entry-latency-us = <274>; >>>>>> + exit-latency-us = <480>; >>>>>> + min-residency-us = <3934>; >>>>>> + arm,psci-suspend-param = <0x40000004>; >>>>>> + local-timer-stop; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + domain-idle-states { >>>>>> + CLUSTER_SLEEP_0: cluster-sleep-0 { >>>>>> + compatible = "domain-idle-state"; >>>>>> + idle-state-name = "cluster-l3-off"; >>>>>> + entry-latency-us = <584>; >>>>>> + exit-latency-us = <2332>; >>>>>> + min-residency-us = <6118>; >>>>>> + arm,psci-suspend-param = <0x41000044>; >>>>>> + }; >>>>>> + >>>>>> + CLUSTER_SLEEP_1: cluster-sleep-1 { >>>>>> + compatible = "domain-idle-state"; >>>>>> + idle-state-name = "cluster-power-collapse"; >>>>>> + entry-latency-us = <2893>; >>>>>> + exit-latency-us = <4023>; >>>>>> + min-residency-us = <9987>; >>>>>> + arm,psci-suspend-param = <0x41003344>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + firmware { >>>>>> + qcom_scm { >>>>>> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm"; >>>>>> + #reset-cells = <1>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + clk_virt: interconnect-0 { >>>>>> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt"; >>>>>> + #interconnect-cells = <2>; >>>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>>> + }; >>>>>> + >>>>>> + mc_virt: interconnect-1 { >>>>>> + compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt"; >>>>>> + #interconnect-cells = <2>; >>>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>>> + }; >>>>>> + >>>>>> + memory@80000000 { >>>>>> + device_type = "memory"; >>>>>> + /* We expect the bootloader to fill in the size */ >>>>>> + reg = <0x0 0x80000000 0x0 0x0>; >>>>>> + }; >>>>>> + >>>>>> + pmu { >>>>>> + compatible = "arm,armv8-pmuv3"; >>>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + }; >>>>>> + >>>>>> + psci { >>>>>> + compatible = "arm,psci-1.0"; >>>>>> + method = "smc"; >>>>>> + >>>>>> + CPU_PD0: cpu-pd0 { >>>>>> + #power-domain-cells = <0>; >>>>>> + power-domains = <&CLUSTER_PD>; >>>>>> + domain-idle-states = <&CPU_OFF>; >>>>>> + }; >>>>>> + >>>>>> + CPU_PD1: cpu-pd1 { >>>>>> + #power-domain-cells = <0>; >>>>>> + power-domains = <&CLUSTER_PD>; >>>>>> + domain-idle-states = <&CPU_OFF>; >>>>>> + }; >>>>>> + >>>>>> + CPU_PD2: cpu-pd2 { >>>>>> + #power-domain-cells = <0>; >>>>>> + power-domains = <&CLUSTER_PD>; >>>>>> + domain-idle-states = <&CPU_OFF>; >>>>>> + }; >>>>>> + >>>>>> + CPU_PD3: cpu-pd3 { >>>>>> + #power-domain-cells = <0>; >>>>>> + power-domains = <&CLUSTER_PD>; >>>>>> + domain-idle-states = <&CPU_OFF>; >>>>>> + }; >>>>>> + >>>>>> + CLUSTER_PD: cluster-pd { >>>>>> + #power-domain-cells = <0>; >>>>>> + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + reserved_memory: reserved-memory { >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <2>; >>>>>> + ranges; >>>>>> + >>>>>> + hyp_mem: memory@80000000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80000000 0x0 0x600000>; >>>>>> + }; >>>>>> + >>>>>> + xbl_dt_log_mem: memory@80600000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80600000 0x0 0x40000>; >>>>>> + }; >>>>>> + >>>>>> + xbl_ramdump_mem: memory@80640000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80640000 0x0 0x1c0000>; >>>>>> + }; >>>>>> + >>>>>> + aop_image_mem: memory@80800000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80800000 0x0 0x60000>; >>>>>> + }; >>>>>> + >>>>>> + aop_cmd_db_mem: memory@80860000 { >>>>>> + compatible = "qcom,cmd-db"; >>>>>> + no-map; >>>>>> + reg = <0x0 0x80860000 0x0 0x20000>; >>>>>> + }; >>>>>> + >>>>>> + aop_config_mem: memory@80880000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80880000 0x0 0x20000>; >>>>>> + }; >>>>>> + >>>>>> + tme_crash_dump_mem: memory@808a0000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x808a0000 0x0 0x40000>; >>>>>> + }; >>>>>> + >>>>>> + tme_log_mem: memory@808e0000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x808e0000 0x0 0x4000>; >>>>>> + }; >>>>>> + >>>>>> + uefi_log_mem: memory@808e4000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x808e4000 0x0 0x10000>; >>>>>> + }; >>>>>> + >>>>>> + /* secdata region can be reused by apps */ >>>>>> + >>>>>> + smem_mem: memory@80900000 { >>>>>> + compatible = "qcom,smem"; >>>>>> + no-map; >>>>>> + reg = <0x0 0x80900000 0x0 0x200000>; >>>>>> + hwlocks = <&tcsr_mutex 3>; >>>>>> + }; >>>>>> + >>>>>> + cpucp_fw_mem: memory@80b00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80b00000 0x0 0x100000>; >>>>>> + }; >>>>>> + >>>>>> + xbl_sc_mem: memory@80c00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x80c00000 0x0 0x40000>; >>>>>> + }; >>>>>> + >>>>>> + /* uefi region can be reused by apps */ >>>>>> + >>>>>> + tz_stat_mem: memory@81d00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x81d00000 0x0 0x100000>; >>>>>> + }; >>>>>> + >>>>>> + tags_mem: memory@81e00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x81e00000 0x0 0x500000>; >>>>>> + }; >>>>>> + >>>>>> + qtee_mem: memory@82300000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x82300000 0x0 0x500000>; >>>>>> + }; >>>>>> + >>>>>> + ta_mem: memory@82800000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x82800000 0x0 0xa00000>; >>>>>> + }; >>>>>> + >>>>>> + fs1_mem: memory@83200000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x83200000 0x0 0x400000>; >>>>>> + }; >>>>>> + >>>>>> + fs2_mem: memory@83600000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x83600000 0x0 0x400000>; >>>>>> + }; >>>>>> + >>>>>> + fs3_mem: memory@83a00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x83a00000 0x0 0x400000>; >>>>>> + }; >>>>>> + >>>>>> + /* Linux kernel image is loaded at 0x83e00000 */ >>>>>> + >>>>>> + ipa_fw_mem: memory@8be00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x8be00000 0x0 0x10000>; >>>>>> + }; >>>>>> + >>>>>> + ipa_gsi_mem: memory@8be10000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x8be10000 0x0 0x14000>; >>>>>> + }; >>>>>> + >>>>>> + mpss_mem: memory@8c000000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x8c000000 0x0 0x12c00000>; >>>>>> + }; >>>>>> + >>>>>> + q6_mpss_dtb_mem: memory@9ec00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0x9ec00000 0x0 0x80000>; >>>>>> + }; >>>>>> + >>>>>> + tenx_mem: memory@a0000000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xa0000000 0x0 0x19600000>; >>>>>> + }; >>>>>> + >>>>>> + oem_tenx_mem: memory@b9600000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xb9600000 0x0 0x6a00000>; >>>>>> + }; >>>>>> + >>>>>> + tenx_q6_buffer_mem: memory@c0000000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xc0000000 0x0 0x3200000>; >>>>>> + }; >>>>>> + >>>>>> + ipa_buffer_mem: memory@c3200000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xc3200000 0x0 0x12c00000>; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + soc: soc@0 { >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <2>; >>>>>> + ranges = <0 0 0 0 0x10 0>; >>>>>> + dma-ranges = <0 0 0 0 0x10 0>; >>>>>> + compatible = "simple-bus"; >>>>>> + >>>>>> + gcc: clock-controller@80000 { >>>>>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon"; >>>>>> + reg = <0x0 0x80000 0x0 0x1f4200>; >>>>>> + #clock-cells = <1>; >>>>>> + #reset-cells = <1>; >>>>>> + #power-domain-cells = <1>; >>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; >>>>>> + clock-names = "bi_tcxo", "sleep_clk"; >>>>>> + }; >>>>>> + >>>>>> + gpi_dma0: dma-controller@900000 { >>>>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>>>> This won't work if you drop series [1]. It won't just fail the schema checks, >>>>> but it would also fail to probe because the driver doesn't recognise it. >>>>> >>>>> I think you were told to rebase on [2], and didn't change your own series >>>>> because it only applied to ee_offset = 0x0. There is another series [3] that >>>>> was sent to you, meant for ee_offset = 0x10000. You're expected to change your >>>>> patches (in both series you sent) based on what was changed in that series. >>>>> >>>>> [1] https://lore.kernel.org/linux-arm-msm/a4db0335-33d8-76cd-6f89-b8bde603aedf@quicinc.com/ >>>>> [2] https://lore.kernel.org/linux-arm-msm/20221018005740.23952-1-mailingradian@gmail.com/T/ >>>>> [3] https://lore.kernel.org/linux-arm-msm/20221018230352.1238479-1-krzysztof.kozlowski@linaro.org/T/ >>>> Hi Richard; I was aware of this feedback and was planning to make that change in v3. >>>> PS [1] will be dropped and this compatible will be modified similar to PS [3]; that was >>>> what I meant by my final comment on [1]. >>> Ok, I should have checked the date. What about the schema patch? It might be >>> helpful for the device tree cleanup efforts if you didn't add a compatible >>> without adding a corresponding entry in the device tree bindings. >>> >>> I'm talking about updating this patch in particular: >>> >>> https://lore.kernel.org/linux-arm-msm/20221014221102.7445-2-quic_molvera@quicinc.com/ >>> >>> We still add compat strings in dt-bindings even when there is a fallback, >>> because the schema is meant to specify every combination of compat strings >>> found in the device trees. >> That will be dropped as well. I'll use the sdm845 compat string instead of what's here. > I hope you're talking about sm6350, because sdm845 has an ee_offset of 0. But if > you think the maintainers will accept this, then it shouldn't be a problem. I > just thought that you would copy what the other platforms are doing, which > required a schema patch. > > Example: > > Documentation/devicetree/bindings/dma/qcom,gpi.yaml: > > properties: > compatible: > oneOf: > - enum: > - qcom,sdm845-gpi-dma > - qcom,sm6350-gpi-dma > - items: > - enum: > - qcom,qdu1000-gpi-dma > - qcom,sc7280-gpi-dma > - qcom,sm8350-gpi-dma > - qcom,sm8450-gpi-dma > - const: qcom,sm6350-gpi-dma > > and > > compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; > > would pass schema checks. > > Documentation/devicetree/bindings/dma/qcom,gpi.yaml: > > properties: > compatible: > oneOf: > - enum: > - qcom,sdm845-gpi-dma > - qcom,sm6350-gpi-dma > - items: > - enum: > - qcom,sc7280-gpi-dma > - qcom,sm8350-gpi-dma > - qcom,sm8450-gpi-dma > - const: qcom,sm6350-gpi-dma > > and > > compatible = "qcom,sm6350-gpi-dma"; > > would also pass schema checks. > > Documentation/devicetree/bindings/dma/qcom,gpi.yaml: > > properties: > compatible: > oneOf: > - enum: > - qcom,sdm845-gpi-dma > - qcom,sm6350-gpi-dma > - items: > - enum: > - qcom,sc7280-gpi-dma > - qcom,sm8350-gpi-dma > - qcom,sm8450-gpi-dma > - const: qcom,sm6350-gpi-dma > > and > > compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; > > would not pass schema checks. Yeah I meant sm6350; my bad. I'll just use that compatible and drop the qdu one. > >>>>>> + #dma-cells = <5>; >>>>>> + reg = <0x0 0x900000 0x0 0x60000>; >>>>>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + dma-channels = <12>; >>>>>> + dma-channel-mask = <0x3f>; >>>>>> + iommus = <&apps_smmu 0xf6 0x0>; >>>>>> + status = "ok"; >>>>>> + }; >>>>>> + >>>>>> + qupv3_id_0: geniqup@9c0000 { >>>>>> + compatible = "qcom,geni-se-qup"; >>>>>> + reg = <0x0 0x9c0000 0x0 0x2000>; >>>>>> + clock-names = "m-ahb", "s-ahb"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >>>>>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >>>>>> + iommus = <&apps_smmu 0xe3 0x0>; >>>>>> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 >>>>>> + &clk_virt SLAVE_QUP_CORE_0 0>; >>>>>> + interconnect-names = "qup-core"; >>>>>> + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; >>>>>> + qcom,iommu-geometry = <0x40000000 0x10000000>; >>>>>> + qcom,iommu-dma = "fastmap"; >>>>>> + dma-coherent; >>>>>> + >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <2>; >>>>>> + ranges; >>>>>> + status = "disabled"; >>>>>> + >>>>>> + uart0: serial@980000 { >>>>>> + compatible = "qcom,geni-uart"; >>>>>> + reg = <0x0 0x980000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_uart0_default>; >>>>>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c1: i2c@984000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c1_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 1 3 64 0>, >>>>>> + <&gpi_dma0 1 1 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi1: spi@984000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x984000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >>>>>> + dmas = <&gpi_dma0 0 1 1 64 0>, >>>>>> + <&gpi_dma0 1 1 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c2: i2c@988000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c2_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 2 3 64 0>, >>>>>> + <&gpi_dma0 1 2 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi2: spi@988000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x988000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >>>>>> + dmas = <&gpi_dma0 0 2 1 64 0>, >>>>>> + <&gpi_dma0 1 2 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c3: i2c@98c000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c3_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 3 3 64 0>, >>>>>> + <&gpi_dma0 1 3 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi3: spi@98c000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x98c000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >>>>>> + dmas = <&gpi_dma0 0 3 1 64 0>, >>>>>> + <&gpi_dma0 1 3 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c4: i2c@990000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c4_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 4 3 64 0>, >>>>>> + <&gpi_dma0 1 4 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi4: spi@990000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x990000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >>>>>> + dmas = <&gpi_dma0 0 4 1 64 0>, >>>>>> + <&gpi_dma0 1 4 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c5: i2c@994000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c5_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 5 3 64 0>, >>>>>> + <&gpi_dma0 1 5 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi5: spi@994000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x994000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >>>>>> + dmas = <&gpi_dma0 0 5 1 64 0>, >>>>>> + <&gpi_dma0 1 5 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c6: i2c@998000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c6_data_clk>; >>>>>> + dmas = <&gpi_dma0 0 6 3 64 0>, >>>>>> + <&gpi_dma0 1 6 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi6: spi@998000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0x998000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>, >>>>>> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >>>>>> + dmas = <&gpi_dma0 0 6 1 64 0>, >>>>>> + <&gpi_dma0 1 6 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + uart7: serial@99c000 { >>>>>> + compatible = "qcom,geni-debug-uart"; >>>>>> + reg = <0x0 0x99c000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; >>>>>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + gpi_dma1: dma-controller@a00000 { >>>>>> + compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma"; >>>>> See above. >>>>> >>>>>> + #dma-cells = <5>; >>>>>> + reg = <0x0 0xa00000 0x0 0x60000>; >>>>>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + dma-channels = <12>; >>>>>> + dma-channel-mask = <0x3f>; >>>>>> + iommus = <&apps_smmu 0x116 0x0>; >>>>>> + status = "ok"; >>>>>> + }; >>>>>> + >>>>>> + qupv3_id_1: geniqup@ac0000 { >>>>>> + compatible = "qcom,geni-se-qup"; >>>>>> + reg = <0x0 0xac0000 0x0 0x2000>; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >>>>>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >>>>>> + iommus = <&apps_smmu 0x103 0x0>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <1>; >>>>>> + clock-names = "m-ahb", "s-ahb"; >>>>>> + >>>>>> + ranges; >>>>>> + status = "disabled"; >>>>>> + >>>>>> + uart8: serial@a80000 { >>>>>> + compatible = "qcom,geni-uart"; >>>>>> + reg = <0x0 0xa80000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_uart8_default>; >>>>>> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c9: i2c@a84000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c9_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 1 3 64 0>, >>>>>> + <&gpi_dma1 1 1 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi9: spi@a84000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa84000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >>>>>> + dmas = <&gpi_dma1 0 1 1 64 0>, >>>>>> + <&gpi_dma1 1 1 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c10: i2c@a88000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c10_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 2 3 64 0>, >>>>>> + <&gpi_dma1 1 2 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi10: spi@a88000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa88000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >>>>>> + dmas = <&gpi_dma1 0 2 1 64 0>, >>>>>> + <&gpi_dma1 1 2 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c11: i2c@a8c000 { >>>>>> + compatible = "qcom,i2c-geni"; >>>>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c11_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 3 3 64 0>, >>>>>> + <&gpi_dma1 1 3 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi11: spi@a8c000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa8c000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >>>>>> + dmas = <&gpi_dma1 0 3 1 64 0>, >>>>>> + <&gpi_dma1 1 3 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c12: i2c@a90000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c12_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 4 3 64 0>, >>>>>> + <&gpi_dma1 1 4 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi12: spi@a90000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa90000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >>>>>> + dmas = <&gpi_dma1 0 4 1 64 0>, >>>>>> + <&gpi_dma1 1 4 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c13: i2c@a94000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c13_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 5 3 64 0>, >>>>>> + <&gpi_dma1 1 5 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + uart13: serial@a94000 { >>>>>> + compatible = "qcom,geni-uart"; >>>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_uart13_default>; >>>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi13: spi@a94000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa94000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >>>>>> + dmas = <&gpi_dma1 0 5 1 64 0>, >>>>>> + <&gpi_dma1 1 5 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c14: i2c@a98000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c14_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 6 3 64 0>, >>>>>> + <&gpi_dma1 1 6 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi14: spi@a98000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa98000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; >>>>>> + dmas = <&gpi_dma1 0 6 1 64 0>, >>>>>> + <&gpi_dma1 1 6 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + i2c15: i2c@a9c000 { >>>>>> + compatible = "qcom,geni-i2c"; >>>>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_i2c15_data_clk>; >>>>>> + dmas = <&gpi_dma1 0 7 3 64 0>, >>>>>> + <&gpi_dma1 1 7 3 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + spi15: spi@a9c000 { >>>>>> + compatible = "qcom,geni-spi"; >>>>>> + reg = <0x0 0xa9c000 0x0 0x4000>; >>>>>> + #address-cells = <1>; >>>>>> + #size-cells = <0>; >>>>>> + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + clock-names = "se"; >>>>>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >>>>>> + interconnect-names = "qup-core", "qup-config", "qup-memory"; >>>>>> + interconnects = >>>>>> + <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, >>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>, >>>>>> + <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; >>>>>> + dmas = <&gpi_dma1 0 7 1 64 0>, >>>>>> + <&gpi_dma1 1 7 1 64 0>; >>>>>> + dma-names = "tx", "rx"; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + system_noc: interconnect@1640000 { >>>>>> + reg = <0x0 0x1640000 0x0 0x45080>; >>>>>> + compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc"; >>>>>> + #interconnect-cells = <1>; >>>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>>> + }; >>>>>> + >>>>>> + tcsr_mutex: hwlock@1f40000 { >>>>>> + compatible = "qcom,tcsr-mutex"; >>>>>> + reg = <0x0 0x1f40000 0x0 0x20000>; >>>>>> + #hwlock-cells = <1>; >>>>>> + }; >>>>>> + >>>>>> + pdc: interrupt-controller@b220000 { >>>>>> + compatible = "qcom,pdc"; >>>>>> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; >>>>>> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg"; >>>>>> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, >>>>>> + <94 609 31>, <125 63 1>; >>>>>> + #interrupt-cells = <2>; >>>>>> + interrupt-parent = <&intc>; >>>>>> + interrupt-controller; >>>>>> + }; >>>>>> + >>>>>> + spmi_bus: spmi@c400000 { >>>>>> + compatible = "qcom,spmi-pmic-arb"; >>>>>> + reg = <0x0 0xc400000 0x0 0x3000>, >>>>>> + <0x0 0xc500000 0x0 0x400000>, >>>>>> + <0x0 0xc440000 0x0 0x80000>, >>>>>> + <0x0 0xc4c0000 0x0 0x10000>, >>>>>> + <0x0 0xc42d000 0x0 0x4000>; >>>>>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >>>>>> + interrupt-names = "periph_irq"; >>>>>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + qcom,ee = <0>; >>>>>> + qcom,channel = <0>; >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <0>; >>>>>> + interrupt-controller; >>>>>> + #interrupt-cells = <4>; >>>>>> + }; >>>>>> + >>>>>> + tlmm: pinctrl@f000000 { >>>>>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; >>>>>> + reg = <0x0 0xf000000 0x0 0x1000000>; >>>>>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + gpio-controller; >>>>>> + #gpio-cells = <2>; >>>>>> + interrupt-controller; >>>>>> + #interrupt-cells = <2>; >>>>>> + gpio-ranges = <&tlmm 0 0 151>; >>>>>> + wakeup-parent = <&pdc>; >>>>>> + >>>>>> + qup_uart0_default: qup-uart0-default-state { >>>>>> + pins = "gpio6", "gpio7", "gpio8", "gpio9"; >>>>>> + function = "qup00"; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c1_data_clk: qup-i2c1-data-clk { >>>>>> + pins = "gpio10", "gpio11"; >>>>>> + function = "qup01"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi1_data_clk: qup-spi1-data-clk { >>>>>> + pins = "gpio10", "gpio11", "gpio12"; >>>>>> + function = "qup01"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi1_cs: qup-spi1-cs { >>>>>> + pins = "gpio13"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c2_data_clk: qup-i2c2-data-clk { >>>>>> + pins = "gpio12", "gpio13"; >>>>>> + function = "qup02"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi2_data_clk: qup-spi2-data-clk { >>>>>> + pins = "gpio12", "gpio13", "gpio10"; >>>>>> + function = "qup02"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi2_cs: qup-spi2-cs { >>>>>> + pins = "gpio11"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c3_data_clk: qup-i2c3-data-clk { >>>>>> + pins = "gpio14", "gpio15"; >>>>>> + function = "qup03"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi3_data_clk: qup-spi3-data-clk { >>>>>> + pins = "gpio14", "gpio15", "gpio16"; >>>>>> + function = "qup03"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi3_cs: qup-spi3-cs { >>>>>> + pins = "gpio17"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c4_data_clk: qup-i2c4-data-clk { >>>>>> + pins = "gpio16", "gpio17"; >>>>>> + function = "qup04"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi4_data_clk: qup-spi4-data-clk { >>>>>> + pins = "gpio16", "gpio17", "gpio14"; >>>>>> + function = "qup04"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi4_cs: qup-spi4-cs { >>>>>> + pins = "gpio15"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c5_data_clk: qup-i2c5-data-clk { >>>>>> + pins = "gpio130", "gpio131"; >>>>>> + function = "qup05"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi5_data_clk: qup-spi5-data-clk { >>>>>> + pins = "gpio130", "gpio131", "gpio132"; >>>>>> + function = "qup05"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi5_cs: qup-spi5-cs { >>>>>> + pins = "gpio133"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c6_data_clk: qup-i2c6-data-clk { >>>>>> + pins = "gpio132", "gpio133"; >>>>>> + function = "qup06"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi6_data_clk: qup-spi6-data-clk { >>>>>> + pins = "gpio132", "gpio133", "gpio130"; >>>>>> + function = "qup06"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi6_cs: qup-spi6-cs { >>>>>> + pins = "gpio131"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_uart7_rx: qup-uart7-rx { >>>>>> + pins = "gpio135"; >>>>>> + function = "qup07"; >>>>>> + drive-strength = <2>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_uart7_tx: qup-uart7-tx { >>>>>> + pins = "gpio134"; >>>>>> + function = "qup07"; >>>>>> + drive-strength = <2>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_uart8_default: qup-uart8-default { >>>>>> + pins = "gpio18", "gpio19", "gpio20", "gpio21"; >>>>>> + function = "qup10"; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c9_data_clk: qup-i2c9-data-clk { >>>>>> + pins = "gpio22", "gpio23"; >>>>>> + function = "qup11"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pull-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi9_data_clk: qup-spi9-data-clk { >>>>>> + pins = "gpio22", "gpio23", "gpio24"; >>>>>> + function = "qup11"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi9_cs: qup-spi9-cs { >>>>>> + pins = "gpio25"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c10_data_clk: qup-i2c10-data-clk { >>>>>> + pins = "gpio24", "gpio25"; >>>>>> + function = "qup12"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi10_data_clk: qup-spi10-data-clk { >>>>>> + pins = "gpio24", "gpio25", "gpio22"; >>>>>> + function = "qup12"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi10_cs: qup-spi10-cs { >>>>>> + pins = "gpio23"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c11_data_clk: qup-i2c11-data-clk { >>>>>> + pins = "gpio26", "gpio27"; >>>>>> + function = "qup13"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi11_data_clk: qup-spi11-data-clk { >>>>>> + pins = "gpio26", "gpio27", "gpio28"; >>>>>> + function = "qup13"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi11_cs: qup-spi11-cs { >>>>>> + pins = "gpio29"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c12_data_clk: qup-i2c12-data-clk { >>>>>> + pins = "gpio28", "gpio29"; >>>>>> + function = "qup14"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi12_data_clk: qup-spi12-data-clk { >>>>>> + pins = "gpio28", "gpio29", "gpio26"; >>>>>> + function = "qup14"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi12_cs: qup-spi12-cs { >>>>>> + pins = "gpio27"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c13_data_clk: qup-i2c13-data-clk { >>>>>> + pins = "gpio30", "gpio31"; >>>>>> + function = "qup15"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi13_data_clk: qup-spi13-data-clk { >>>>>> + pins = "gpio30", "gpio31", "gpio32"; >>>>>> + function = "qup15"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi13_cs: qup-spi13-cs { >>>>>> + pins = "gpio33"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_uart13_default: qup-uart13-default { >>>>>> + pins = "gpio30", "gpio31", "gpio32", "gpio33"; >>>>>> + function = "qup15"; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c14_data_clk: qup-i2c14-data-clk { >>>>>> + pins = "gpio34", "gpio35"; >>>>>> + function = "qup16"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi14_data_clk: qup-spi14-data-clk { >>>>>> + pins = "gpio34", "gpio35", "gpio36"; >>>>>> + function = "qup16"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi14_cs: qup-spi14-cs { >>>>>> + pins = "gpio37", "gpio38"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_i2c15_data_clk: qup-i2c15-data-clk { >>>>>> + pins = "gpio40", "gpio41"; >>>>>> + function = "qup17"; >>>>>> + drive-strength = <2>; >>>>>> + bias-pulll-up; >>>>>> + }; >>>>>> + >>>>>> + qup_spi15_data_clk: qup-spi15-data-clk { >>>>>> + pins = "gpio40", "gpio41", "gpio30"; >>>>>> + function = "qup17"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + >>>>>> + qup_spi15_cs: qup-spi15-cs { >>>>>> + pins = "gpio31"; >>>>>> + drive-strength = <6>; >>>>>> + bias-disable; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + apps_smmu: apps-smmu@15000000 { >>>>>> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500", >>>>>> + "arm,mmu-500"; >>>>>> + reg = <0x0 0x15000000 0x0 0x100000>; >>>>>> + #iommu-cells = <2>; >>>>>> + #global-interrupts = <2>; >>>>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + }; >>>>>> + >>>>>> + intc: interrupt-controller@17200000 { >>>>>> + compatible = "arm,gic-v3"; >>>>>> + #interrupt-cells = <3>; >>>>>> + interrupt-controller; >>>>>> + #redistributor-regions = <1>; >>>>>> + redistributor-stride = <0x0 0x20000>; >>>>>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ >>>>>> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ >>>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; >>>>>> + }; >>>>>> + >>>>>> + timer@17420000 { >>>>>> + compatible = "arm,armv7-timer-mem"; >>>>>> + #address-cells = <2>; >>>>>> + #size-cells = <2>; >>>>>> + ranges; >>>>>> + reg = <0x0 0x17420000 0x0 0x1000>; >>>>>> + clock-frequency = <19200000>; >>>>>> + >>>>>> + frame@17421000 { >>>>>> + frame-number = <0>; >>>>>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x17421000 0x0 0x1000>, >>>>>> + <0x0 0x17422000 0x0 0x1000>; >>>>>> + }; >>>>>> + >>>>>> + frame@17423000 { >>>>>> + frame-number = <1>; >>>>>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x17423000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + frame@17425000 { >>>>>> + frame-number = <2>; >>>>>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x17425000 0x0 0x1000>, >>>>>> + <0x0 0x17426000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + frame@17427000 { >>>>>> + frame-number = <3>; >>>>>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x17427000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + frame@17429000 { >>>>>> + frame-number = <4>; >>>>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x17429000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + frame@1742b000 { >>>>>> + frame-number = <5>; >>>>>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x1742b000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + >>>>>> + frame@1742d000 { >>>>>> + frame-number = <6>; >>>>>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + reg = <0x0 0x1742d000 0x0 0x1000>; >>>>>> + status = "disabled"; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + apps_rsc: rsc@17a00000 { >>>>>> + label = "apps_rsc"; >>>>>> + compatible = "qcom,rpmh-rsc"; >>>>>> + reg = <0x0 0x17a00000 0x0 0x10000>, >>>>>> + <0x0 0x17a10000 0x0 0x10000>, >>>>>> + <0x0 0x17a20000 0x0 0x10000>; >>>>>> + reg-names = "drv-0", "drv-1", "drv-2"; >>>>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, >>>>>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + qcom,tcs-offset = <0xd00>; >>>>>> + qcom,drv-id = <2>; >>>>>> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, >>>>>> + <WAKE_TCS 3>, <CONTROL_TCS 0>; >>>>>> + >>>>>> + apps_bcm_voter: bcm_voter { >>>>>> + compatible = "qcom,bcm-voter"; >>>>>> + }; >>>>>> + >>>>>> + rpmhcc: clock-controller { >>>>>> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk"; >>>>>> + #clock-cells = <1>; >>>>>> + clock-names = "xo"; >>>>>> + clocks = <&xo_board>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd: power-controller { >>>>>> + compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd"; >>>>>> + #power-domain-cells = <1>; >>>>>> + operating-points-v2 = <&rpmhpd_opp_table>; >>>>>> + >>>>>> + rpmhpd_opp_table: opp-table { >>>>>> + compatible = "operating-points-v2"; >>>>>> + >>>>>> + rpmhpd_opp_ret: opp1 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_min_svs: opp2 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_low_svs: opp3 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_svs: opp4 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_svs_l1: opp5 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_nom: opp6 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_nom_l1: opp7 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_nom_l2: opp8 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_turbo: opp9 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >>>>>> + }; >>>>>> + >>>>>> + rpmhpd_opp_turbo_l1: opp10 { >>>>>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + }; >>>>>> + >>>>>> + cpufreq_hw: cpufreq@17d91000 { >>>>>> + compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss", >>>>>> + "qcom,cpufreq-epss"; >>>>>> + reg = <0x0 0x17d91000 0x0 0x1000>; >>>>>> + reg-names = "freq-domain0"; >>>>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; >>>>>> + clock-names = "xo", "alternate"; >>>>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; >>>>>> + interrupt-names = "dcvsh-irq-0"; >>>>>> + #freq-domain-cells = <1>; >>>>>> + }; >>>>>> + >>>>>> + gem_noc: interconnect@19100000 { >>>>>> + reg = <0x0 0x19100000 0x0 0xB8080>; >>>>>> + compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc"; >>>>>> + #interconnect-cells = <1>; >>>>>> + qcom,bcm-voters = <&apps_bcm_voter>; >>>>>> + }; >>>>>> + >>>>>> + arch_timer: timer { >>>>>> + compatible = "arm,armv8-timer"; >>>>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >>>>>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >>>>>> + clock-frequency = <19200000>; >>>>>> + }; >>>>>> + }; >>>>>> +}; >>>>>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>>> new file mode 100644 >>>>>> index 000000000000..074fe126e85e >>>>>> --- /dev/null >>>>>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi >>>>>> @@ -0,0 +1,27 @@ >>>>>> +// SPDX-License-Identifier: BSD-3-Clause >>>>>> +/* >>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>>>>> + */ >>>>>> + >>>>>> +#include "qdu1000.dtsi" >>>>>> + >>>>>> +&reserved_memory { >>>>>> + /delete-node/ memory@a0000000; >>>>>> + /delete-node/ memory@b9600000; >>>>>> + /delete-node/ memory@c0000000; >>>>>> + >>>>>> + oem_tenx_mem: memory@a0000000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xa0000000 0x0 0x6400000>; >>>>>> + }; >>>>>> + >>>>>> + mpss_diag_buffer_mem: memory@aea00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xaea00000 0x0 0x6400000>; >>>>>> + }; >>>>>> + >>>>>> + tenx_q6_buffer_mem: memory@b4e00000 { >>>>>> + no-map; >>>>>> + reg = <0x0 0xb4e00000 0x0 0x3200000>; >>>>>> + }; >>>>>> +}; >>>>>> -- >>>>>> 2.38.0 >>>> Thanks, >>>> Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs 2022-10-14 22:11 [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera 2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera @ 2022-10-14 22:11 ` Melody Olvera 2022-10-15 13:29 ` Krzysztof Kozlowski 2022-10-15 0:04 ` [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera 3 siblings, 1 reply; 28+ messages in thread From: Melody Olvera @ 2022-10-14 22:11 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++++++++++++++++++++++ 3 files changed, 462 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d7669a7cee9f..8417295adfeb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts new file mode 100644 index 000000000000..47a8eaf4fda2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qdu1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + pm8150-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts new file mode 100644 index 000000000000..54770c697db8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qru1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; + compatible = "qcom,qru1000-idp", "qcom,qru1000"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + pm8150-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; -- 2.38.0 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs 2022-10-14 22:11 ` [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera @ 2022-10-15 13:29 ` Krzysztof Kozlowski 2022-10-19 21:16 ` Melody Olvera 0 siblings, 1 reply; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-15 13:29 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 14/10/2022 18:11, Melody Olvera wrote: > Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 > SoCs. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 2 + > arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++++++++++++++++++++++ > 3 files changed, 462 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts > create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index d7669a7cee9f..8417295adfeb 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb > +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb > diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts > new file mode 100644 > index 000000000000..47a8eaf4fda2 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts > @@ -0,0 +1,230 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> > +#include "qdu1000.dtsi" > +#include "pm8150.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; > + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; > + > + aliases { > + serial0 = &uart7; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + ppvar_sys: ppvar-sys-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "ppvar_sys"; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vph_pwr: vph-pwr-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vph_pwr"; > + regulator-min-microvolt = <3700000>; > + regulator-max-microvolt = <3700000>; > + > + regulator-always-on; > + regulator-boot-on; > + > + vin-supply = <&ppvar_sys>; > + }; > +}; > + > +&apps_rsc { > + pm8150-regulators { regulators > + compatible = "qcom,pm8150-rpmh-regulators"; > + qcom,pmic-id = "a"; > + > + vdd-s1-supply = <&vph_pwr>; > + vdd-s2-supply = <&vph_pwr>; > + vdd-s3-supply = <&vph_pwr>; > + vdd-s4-supply = <&vph_pwr>; > + vdd-s5-supply = <&vph_pwr>; > + vdd-s6-supply = <&vph_pwr>; > + vdd-s7-supply = <&vph_pwr>; > + vdd-s8-supply = <&vph_pwr>; > + vdd-s9-supply = <&vph_pwr>; > + vdd-s10-supply = <&vph_pwr>; > + > + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; > + vdd-l2-l10-supply = <&vph_pwr>; > + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; > + vdd-l6-l9-supply = <&vreg_s6a_0p9>; > + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; > + vdd-l13-l16-l17-supply = <&vph_pwr>; > + > + vreg_s2a_0p5: smps2 { > + regulator-name = "vreg_s2a_0p5"; > + regulator-min-microvolt = <320000>; > + regulator-max-microvolt = <570000>; > + }; > + > + vreg_s3a_1p05: smps3 { > + regulator-name = "vreg_s3a_1p05"; > + regulator-min-microvolt = <950000>; > + regulator-max-microvolt = <1170000>; > + }; > + > + vreg_s4a_1p8: smps4 { > + regulator-name = "vreg_s4a_1p8"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + }; > + > + vreg_s5a_2p0: smps5 { > + regulator-name = "vreg_s5a_2p0"; > + regulator-min-microvolt = <1904000>; > + regulator-max-microvolt = <2000000>; > + }; > + > + vreg_s6a_0p9: smps6 { > + regulator-name = "vreg_s6a_0p9"; > + regulator-min-microvolt = <920000>; > + regulator-max-microvolt = <1128000>; > + }; > + > + vreg_s7a_1p2: smps7 { > + regulator-name = "vreg_s7a_1p2"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + }; > + > + vreg_s8a_1p3: smps8 { > + regulator-name = "vreg_s8a_1p3"; > + regulator-min-microvolt = <1352000>; > + regulator-max-microvolt = <1352000>; > + }; > + > + vreg_l1a_0p91: ldo1 { > + regulator-name = "vreg_l1a_0p91"; > + regulator-min-microvolt = <312000>; > + regulator-max-microvolt = <1304000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l2a_2p3: ldo2 { > + regulator-name = "vreg_l2a_2p3"; > + regulator-min-microvolt = <2970000>; > + regulator-max-microvolt = <3300000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l3a_1p2: ldo3 { > + regulator-name = "vreg_l3a_1p2"; > + regulator-min-microvolt = <920000>; > + regulator-max-microvolt = <1260000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l5a_0p8: ldo5 { > + regulator-name = "vreg_l5a_0p8"; > + regulator-min-microvolt = <312000>; > + regulator-max-microvolt = <1304000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l6a_0p91: ldo6 { > + regulator-name = "vreg_l6a_0p91"; > + regulator-min-microvolt = <880000>; > + regulator-max-microvolt = <950000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l7a_1p8: ldo7 { > + regulator-name = "vreg_l7a_1p8"; > + regulator-min-microvolt = <1650000>; > + regulator-max-microvolt = <2000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + > + }; > + > + vreg_l8a_0p91: ldo8 { > + regulator-name = "vreg_l8a_0p91"; > + regulator-min-microvolt = <888000>; > + regulator-max-microvolt = <925000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l9a_0p91: ldo9 { > + regulator-name = "vreg_l8a_0p91"; > + regulator-min-microvolt = <312000>; > + regulator-max-microvolt = <1304000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l10a_2p95: ldo10 { > + regulator-name = "vreg_l10a_2p95"; > + regulator-min-microvolt = <2700000>; > + regulator-max-microvolt = <3544000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l11a_0p91: ldo11 { > + regulator-name = "vreg_l11a_0p91"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l12a_1p8: ldo12 { > + regulator-name = "vreg_l12a_1p8"; > + regulator-min-microvolt = <1504000>; > + regulator-max-microvolt = <1504000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l14a_1p8: ldo14 { > + regulator-name = "vreg_l14a_1p8"; > + regulator-min-microvolt = <1650000>; > + regulator-max-microvolt = <1950000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l15a_1p8: ldo15 { > + regulator-name = "vreg_l15a_1p8"; > + regulator-min-microvolt = <1504000>; > + regulator-max-microvolt = <2000000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l16a_1p8: ldo16 { > + regulator-name = "vreg_l16a_1p8"; > + regulator-min-microvolt = <1710000>; > + regulator-max-microvolt = <1890000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l17a_3p3: ldo17 { > + regulator-name = "vreg_l17a_3p3"; > + regulator-min-microvolt = <3000000>; > + regulator-max-microvolt = <3544000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + > + vreg_l18a_1p2: ldo18 { > + regulator-name = "vreg_l18a_1p2"; > + regulator-min-microvolt = <312000>; > + regulator-max-microvolt = <1304000>; > + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; > + }; > + }; > +}; > + > +&qupv3_id_0 { > + status = "okay"; > +}; > + > +&uart7 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts > new file mode 100644 > index 000000000000..54770c697db8 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts > @@ -0,0 +1,230 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> > +#include "qru1000.dtsi" > +#include "pm8150.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; > + compatible = "qcom,qru1000-idp", "qcom,qru1000"; > + > + aliases { > + serial0 = &uart7; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + ppvar_sys: ppvar-sys-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "ppvar_sys"; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vph_pwr: vph-pwr-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "vph_pwr"; > + regulator-min-microvolt = <3700000>; > + regulator-max-microvolt = <3700000>; > + > + regulator-always-on; > + regulator-boot-on; > + > + vin-supply = <&ppvar_sys>; > + }; > +}; > + > +&apps_rsc { > + pm8150-regulators { regulators Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs 2022-10-15 13:29 ` Krzysztof Kozlowski @ 2022-10-19 21:16 ` Melody Olvera 2022-10-20 12:39 ` Krzysztof Kozlowski 0 siblings, 1 reply; 28+ messages in thread From: Melody Olvera @ 2022-10-19 21:16 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/15/2022 6:29 AM, Krzysztof Kozlowski wrote: > On 14/10/2022 18:11, Melody Olvera wrote: >> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 >> SoCs. >> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 2 + >> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++++++++++++++++++++++ >> 3 files changed, 462 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts >> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index d7669a7cee9f..8417295adfeb 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb >> dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb >> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts >> new file mode 100644 >> index 000000000000..47a8eaf4fda2 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts >> @@ -0,0 +1,230 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> >> +#include "qdu1000.dtsi" >> +#include "pm8150.dtsi" >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; >> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; >> + >> + aliases { >> + serial0 = &uart7; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + ppvar_sys: ppvar-sys-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "ppvar_sys"; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + vph_pwr: vph-pwr-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "vph_pwr"; >> + regulator-min-microvolt = <3700000>; >> + regulator-max-microvolt = <3700000>; >> + >> + regulator-always-on; >> + regulator-boot-on; >> + >> + vin-supply = <&ppvar_sys>; >> + }; >> +}; >> + >> +&apps_rsc { >> + pm8150-regulators { > regulators Just 'regulators' as the node name isn't compliant with the bindings for rpmh-rsc devices. Do the bindings need to be updated or should I leave this as is? > >> + compatible = "qcom,pm8150-rpmh-regulators"; >> + qcom,pmic-id = "a"; >> + >> + vdd-s1-supply = <&vph_pwr>; >> + vdd-s2-supply = <&vph_pwr>; >> + vdd-s3-supply = <&vph_pwr>; >> + vdd-s4-supply = <&vph_pwr>; >> + vdd-s5-supply = <&vph_pwr>; >> + vdd-s6-supply = <&vph_pwr>; >> + vdd-s7-supply = <&vph_pwr>; >> + vdd-s8-supply = <&vph_pwr>; >> + vdd-s9-supply = <&vph_pwr>; >> + vdd-s10-supply = <&vph_pwr>; >> + >> + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; >> + vdd-l2-l10-supply = <&vph_pwr>; >> + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; >> + vdd-l6-l9-supply = <&vreg_s6a_0p9>; >> + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; >> + vdd-l13-l16-l17-supply = <&vph_pwr>; >> + >> + vreg_s2a_0p5: smps2 { >> + regulator-name = "vreg_s2a_0p5"; >> + regulator-min-microvolt = <320000>; >> + regulator-max-microvolt = <570000>; >> + }; >> + >> + vreg_s3a_1p05: smps3 { >> + regulator-name = "vreg_s3a_1p05"; >> + regulator-min-microvolt = <950000>; >> + regulator-max-microvolt = <1170000>; >> + }; >> + >> + vreg_s4a_1p8: smps4 { >> + regulator-name = "vreg_s4a_1p8"; >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + }; >> + >> + vreg_s5a_2p0: smps5 { >> + regulator-name = "vreg_s5a_2p0"; >> + regulator-min-microvolt = <1904000>; >> + regulator-max-microvolt = <2000000>; >> + }; >> + >> + vreg_s6a_0p9: smps6 { >> + regulator-name = "vreg_s6a_0p9"; >> + regulator-min-microvolt = <920000>; >> + regulator-max-microvolt = <1128000>; >> + }; >> + >> + vreg_s7a_1p2: smps7 { >> + regulator-name = "vreg_s7a_1p2"; >> + regulator-min-microvolt = <1200000>; >> + regulator-max-microvolt = <1200000>; >> + }; >> + >> + vreg_s8a_1p3: smps8 { >> + regulator-name = "vreg_s8a_1p3"; >> + regulator-min-microvolt = <1352000>; >> + regulator-max-microvolt = <1352000>; >> + }; >> + >> + vreg_l1a_0p91: ldo1 { >> + regulator-name = "vreg_l1a_0p91"; >> + regulator-min-microvolt = <312000>; >> + regulator-max-microvolt = <1304000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l2a_2p3: ldo2 { >> + regulator-name = "vreg_l2a_2p3"; >> + regulator-min-microvolt = <2970000>; >> + regulator-max-microvolt = <3300000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l3a_1p2: ldo3 { >> + regulator-name = "vreg_l3a_1p2"; >> + regulator-min-microvolt = <920000>; >> + regulator-max-microvolt = <1260000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l5a_0p8: ldo5 { >> + regulator-name = "vreg_l5a_0p8"; >> + regulator-min-microvolt = <312000>; >> + regulator-max-microvolt = <1304000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l6a_0p91: ldo6 { >> + regulator-name = "vreg_l6a_0p91"; >> + regulator-min-microvolt = <880000>; >> + regulator-max-microvolt = <950000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l7a_1p8: ldo7 { >> + regulator-name = "vreg_l7a_1p8"; >> + regulator-min-microvolt = <1650000>; >> + regulator-max-microvolt = <2000000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + >> + }; >> + >> + vreg_l8a_0p91: ldo8 { >> + regulator-name = "vreg_l8a_0p91"; >> + regulator-min-microvolt = <888000>; >> + regulator-max-microvolt = <925000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l9a_0p91: ldo9 { >> + regulator-name = "vreg_l8a_0p91"; >> + regulator-min-microvolt = <312000>; >> + regulator-max-microvolt = <1304000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l10a_2p95: ldo10 { >> + regulator-name = "vreg_l10a_2p95"; >> + regulator-min-microvolt = <2700000>; >> + regulator-max-microvolt = <3544000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l11a_0p91: ldo11 { >> + regulator-name = "vreg_l11a_0p91"; >> + regulator-min-microvolt = <800000>; >> + regulator-max-microvolt = <1000000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l12a_1p8: ldo12 { >> + regulator-name = "vreg_l12a_1p8"; >> + regulator-min-microvolt = <1504000>; >> + regulator-max-microvolt = <1504000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l14a_1p8: ldo14 { >> + regulator-name = "vreg_l14a_1p8"; >> + regulator-min-microvolt = <1650000>; >> + regulator-max-microvolt = <1950000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l15a_1p8: ldo15 { >> + regulator-name = "vreg_l15a_1p8"; >> + regulator-min-microvolt = <1504000>; >> + regulator-max-microvolt = <2000000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l16a_1p8: ldo16 { >> + regulator-name = "vreg_l16a_1p8"; >> + regulator-min-microvolt = <1710000>; >> + regulator-max-microvolt = <1890000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l17a_3p3: ldo17 { >> + regulator-name = "vreg_l17a_3p3"; >> + regulator-min-microvolt = <3000000>; >> + regulator-max-microvolt = <3544000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + >> + vreg_l18a_1p2: ldo18 { >> + regulator-name = "vreg_l18a_1p2"; >> + regulator-min-microvolt = <312000>; >> + regulator-max-microvolt = <1304000>; >> + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; >> + }; >> + }; >> +}; >> + >> +&qupv3_id_0 { >> + status = "okay"; >> +}; >> + >> +&uart7 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts >> new file mode 100644 >> index 000000000000..54770c697db8 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts >> @@ -0,0 +1,230 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> >> +#include "qru1000.dtsi" >> +#include "pm8150.dtsi" >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; >> + compatible = "qcom,qru1000-idp", "qcom,qru1000"; >> + >> + aliases { >> + serial0 = &uart7; >> + }; >> + >> + chosen { >> + stdout-path = "serial0:115200n8"; >> + }; >> + >> + ppvar_sys: ppvar-sys-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "ppvar_sys"; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + vph_pwr: vph-pwr-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "vph_pwr"; >> + regulator-min-microvolt = <3700000>; >> + regulator-max-microvolt = <3700000>; >> + >> + regulator-always-on; >> + regulator-boot-on; >> + >> + vin-supply = <&ppvar_sys>; >> + }; >> +}; >> + >> +&apps_rsc { >> + pm8150-regulators { > regulators Same as above. > > > Best regards, > Krzysztof > Thanks, Melody ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs 2022-10-19 21:16 ` Melody Olvera @ 2022-10-20 12:39 ` Krzysztof Kozlowski 0 siblings, 0 replies; 28+ messages in thread From: Krzysztof Kozlowski @ 2022-10-20 12:39 UTC (permalink / raw) To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 19/10/2022 17:16, Melody Olvera wrote: > > > On 10/15/2022 6:29 AM, Krzysztof Kozlowski wrote: >> On 14/10/2022 18:11, Melody Olvera wrote: >>> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000 >>> SoCs. >>> >>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 2 + >>> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++++++++++++++++++++++ >>> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++++++++++++++++++++++ >>> 3 files changed, 462 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts >>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index d7669a7cee9f..8417295adfeb 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -51,7 +51,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb >>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts >>> new file mode 100644 >>> index 000000000000..47a8eaf4fda2 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts >>> @@ -0,0 +1,230 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> >>> +#include "qdu1000.dtsi" >>> +#include "pm8150.dtsi" >>> + >>> +/ { >>> + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; >>> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; >>> + >>> + aliases { >>> + serial0 = &uart7; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> + >>> + ppvar_sys: ppvar-sys-regulator { >>> + compatible = "regulator-fixed"; >>> + regulator-name = "ppvar_sys"; >>> + regulator-always-on; >>> + regulator-boot-on; >>> + }; >>> + >>> + vph_pwr: vph-pwr-regulator { >>> + compatible = "regulator-fixed"; >>> + regulator-name = "vph_pwr"; >>> + regulator-min-microvolt = <3700000>; >>> + regulator-max-microvolt = <3700000>; >>> + >>> + regulator-always-on; >>> + regulator-boot-on; >>> + >>> + vin-supply = <&ppvar_sys>; >>> + }; >>> +}; >>> + >>> +&apps_rsc { >>> + pm8150-regulators { >> regulators > Just 'regulators' as the node name isn't compliant with the bindings for rpmh-rsc devices. > Do the bindings need to be updated or should I leave this as is? If bindings expect this, I propose to change them. Which schema is expecting this? I already fixed SMD RPM: https://lore.kernel.org/all/20220926092104.111449-1-krzysztof.kozlowski@linaro.org/ Best regards, Krzysztof ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 2022-10-14 22:11 [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera ` (2 preceding siblings ...) 2022-10-14 22:11 ` [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera @ 2022-10-15 0:04 ` Melody Olvera 3 siblings, 0 replies; 28+ messages in thread From: Melody Olvera @ 2022-10-15 0:04 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 10/14/2022 3:11 PM, Melody Olvera wrote: > This series adds the base device tree files and DTS support for the > Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu, > regulators, mmc, interconnects, cpufreq, and qup. > > This patchset is based off of [1] which adds support for the PMIC arb used > on these SoCs. > > The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit > 1000 are new SoCs meant for enabling Open RAN solutions. See more at > https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf > > [1] https://lore.kernel.org/all/20220914165212.3705892-3-vkoul@kernel.org/ Changes from v1: - squashed dtsi changes and dts changes into one commit each - changed qdru to qdu and used qru dtsi file for changes from qdu - removed underscores from node names - revised idle states and domain idle states - sorted devices by addr - removed undocumented fields - fixed pin functions - revised regulator node names > > Melody Olvera (3): > dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards > arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs > arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs > > .../devicetree/bindings/arm/qcom.yaml | 16 + > arch/arm64/boot/dts/qcom/Makefile | 2 + > arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 230 +++ > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1646 +++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000-idp.dts | 230 +++ > arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + > 6 files changed, 2151 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > > base-commit: dca0a0385a4963145593ba417e1417af88a7c18d > prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54 ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2022-10-25 0:32 UTC | newest] Thread overview: 28+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-10-14 22:11 [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera 2022-10-14 22:11 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Document QDU1000/QRU1000 SoCs and boards Melody Olvera 2022-10-15 13:19 ` Krzysztof Kozlowski 2022-10-16 22:58 ` Rob Herring 2022-10-14 22:11 ` [PATCH v2 2/3] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera 2022-10-15 13:28 ` Krzysztof Kozlowski 2022-10-19 20:21 ` Melody Olvera 2022-10-20 12:41 ` Krzysztof Kozlowski 2022-10-20 13:54 ` Stephan Gerhold 2022-10-20 16:08 ` Krzysztof Kozlowski 2022-10-20 16:26 ` Krzysztof Kozlowski 2022-10-20 17:18 ` Stephan Gerhold 2022-10-20 17:59 ` Krzysztof Kozlowski 2022-10-20 18:55 ` Melody Olvera 2022-10-15 15:11 ` Krzysztof Kozlowski 2022-10-18 22:15 ` Krzysztof Kozlowski 2022-10-19 18:56 ` Melody Olvera 2022-10-24 0:53 ` Richard Acayan 2022-10-24 17:10 ` Melody Olvera 2022-10-24 22:28 ` Richard Acayan 2022-10-24 22:31 ` Melody Olvera 2022-10-24 22:51 ` Richard Acayan 2022-10-24 22:56 ` Melody Olvera 2022-10-14 22:11 ` [PATCH v2 3/3] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera 2022-10-15 13:29 ` Krzysztof Kozlowski 2022-10-19 21:16 ` Melody Olvera 2022-10-20 12:39 ` Krzysztof Kozlowski 2022-10-15 0:04 ` [PATCH v2 0/3] Add base device tree files for QDU1000/QRU1000 Melody Olvera
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