* [PATCH 1/3] arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride
2023-02-14 15:57 [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
@ 2023-02-14 15:57 ` Bartosz Golaszewski
2023-02-14 15:57 ` [PATCH 2/3] arm64: dts: qcom: sa8775p: add the SPI " Bartosz Golaszewski
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Bartosz Golaszewski @ 2023-02-14 15:57 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add the i2c node for the interface exposed on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 +++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 3adf7349f4e5..5fdce8279537 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -13,6 +13,7 @@ / {
aliases {
serial0 = &uart10;
+ i2c18 = &i2c18;
};
chosen {
@@ -20,10 +21,21 @@ chosen {
};
};
+&i2c18 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&qup_i2c18_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
+&qupv3_id_2 {
+ status = "okay";
+};
+
&sleep_clk {
clock-frequency = <32764>;
};
@@ -33,6 +45,13 @@ qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
+
+ qup_i2c18_default: qup-i2c18-state {
+ pins = "gpio95", "gpio96";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
};
&uart10 {
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 565c1376073e..82582825f92a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -491,6 +491,40 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
};
};
+ qupv3_id_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x8c0000 0x0 0x6000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x5a3 0x0>;
+ status = "disabled";
+
+ i2c18: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x890000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+ &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
--
2.37.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/3] arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
2023-02-14 15:57 [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
2023-02-14 15:57 ` [PATCH 1/3] arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride Bartosz Golaszewski
@ 2023-02-14 15:57 ` Bartosz Golaszewski
2023-02-14 15:57 ` [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART " Bartosz Golaszewski
2023-02-15 7:06 ` [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Shazad Hussain
3 siblings, 0 replies; 8+ messages in thread
From: Bartosz Golaszewski @ 2023-02-14 15:57 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add the SPI node for the interface exposed on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 5fdce8279537..d01ca3a9ee37 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -14,6 +14,7 @@ / {
aliases {
serial0 = &uart10;
i2c18 = &i2c18;
+ spi16 = &spi16;
};
chosen {
@@ -40,12 +41,25 @@ &sleep_clk {
clock-frequency = <32764>;
};
+&spi16 {
+ pinctrl-0 = <&qup_spi16_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&tlmm {
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
+ qup_spi16_default: qup-spi16-state {
+ pins = "gpio86", "gpio87", "gpio88", "gpio89";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_i2c18_default: qup-i2c18-state {
pins = "gpio95", "gpio96";
function = "qup2_se4";
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 82582825f92a..1abb545ff4f4 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -503,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 {
iommus = <&apps_smmu 0x5a3 0x0>;
status = "disabled";
+ spi16: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x888000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+ &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x890000 0x0 0x4000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
2023-02-14 15:57 [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
2023-02-14 15:57 ` [PATCH 1/3] arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride Bartosz Golaszewski
2023-02-14 15:57 ` [PATCH 2/3] arm64: dts: qcom: sa8775p: add the SPI " Bartosz Golaszewski
@ 2023-02-14 15:57 ` Bartosz Golaszewski
2023-02-15 7:06 ` Shazad Hussain
2023-02-16 9:21 ` Krzysztof Kozlowski
2023-02-15 7:06 ` [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Shazad Hussain
3 siblings, 2 replies; 8+ messages in thread
From: Bartosz Golaszewski @ 2023-02-14 15:57 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add the serial port connected to the GNSS on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 17 ++++++++++++
2 files changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index d01ca3a9ee37..9aee6e4c1ba1 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -13,6 +13,7 @@ / {
aliases {
serial0 = &uart10;
+ serial1 = &uart17;
i2c18 = &i2c18;
spi16 = &spi16;
};
@@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
drive-strength = <2>;
bias-pull-up;
};
+
+ qup_uart17_cts: qup-uart17-cts-state {
+ pins = "gpio91";
+ function = "qup2_se3";
+ bias-disable;
+ };
+
+ qup_uart17_rts: qup0_uart17_rts-state {
+ pins = "gpio92";
+ function = "qup2_se3";
+ bias-pull-down;
+ };
+
+ qup_uart17_tx: qup0_uart17_tx-state {
+ pins = "gpio93";
+ function = "qup2_se3";
+ bias-pull-up;
+ };
+
+ qup_uart17_rx: qup0_uart17_rx-state {
+ pins = "gpio94";
+ function = "qup2_se3";
+ bias-pull-down;
+ };
};
&uart10 {
@@ -75,6 +100,15 @@ &uart10 {
status = "okay";
};
+&uart17 {
+ pinctrl-0 = <&qup_uart17_cts>,
+ <&qup_uart17_rts>,
+ <&qup_uart17_tx>,
+ <&qup_uart17_rx>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 1abb545ff4f4..b009e1100c0a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -524,6 +524,23 @@ &config_noc SLAVE_QUP_2 0>,
status = "disabled";
};
+ uart17: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x88c000 0x0 0x4000>;
+ interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+ &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x890000 0x0 0x4000>;
--
2.37.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
2023-02-14 15:57 ` [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART " Bartosz Golaszewski
@ 2023-02-15 7:06 ` Shazad Hussain
2023-02-16 9:21 ` Krzysztof Kozlowski
1 sibling, 0 replies; 8+ messages in thread
From: Shazad Hussain @ 2023-02-15 7:06 UTC (permalink / raw)
To: Bartosz Golaszewski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
On 2/14/2023 9:27 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>
> Add the serial port connected to the GNSS on sa8775p-ride.
>
Same here, this is for BT HS UART.
-Shazad
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 17 ++++++++++++
> 2 files changed, 51 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index d01ca3a9ee37..9aee6e4c1ba1 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -13,6 +13,7 @@ / {
>
> aliases {
> serial0 = &uart10;
> + serial1 = &uart17;
> i2c18 = &i2c18;
> spi16 = &spi16;
> };
> @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
> drive-strength = <2>;
> bias-pull-up;
> };
> +
> + qup_uart17_cts: qup-uart17-cts-state {
> + pins = "gpio91";
> + function = "qup2_se3";
> + bias-disable;
> + };
> +
> + qup_uart17_rts: qup0_uart17_rts-state {
> + pins = "gpio92";
> + function = "qup2_se3";
> + bias-pull-down;
> + };
> +
> + qup_uart17_tx: qup0_uart17_tx-state {
> + pins = "gpio93";
> + function = "qup2_se3";
> + bias-pull-up;
> + };
> +
> + qup_uart17_rx: qup0_uart17_rx-state {
> + pins = "gpio94";
> + function = "qup2_se3";
> + bias-pull-down;
> + };
> };
>
> &uart10 {
> @@ -75,6 +100,15 @@ &uart10 {
> status = "okay";
> };
>
> +&uart17 {
> + pinctrl-0 = <&qup_uart17_cts>,
> + <&qup_uart17_rts>,
> + <&qup_uart17_tx>,
> + <&qup_uart17_rx>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> &xo_board_clk {
> clock-frequency = <38400000>;
> };
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 1abb545ff4f4..b009e1100c0a 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -524,6 +524,23 @@ &config_noc SLAVE_QUP_2 0>,
> status = "disabled";
> };
>
> + uart17: serial@88c000 {
> + compatible = "qcom,geni-uart";
> + reg = <0x0 0x88c000 0x0 0x4000>;
> + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
> + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> + clock-names = "se";
> + interconnects = <&clk_virt MASTER_QUP_CORE_2 0
> + &clk_virt SLAVE_QUP_CORE_2 0>,
> + <&gem_noc MASTER_APPSS_PROC 0
> + &config_noc SLAVE_QUP_2 0>;
> + interconnect-names = "qup-core",
> + "qup-config";
> + power-domains = <&rpmhpd SA8775P_CX>;
> + status = "disabled";
> + };
> +
> i2c18: i2c@890000 {
> compatible = "qcom,geni-i2c";
> reg = <0x0 0x890000 0x0 0x4000>;
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for sa8775p-ride
2023-02-14 15:57 ` [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART " Bartosz Golaszewski
2023-02-15 7:06 ` Shazad Hussain
@ 2023-02-16 9:21 ` Krzysztof Kozlowski
1 sibling, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-16 9:21 UTC (permalink / raw)
To: Bartosz Golaszewski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
On 14/02/2023 16:57, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>
> Add the serial port connected to the GNSS on sa8775p-ride.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 17 ++++++++++++
> 2 files changed, 51 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index d01ca3a9ee37..9aee6e4c1ba1 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -13,6 +13,7 @@ / {
>
> aliases {
> serial0 = &uart10;
> + serial1 = &uart17;
> i2c18 = &i2c18;
> spi16 = &spi16;
> };
> @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
> drive-strength = <2>;
> bias-pull-up;
> };
> +
> + qup_uart17_cts: qup-uart17-cts-state {
> + pins = "gpio91";
> + function = "qup2_se3";
> + bias-disable;
> + };
> +
> + qup_uart17_rts: qup0_uart17_rts-state {
No underscores in node names.
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs
2023-02-14 15:57 [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
` (2 preceding siblings ...)
2023-02-14 15:57 ` [PATCH 3/3] arm64: dts: qcom: sa8775p: add the GNSS high-speed UART " Bartosz Golaszewski
@ 2023-02-15 7:06 ` Shazad Hussain
2023-02-15 9:05 ` Bartosz Golaszewski
3 siblings, 1 reply; 8+ messages in thread
From: Shazad Hussain @ 2023-02-15 7:06 UTC (permalink / raw)
To: Bartosz Golaszewski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski
On 2/14/2023 9:27 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
>
> This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
> board: I2C, SPI and the GNSS UART.
>
> Bartosz Golaszewski (3):
> arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride
> arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
> arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for
Hi Bartosz,
This instance is for BT HS UART , not for GNSS.
For GNSS we have uart12 (0x00A94000).
-Shazad
> sa8775p-ride
>
> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 67 +++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 72 +++++++++++++++++++++++
> 2 files changed, 139 insertions(+)
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs
2023-02-15 7:06 ` [PATCH 0/3] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Shazad Hussain
@ 2023-02-15 9:05 ` Bartosz Golaszewski
0 siblings, 0 replies; 8+ messages in thread
From: Bartosz Golaszewski @ 2023-02-15 9:05 UTC (permalink / raw)
To: Shazad Hussain
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel,
Bartosz Golaszewski
On Wed, Feb 15, 2023 at 8:06 AM Shazad Hussain
<quic_shazhuss@quicinc.com> wrote:
>
>
>
> On 2/14/2023 9:27 PM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >
> > This enables the QUPv3 interfaces that are exposed on the sa8775p-ride
> > board: I2C, SPI and the GNSS UART.
> >
> > Bartosz Golaszewski (3):
> > arm64: dts: qcom: sa8775p: add the i2c node for sa8775p-ride
> > arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
> > arm64: dts: qcom: sa8775p: add the GNSS high-speed UART for
>
> Hi Bartosz,
> This instance is for BT HS UART , not for GNSS.
> For GNSS we have uart12 (0x00A94000).
>
Thanks, I'll rectify it in v2.
Bart
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