From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Iskren Chernev <me@iskren.info>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH 1/2] clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
Date: Thu, 01 Jun 2023 11:39:07 +0200 [thread overview]
Message-ID: <20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org> (raw)
In-Reply-To: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org>
The "vanilla" Alpha PLL configs are sometimes provided with an intention
to only update certain bits of th register.
Do so if a mask is found.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 19 +++++++++++++++----
drivers/clk/qcom/clk-alpha-pll.h | 2 ++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index f81c7c561352..e4ef645f65d1 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -384,10 +384,21 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
- clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
- config->test_ctl_val);
- clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
- config->test_ctl_hi_val);
+ if (config->test_ctl_mask)
+ regmap_update_bits(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_mask,
+ config->test_ctl_val);
+ else
+ clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_val);
+
+ if (config->test_ctl_hi_mask)
+ regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_mask,
+ config->test_ctl_hi_val);
+ else
+ clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_val);
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 6ff0d08eb938..e4bd863027ab 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -123,7 +123,9 @@ struct alpha_pll_config {
u32 user_ctl_hi_val;
u32 user_ctl_hi1_val;
u32 test_ctl_val;
+ u32 test_ctl_mask;
u32 test_ctl_hi_val;
+ u32 test_ctl_hi_mask;
u32 test_ctl_hi1_val;
u32 test_ctl_hi2_val;
u32 main_output_mask;
--
2.40.1
next prev parent reply other threads:[~2023-06-01 9:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-01 9:39 [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Konrad Dybcio
2023-06-01 9:39 ` Konrad Dybcio [this message]
2023-06-01 9:39 ` [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties Konrad Dybcio
2023-06-02 11:08 ` [PATCH 0/2] Update parts of PLL_TEST_CTL(_U) if required Iskren Chernev
2023-06-13 23:48 ` Bjorn Andersson
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