[PATCH 1/3] dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ6018

[PATCH 1/3] dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ6018

[Robert Marko]

Document IPQ6018 compatible for Qcom NVMEM CPUFreq driver.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 .../devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml          | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
index 7391660a25ac9..f929892d654ea 100644
--- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
@@ -28,6 +28,7 @@ select:
           - qcom,apq8064
           - qcom,apq8096
           - qcom,ipq5332
+          - qcom,ipq6018
           - qcom,ipq8064
           - qcom,ipq8074
           - qcom,ipq9574
-- 
2.41.0

[PATCH 2/3] cpufreq: qcom-nvmem: add support for IPQ6018

[Robert Marko]

IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
high frequency OPP points.

SoC itself does however have a single bit in QFPROM to indicate the CPU
speed-bin.
That bit is used to indicate frequency limit of 1.5GHz, but that alone is
not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
limit it further.

IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
will get created by NVMEM CPUFreq driver.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 675da7f368469..07181913448f4 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {
 	{ .compatible = "ti,am62a7", },
 	{ .compatible = "ti,am62p5", },
 
+	{ .compatible = "qcom,ipq6018", },
 	{ .compatible = "qcom,ipq8064", },
 	{ .compatible = "qcom,ipq8074", },
 	{ .compatible = "qcom,apq8064", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 3fa12648ceb64..4a6c84b4a6d3c 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -35,6 +35,8 @@ enum ipq8074_versions {
 	IPQ8074_ACORN_VERSION,
 };
 
+#define IPQ6000_VERSION	BIT(2)
+
 struct qcom_cpufreq_drv;
 
 struct qcom_cpufreq_match_data {
@@ -246,6 +248,57 @@ static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
 	return 0;
 }
 
+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
+					     struct nvmem_cell *speedbin_nvmem,
+					     char **pvs_name,
+					     struct qcom_cpufreq_drv *drv)
+{
+	u32 msm_id;
+	int ret;
+	u8 *speedbin;
+	*pvs_name = NULL;
+
+	ret = qcom_smem_get_soc_id(&msm_id);
+	if (ret)
+		return ret;
+
+	speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
+	if (IS_ERR(speedbin))
+		return PTR_ERR(speedbin);
+
+	switch (msm_id) {
+	case QCOM_ID_IPQ6005:
+	case QCOM_ID_IPQ6010:
+	case QCOM_ID_IPQ6018:
+	case QCOM_ID_IPQ6028:
+		/* Fuse Value    Freq    BIT to set
+		 * ---------------------------------
+		 *   2’b0     No Limit     BIT(0)
+		 *   2’b1     1.5 GHz      BIT(1)
+		 */
+		drv->versions = 1 << (unsigned int)(*speedbin);
+		break;
+	case QCOM_ID_IPQ6000:
+		/*
+		 * IPQ6018 family only has one bit to advertise the CPU
+		 * speed-bin, but that is not enough for IPQ6000 which
+		 * is only rated up to 1.2GHz.
+		 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
+		 */
+		drv->versions = IPQ6000_VERSION;
+		break;
+	default:
+		dev_err(cpu_dev,
+			"SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
+			msm_id);
+		drv->versions = IPQ6000_VERSION;
+		break;
+	}
+
+	kfree(speedbin);
+	return 0;
+}
+
 static const struct qcom_cpufreq_match_data match_data_kryo = {
 	.get_version = qcom_cpufreq_kryo_name_version,
 };
@@ -260,6 +313,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 	.genpd_names = qcs404_genpd_names,
 };
 
+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
+	.get_version = qcom_cpufreq_ipq6018_name_version,
+};
+
 static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
 	.get_version = qcom_cpufreq_ipq8074_name_version,
 };
@@ -406,6 +463,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
 	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
-- 
2.41.0

[PATCH 3/3] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM

[Robert Marko]

IPQ6018 comes in multiple SKU-s and some of them dont support all of the
OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
supported OPP-s based on the SoC dynamically.

As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
goes up to 1.5GHz and is marked as such via an eFuse.

Signed-off-by: Robert Marko <robimarko@gmail.com>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9aec89d5e095b..49f0e6aa4b5bb 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -96,42 +96,49 @@ scm {
 	};
 
 	cpu_opp_table: opp-table-cpu {
-		compatible = "operating-points-v2";
+		compatible = "operating-points-v2-kryo-cpu";
+		nvmem-cells = <&cpu_speed_bin>;
 		opp-shared;
 
 		opp-864000000 {
 			opp-hz = /bits/ 64 <864000000>;
 			opp-microvolt = <725000>;
+			opp-supported-hw = <0xf>;
 			clock-latency-ns = <200000>;
 		};
 
 		opp-1056000000 {
 			opp-hz = /bits/ 64 <1056000000>;
 			opp-microvolt = <787500>;
+			opp-supported-hw = <0xf>;
 			clock-latency-ns = <200000>;
 		};
 
 		opp-1320000000 {
 			opp-hz = /bits/ 64 <1320000000>;
 			opp-microvolt = <862500>;
+			opp-supported-hw = <0x3>;
 			clock-latency-ns = <200000>;
 		};
 
 		opp-1440000000 {
 			opp-hz = /bits/ 64 <1440000000>;
 			opp-microvolt = <925000>;
+			opp-supported-hw = <0x3>;
 			clock-latency-ns = <200000>;
 		};
 
 		opp-1608000000 {
 			opp-hz = /bits/ 64 <1608000000>;
 			opp-microvolt = <987500>;
+			opp-supported-hw = <0x1>;
 			clock-latency-ns = <200000>;
 		};
 
 		opp-1800000000 {
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <1062500>;
+			opp-supported-hw = <0x1>;
 			clock-latency-ns = <200000>;
 		};
 	};
@@ -314,6 +321,11 @@ qfprom: efuse@a4000 {
 			reg = <0x0 0x000a4000 0x0 0x2000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			cpu_speed_bin: cpu_speed_bin@135 {
+				reg = <0x135 0x1>;
+				bits = <7 1>;
+			};
 		};
 
 		prng: qrng@e3000 {
-- 
2.41.0

Re: [PATCH 3/3] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM

[Konrad Dybcio]

On 10/16/23 19:55, Robert Marko wrote:
> IPQ6018 comes in multiple SKU-s and some of them dont support all of the
> OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
> supported OPP-s based on the SoC dynamically.
> 
> As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
> goes up to 1.5GHz and is marked as such via an eFuse.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 9aec89d5e095b..49f0e6aa4b5bb 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -96,42 +96,49 @@ scm {
>   	};
>   
[...]

> +			cpu_speed_bin: cpu_speed_bin@135 {
underscore -> minus sign

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH 3/3] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM

[Krzysztof Kozlowski]

On 17/10/2023 18:55, Konrad Dybcio wrote:
> 
> 
> On 10/16/23 19:55, Robert Marko wrote:
>> IPQ6018 comes in multiple SKU-s and some of them dont support all of the
>> OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
>> supported OPP-s based on the SoC dynamically.
>>
>> As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
>> goes up to 1.5GHz and is marked as such via an eFuse.
>>
>> Signed-off-by: Robert Marko <robimarko@gmail.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
>>   1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> index 9aec89d5e095b..49f0e6aa4b5bb 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -96,42 +96,49 @@ scm {
>>   	};
>>   
> [...]
> 
>> +			cpu_speed_bin: cpu_speed_bin@135 {
> underscore -> minus sign
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

I think Bjorn does not read comments, so he just picks up such patches
because they got review. Better to ask for fixing it, instead of giving
conditional review tag, IMHO.

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM

[Robert Marko]

On Tue, 17 Oct 2023 at 19:13, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 17/10/2023 18:55, Konrad Dybcio wrote:
> >
> >
> > On 10/16/23 19:55, Robert Marko wrote:
> >> IPQ6018 comes in multiple SKU-s and some of them dont support all of the
> >> OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
> >> supported OPP-s based on the SoC dynamically.
> >>
> >> As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
> >> goes up to 1.5GHz and is marked as such via an eFuse.
> >>
> >> Signed-off-by: Robert Marko <robimarko@gmail.com>
> >> ---
> >>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
> >>   1 file changed, 13 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> index 9aec89d5e095b..49f0e6aa4b5bb 100644
> >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> >> @@ -96,42 +96,49 @@ scm {
> >>      };
> >>
> > [...]
> >
> >> +                    cpu_speed_bin: cpu_speed_bin@135 {
> > underscore -> minus sign
> >
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> I think Bjorn does not read comments, so he just picks up such patches
> because they got review. Better to ask for fixing it, instead of giving
> conditional review tag, IMHO.

I will fix it up in v2, I am just waiting to see if there are comments
on the driver patch.

Regards,
Robert
>
> Best regards,
> Krzysztof
>

Re: [PATCH 1/3] dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ6018

[Viresh Kumar]

On 16-10-23, 19:55, Robert Marko wrote:
> Document IPQ6018 compatible for Qcom NVMEM CPUFreq driver.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  .../devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml          | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
> index 7391660a25ac9..f929892d654ea 100644
> --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
> @@ -28,6 +28,7 @@ select:
>            - qcom,apq8064
>            - qcom,apq8096
>            - qcom,ipq5332
> +          - qcom,ipq6018
>            - qcom,ipq8064
>            - qcom,ipq8074
>            - qcom,ipq9574

Applied. Thanks.

-- 
viresh

Re: [PATCH 2/3] cpufreq: qcom-nvmem: add support for IPQ6018

[Viresh Kumar]

On 16-10-23, 19:55, Robert Marko wrote:
> IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
> high frequency OPP points.
> 
> SoC itself does however have a single bit in QFPROM to indicate the CPU
> speed-bin.
> That bit is used to indicate frequency limit of 1.5GHz, but that alone is
> not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
> limit it further.
> 
> IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
> will get created by NVMEM CPUFreq driver.
> 
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)

Applied. Thanks.

-- 
viresh