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* [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy
@ 2023-11-10  0:02 Jonathan Marek
  2023-11-16 20:36 ` Abhinav Kumar
  2023-11-21 18:29 ` Abhinav Kumar
  0 siblings, 2 replies; 4+ messages in thread
From: Jonathan Marek @ 2023-11-10  0:02 UTC (permalink / raw)
  To: freedreno
  Cc: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
	Marijn Suijten, David Airlie, Daniel Vetter, Konrad Dybcio,
	Vinod Koul, Robert Foss, Neil Armstrong,
	open list:DRM DRIVER FOR MSM ADRENO GPU,
	open list:DRM DRIVER FOR MSM ADRENO GPU, open list

Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.

Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
v2: fixed the Fixes: line

 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d..89a6344bc865 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 	if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
 		if (phy->cphy_mode) {
 			vreg_ctrl_0 = 0x45;
-			vreg_ctrl_1 = 0x45;
+			vreg_ctrl_1 = 0x41;
 			glbl_rescode_top_ctrl = 0x00;
 			glbl_rescode_bot_ctrl = 0x00;
 		} else {
-- 
2.26.1


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end of thread, other threads:[~2023-11-21 18:29 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-11-10  0:02 [PATCH v2] drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy Jonathan Marek
2023-11-16 20:36 ` Abhinav Kumar
2023-11-16 20:49   ` [Freedreno] " Abhinav Kumar
2023-11-21 18:29 ` Abhinav Kumar

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