Re: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s

[kernel test robot <lkp@intel.com>]

Hi Ziyue,

kernel test robot noticed the following build warnings:

[auto build test WARNING on e04c78d86a9699d136910cfc0bdcf01087e3267e]

url:    https://github.com/intel-lab-lkp/linux/commits/Ziyue-Zhang/PCI-qcom-Add-equalization-settings-for-8-0-GT-s/20250625-170049
base:   e04c78d86a9699d136910cfc0bdcf01087e3267e
patch link:    https://lore.kernel.org/r/20250625085801.526669-2-quic_ziyuzhan%40quicinc.com
patch subject: [PATCH v3 1/3] PCI: qcom: Add equalization settings for 8.0 GT/s
config: i386-buildonly-randconfig-002-20250626 (https://download.01.org/0day-ci/archive/20250626/202506260310.BUxJgnmS-lkp@intel.com/config)
compiler: clang version 20.1.7 (https://github.com/llvm/llvm-project 6146a88f60492b520a36f8f8f3231e15f3cc6082)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250626/202506260310.BUxJgnmS-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506260310.BUxJgnmS-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-qcom-common.c:15:17: warning: unused variable 'dev' [-Wunused-variable]
      15 |         struct device *dev = pci->dev;
         |                        ^~~
   1 warning generated.


vim +/dev +15 drivers/pci/controller/dwc/pcie-qcom-common.c

    10	
    11	void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
    12	{
    13		u32 reg;
    14		u16 speed, max_speed = PCIE_SPEED_16_0GT;
  > 15		struct device *dev = pci->dev;
    16	
    17		/*
    18		 * GEN3_RELATED_OFF register is repurposed to apply equalization
    19		 * settings at various data transmission rates through registers namely
    20		 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF
    21		 * determines the data rate for which these equalization settings are
    22		 * applied.
    23		 */
    24		if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT)
    25			max_speed = pcie_link_speed[pci->max_link_speed];
    26	
    27		for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) {
    28			reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
    29			reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
    30			reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
    31			reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
    32				  speed - PCIE_SPEED_8_0GT);
    33			dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
    34	
    35			reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
    36			reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
    37				GEN3_EQ_FMDC_N_EVALS |
    38				GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA |
    39				GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA);
    40			reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
    41				FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
    42				FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) |
    43				FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5);
    44			dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
    45	
    46			reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
    47			reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE |
    48				GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE |
    49				GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL |
    50				GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC);
    51			dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
    52		}
    53	}
    54	EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization);
    55	

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